Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, and relates to the technical field of semiconductor chips. The semiconductor structure comprises a first device layer, and the first device layer comprises a first wafer layer, a first redistribution layer and a first heat conduction wall. Wherein the first wafer layer is oppositely provided with a first surface and a second surface in a first direction, and the first direction is perpendicular to the extension direction of the first wafer layer. The first rewiring layer is parallel to the first wafer layer and is in contact with the first wafer layer, and the first rewiring layer comprises a first heat conduction wire; the first heat conduction wall covers at least one surface, adjacent to the first surface, of the first wafer layer, and one end of the first heat conduction wire is connected with the first heat conduction wall. The semiconductor structure is applied to the dynamic random access memory so as to realize data reading and writing operation.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chip, and particularly relates to a semiconductor structure, a preparation method thereof, a storage system and an electronic device. BACKGROUND

[0002] The heat generated by an electronic product in the running process comes from the switching of the internal semiconductor structure and the Joule law. With the integration of 3D packaging, the power in the unit volume of the semiconductor structure will be more, and the heat will also increase, thereby reducing the electrical performance and reliability of the semiconductor structure, and even causing the semiconductor structure to fail.

[0003] Therefore, how to improve the heat dissipation performance of the semiconductor structure is a technical problem to be solved by related technical personnel. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor structure, a preparation method thereof, a storage system and an electronic device.

[0005] Embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, the embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure comprises a first device layer, the first device layer comprising a first wafer layer, a first rewiring layer and a first heat-conducting wall. The first wafer layer has a first surface and a second surface arranged oppositely in a first direction, and the first direction is perpendicular to the extension direction of the first wafer layer. The first rewiring layer is parallel to the first wafer layer and in contact with the first wafer layer, and the first rewiring layer comprises a first heat-conducting line. The first heat-conducting wall covers at least one surface of the first wafer layer adjacent to the first surface, and one end of the first heat-conducting line is connected to the first heat-conducting wall.

[0007] In some embodiments, the first rewiring layer is arranged in the first wafer layer, or the first rewiring layer is arranged on the first surface or the second surface.

[0008] In some embodiments, the first device layer is provided with a first conductive column and a second conductive column, and the first conductive column and the second conductive column are arranged at intervals. The first conductive column and the second conductive column both penetrate through the first wafer layer and are connected to the first rewiring layer, and the first conductive column is used for electrical connection with a transistor in the first wafer layer.

[0009] In some embodiments, the first rewiring layer further comprises a second heat-conducting line, and one end of the second heat-conducting line is connected to the second conductive column.

[0010] In some embodiments, the semiconductor structure further comprises: a second device layer, the first device layer and the second device layer are stacked. The second device layer comprises a second wafer layer and a second heat-conducting wall, the second wafer layer is stacked with the first wafer layer, wherein the second wafer layer is oppositely provided with a third surface and a fourth surface in the first direction, the second heat-conducting wall covers at least one surface of the second wafer layer adjacent to the third surface, and the second heat-conducting wall is connected with the first heat-conducting wall.

[0011] In some embodiments, the second device layer further comprises: a second redistribution layer. The second redistribution layer is arranged in the second wafer layer, or the second redistribution layer is arranged on the third surface or the fourth surface. The second redistribution layer comprises a third heat-conducting line, one end of the third heat-conducting line is connected with the second heat-conducting wall.

[0012] In some embodiments, the second device layer is provided with a third conductive column and a fourth conductive column. The third conductive column and the fourth conductive column are arranged at intervals, the third conductive column and the fourth conductive column both penetrate through the second wafer layer and are connected with the second redistribution layer, and the third conductive column is used to connect with a transistor in the second wafer layer.

[0013] In some embodiments, the second redistribution layer further comprises a fourth heat-conducting line, one end of the fourth heat-conducting line is connected with the fourth conductive column.

[0014] In some embodiments, the semiconductor structure further comprises: a heat-conducting filling part. The semiconductor structure further comprises a second device layer, the second device layer is arranged in the same layer as the first device layer. The heat-conducting filling part is filled between the first device layer and the second device layer.

[0015] In some embodiments, the semiconductor structure further comprises: a heat-conducting layer. The heat-conducting layer is stacked on the first device layer and the second device layer, and the heat-conducting layer is in contact with the heat-conducting filling part.

[0016] In another aspect, embodiments of the present disclosure provide a preparation method of a semiconductor structure. The preparation method comprises: forming a first wafer layer, the first wafer layer is oppositely provided with a first surface and a second surface in a first direction, and the first direction is perpendicular to an extension direction of the first wafer layer. Forming a first redistribution layer, the first redistribution layer is parallel to the first wafer layer and in contact with the first wafer layer, wherein the first redistribution layer comprises a first heat-conducting line. Forming a first heat-conducting wall on at least one surface of the first wafer layer adjacent to the first surface, and the first heat-conducting wall is connected with one end of the first heat-conducting line. The first wafer layer, the first redistribution layer and the first heat-conducting wall constitute a first device layer.

[0017] In some embodiments, the first wafer layer and the first redistribution layer are formed in the same process. Forming the first wafer layer and forming the first redistribution layer include: forming a first film layer. Forming the first redistribution layer on the first film layer. Forming a second film layer on the first redistribution layer, wherein the first film layer and the second film layer constitute the first wafer layer.

[0018] In some embodiments, forming the first redistribution layer on the first film layer includes: forming a first insulating layer on one side of the first film layer. Forming a first strip-shaped groove on the first insulating layer. Forming a first heat-conducting wire in the first strip-shaped groove.

[0019] In some embodiments, forming the first redistribution layer includes: forming a second insulating layer on the first surface or the second surface. Forming a second strip-shaped groove on the second insulating layer. Forming a first heat-conducting wire in the second strip-shaped groove to form the first redistribution layer.

[0020] In some embodiments, forming the first heat-conducting wall on at least one surface adjacent to the first surface of the first wafer layer includes: forming a third insulating layer on at least one surface adjacent to the first surface of the first wafer layer. Forming a first opening on the third insulating layer, the first opening exposing one end of the first heat-conducting wire. Forming the first heat-conducting wall in the first opening.

[0021] In some embodiments, the preparation method further includes: forming a first via hole and a second via hole on the first wafer layer, the first via hole and the second via hole being arranged at intervals. Forming a first conductive column in the first via hole, wherein the first conductive column is connected with a transistor in the first wafer layer. Forming a second conductive column in the second via hole, the first redistribution layer further including a second heat-conducting wire, and the second conductive column being connected with one end of the second heat-conducting wire.

[0022] In some embodiments, the preparation method further includes: forming a second device layer, the second device layer being arranged in the same layer as the first device layer. Forming a fourth insulating layer between the first device layer and the second device layer. Forming a second opening on the fourth insulating layer. Forming a heat-conducting filling portion in the second opening.

[0023] In some embodiments, the preparation method further includes: forming a heat-conducting layer on one side of the first device layer and the second device layer, the heat-conducting layer being in contact with the heat-conducting filling portion.

[0024] In another aspect, embodiments of the present disclosure provide a storage system, including: a semiconductor structure and a controller. The semiconductor structure is as described above, and the controller is coupled to the semiconductor structure to control the semiconductor structure to store data.

[0025] In another aspect, embodiments of the present disclosure provide an electronic device, including a mainboard and a storage system as described above arranged on the mainboard. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0027] Figure 1 Structural block diagrams of electronic devices provided in some embodiments of this disclosure;

[0028] Figure 2 Structural block diagrams of the memory provided in some embodiments of this disclosure;

[0029] Figure 3 This is a schematic diagram of a semiconductor structure provided in some embodiments of the present disclosure;

[0030] Figure 4 A top view of a semiconductor structure provided for some embodiments of this disclosure;

[0031] Figure 5 This is a schematic diagram of another semiconductor structure provided in some embodiments of the present disclosure;

[0032] Figure 6 This is a schematic diagram of another semiconductor structure provided in some embodiments of the present disclosure;

[0033] Figure 7 This is a schematic diagram of another semiconductor structure provided in some embodiments of the present disclosure;

[0034] Figure 8 A top view of another semiconductor structure provided in some embodiments of this disclosure;

[0035] Figure 9 This is a schematic diagram of another semiconductor structure provided in some embodiments of the present disclosure;

[0036] Figure 10 This is a schematic diagram of another semiconductor structure provided in some embodiments of the present disclosure;

[0037] Figure 11 A top view of yet another semiconductor structure provided in some embodiments of this disclosure;

[0038] Figure 12 A flowchart illustrating a method for fabricating a semiconductor structure according to some embodiments of this disclosure;

[0039] Figure 13 Flow chart of forming the first wafer layer and the first redistribution layer in the semiconductor structure preparation method provided by some embodiments of the present disclosure;

[0040] Figure 14 Structure schematic diagram after forming the first wafer layer and the first redistribution layer in the semiconductor structure preparation method provided by some embodiments of the present disclosure;

[0041] Figure 15 Flow chart of forming the first redistribution layer in the semiconductor structure preparation method provided by some embodiments of the present disclosure;

[0042] Figure 16 Structure schematic diagram after forming the first redistribution layer in the semiconductor structure preparation method provided by some embodiments of the present disclosure;

[0043] Figure 17 Flow chart of another preparation method of forming the first redistribution layer in the semiconductor structure preparation method provided by some embodiments of the present disclosure;

[0044] Figure 18 Structure schematic diagram after forming the first redistribution layer in the semiconductor structure preparation method provided by some embodiments of the present disclosure;

[0045] Figure 19 Flow chart of forming the first thermal conductive wall in the semiconductor structure preparation method provided by some embodiments of the present disclosure;

[0046] Figure 20 Structure side view after forming the first thermal conductive wall in the semiconductor structure preparation method provided by some embodiments of the present disclosure;

[0047] Figure 21 Flow chart of another semiconductor structure preparation method provided by some embodiments of the present disclosure;

[0048] Figure 22 Structure schematic diagram of another semiconductor structure provided by some embodiments of the present disclosure;

[0049] Figure 23 Flow chart of another semiconductor structure preparation method provided by some embodiments of the present disclosure;

[0050] Figure 24 Top view of another semiconductor structure provided by some embodiments of the present disclosure. DETAILED DESCRIPTION

[0051] In the following, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0052] Unless otherwise required by context, the term "including" as used in the specification and the claims is to be interpreted as "including, but not limited to". The terms "a", "an", and "the" as used in the specification and the claims are to be construed to be open, non-limiting identifications, i.e. "one or more". The terms "some" and "another" as used in the specification and the claims are to be construed as "one or more". The terms "first", "second", "third", etc. as used in the specification and the claims are to be construed as "first", "second", "third", etc. only and do not imply any relative importance of the described features. The use of the terms "first", "second", "third", etc. in the description of the embodiments does not limit the number of features to which the terms are applied. The terms "plurality" and "a plurality" as used in the specification and the claims are to be construed as "two or more". The terms "plurality" and "a plurality" as used in the specification and the claims are to be construed as "two or more". The terms "plurality" and "a plurality" as used in the specification and the claims are to be construed as "two or more".

[0053] In the following, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0054] In describing some embodiments, there is used the expressions "coupled" and "connected" along with their derivatives. For example, some embodiments can be described as being "connected" to indicate that two or more components are in direct physical or electrical contact with each other. As another example, some embodiments can be described as being "coupled" to indicate that two or more components are in direct physical or electrical contact. However, "coupled" can also mean that two or more components are not in direct contact with each other, but yet are still in cooperation or interaction with each other. The embodiments disclosed herein are not necessarily limited in terms of the wording used.

[0055] Exemplary embodiments are described herein with reference to the drawings, which are idealized illustrations. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded corners and / or irregular edges due to etching. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0056] Figure 1 A structural block diagram of an electronic device 9000 is provided for some embodiments of the disclosure.

[0057] As shown in some embodiments, the electronic device 9000 includes a main board 910 and a storage system 920 disposed on the main board 910. Figure 1

[0058] The electronic device 9000 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device (e.g., a smart watch, a smart bracelet, smart glasses, etc.), a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic device having a storage.

[0059] The main board 910 can include a processor of the electronic device 9000, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The processor on the main board 910 can be configured to send data to or receive data from the memory 921.

[0060] The storage system 920 can be integrated into various types of storage devices, such as a memory card. The memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD), and a universal flash storage (UFS). That is, the storage system 920 can be applied to and packaged into different types of electronic products.

[0061] ​In some embodiments, the storage system 920 can have one or more memories 921 and a controller 922. For example, the controller 922 can be configured to operate in a low duty cycle environment, such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile telephones, etc. Alternatively, in other examples, the controller 922 is configured to operate in a high duty cycle environment, such as an SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Yet alternatively, in some examples, the controller 922 is coupled to the memory 921 and the motherboard 910 and configured to control data in the memory 921 while being able to communicate with external devices, such as a host.

[0062] The number of memories 921 in the storage system 920 can be one or more, Figure 1The three memories 921 are illustrated as an example. The controller 922 can manage data stored in each memory 921 and communicate with the motherboard 910. The controller 922 can be configured to control operations of each memory 921, such as read, write, and refresh operations. The controller 922 can also be configured to manage various functions related to data stored or to be stored in each memory 921, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the controller 922 is also configured to determine the maximum memory capacity, the number of memory banks, the memory type and speed, the memory grain data depth and data width, and other important parameters that the computer system can use. Any other suitable functions can also be performed by the controller 922. The controller 922 can communicate with external devices (e.g., processors on the motherboard 910) according to a specific communication protocol. For example, the controller 922 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, and the like.

[0063] Figure 2 A structural block diagram of the memory 921 provided for some embodiments of the present disclosure is shown.

[0064] As Figure 2As shown, the memory 921 includes a memory cell array 913 and a peripheral circuit 914 for controlling the memory cell array 913, which can include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory cell array 913. For example, the peripheral circuit 914 can include one or more of a page buffer, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the functional circuitry described above (e.g., sub-circuits), or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors).

[0065] For example, the peripheral circuit 914 can be implemented using complementary metal-oxide-semiconductor (CMOS) technology, which can utilize logic processes (e.g., technology nodes of 90 nm, 65 nm, 60 nm, 45 nm, 32 nm, 28 nm, 22 nm, 20 nm, 16 nm, 14 nm, 10 nm, 7 nm, 5 nm, 3 nm, 2 nm, etc.).

[0066] The memory cell array 913 and the peripheral circuit 914 can be arranged side-by-side in the same plane, e.g., on the same wafer, i.e., the memory cell array 913 and the peripheral circuit 914 can be located in the same semiconductor structure. The memory cell array 913 and the peripheral circuit 914 can also be formed on different wafers and bonded together in a face-to-face manner, i.e., the memory cell array 913 and the peripheral circuit 914 can be located in different semiconductor structures. As Figure 2 As shown, when the memory cell array 913 and the peripheral circuit 914 are formed on different wafers and bonded together in a face-to-face manner, the memory 921 can include a first semiconductor structure 901 and a second semiconductor structure 902, and a bonding interface 903 between the first semiconductor structure 901 and the second semiconductor structure 902.

[0067] The first semiconductor structure 901 can include an array of memory cells 913, and the second semiconductor structure 902 can include a peripheral circuit 914. A large number of interconnects (e.g., bonding contacts) are formed through the bonding interface 903, and direct short-distance (e.g., micron-level) electrical connections can be made between the first semiconductor structure 901 and the second semiconductor structure 902, instead of long-distance (e.g., millimeter- or centimeter-level) chip-to-chip data buses on a circuit board (e.g., a printed circuit board (PCB)), thereby eliminating chip interface delays and enabling high-speed I / O throughput with reduced power consumption. Data transfer between the array of memory cells 913 in the first semiconductor structure 901 and the peripheral circuit 914 in the second semiconductor structure 902 can be performed through the interconnects (e.g., bonding contacts) through the bonding interface 903. By vertically integrating the first semiconductor structure 901 and the second semiconductor structure 902, chip size can be reduced, and storage density of the memory 921 can be increased.

[0068] The array of memory cells 913 can be an array of memory cells that use vertical transistors as switching and selection devices. In some embodiments, the array of memory cells 913 can be an array of dynamic random access memory (DRAM) cells. For ease of description, DRAM cell arrays can be used to describe examples of the array of memory cells 913 in the present disclosure. However, it should be understood that the array of memory cells 913 is not limited to DRAM cell arrays, and can include any other suitable type of array of memory cells 913 that can use vertical transistors as switching and selection devices, such as an array of phase change memory (PCM) cells, an array of static random-access memory (SRAM) cells, an array of ferroelectric random access memory (FRAM) cells, an array of resistive memory cells, an array of magnetic memory cells, an array of spin transfer torque (STT) memory cells, and the like.

[0069] In the scenario where the memory cell array 913 is a DRAM cell array, the memory cells therein are DRAM cells, which include a capacitor for storing a data bit as a positive or negative charge and one or more transistors (also referred to as pass transistors) that control (e.g., switch and select) access to the DRAM cell. In some implementations, each DRAM cell is a one-transistor and one-capacitor (1T1C) cell. According to some implementations, the DRAM cells can be refreshed by the peripheral circuit 914 to maintain data.

[0070] Figure 3 A structural schematic diagram of a semiconductor structure 100 provided by some embodiments of the present disclosure, Figure 4 A top view of a semiconductor structure 100 provided by some embodiments of the present disclosure.

[0071] As shown in Figure 3 and Figure 4 In some embodiments, the semiconductor structure 100 includes a first device layer 110, the first device layer 110 including a first wafer layer 111, a first rewiring layer 112, and a first heat-conducting wall 113. The first wafer layer 111 has a first surface 1111 and a second surface 1112 oppositely arranged in a first direction Z, the first direction Z being perpendicular to the extension direction of the first wafer layer 111. The first rewiring layer 112 is parallel to the first wafer layer 111 and in contact with the first wafer layer 111, wherein the first rewiring layer 112 includes a first heat-conducting line 1121. The first heat-conducting wall 113 covers at least one surface of the first wafer layer 111 adjacent to the first surface 1111, and one end of the first heat-conducting line 1121 is connected to the first heat-conducting wall 113.

[0072] The semiconductor structure 100 will generate a large amount of heat during operation, and as the power per unit volume of the semiconductor structure 100 increases, the heat will also increase. If the heat generated by the semiconductor structure 100 cannot be conducted to the outside in time, the electrical performance and reliability of the semiconductor structure 100 will be reduced, and even cause the semiconductor structure 100 to malfunction.

[0073] Based on this, in the embodiment, the first re-wiring layer 112 in contact with the first wafer layer 111 can timely conduct the heat generated by the first wafer layer 111 to the outside, wherein the first re-wiring layer 112 is provided with a first heat conduction line 1121 with high thermal conductivity. For example, the first wafer layer 111 can have a plurality of layers of circuit traces or electronic components and the like inside, and a large amount of heat will be generated in the plurality of layers of circuit traces or electronic components and the like inside the first wafer layer 111 during operation. By providing the first heat conduction line 1121, the heat generated by the first wafer layer 111 can be transferred to the first heat conduction line 1121, and then dissipated to the outside through the first heat conduction line 1121, thereby achieving heat dissipation of the first wafer layer 111.

[0074] In the embodiment, Figure 3 and Figure 4 are only for illustrative purposes and may not necessarily reflect the actual device structure (e.g., interconnection, layout of lines, etc.). For example, the first wafer layer 111 in the semiconductor structure 100 can be a whole wafer structure or a partial wafer structure (e.g., a semiconductor memory chip) obtained by cutting the whole wafer structure, and thus the first wafer layer 111 can have any suitable shape such as a cylindrical shape or a cubic shape.

[0075] For example, the number of the first heat conduction lines 1121 in the first re-wiring layer 112 can be one or more, and the plurality of first heat conduction lines 1121 can be connected to each other or can be independent of each other. In addition, in the case where the number of the first heat conduction lines 1121 is a plurality, the extension directions of the plurality of first heat conduction lines 1121 can be the same or different, and the embodiment of the present disclosure is not limited in this regard.

[0076] For example, the material of the first heat conduction line 1121 can be a metal material such as copper or silver with high thermal conductivity, and in another example, the material of the first heat conduction line 1121 can be another material with high thermal conductivity, and the embodiment of the present disclosure is not limited in this regard.

[0077] In addition, in the embodiment, at least one surface of the first wafer layer 111 adjacent to the first surface 1111 is covered with a first heat conduction wall 113. For example, the first wafer layer 111 has an upper surface (the first surface 1111) and a lower surface (the second surface 1112) arranged opposite in the first direction Z, and the first heat conduction wall 113 can cover at least one side surface other than the upper and lower surfaces. For example, the number of side surfaces covered by the first heat conduction wall 113 can be one, two, three, or four. The first heat conduction wall 113 can partially cover or completely cover each side surface, and the present disclosure is not limited in this regard.

[0078] Exemplarily, the material of the first heat-conducting wall 113 can be a metal material with high heat conductivity, such as copper, silver, or other materials with high heat conductivity, and the embodiments of the present disclosure are not limited thereto.

[0079] In this way, the first heat-conducting wall 113 can be used to conduct the heat generated by the first wafer layer 111 to the outside in time, so as to achieve heat dissipation of the first wafer layer 111, thereby improving the heat dissipation performance of the semiconductor structure 100. Since the first heat-conducting wall 113 covers the side surface of the first wafer layer 111, the heat conducted by the first heat-conducting wire 1121 can be transferred to the first heat-conducting wall 113 by connecting the first heat-conducting wall 113 with one end of the first heat-conducting wire 1121, and then the first heat-conducting wall 113 can be used to quickly dissipate the heat. Since the first heat-conducting wall 113 has a larger heat dissipation surface than the first heat-conducting wire 1121, such connection can further improve the heat dissipation rate of the semiconductor structure 100, thereby improving the electrical performance and reliability of the semiconductor structure 100.

[0080] Figure 5 Another structural schematic diagram of a semiconductor structure 100 provided by some embodiments of the present disclosure is shown in FIG. 2.

[0081] Referring to FIG. 2, Figures 3-5 In some embodiments, the first rewiring layer 112 is arranged in the first wafer layer 111, or the first rewiring layer 112 is arranged on the first surface 1111 or the second surface 1112.

[0082] In the present embodiment, the first rewiring layer 112 can be arranged at different positions of the first wafer layer 111, so as to adapt to the first wafer layer 111 in different application scenarios.

[0083] In some examples, for the first wafer layer 111 that has been prepared, the first rewiring layer 112 can be arranged on the first surface 1111 or the second surface 1112 of the first wafer layer 111, so as to achieve heat dissipation of the first wafer layer 111, thereby improving the heat dissipation performance of the first wafer layer 111 and even the entire semiconductor structure 100. Exemplarily, the first rewiring layer 112 can be arranged only on the first surface 1111 of the first wafer layer 111, or only on the second surface 1112 of the first wafer layer 111, or the first rewiring layer 112 can be arranged on both the first surface 1111 and the second surface 1112 of the first wafer layer 111, so as to improve the flexibility of the layout of the first rewiring layer 112, thereby improving the universality of the first rewiring layer 112 in different application scenarios.

[0084] In some examples, the first wafer layer 111 can have a multi-layer circuit structure inside, and the first re-wiring layer 112 can be prepared in the process of preparing the multi-layer circuit structure of the first wafer layer 111, so that the first re-wiring layer 112 is arranged inside the first wafer layer 111, thereby improving the heat dissipation capacity, simplifying the preparation process, and reducing the preparation cost. For example, the first re-wiring layer 112 can be arranged near the circuit structure that generates more heat inside the first wafer layer 111, so that the first re-wiring layer 112 is in contact with the circuit structure to achieve timely heat dissipation of the circuit structure, and then achieve rapid heat dissipation of the entire first wafer layer 111. In this way, the distance between the first re-wiring layer 112 and the main heat generating part inside the first wafer layer 111 can be shortened, so that the main heat generating part inside the first wafer layer 111 can be precisely and quickly heat-dissipated, thereby improving the heat dissipation performance and reliability of the first wafer layer 111.

[0085] In some examples, the first wafer layer 111 can have a multi-layer circuit structure inside, and the first re-wiring layer 112 can be prepared in the process of preparing the multi-layer circuit structure of the first wafer layer 111, so that the first re-wiring layer 112 is arranged inside the first wafer layer 111, thereby improving the heat dissipation capacity, simplifying the preparation process, and reducing the preparation cost. For example, the first re-wiring layer 112 can be arranged near the circuit structure that generates more heat inside the first wafer layer 111, so that the first re-wiring layer 112 is in contact with the circuit structure to achieve timely heat dissipation of the circuit structure, and then achieve rapid heat dissipation of the entire first wafer layer 111. In this way, the distance between the first re-wiring layer 112 and the main heat generating part inside the first wafer layer 111 can be shortened, so that the main heat generating part inside the first wafer layer 111 can be precisely and quickly heat-dissipated, thereby improving the heat dissipation performance and reliability of the first wafer layer 111.

[0086] Figure 6 Some embodiments of the present disclosure provide another structure diagram of a semiconductor structure 100.

[0087] Please refer to Figure 5 and Figure 6 In some examples, the first wafer layer 111 can have a multi-layer circuit structure inside, and the first re-wiring layer 112 can be prepared in the process of preparing the multi-layer circuit structure of the first wafer layer 111, so that the first re-wiring layer 112 is arranged inside the first wafer layer 111, thereby improving the heat dissipation capacity, simplifying the preparation process, and reducing the preparation cost. For example, the first re-wiring layer 112 can be arranged near the circuit structure that generates more heat inside the first wafer layer 111, so that the first re-wiring layer 112 is in contact with the circuit structure to achieve timely heat dissipation of the circuit structure, and then achieve rapid heat dissipation of the entire first wafer layer 111. In this way, the distance between the first re-wiring layer 112 and the main heat generating part inside the first wafer layer 111 can be shortened, so that the main heat generating part inside the first wafer layer 111 can be precisely and quickly heat-dissipated, thereby improving the heat dissipation performance and reliability of the first wafer layer 111.

[0088] As a feasible implementation, the first conductive column 114 and the second conductive column 115 can include any one or more of a through silicon contact (TSC) and a through silicon via. The material of the first conductive column 114 and the second conductive column 115 can be a conductive material such as copper or silver that has good heat conduction properties. In other examples, the material of the first conductive column 114 and the second conductive column 115 can also be any other suitable conductive material.

[0089] In addition, in terms of shape, the first conductive column 114 and the second conductive column 115 can have any suitable columnar structure such as a cylindrical shape, a circular truncated cone shape, a prismatic shape, and the like, and the present disclosure is not limited in this regard. In terms of quantity, the first conductive column 114 and the second conductive column 115 can be one or more in number. In addition, the first conductive column 114 and the second conductive column 115 can be identical conductive columns or different conductive columns.

[0090] In the present embodiment, the first conductive column 114 and the second conductive column 115 can extend along the first direction Z and pass through the first wafer layer 111. By providing the first conductive column 114 and the second conductive column 115 in the first device layer 110, heat generated by the first device layer 110 in the vertical direction (i.e., the first direction Z) can be transferred.

[0091] For example, since the first wafer layer 111 can have a multi-layer circuit structure inside, by providing the first conductive column 114 and the second conductive column 115, heat transfer in the vertical direction (i.e., the first direction Z) of the multi-layer circuit structure can be achieved. That is, heat generated by each layer of circuit structure inside the first wafer layer 111 can be transmitted to both ends of the first conductive column 114 and the second conductive column 115 via the first conductive column 114 and the second conductive column 115, and after being transmitted to both ends, the heat can be dissipated using the first redistribution layer 112 connected to both ends, or the heat can be dissipated directly using both ends of the first conductive column 114 and the second conductive column 115. In this way, heat inside the first wafer layer 111 can be conducted to the outside more quickly, thereby improving the heat dissipation rate of the first wafer layer 111 and even the semiconductor structure 100, and further improving the electrical performance and reliability of the semiconductor structure 100.

[0092] In addition, in the embodiment, the first conductive column 114 and the second conductive column 115 can have electrical performance in addition to the heat conduction performance, that is, the first conductive column 114 or the second conductive column 115 can be connected with the circuit structure in the first wafer layer 111 to realize the transmission of electrical signals. For example, by electrically connecting the first conductive column 114 with the transistor 300 in the first wafer layer 111, the first conductive column 114 can be used to provide electrical signals for the operation of the transistor 300 in the first wafer layer 111, so as to realize the control of the storage structure inside the first wafer layer 111, and further realize the write, read or erase operation of the storage structure inside the first wafer layer 111.

[0093] For further reference, please see Figure 4 In some embodiments, the first rewiring layer 112 further includes a second heat conduction line 1122, one end of the second heat conduction line 1122 being connected with the second conductive column 115.

[0094] In the embodiment, by connecting the second conductive column 115 with the second heat conduction line 1122 of the first rewiring layer 112, the heat transmitted by the second conductive column 115 in the longitudinal direction (that is, the first direction Z) can be transmitted to the second heat conduction line 1122, so as to realize the dissipation of the heat to the outside through the second heat conduction line 1122, thereby improving the rate of heat dissipation to the outside.

[0095] For example, the number of the second heat conduction line 1122 can be one or more, and the present disclosure does not limit the number.

[0096] As a feasible implementation manner, in the case where the first rewiring layer 112 is arranged on the first surface 1111 or the second surface 1112, the second conductive column 115 is connected with the second heat conduction line 1122, and the structure feature of the second heat conduction line 1122 exposed outside the first wafer layer 111 can be used to realize the rapid dissipation of the heat conducted by the second conductive column 115, thereby improving the heat dissipation efficiency and further improving the heat dissipation performance of the first wafer layer 111.

[0097] In another feasible implementation, where the first redistribution layer 112 is located within the first wafer layer 111, the second conductive post 115 is connected to the second heat-conducting wire 1122. The second conductive post 115 can be used to transfer the heat conducted by the second heat-conducting wire 1122 longitudinally and dissipate it outwards. Furthermore, in this scenario, the first redistribution layer 112, where the second heat-conducting wire 1122 is located, can also utilize its structural features to dissipate heat laterally (i.e., in any direction perpendicular to the first direction Z). With this configuration, the second conductive post 115 and the second heat-conducting wire 1122 can form a heat dissipation network for the first wafer layer 111 in both the longitudinal and lateral directions, thereby enabling rapid heat dissipation and improving the efficiency of heat dissipation for the first wafer layer 111.

[0098] Figure 7 This is a schematic diagram of another semiconductor structure 100 provided in some embodiments of the present disclosure.

[0099] like Figure 7 As shown, in some embodiments, the semiconductor structure 100 further includes a second device layer 120, wherein the first device layer 110 and the second device layer 120 are stacked. The second device layer 120 includes a second wafer layer 121 and a second thermally conductive wall 122, wherein the second wafer layer 121 is stacked with the first wafer layer 111, wherein the second wafer layer 121 has a third surface 1211 and a fourth surface 1212 disposed opposite each other in a first direction Z, the second thermally conductive wall 122 covers at least one surface of the second wafer layer 121 adjacent to the third surface 1211, and the second thermally conductive wall 122 is connected to the first thermally conductive wall 113.

[0100] In this embodiment, at least one surface of the second wafer layer 121 adjacent to the third surface 1211 is covered with a second heat-conducting wall 122. In some examples, the second wafer layer 121 is described as having a cuboid shape. The second wafer layer 121 has an upper surface (third surface 1211) and a lower surface (third surface 1211) disposed opposite each other in a first direction Z. The second heat-conducting wall 122 can cover at least one side surface other than the upper and lower surfaces. Exemplarily, the number of side surfaces that the second heat-conducting wall 122 can cover can be 1, 2, 3, or 4. The second heat-conducting wall 122 can partially or completely cover each side surface, and this disclosure does not impose specific limitations on this.

[0101] For example, the material of the second heat-conducting wall 122 can be a metal material with high thermal conductivity, such as copper or silver, or other materials with high thermal conductivity. This disclosure does not limit the material used in this embodiment.

[0102] In this way, the high thermal conductivity of the second thermal conductive wall 122 can be utilized to transfer the heat generated by the second wafer layer 121 to the second thermal conductive wall 122, and the heat can be quickly dissipated via the second thermal conductive wall 122, so that the second wafer layer 121 can be quickly cooled, and the heat dissipation performance of the second wafer layer 121 and the entire semiconductor structure 100 can be improved.

[0103] Figure 8 Another top view of the semiconductor structure 100 provided by some embodiments of the present disclosure.

[0104] Referring to Figure 7 and Figure 8 In some embodiments, the second device layer 120 further includes a second redistribution layer 123. The second redistribution layer 123 is arranged in the second wafer layer 121, or the second redistribution layer 123 is arranged on the third surface 1211 or the fourth surface 1212. The second redistribution layer 123 includes a third thermal conductive line 1231, one end of the third thermal conductive line 1231 being connected to the second thermal conductive wall 122.

[0105] By arranging the second redistribution layer 123 in contact with the second wafer layer 121, the heat generated by the second wafer layer 121 can be quickly conducted to the outside, wherein the second redistribution layer 123 includes the third thermal conductive line 1231 having high thermal conductivity. For example, the second wafer layer 121 can include multiple layers of circuit traces and electronic components, and a large amount of heat will be generated during the operation of the second wafer layer 121. By arranging the third thermal conductive line 1231, the heat generated by the second wafer layer 121 can be transferred to the third thermal conductive line 1231, and then dissipated to the outside via the third thermal conductive line 1231, so that the heat dissipation of the second wafer layer 121 can be achieved.

[0106] For example, the second wafer layer 121 can be a whole wafer structure or a partial wafer structure (for example, a semiconductor memory chip) obtained by cutting the whole wafer structure, and thus the shape of the second wafer layer 121 can be a cylindrical shape, a cubic shape, or any other suitable shape. The shape of the second wafer layer 121 can be the same as that of the first wafer layer 111, so that the stacked semiconductor structure 100 can be obtained by stacking the first wafer layer 111 and the second wafer layer 121.

[0107] For example, the number of the third thermal conductive lines 1231 in the second redistribution layer 123 can be one or more, and the multiple third thermal conductive lines 1231 can be connected to each other or independent of each other. In addition, the extension directions of the multiple third thermal conductive lines 1231 can be the same or different. Figure 7For illustrative purposes only, the actual device structure may not necessarily be reflected, and in actual applications, the layout of the plurality of third heat-conducting lines 1231 can also be other layout forms.

[0108] In some examples, the material of the third heat-conducting line 1231 can be a metal material with high thermal conductivity such as copper, silver, etc. In other examples, the material of the third heat-conducting line 1231 can also be other materials with high thermal conductivity, and the embodiments of the present disclosure do not limit this.

[0109] In this way, since the side surface of the second wafer layer 121 is covered with the second heat-conducting wall 122, by connecting the third heat-conducting line 1231 with the second heat-conducting wall 122, the heat conducted by the third heat-conducting line 1231 can be dissipated by using the large heat dissipation surface of the second heat-conducting wall 122, thereby further improving the heat dissipation capability of the second wafer layer 121, and further improving the electrical performance and reliability of the semiconductor structure 100.

[0110] In addition, in the present embodiment, the second redistribution layer 123 can be arranged at different positions of the second wafer layer 121, thereby realizing the adaptation to the second wafer layer 121 in different application scenarios.

[0111] In some examples, for the second wafer layer 121 that has been prepared, the second redistribution layer 123 can be arranged on the third surface 1211 or the fourth surface 1212 of the second wafer layer 121, thereby realizing the heat dissipation treatment of the second wafer layer 121, and further improving the heat dissipation capability of the second wafer layer 121. For example, the second redistribution layer 123 can be arranged only on the third surface 1211 of the second wafer layer 121, or arranged only on the fourth surface 1212 of the second wafer layer 121, or arranged on both the third surface 1211 and the fourth surface 1212 of the second wafer layer 121, thereby improving the flexibility of the layout of the second redistribution layer 123, and further improving the universality of the second redistribution layer 123 in different application scenarios.

[0112] In some examples, the second wafer layer 121 can have a multi-layer circuit structure inside. In this case, the second redistribution layer 123 can be prepared during the preparation of the multi-layer circuit structure of the second wafer layer 121, so that the second redistribution layer 123 is arranged inside the second wafer layer 121. In this way, the heat dissipation capacity is improved, the preparation process is simplified, and the preparation cost is reduced. For example, the second redistribution layer 123 can be arranged near the circuit structure that generates more heat inside the second wafer layer 121. In this way, the second redistribution layer 123 can be in contact with the circuit structure, so as to dissipate heat from the circuit structure in time, and then dissipate heat from the entire second wafer layer 121. In this way, the distance between the second redistribution layer 123 and the main heat generating part inside the second wafer layer 121 can be shortened, so as to accurately and quickly dissipate heat from the heat generating part inside the second wafer layer 121, thereby improving the heat dissipation performance and reliability of the second wafer layer 121.

[0113] Please continue to participate Figure 7 In some examples, the second device layer 120 can be provided with a third conductive column 124 and a fourth conductive column 125. The third conductive column 124 and the fourth conductive column 125 are arranged at intervals, and the third conductive column 124 and the fourth conductive column 125 both penetrate the second wafer layer 121 and are connected with the second redistribution layer 123. The third conductive column 124 is used to connect with the transistor 300 in the second wafer layer 121.

[0114] As a feasible implementation manner, the third conductive column 124 and the fourth conductive column 125 can include any one or more of a through-silicon contact and a through-silicon via. The material of the third conductive column 124 and the fourth conductive column 125 can be copper, silver or other conductive materials with good heat dissipation properties. In other implementation manners, the material of the third conductive column 124 and the fourth conductive column 125 can also be any other suitable conductive material. In addition, in terms of shape, the third conductive column 124 and the fourth conductive column 125 can have any suitable columnar structure such as a cylindrical shape, a circular truncated cone shape, a prismatic shape, and the like. The number of the third conductive column 124 and the fourth conductive column 125 can be one or more. In addition, the third conductive column 124 and the fourth conductive column 125 can be the same conductive column or different conductive columns.

[0115] In this embodiment, the third conductive column 124 and the fourth conductive column 125 can extend along the first direction Z and penetrate the second wafer layer 121. By arranging the third conductive column 124 and the fourth conductive column 125 in the second device layer 120, heat generated by the second device layer 120 can be transferred in the vertical direction (i.e., the first direction Z).

[0116] Exemplarily, since the second wafer layer 121 can have a multi-layer circuit structure inside, by arranging the third conductive column 124 and the fourth conductive column 125, the connection of the multi-layer circuit structure in the longitudinal direction (i.e. the first direction Z) can be realized, so as to realize the heat generated by each layer of the circuit structure inside the second wafer layer 121 to be transmitted to both ends of the third conductive column 124 and the fourth conductive column 125, and after being transmitted to both ends of the third conductive column 124 and the fourth conductive column 125, the heat is dissipated by using the second redistribution layer 123 connected to both ends thereof, or the heat is directly dissipated at both ends of the third conductive column 124 and the fourth conductive column 125. By such an arrangement, the heat dissipation performance of the second device layer 120 and even the semiconductor structure 100 can be improved, and the electrical performance and reliability of the semiconductor structure 100 can be improved.

[0117] In addition, in the embodiment, the third conductive column 124 and the fourth conductive column 125 can have electrical performance in addition to the heat dissipation performance, i.e. the third conductive column 124 and the fourth conductive column 125 can be connected with the circuit structure inside the second wafer layer 121 to realize the transmission of electrical signals. Exemplarily, by electrically connecting the third conductive column 124 with the transistor 300 in the second wafer layer 121, the third conductive column 124 can be used to provide electrical signals for the operation of the transistor 300 in the second wafer layer 121, so as to realize the control of the storage structure inside the second wafer layer 121, and further realize the write, read or erase operation of the data by the storage structure inside the second wafer layer 121.

[0118] Please continue to refer to Figure 8 In some embodiments, the second redistribution layer 123 further includes a fourth heat conduction line 1232, one end of the fourth heat conduction line 1232 being connected with the fourth conductive column 125.

[0119] In the embodiment, by connecting the fourth conductive column 125 with the fourth heat conduction line 1232 of the second redistribution layer 123, the heat transmitted by the fourth conductive column 125 in the longitudinal direction (i.e. the first direction Z) can be transmitted to the fourth heat conduction line 1232, so as to realize the dissipation of the heat to the outside through the fourth heat conduction line 1232, thereby improving the rate of heat dissipation to the outside.

[0120] Exemplarily, the number of the fourth heat conduction line 1232 can be one or more, and the extension directions of the multiple fourth heat conduction lines 1232 can be the same or different, which is not limited in the present disclosure.

[0121] As a feasible implementation, in the case where the second redistribution layer 123 is arranged on the third surface 1211 or the fourth surface 1212, the fourth conductive column 125 is connected with the fourth heat conduction line 1232, and the fourth heat conduction line 1232 can be used to expose the structure feature outside the second wafer layer 121, so as to realize rapid dissipation of the heat conducted by the fourth conductive column 125, thereby improving the heat dissipation efficiency and further improving the heat dissipation performance of the second wafer layer 121.

[0122] In another feasible implementation, in the case where the second redistribution layer 123 is arranged in the second wafer layer 121, the fourth conductive column 125 is connected with the fourth heat conduction line 1232, and the fourth conductive column 125 can be used to realize longitudinal transmission and outward dissipation of the heat conducted by the fourth heat conduction line 1232. In addition, in this case, the second redistribution layer 123 where the fourth heat conduction line 1232 is arranged can also use its own structure feature to realize dissipation of heat in the transverse direction (that is, any direction perpendicular to the first direction Z). In this way, the fourth conductive column 125 and the fourth heat conduction line 1232 can form a heat dissipation network of the second wafer layer 121 in the longitudinal direction and the transverse direction, so as to realize timely dissipation of heat and further improve the heat dissipation efficiency of the second wafer layer 121.

[0123] Figure 9 Another structural schematic diagram of a semiconductor structure 100 provided by some embodiments of the present disclosure is shown.

[0124] As shown in Figure 9 illustrated, the number of the second device layers 120 can be one or more, and the multiple second device layers 120 can be arranged in a stacked manner, so as to jointly form the stacked semiconductor structure 100 with the first device layer 110. In this embodiment, by increasing the number of the second device layers 120, the storage capacity of the semiconductor structure 100 can be increased, so as to meet the storage demand of a larger capacity.

[0125] For example, the circuit structure and the heat dissipation network inside the multiple second device layers 120 can be completely the same, and therefore, the specific structure of the multiple second device layers 120 will not be described here.

[0126] Figure 10 Another structural schematic diagram of a semiconductor structure 100 provided by some embodiments of the present disclosure is shown, Figure 11 Another top view of a semiconductor structure 100 provided by some embodiments of the present disclosure is shown.

[0127] As shown in Figure 10 and Figure 11As shown, in some embodiments, the semiconductor structure 100 further comprises: a heat-conductive filling part 130. The second device layer 120 is arranged in the same layer as the first device layer 110, and the heat-conductive filling part 130 is filled between the first device layer 110 and the second device layer 120.

[0128] In some examples, by arranging the heat-conductive filling part 130, the first device layer 110 and the second device layer 120 arranged in the same layer can be isolated, and the heat generated by the first device layer 110 and the second device layer 120 can be timely conducted to the outside, so as to improve the heat dissipation rate. The heat-conductive filling part 130 has a relatively high thermal conductivity, for example, the thermal conductivity of the heat-conductive filling part 130 is greater than that of the oxide, and therefore, the heat conduction capacity of the heat-conductive filling part 130 is higher than that of the oxide.

[0129] For example, the material of the heat-conductive filling part 130 can be a polymer material such as polyaniline or polyacetylene having a high thermal conductivity, or any other material having a high thermal conductivity, which is not limited in the present disclosure.

[0130] In this way, the heat dissipation capacity of the layered structure in which the first device layer 110 and the second device layer 120 are arranged can be improved, and the heat dissipation capacity of the entire semiconductor structure 100 can be improved, so as to ensure that the semiconductor structure 100 has good electrical performance and reliability.

[0131] Please continue to refer to Figure 10 and Figure 11 In some embodiments, the semiconductor structure 100 further comprises: a heat-conductive layer 140. The heat-conductive layer 140 is arranged in a stacked manner on the first device layer 110 and the second device layer 120, and the heat-conductive layer 140 is in contact with the heat-conductive filling part 130.

[0132] In the present embodiment, by arranging the heat-conductive layer 140 in a stacked manner in the first direction Z, the heat generated by the first device layer 110 and the second device layer 120 can be timely conducted to the heat-conductive layer 140, and the heat can be dissipated to the outside via the heat-conductive layer 140, so as to improve the heat dissipation capacity of the first device layer 110 and the second device layer 120. In addition, by being in contact with the heat-conductive filling part 130, the heat-conductive layer 140 can utilize the large heat dissipation surface thereof to timely dissipate the heat transferred by the heat-conductive filling part 130, so as to further improve the heat dissipation efficiency.

[0133] The heat conduction layer 140 has a higher heat conduction capacity. For example, the heat conduction coefficient of the heat conduction layer 140 is greater than the heat conduction coefficient of the oxide, and thus the heat conduction capacity of the heat conduction layer 140 is higher than the heat conduction capacity of the oxide. For example, the material of the heat conduction layer 140 can be polyaniline, polyacetylene, or other polymer materials with a higher heat conduction rate, and the present disclosure is not limited in this regard.

[0134] In some examples, the material of the heat conduction layer 140 can be the same as or different from the material of the heat conduction filling portion 130. As a feasible implementation, in the case where the material of the heat conduction layer 140 is the same as the material of the heat conduction filling portion 130, the heat conduction layer 140 and the heat conduction filling portion 130 can be prepared in the same preparation process, thereby simplifying the preparation process of the semiconductor structure 100 and improving the preparation efficiency of the semiconductor structure 100. In this case, the heat conduction layer 140 and the heat conduction filling portion 130 can be an integrated structure, that is, there is no obvious boundary between the heat conduction layer 140 and the heat conduction filling portion 130 in structure.

[0135] Based on the semiconductor structure 100 provided by some of the above embodiments, the present disclosure further provides a preparation method of the semiconductor structure 100.

[0136] Figure 12 A flowchart of a preparation method of a semiconductor structure 100 according to some embodiments of the present disclosure.

[0137] As shown in Figure 12 In some embodiments, the preparation method of the semiconductor structure 100 includes the following steps S1-S3.

[0138] S1, forming a first wafer layer, the first wafer layer oppositely has a first surface and a second surface in a first direction, and the first direction is perpendicular to the extension direction of the first wafer layer.

[0139] As shown in Figure 3 In this step S1, the first wafer layer 111 can have multiple layers of circuit traces or electronic components inside.

[0140] In actual applications, the first wafer layer 111 can be a semiconductor memory chip obtained by cutting a whole wafer, and the first wafer layer 111 can implement reading, writing, or erasing operations on data.

[0141] S2, forming a first redistribution layer, the first redistribution layer is parallel to the first wafer layer and in contact with the first wafer layer, and the first redistribution layer includes a first heat conduction line.

[0142] In this step S2, the material of the first heat conduction line 1121 can be a metal material with a high thermal conductivity such as copper or silver; in some other examples, the material of the first heat conduction line 1121 can also be any other material with a high thermal conductivity, and the embodiments of the present disclosure do not limit this.

[0143] Exemplarily, the first redistribution layer 112 can be fabricated in the same process as the first wafer layer 111. Alternatively, the first redistribution layer 112 can also be fabricated in different processes from the first wafer layer 111.

[0144] In some examples, in the scenario where the first redistribution layer 112 and the first wafer layer 111 are fabricated in the same process, the first redistribution layer 112 can be formed inside the first wafer layer 111, thereby obtaining a structure as shown in Figure 5 Figure [not provided]. With such a setting, the first redistribution layer 112 can be used to dissipate heat from the main heat - generating parts inside the first wafer layer 111, thereby achieving timely heat dissipation for the entire first wafer layer 111. Among them, the fabrication process of the first redistribution layer 112 in this scenario will be introduced in detail later and will not be elaborated here.

[0145] In some other examples, in the scenario where the first redistribution layer 112 and the first wafer layer 111 are fabricated in different processes, the first redistribution layer 112 can be formed on the first surface 1111 or the second surface 1112 of the first wafer layer 111, thereby obtaining a structure as shown in Figure 3 Figure [not provided]. With such a setting, the first redistribution layer 112 can quickly conduct the heat generated by the first wafer layer 111 to the outside, thereby improving the heat - dissipation ability of the first wafer layer 111, and further improving the electrical performance and reliability of the first wafer layer 111. Among them, the fabrication process of the first redistribution layer 112 in this scenario will also be introduced in detail later and will not be elaborated here.

[0146] S3. Form a first heat - conducting wall on at least one surface of the first wafer layer adjacent to the first surface, and the first heat - conducting wall is connected to one end of the first heat - conduction line. Among them, the first wafer layer, the first redistribution layer, and the first heat - conducting wall constitute the first device layer.

[0147] The material of the first heat - conducting wall 113 can be a metal material with a high thermal conductivity such as copper or silver, or other materials with a high thermal conductivity. The embodiments of the present disclosure do not limit this.

[0148] In this step S3, by forming the first heat - conducting wall on the outside of the first wafer layer 111, a structure as shown in Figure 3 or Figure 5The first wafer layer 111 can be arranged on the substrate 200. The first wafer layer 111 can be arranged on the substrate 200 in a manner shown in the structure. In this way, the heat generated by the first wafer layer 111 can be dissipated in time, thereby improving the heat dissipation performance of the first wafer layer 111 and even the semiconductor structure 100. The first heat-conducting wall 113 is connected to one end of the first heat-conducting line 1121. In this way, the heat on the first heat-conducting line 1121 can be conducted to the first heat-conducting wall 113, and then rapidly dissipated by the first heat-conducting wall 113. Since the first heat-conducting wall 113 has a large heat dissipation surface, the connection can improve the efficiency of heat dissipation on the first heat-conducting line 1121, thereby improving the heat dissipation efficiency of the first wafer layer 111.

[0149] In the embodiment, the first redistribution layer 112 and the first heat-conducting wall 113 can form a good heat dissipation network. By preparing the above heat dissipation network on the first wafer layer 111 of the semiconductor structure 100, the heat generated by the semiconductor structure 100 can be dissipated in time, thereby improving the heat dissipation performance of the semiconductor structure 100, and further improving the electrical performance and reliability of the semiconductor structure 100.

[0150] Figure 13 A flowchart of a method for preparing a semiconductor structure according to some embodiments of the present disclosure is provided. Figure 14 A structure diagram of a semiconductor structure 100 after forming a first wafer layer 111 and a first redistribution layer 112 in a method for preparing the semiconductor structure 100 according to some embodiments of the present disclosure is provided.

[0151] In some embodiments, the first wafer layer 111 and the first redistribution layer 112 are formed in the same process. As shown in the structure, Figure 13 In the method for preparing the semiconductor structure 100, forming the first wafer layer 111 and forming the first redistribution layer 112 include the following steps S11-S13.

[0152] S11, forming a first film layer.

[0153] For example, in actual applications, the preparation of the first wafer layer 111 needs to be based on the substrate 200, so as to provide support for the first wafer layer 111 by the substrate 200, thereby improving the firmness and reliability of the first wafer layer 111. In some examples, the first wafer layer 111 obtained after preparation can be removed according to actual needs, or the substrate 200 on one side of the first wafer layer 111 can be retained in the subsequent preparation process of the semiconductor structure 100.

[0154] As a feasible implementation manner, the removal of the substrate 200 on one side of the first wafer layer 111 can be realized by a chemical mechanical polishing (CMP) process.

[0155] Therefore, as Figure 14 shown, before forming the first film layer 150, a substrate 200 needs to be provided in advance. Herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate 200 itself can be patterned. The materials added on the substrate 200 can be patterned or can remain unpatterned. In addition, the substrate 200 can include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate 200 can be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0156] In this step S11, after performing an appropriate cleaning operation on the substrate 200, an oxidation operation is performed on one side of the substrate 200 to form an oxide film. Exemplarily, the ways of the oxidation operation can be classified into thermal oxidation, electrochemical anodic oxidation, plasma enhanced chemical vapor deposition (PECVD), etc. A protective film is formed on the surface of the substrate 200 through the oxidation operation to protect the subsequent preparation processes from chemical impurities, prevent ion diffusion during the subsequent ion implantation process, and prevent problems such as slippage during the subsequent etching process.

[0157] After the oxidation operation is completed, a photoresist is applied on the side of the oxide film away from the substrate 200 to form a photoresist pattern, and then the oxide film is etched using the photoresist pattern to form a semiconductor circuit diagram. The oxide film is doped according to the semiconductor circuit diagram by means of ion implantation or thermal diffusion, etc., so as to form a doped region for the subsequent preparation of transistors. In addition, after the foregoing operations are completed, multiple film-forming operations need to be continued on this basis. Exemplarily, the foregoing film-forming operations can include depositing a film of molecular or atomic units required for preparation, and performing operations such as photolithography, etching, and cleaning on the film, so as to achieve isolation, connection, and protection between single-layer or multi-layer semiconductor circuits. The processes adopted in the deposition process can include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc. <E

[0158] Thus, this step S11 completes the preparation of the first film layer 150.

[0159] S12. Form a first re-wiring layer by laminating on the first film layer.

[0160] Please continue to refer to Figure 14In this step S12, the first re-wiring layer 112 is formed on the side of the first film layer 150 away from the substrate 200, so that the heat generated by the first film layer 150 can be timely transferred to the first re-wiring layer 112, and then dissipated to the outside through the first re-wiring layer 112, thereby achieving heat dissipation treatment of the first film layer 150.

[0161] In this way, since the first re-wiring layer 112 has the first heat-conducting lines with high thermal conductivity, the first re-wiring layer 112 can improve the heat dissipation efficiency of the first film layer 150, and further improve the heat dissipation performance and reliability of the first film layer 150.

[0162] S13, a second film layer is formed on the first re-wiring layer, and the first film layer and the second film layer constitute a first wafer layer.

[0163] Please continue to refer to Figure 14 In this step S13, the second film layer 220 is formed on the side of the first re-wiring layer 112 away from the first film layer 150, so as to complete the preparation of the first wafer layer 111, and the first re-wiring layer 112 is prepared in the inside of the first wafer layer 111.

[0164] In some examples, the thickness of the first film layer 150 and the second film layer 220 in the first direction Z can be the same or different. For example, the thickness of the first film layer 150 and the second film layer 220 in the first direction Z can be determined according to the film layer position of the main heat generating part in the first wafer layer 111, so that the first re-wiring layer 112 can be in contact with the main heat generating part in the first wafer layer 111, and the first re-wiring layer 112 can timely dissipate heat from the main heat generating part in the first wafer layer 111, thereby timely dissipating heat from the first wafer layer 111, avoiding the problem that the electrical performance of the first wafer layer 111 is reduced or even fails or is damaged due to the delayed heat dissipation.

[0165] Figure 15 The flowchart of the preparation method of the first re-wiring layer 112 in the semiconductor structure preparation method provided by some embodiments of the present disclosure is shown in Figure 16 The structure schematic diagram of the semiconductor structure preparation method provided by some embodiments of the present disclosure after forming the first re-wiring layer is shown in

[0166] As Figure 15 shown, the above step S12 further includes the following steps S121-S123.

[0167] S121, a first insulating layer is formed on one side of the first film layer.

[0168] As Figure 16As shown in the figure, in this step S121, an insulating material can be deposited on the side surface of the first film layer 150 away from the substrate 200 by CVD, PVD, ALD or any thin film deposition process, so as to form a first insulating layer 160.

[0169] For example, the insulating material can include but is not limited to one or more of oxide materials (such as silicon oxide), nitride materials (such as silicon nitride), and oxynitride materials (such as silicon oxynitride).

[0170] S122, forming a first strip-shaped groove on the first insulating layer.

[0171] Please continue to refer to Figure 16 In this step S122, a photoresist layer is formed on the side of the first insulating layer 160 away from the first film layer 150, and the photoresist layer is patterned to obtain a first mask layer with multiple openings. The side surface of the first insulating layer 160 away from the first film layer 150 is etched based on the first mask layer to form multiple first strip-shaped grooves 161.

[0172] For example, the side surface of the first insulating layer 160 away from the first film layer 150 can be etched by dry etching to obtain the first strip-shaped groove 161. The number of first strip-shaped grooves 161 can be one or more, and the extension direction of the multiple first strip-shaped grooves 161 can be the same or different.

[0173] For example, the side surface of the first insulating layer 160 away from the first film layer 150 can be etched by dry etching to obtain the first strip-shaped groove 161. The number of first strip-shaped grooves 161 can be one or more, and the extension direction of the multiple first strip-shaped grooves 161 can be the same or different. Figure 16 For illustrative purposes only, the actual device structure can not necessarily be reflected, and in actual applications, the layout of the multiple first strip-shaped grooves 161 can also be other layout forms.

[0174] S123, forming a first heat-conducting line in the first strip-shaped groove.

[0175] In this step S123, a heat-conducting material is deposited in the first strip-shaped groove 161 to form a first heat-conducting line 1121 as shown in the figure. Figure 4 The first heat-conducting line 1121 and the first insulating layer 160 can constitute a first redistribution layer 112.

[0176] For example, the heat-conducting material can be a metal material such as copper or silver with high thermal conductivity, or other materials with high thermal conductivity. The filling of the heat-conducting material can be performed by CVD, PVD, ALD or any thin film deposition process.

[0177] In this embodiment, by forming the first heavy wiring layer 112 on one side of the first film layer 150, the heat generated by the first film layer 150 can be promptly transmitted to the first heavy wiring layer 112, and then dissipated to the outside through the first heat-conducting lines 1121 of the first heavy wiring layer 112, thereby improving the heat dissipation efficiency of the first film layer 150. The number of the first heat-conducting lines 1121 can be one or more, and the extension directions of the multiple first heat-conducting lines 1121 can be the same or different.

[0178] In addition, after the first film layer 150 and other film layer structures are continuously prepared to complete the preparation of the first wafer layer 111, the first heavy wiring layer 112 will exist inside the first wafer layer 111. In this way, the heat of the film layer structures on both sides of the first heavy wiring layer 112 can be simultaneously conducted and promptly dissipated to the outside, thereby improving the heat dissipation capability of the film layer structures on both sides and further improving the heat dissipation performance and reliability of the entire first wafer layer 111.

[0179] In the actual application, the first heavy wiring layer 112 can be arranged close to the main heat generating part inside the first wafer layer 111, because the first film layer 150 and other film layer structures prepared subsequently are provided with various circuit traces or electronic components. In this way, by shortening the distance between the first heavy wiring layer 112 and the main heat generating part inside the first wafer layer 111, precise and rapid heat dissipation treatment of the main heat generating part inside the first wafer layer 111 can be achieved, thereby improving the electrical performance and reliability of the first wafer layer 111.

[0180] Figure 17 The flowchart of another method for forming the first heavy wiring layer 112 in the semiconductor structure preparation method provided by some embodiments of the present disclosure is shown in Figure 18 The structure schematic diagram of the semiconductor structure preparation method provided by some embodiments of the present disclosure after forming the first heavy wiring layer 112 is shown in

[0181] As shown in Figure 17 In some embodiments, when the first heavy wiring layer 112 is formed on the first surface 1111 or the second surface 1112 of the first wafer layer 111, the above step S2 further includes the following steps S21-S23.

[0182] S21, forming a second insulating layer on the first surface or the second surface.

[0183] As shown in Figure 18 In this step S21, an insulating material can be deposited on the first surface 1111 or the second surface 1112 of the first wafer layer 111 by using CVD, PVD, ALD or any thin film deposition process, so as to form the second insulating layer 170.

[0184] Exemplarily, the insulating material includes one or more of an oxide material (e.g., silicon oxide), a nitride material (e.g., silicon nitride), and an oxynitride material (e.g., silicon oxynitride).

[0185] S22. Forming a second strip-shaped groove on the second insulating layer.

[0186] Please continue to refer to Figure 18 In this step S22, a photoresist layer is formed on the side of the second insulating layer 170 away from the first surface 1111 or the second surface 1112, and the photoresist layer is patterned to obtain a second mask layer having a plurality of openings. The surface of the second insulating layer 170 away from the first surface 1111 or the second surface 1112 is etched based on the second mask layer to form a second strip-shaped groove 171. The number of the second strip-shaped groove 171 can be one or more, and the extension directions of the plurality of second strip-shaped grooves 171 can be the same or different.

[0187] Exemplarily, the side surface of the second insulating layer 170 away from the first surface 1111 or the second surface 1112 can be etched by a dry etching method to obtain the second strip-shaped groove 171.

[0188] S23. Forming a first heat-conducting line in the second strip-shaped groove to form a first redistribution layer.

[0189] In this step S23, a heat-conducting material is deposited in the second strip-shaped groove 171 to form a first heat-conducting line 1121 as shown in Figure 4 . The first heat-conducting line 1121 and the second insulating layer 170 can constitute a first redistribution layer 112.

[0190] Exemplarily, the heat-conducting material can be a metal material such as copper or silver having a high thermal conductivity, or other materials having a high thermal conductivity. The filling of the heat-conducting material can be performed by CVD, PVD, ALD, or any thin film deposition process.

[0191] In this embodiment, by setting the first redistribution layer 112 in contact with the first wafer layer 111, the first heat-conducting wire 1121 in the first redistribution layer 112 can be used to dissipate heat from the first wafer layer 111. For example, the first wafer layer 111 can have multiple layers of circuit traces or electronic components inside. During the operation of the first wafer layer 111, the multiple layers of circuit traces or electronic components inside will generate a large amount of heat. By setting the first heat-conducting wire 1121, the heat generated by the first wafer layer 111 can be quickly transferred to the first heat-conducting wire 1121, and then quickly dissipated to the outside through the first heat-conducting wire 1121, thereby improving the heat dissipation rate of the first wafer layer 111, and further improving the electrical performance and reliability of the first wafer layer 111.

[0192] Figure 19 The flowchart of the preparation method of the first heat-conducting wall 113 in the semiconductor structure preparation method provided by some embodiments of the present disclosure is shown in Figure 20 The structure side view after forming the first heat-conducting wall 113 in the semiconductor structure preparation method provided by some embodiments of the present disclosure is shown in

[0193] As Figure 19 shown, in some embodiments, the above step S3 further includes steps S31-S33.

[0194] S31, forming a third insulating layer on at least one surface of the first wafer layer adjacent to the first surface.

[0195] As Figure 20 shown, in this step S31, CVD, PVD, ALD or any thin film deposition process can be used to deposit an insulating material on at least one surface of the first wafer layer 111 adjacent to the first surface 1111, thereby forming a third insulating layer 180.

[0196] For example, the insulating material includes but is not limited to one or more of oxide materials (such as silicon oxide), nitride materials (such as silicon nitride), and oxynitride materials (such as silicon oxynitride).

[0197] S32, forming a first opening on the third insulating layer, the first opening exposing one end of the first heat-conducting wire.

[0198] Please continue to refer to Figure 20 In this step S32, a photoresist layer is formed on the side surface of the third insulating layer 180 away from the first wafer layer 111, and the photoresist layer is patterned to obtain a third mask layer with multiple openings. Based on the third mask layer, the side surface of the third insulating layer 180 away from the first wafer layer 111 is etched to form a first opening 181.

[0199] Exemplarily, the third insulating layer 180 can be etched away from the side surface of the first wafer layer 111 by dry etching to obtain the first opening 181.

[0200] S33, forming a first heat-conductive wall in the first opening.

[0201] Please continue to refer to Figure 20 In this step S33, a heat-conductive material is deposited in the first opening 181 to form the first heat-conductive wall 113.

[0202] Exemplarily, the heat-conductive material can be a metal material with high thermal conductivity, such as copper or silver, or other materials with high thermal conductivity. The filling of the heat-conductive material can be performed by CVD, PVD, ALD or any thin film deposition process.

[0203] In this embodiment, by arranging the first heat-conductive wall 113 on the sidewall of the first wafer layer 111, the heat generated by the first wafer layer 111 can be transferred to the first heat-conductive wall 113 in time, and then dissipated to the outside through the first heat-conductive wall 113, so as to quickly dissipate the heat of the first wafer layer 111, thereby improving the heat dissipation rate of the first wafer layer 111 and even the semiconductor structure 100. Since the first heat-conductive wall 113 has a larger heat dissipation surface than the first heat-conductive line 1121, connecting the first heat-conductive wall 113 with one end of the first heat-conductive line 1121 can quickly dissipate the heat conducted by the first heat-conductive line 1121 through the first heat-conductive wall 113, thereby further improving the heat dissipation capability of the first wafer layer 111, and further improving the electrical performance and reliability of the first wafer layer 111 and even the whole semiconductor structure 100.

[0204] Figure 21 Another flowchart of a method for manufacturing a semiconductor structure 100 is provided for some embodiments of the present disclosure, Figure 22 Another structure diagram of a semiconductor structure 100 is provided for some embodiments of the present disclosure.

[0205] As Figure 21 shown, in some embodiments, the above manufacturing method further includes the following steps S4-S6.

[0206] S4, forming a first via hole and a second via hole on the first wafer layer, and the first via hole and the second via hole are arranged at intervals.

[0207] As Figure 22As shown, in this step S4, a photoresist layer is formed on the first surface 1111 or the second surface 1112 of the first wafer layer 111 in the stacking direction, and the photoresist layer is patterned to obtain a fourth mask layer with a plurality of openings. The first wafer layer 111 is etched based on the fourth mask layer to form the first through hole 190 and the second through hole 400 arranged at intervals.

[0208] The number of the first through hole 190 can be one or more, and the number of the second through hole 400 can also be one or more.

[0209] For example, the first wafer layer 111 can be etched by dry etching to obtain the first through hole 190 and the second through hole 400. The first through hole 190 and the second through hole 400 can extend along the first direction Z and penetrate the first wafer layer 111.

[0210] S5, forming a first conductive column in the first through hole, wherein the first conductive column is connected with the transistor in the first wafer layer.

[0211] In this step S5, a conductive material is deposited in the first through hole 190 to form a first conductive column 114, and a structure as shown in Figure 3 is obtained.

[0212] For example, the conductive material can be a metal material such as copper, aluminum, and silver, and can also be other suitable materials. The filling of the conductive material can use CVD, PVD, ALD or any thin film deposition process.

[0213] For example, the first through hole 190 obtained by etching the first wafer layer 111 by dry etching can expose the transistor in the first wafer layer 111, so that when the first conductive column 114 is formed based on the first through hole 190 subsequently, the connection between the first conductive column 114 and the transistor can be realized.

[0214] In this embodiment, by using the first conductive column 114 to electrically connect with the transistor in the first wafer layer 111, an electrical signal can be provided for the operation of the transistor in the first wafer layer 111, so as to realize the control of the storage structure inside the first wafer layer 111, and further realize the write, read or erase operation of the data by the storage structure inside the first wafer layer 111.

[0215] S6, forming a second conductive column in the second through hole, the first redistribution layer further comprising a second heat conduction line, and the second conductive column being connected with one end of the second heat conduction line.

[0216] In this step S6, a conductive material is deposited in the second through hole 400 to form a second conductive column 115, and a structure as shown in Figure 3 is obtained.

[0217] Exemplarily, the conductive material can be a metal material such as copper, aluminum, silver, and the like, and can also be other suitable materials. The filling of the conductive material can be performed by CVD, PVD, ALD or any thin film deposition process.

[0218] In this embodiment, since the first wafer layer 111 can have a multi-layer circuit structure inside, by arranging the first conductive column 114 and the second conductive column 115, the connection of the multi-layer circuit structure in the vertical direction (i.e. the first direction Z) can be realized, so as to realize the heat generated by each layer of the circuit structure in the first wafer layer 111 to be transmitted outwardly via the first conductive column 114 and the second conductive column 115, and after being transmitted to both ends of the first conductive column 114 and the second conductive column 115, the heat can be dissipated by the first redistribution layer 112 connected to both ends thereof, or the heat can be directly dissipated at both ends of the first conductive column 114 and the second conductive column 115, so as to improve the heat dissipation performance of the first wafer layer 111 and even the semiconductor structure 100, and further improve the electrical performance and reliability of the semiconductor structure 100.

[0219] Figure 23 A flowchart of another method for manufacturing a semiconductor structure 100 is provided for some embodiments of the present disclosure, Figure 24 A top view of another semiconductor structure 100 is provided for some embodiments of the present disclosure.

[0220] As shown in Figure 23 In some embodiments, the above manufacturing method further includes the following steps S7-S11.

[0221] S7, forming a second device layer, the second device layer is arranged in the same layer as the first device layer.

[0222] As shown in Figure 24 In this step S7, a second device layer 120 can be prepared in the same layer as the first device layer 110, wherein the preparation process of the second device layer 120 is substantially the same as the preparation process of the first device layer 110, and the preparation process of the second device layer 120 will not be described here.

[0223] Exemplarily, the first device layer 110 can be the same device layer as the second device layer 120, or can be a different device layer, which is not limited in the embodiments of the present disclosure.

[0224] S8, forming a fourth insulating layer between the first device layer and the second device layer.

[0225] Please continue to refer to Figure 24In this step S8, an insulating material is deposited between the first device layer 110 and the second device layer 120 by CVD, PVD, ALD or any thin film deposition process to form the fourth insulating layer 210.

[0226] Exemplarily, the insulating material includes but is not limited to one or more of oxide material (e.g. silicon oxide), nitride material (e.g. silicon nitride), oxynitride material (e.g. silicon oxynitride).

[0227] S9, forming a second opening on the fourth insulating layer.

[0228] Please continue to refer to Figure 24 In this step S9, a photoresist layer is formed on one side surface of the fourth insulating layer 210, and the photoresist layer is patterned to obtain a fifth mask layer with multiple openings. The one side surface of the fourth insulating layer 210 is etched based on the fifth mask layer to form a second opening 211.

[0229] Exemplarily, the one side surface of the fourth insulating layer 210 is etched by dry etching to obtain the second opening 211.

[0230] S10, forming a thermally conductive filling part in the second opening.

[0231] In this step S10, a thermally conductive material is deposited in the second opening 211 to form a thermally conductive filling part 130 as shown in Figure 11 .

[0232] Exemplarily, the material of the thermally conductive filling part 130 can be a polymer material with high thermal conductivity such as polyaniline, polyacetylene or any other material with high thermal conductivity. The filling of the thermally conductive material can be performed by CVD, PVD, ALD or any thin film deposition process.

[0233] The thermally conductive filling part 130 has high thermal conductivity. Exemplarily, the thermal conductivity of the thermally conductive filling part 130 is higher than that of the fourth insulating layer 210, so the heat conduction capacity of the thermally conductive filling part 130 is higher than that of the fourth insulating layer 210.

[0234] In this embodiment, by arranging the thermally conductive filling part 130, the first device layer 110 and the second device layer 120 arranged in the same layer can be isolated, and the heat generated by the first device layer 110 and the second device layer 120 can be conducted to the thermally conductive filling part 130 in time, and then the heat can be quickly dissipated to the outside through the thermally conductive filling part 130.

[0235] In this way, the heat dissipation rate of the layered structure in which the first device layer 110 and the second device layer 120 are located can be improved, and the heat dissipation capacity of the semiconductor structure 100 composed of the first device layer 110 and the second device layer 120 can be improved, so as to ensure that the semiconductor structure 100 has good electrical performance and reliability.

[0236] In some embodiments, the preparation method further includes the following step S11.

[0237] S11, a heat conduction layer is formed on one side of the first device layer and the second device layer, and the heat conduction layer is in contact with the heat conduction filling part.

[0238] In this step S11, a heat conduction material is deposited on the side surface of the first device layer 110 and the second device layer 120, so as to form the heat conduction layer 140.

[0239] For example, the material of the heat conduction layer 140 can be polyaniline, polyacetylene, or other polymer materials with high thermal conductivity, or any other material with high thermal conductivity. Among them, the filling of the heat conduction material can use CVD, PVD, ALD or any thin film deposition process.

[0240] For example, the material of the heat conduction layer 140 can be the same as or different from the material of the heat conduction filling part 130.

[0241] As a feasible implementation, when the material of the heat conduction layer 140 is the same as the material of the heat conduction filling part 130, the heat conduction layer 140 and the heat conduction filling part 130 can be prepared in the same preparation process, so as to simplify the preparation process of the semiconductor structure 100 and improve the preparation efficiency of the semiconductor structure 100.

[0242] When the material of the heat conduction layer 140 is the same as the material of the heat conduction filling part 130, the heat conduction layer 140 and the heat conduction filling part 130 can be an integral structure, that is, there is no obvious boundary between the heat conduction layer 140 and the heat conduction filling part 130 in structure.

[0243] In this way, the heat conduction layer 140 can be used to quickly conduct the heat generated by the first device layer 110 and the second device layer 120 to the outside, so as to realize the heat dissipation treatment of the first device layer 110 and the second device layer 120, and improve the electrical performance and reliability of the first device layer 110 and the second device layer 120.

[0244] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a first device layer, the first device layer comprising a first wafer layer, a first rewiring layer and a first heat-conducting wall; wherein the first wafer layer is provided with a first surface and a second surface opposite to each other in a first direction, the first direction being perpendicular to the extension direction of the first wafer layer; the first rewiring layer is parallel to the first wafer layer and in contact with the first wafer layer, wherein the first rewiring layer comprises a first heat-conducting line; the first heat-conducting wall covers at least one surface of the first wafer layer adjacent to the first surface, and one end of the first heat-conducting line is connected to the first heat-conducting wall.

2. The semiconductor structure according to claim 1, wherein: the first rewiring layer is arranged in the first wafer layer, or the first rewiring layer is arranged on the first surface or the second surface.

3. The semiconductor structure according to claim 2, wherein: the first device layer is provided with a first conductive column and a second conductive column, the first conductive column and the second conductive column are arranged at intervals, the first conductive column and the second conductive column both penetrate through the first wafer layer and are connected to the first rewiring layer, and the first conductive column is used to electrically connect to a transistor in the first wafer layer.

4. The semiconductor structure according to claim 3, wherein: the first rewiring layer further comprises a second heat-conducting line, and one end of the second heat-conducting line is connected to the second conductive column.

5. The semiconductor structure according to any of claims 1-4, characterized in that, The semiconductor structure further comprises: a second device layer, the first device layer and the second device layer being arranged in a stack; the second device layer comprises a second wafer layer and a second heat-conducting wall, the second wafer layer is arranged in a stack with the first wafer layer, wherein the second wafer layer is provided with a third surface and a fourth surface opposite to each other in the first direction, the second heat-conducting wall covers at least one surface of the second wafer layer adjacent to the third surface, and the second heat-conducting wall is connected to the first heat-conducting wall.

6. The semiconductor structure of claim 5, wherein, the second device layer further comprises a second rewiring layer; the second rewiring layer is arranged in the second wafer layer, or the second rewiring layer is arranged on the third surface or the fourth surface, the second rewiring layer comprises a third heat-conducting line, and one end of the third heat-conducting line is connected to the second heat-conducting wall.

7. The semiconductor structure according to claim 6, wherein: the second device layer is provided with a third conductive column and a fourth conductive column, the third conductive column and the fourth conductive column are arranged at intervals, the third conductive column and the fourth conductive column both penetrate through the second wafer layer and are connected to the second rewiring layer, and the third conductive column is used to connect to a transistor in the second wafer layer.

8. The semiconductor structure according to claim 7, wherein: the second rewiring layer further comprises a fourth heat-conducting line, and one end of the fourth heat-conducting line is connected to the fourth conductive column.

9. The semiconductor structure of any of claims 1-4, wherein, The semiconductor structure further comprises: a heat-conducting filling part; the semiconductor structure further comprises a second device layer, the second device layer is arranged in the same layer as the first device layer; the heat-conducting filling part is filled between the first device layer and the second device layer.

10. The semiconductor structure of claim 9, wherein, Also comprising: a thermally conductive layer; the thermally conductive layer is arranged on the first device layer and the second device layer in a laminated manner, and the thermally conductive layer is in contact with the thermally conductive filling part.

11. A method of fabricating a semiconductor structure, characterized by, Comprising: forming a first wafer layer, the first wafer layer is oppositely provided with a first surface and a second surface in a first direction, the first direction is perpendicular to the extension direction of the first wafer layer; forming a first redistribution layer, the first redistribution layer is parallel to the first wafer layer and in contact with the first wafer layer, wherein the first redistribution layer comprises a first thermally conductive line; forming a first thermally conductive wall on at least one surface of the first wafer layer adjacent to the first surface, the first thermally conductive wall is connected to one end of the first thermally conductive line; wherein the first wafer layer, the first redistribution layer and the first thermally conductive wall constitute a first device layer.

12. The method of claim 11, wherein, The first wafer layer and the first redistribution layer are formed in the same process; The forming of the first wafer layer and the forming of the first redistribution layer comprise: forming a first film layer; forming the first redistribution layer on the first film layer in a laminated manner; forming a second film layer on the first redistribution layer in a laminated manner, wherein the first film layer and the second film layer constitute the first wafer layer.

13. The method of claim 12, wherein, The forming of the first redistribution layer on the first film layer comprises: forming a first insulating layer on one side of the first film layer; forming a first strip-shaped groove on the first insulating layer; forming the first thermally conductive line in the first strip-shaped groove.

14. The method of claim 11, wherein, The forming of the first redistribution layer comprises: forming a second insulating layer on the first surface or the second surface; forming a second strip-shaped groove on the second insulating layer; forming the first thermally conductive line in the second strip-shaped groove to form the first redistribution layer.

15. The production method according to any one of claims 11 to 14, characterized by, The forming of the first thermally conductive wall on at least one surface of the first wafer layer adjacent to the first surface comprises: forming a third insulating layer on at least one surface of the first wafer layer adjacent to the first surface; forming a first opening on the third insulating layer, the first opening exposes one end of the first thermally conductive line; forming the first thermally conductive wall in the first opening.

16. The production method according to any one of claims 11 to 14, characterized by, The preparation method further comprises: forming a first via hole and a second via hole on the first wafer layer, the first via hole and the second via hole are arranged at intervals; forming a first conductive column in the first via hole, wherein the first conductive column is connected with a transistor in the first wafer layer; forming a second conductive column in the second via hole, the first redistribution layer further comprises a second thermally conductive line, and the second conductive column is connected to one end of the second thermally conductive line.

17. The production method according to any one of claims 11 to 14, characterized by, The preparation method further comprises: forming a second device layer, the second device layer is arranged in the same layer as the first device layer; forming a fourth insulating layer between the first device layer and the second device layer; forming a second opening on the fourth insulating layer; forming a thermally conductive filling part in the second opening.

18. The method of claim 17, wherein, The preparation method further comprises: forming a thermally conductive layer on one side of the first device layer and the second device layer, the thermally conductive layer is in contact with the thermally conductive filling part.

19. A storage system, characterized by Comprising: A semiconductor structure as claimed in any one of claims 1-10; a controller coupled to the semiconductor structure to control the semiconductor structure to store data.

20. An electronic device, comprising: A memory system as claimed in claim 19, comprising a motherboard and the memory system disposed on the motherboard.

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