Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the structure comprises a substrate which comprises a plurality of chip regions arranged in an array and cutting channel regions located between the adjacent chip regions; the device layer is located on the substrate of the chip area, and the device layer comprises a plurality of devices, an interconnection structure electrically connected with the devices and a first dielectric layer covering the devices and the interconnection structure; and the alignment mark is positioned on the substrate in the cutting channel area. The alignment mark is arranged on the substrate of the cutting channel region, so that the probability that the alignment mark occupies the effective area of the chip region is reduced, the effective usable area of the device layer on the chip region is increased, and the performance and the product yield of the semiconductor structure are improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] Photolithography is a key technology in semiconductor manufacturing, which can realize the transfer of patterns from a mask to a wafer surface to form a semiconductor product meeting design requirements. In the photolithography process, first, through an exposure step, light is irradiated to a wafer coated with photoresist through the light-transmitting or light-reflecting area of the mask, and a photochemical reaction occurs with the photoresist; then, through a developing step, the light-exposed and non-exposed photoresist is dissolved to different degrees in the developing agent to form a lithography pattern, realizing the transfer of the mask pattern; and then, through an etching step, the wafer is etched based on the lithography pattern formed by the photoresist layer to further transfer the mask pattern to the wafer.

[0003] With the continuous reduction of lithography feature size, the overlay accuracy and critical dimension uniformity of the lithography machine are also continuously improved. The manufacturing of a semiconductor device usually includes several tens of photolithography processes. In order to ensure the correspondence of each level, the wafer must be aligned before lithography, so that the pattern can be accurately transferred to the photoresist layer of the wafer.

[0004] At present, the performance and product yield of the semiconductor structure still need to be improved. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which is beneficial to further improve the performance and product yield of the semiconductor structure.

[0006] To solve the above problems, embodiments of the present application provide a semiconductor structure, comprising: a substrate, the substrate comprising a plurality of arrayed chip regions and a cutting lane region between adjacent chip regions; a device layer on the substrate of the chip region, the device layer comprising a plurality of devices, an interconnection structure electrically connected with the devices, and a first dielectric layer covering the devices and the interconnection structure; and an alignment mark on the substrate of the cutting lane region.

[0007] Optionally, the alignment mark comprises a plurality of first sub-alignment marks distributed at different positions of the cutting lane region.

[0008] Optionally, the scribe region includes a first scribe region and a second scribe region orthogonal to the first scribe region, the first scribe region extends along a first direction and is spaced along a second direction, the second scribe region extends along the second direction and is spaced along the first direction, the first direction is perpendicular to the second direction; part of the first sub-alignment marks are located in the first scribe region, and the remaining first sub-alignment marks are located in the second scribe region.

[0009] Optionally, the first sub-alignment marks located in the first scribe region include a plurality of second sub-alignment marks extending along the second direction and spaced along the first direction; the first sub-alignment marks located in the second scribe region include a plurality of second sub-alignment marks extending along the first direction and spaced along the second direction.

[0010] Optionally, the number of first sub-alignment marks located in the first scribe region is equal to the number of first sub-alignment marks located in the second scribe region.

[0011] Optionally, the number of first sub-alignment marks is at least greater than 3.

[0012] Optionally, the semiconductor structure further includes: a second dielectric layer located on the substrate of the scribe region, and the alignment marks are located in the second dielectric layer.

[0013] Optionally, the material of the alignment marks includes one or both of titanium nitride and silicon oxide.

[0014] Optionally, the width of the scribe region is 60-80 microns.

[0015] Optionally, the shape of the area surrounded by the alignment marks includes a rectangle; the diagonals of the rectangle coincide with the center point of the substrate and are perpendicular to each other.

[0016] Correspondingly, the embodiment of the present application provides a forming method of a semiconductor structure, including: providing a substrate, the substrate including a plurality of array-arranged chip regions and scribe regions located between adjacent chip regions; forming a device layer on the substrate of the chip region, the device layer including a plurality of devices, an interconnection structure electrically connected with the devices, and a first dielectric layer covering the devices and the interconnection structure; forming an alignment mark on the substrate of the scribe region.

[0017] Optionally, the step of forming the alignment mark includes: forming a second dielectric layer on the substrate of the scribe region; forming an alignment groove in the second dielectric layer; forming an alignment material layer in the alignment groove, and taking the alignment material layer located in the alignment groove as the alignment mark.

[0018] Optionally, in the step of forming the alignment mark, the alignment groove comprises a plurality of first sub-alignment grooves distributed in different positions of the scribe lane region.

[0019] Optionally, in the step of providing the substrate, the scribe lane region comprises a first scribe lane region and a second scribe lane region orthogonal to the first scribe lane region, the first scribe lane region extends along a first direction and is arranged at intervals along a second direction, the second scribe lane region extends along the second direction and is arranged at intervals along the first direction, the first direction is perpendicular to the second direction; in the step of forming the alignment mark, part of the first sub-alignment grooves are located in the first scribe lane region, and the remaining first sub-alignment grooves are located in the second scribe lane region.

[0020] Optionally, in the step of forming the alignment mark, the first sub-alignment grooves located in the first scribe lane region comprise a plurality of second sub-alignment grooves extending along the second direction and arranged at intervals along the first direction; in the step of forming the alignment mark, the first sub-alignment grooves located in the second scribe lane region comprise a plurality of second sub-alignment grooves extending along the first direction and arranged at intervals along the second direction.

[0021] Optionally, in the step of forming the alignment mark, the number of the first sub-alignment grooves located in the first scribe lane region is equal to the number of the first sub-alignment grooves located in the second scribe lane region.

[0022] Optionally, in the step of forming the alignment mark, the number of the first sub-alignment grooves is at least greater than 3.

[0023] Optionally, the material of the alignment mark comprises one or both of titanium nitride and silicon oxide.

[0024] Optionally, the width of the scribe lane region is 60-80 microns.

[0025] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0026] The embodiment of the present application provides a semiconductor structure, the substrate comprises a plurality of array-arranged chip regions and scribe lane regions located between adjacent chip regions, a device layer is located on the substrate of the chip region, the device layer comprises a plurality of devices, an interconnection structure electrically connected with the device, and a first dielectric layer covering the device and the interconnection structure, and an alignment mark is located on the substrate of the scribe lane region. Compared with the scheme that the alignment mark is arranged on the chip region, the embodiment of the present application arranges the alignment mark on the substrate of the scribe lane region, reduces the probability that the alignment mark occupies the effective area of the chip region, increases the effective use area of the device layer on the chip region, and thus improves the performance and product yield of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figures 1 to 4 is a structure diagram corresponding to an embodiment of the semiconductor structure of the present application;

[0028] Figures 5 to 10 is a structure diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application. DETAILED DESCRIPTION

[0029] As can be seen from the background, at present, the performance and product yield of the semiconductor structure still need to be improved. Especially, the setting region of the alignment mark is the chip area of the semiconductor structure, which is easy to cause the effective use area of the chip area of the semiconductor structure to decrease, causes the number of device chips set in the chip area of the semiconductor structure to decrease, and thus affects the performance and product yield of the semiconductor structure.

[0030] In order to solve the technical problem, an embodiment of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a plurality of array-arranged chip areas and a cutting lane area located between adjacent chip areas; a device layer located on the substrate of the chip area, the device layer comprising a plurality of devices, an interconnection structure electrically connected with the device, and a first dielectric layer covering the device and the interconnection structure; an alignment mark located on the substrate of the cutting lane area.

[0031] An embodiment of the present application provides a semiconductor structure, the substrate comprising a plurality of array-arranged chip areas and a cutting lane area located between adjacent chip areas, the device layer located on the substrate of the chip area, the device layer comprising a plurality of devices, an interconnection structure electrically connected with the device, and a first dielectric layer covering the device and the interconnection structure, the alignment mark located on the substrate of the cutting lane area, compared with the scheme that the alignment mark is arranged on the chip area, the embodiment of the present application arranges the alignment mark on the substrate of the cutting lane area, reduces the probability that the alignment mark occupies the effective area of the chip area, increases the effective use area of the device layer on the chip area, and thus improves the performance and product yield of the semiconductor structure.

[0032] In order to make the above-mentioned purpose, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings.

[0033] Figures 1 to 4 is a structure diagram corresponding to an embodiment of the semiconductor structure of the present application. Among them, Figure 1 is a top view, Figure 2 is Figure 1 is a sectional view along the AA direction, Figure 3 and Figure 4 is an enlarged view of the alignment mark.

[0034] The semiconductor structure comprises: a substrate 106, the substrate 106 comprising a plurality of chip regions 100A arranged in an array and a scribe region 100C located between adjacent chip regions 100A; a device layer located on the substrate 106 of the chip region 100A, the device layer comprising a plurality of devices 107, an interconnection structure 104 electrically connected to the device 107, and a first dielectric layer 103 covering the device 107 and the interconnection structure 104; and an alignment mark 110 located on the substrate 106 of the scribe region 100C.

[0035] It should be noted that the substrate 106 comprises a plurality of chip regions 100A arranged in an array and a scribe region 100C located between adjacent chip regions 100A, the device layer is located on the substrate 106 of the chip region 100A, the device layer comprises a plurality of devices 107, an interconnection structure 104 electrically connected to the device 107, and a first dielectric layer 103 covering the device 107 and the interconnection structure 104, and the alignment mark 110 is located on the substrate 106 of the scribe region 100C. Compared with the scheme that the alignment mark 110 is arranged on the chip region 100A, the alignment mark 110 is arranged on the substrate 106 of the scribe region 100C in the embodiment of the present application, which reduces the probability of the alignment mark 110 occupying the effective area of the chip region 100A, increases the effective use area of the device layer on the chip region 100A, and thus improves the performance and product yield of the semiconductor structure.

[0036] The substrate 106 provides a process basis for the process of the semiconductor structure.

[0037] In the embodiment, the material of the substrate 106 is silicon. In other embodiments, the material of the substrate 106 can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and other materials, and the substrate 106 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, and other types of substrates. The material of the substrate 106 can be a material suitable for process needs or easy to integrate.

[0038] The chip region 100A is a region where the device layer is arranged.

[0039] As an example, the plurality of chip regions 100A are arranged in an array, which can make the scribe region 100C located between adjacent chip regions 100A straight, reducing the difficulty of subsequent cutting of the semiconductor structure.

[0040] Specifically, in the packaging process of the semiconductor structure (wafer), the semiconductor structure needs to be cut, the scribe region 100C in the substrate 106 is a cutting channel in the wafer cutting process, and at the same time, the scribe region 100C also provides a space region for arranging the alignment mark 110.

[0041] In the embodiment, the cutting lane region 100C includes a first cutting lane region 100B extending along a first direction (e.g., the X direction) and spaced along a second direction (e.g., the Y direction), and a second cutting lane region 100D extending along the second direction and spaced along the first direction, the first direction being perpendicular to the second direction. Figure 1 In the embodiment, the cutting lane region 100C includes a first cutting lane region 100B extending along a first direction (e.g., the X direction) and spaced along a second direction (e.g., the Y direction), and a second cutting lane region 100D extending along the second direction and spaced along the first direction, the first direction being perpendicular to the second direction. Figure 1 In the embodiment, the cutting lane region 100C includes a first cutting lane region 100B extending along a first direction (e.g., the X direction) and spaced along a second direction (e.g., the Y direction), and a second cutting lane region 100D extending along the second direction and spaced along the first direction, the first direction being perpendicular to the second direction.

[0042] It should be noted that, by arranging the first cutting lane region 100B and the second cutting lane region 100D, the extension directions of the alignment marks 110 distributed in the first cutting lane region 100B and the extension directions of the alignment marks 110 distributed in the second cutting lane region 100D are perpendicular to each other. Accordingly, in the subsequent alignment process of the semiconductor structure, the alignment marks 110 in the first direction and the alignment marks 110 in the second direction can improve the alignment accuracy. At the same time, even if the alignment marks 110 in one direction cannot be correctly identified, the alignment marks 110 in the other direction can still be used for alignment, thereby improving the redundancy of the alignment of the semiconductor structure.

[0043] It should be further noted that the width dimension of the cutting lane region 100C should not be too large or too small. If the width dimension of the cutting lane region 100C is too large, it is easy to occupy too much of the effective use area of the chip region 100A, so that the number of device layers arranged in a unit area of the semiconductor structure is too small, which affects the performance of the semiconductor structure. If the width dimension of the cutting lane region 100C is too small, in the formation process of the alignment marks 110, the process difficulty of forming the alignment marks 110 in the cutting lane region 100C is increased, so that the process window of forming the alignment marks 110 is too small, and the probability of damage to the device layers in the chip region 100A is increased. Therefore, in the embodiment, the width dimension of the cutting lane region 100C is 60 microns to 80 microns.

[0044] Specifically, the plurality of devices 107 includes transistors, resistors, capacitors, and other electronic devices 107.

[0045] The plurality of devices 107 and the interconnection structure 104 constitute an integrated circuit.

[0046] It should be noted that the first dielectric layer 103 plays an electrical isolation role for the plurality of devices 107 and the interconnection structure 104.

[0047] In the embodiment, the material of the first dielectric layer 103 includes a dielectric material, and the dielectric material includes one or more of titanium oxide, zirconium oxide, hafnium oxide, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride.

[0048] It should be noted that during the formation of a multilayer semiconductor structure, the pattern of each layer needs to be precisely aligned with the pattern of the next layer. The alignment mark 110 serves as a reference point to help the alignment system ensure that the pattern of each layer is set in the correct position.

[0049] It should also be noted that by setting the alignment mark 110 on the substrate 106 of the dicing area 100C, the probability of the alignment mark 110 occupying the effective area of ​​the chip area 100A is reduced, and the effective usable area of ​​the device layer on the chip area 100A is increased. More device layers can be set in the same unit area, thereby improving the performance of the semiconductor structure and the product yield.

[0050] In this embodiment, the alignment mark 110 includes a plurality of first sub-alignment marks 111 distributed at different positions in the cutting channel area 100C.

[0051] It should be noted that multiple first sub-alignment marks 111 distributed at different positions in the cutting channel area 100C can provide more geometric constraints, which helps the alignment system to calculate a more accurate relative positional relationship through these geometric constraints, thereby improving the alignment accuracy of the alignment system (e.g., binocular microscope alignment) and the semiconductor structure.

[0052] In this embodiment, a portion of the first sub-alignment marks 111 are located in the first cutting channel area 100B, and the remaining first sub-alignment marks 111 are located in the second cutting channel area 100D.

[0053] It should be noted that the extension direction of the first sub-alignment mark 111 distributed in the first dicing region 100B and the extension direction of the first sub-alignment mark 111 distributed in the second dicing region 100D are perpendicular to each other. Accordingly, in the subsequent alignment process of the semiconductor structure, the first sub-alignment mark 111 in the first direction and the first sub-alignment mark 111 in the second direction can improve the alignment accuracy. At the same time, even if the first sub-alignment mark 111 in one direction cannot be correctly identified, the first sub-alignment mark 111 in the other direction can still be used for alignment, thereby improving the redundancy of aligning the semiconductor structure.

[0054] like Figures 3 to 4 As shown, as an example, the first sub-alignment mark 111 located in the first cutting channel area 100B includes a plurality of second sub-alignment marks 112 that extend along the second direction and are spaced apart along the first direction; the first sub-alignment mark 111 located in the second cutting channel area 100D includes a plurality of second sub-alignment marks 112 that extend along the first direction and are spaced apart along the second direction.

[0055] Specifically, the second sub-alignment marks 112 arranged at intervals can generate obvious diffraction patterns, which can provide strong signals, thereby facilitating the recognition and processing of the alignment system.

[0056] It should be noted that the second sub-alignment marks 112 extend in the first direction and the second direction, which can provide alignment information in different directions for the alignment system, and help the alignment system to accurately align in the first direction and the second direction, thereby improving the alignment accuracy.

[0057] In this embodiment, the second sub-alignment marks 112 are rectangular in shape.

[0058] It should be noted that the second sub-alignment marks 112 are rectangular in shape, which can provide clear geometric edges, facilitating the recognition and measurement of the alignment system through image processing algorithms, thereby determining the accurate position of the alignment mark 110.

[0059] In this embodiment, the number of first sub-alignment marks 111 located in the first scribe lane region 100B is equal to the number of first sub-alignment marks 111 located in the second scribe lane region 100D.

[0060] Specifically, the number of first sub-alignment marks 111 in the first scribe lane region 100B is equal to the number of first sub-alignment marks 111 in the second scribe lane region 100D, which means that the number of first sub-alignment marks 111 in the first direction is equal to the number of first sub-alignment marks 111 in the second direction. The equal number of first sub-alignment marks 111 in the first direction and the second direction can provide uniform alignment reference, ensuring the consistency of the alignment process of the semiconductor structure, and at the same time, the equal number of first sub-alignment marks 111 in the first direction and the second direction can simplify the alignment algorithm and reduce the complexity of the alignment system, thereby improving the production efficiency.

[0061] In this embodiment, the number of first sub-alignment marks 111 is at least greater than 3.

[0062] Specifically, more than 3 first sub-alignment marks 111 can improve the alignment accuracy of the alignment system in a two-dimensional space. As an example, Figure 1 four first sub-alignment marks 111 are shown in FIG. 4.

[0063] In this embodiment, the shape of the area surrounded by the alignment mark 110 includes a rectangle.

[0064] Specifically, the shape of the area surrounded by the alignment mark 110 includes a rectangle, which can provide clear geometric edges, facilitating the recognition and measurement of the alignment system through image processing algorithms, thereby determining the accurate position of the alignment mark 110.

[0065] As an example, the diagonals of the rectangle coincide with the center points of the substrate 106 and are perpendicular to each other.

[0066] It should be noted that the diagonals of the rectangle coincide with the center points of the substrate 106 and are perpendicular to each other, so that the alignment marks 110 are uniformly distributed in the substrate 106, that is, the alignment marks 110 are uniformly distributed in the wafer, thereby helping the alignment system to calculate a more accurate relative positional relationship, thereby improving the alignment accuracy of the alignment system (for example, binocular microscope alignment) and the semiconductor structure (that is, the wafer).

[0067] In this embodiment, the material of the alignment mark 110 includes one or both of titanium nitride and silicon oxide.

[0068] Specifically, titanium nitride and silicon oxide have a high refractive index, which helps to improve the recognition in the alignment system.

[0069] In this embodiment, the semiconductor structure further includes: a second dielectric layer located on the substrate 106 of the cutting lane area 100C, and the alignment mark 110 is located in the second dielectric layer.

[0070] Specifically, in the forming process of the semiconductor structure, the second dielectric layer provides a process basis for the alignment mark 110.

[0071] In this embodiment, the material of the second dielectric layer includes a dielectric material, and the dielectric material includes one or more of titanium oxide, zirconium oxide, hafnium oxide, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride.

[0072] Figures 5 to 10 is a structure diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present application.

[0073] Referring to Figures 5 to 7 , a substrate 206 is provided, which includes a plurality of arrayed chip areas 200A and cutting lane areas 200C located between adjacent chip areas 200A.

[0074] Specifically, the substrate 206 provides a process basis for the process of the semiconductor structure.

[0075] In this embodiment, the material of the substrate 206 is silicon. In other embodiments, the material of the substrate 206 can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, and other materials, and the substrate 206 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, and other types of substrates. The material of the substrate 206 can be a material suitable for process needs or easy to integrate.

[0076] The chip area 200A is an area where a device layer is arranged.

[0077] As an example, the plurality of chip regions 200A are arranged in an array, which can make the cutting lane regions 200C between adjacent chip regions 200A linear, thereby reducing the difficulty of subsequent cutting of the semiconductor structure.

[0078] Specifically, in a semiconductor structure (wafer) packaging process, the semiconductor structure needs to be cut, and the cutting lane regions 200C in the substrate 206 are cutting channels in the wafer cutting process, and the cutting lane regions 200C also provide space regions for setting alignment marks.

[0079] In this embodiment, the cutting lane regions 200C include first cutting lane regions 200B and second cutting lane regions 200D which are orthogonal to the first cutting lane regions 200B, the first cutting lane regions 200B extend along a first direction (for example, the X direction in the figure) and are arranged at intervals along a second direction (for example, the Y direction in the figure), and the second cutting lane regions 200D extend along the second direction and are arranged at intervals along the first direction, and the first direction is perpendicular to the second direction. Figure 5 Figure 5 In this embodiment, the cutting lane regions 200C include first cutting lane regions 200B and second cutting lane regions 200D which are orthogonal to the first cutting lane regions 200B, the first cutting lane regions 200B extend along a first direction (for example, the X direction in the figure) and are arranged at intervals along a second direction (for example, the Y direction in the figure), and the second cutting lane regions 200D extend along the second direction and are arranged at intervals along the first direction, and the first direction is perpendicular to the second direction.

[0080] It should be noted that by arranging the first cutting lane regions 200B and the second cutting lane regions 200D, the extension directions of the alignment marks distributed in the first cutting lane regions 200B and the extension directions of the alignment marks distributed in the second cutting lane regions 200D can be perpendicular to each other, and accordingly, in the subsequent alignment process of the semiconductor structure, the alignment marks in the first direction and the alignment marks in the second direction can improve the alignment accuracy, and even if the alignment marks in one direction cannot be correctly identified, the alignment marks in the other direction can still be used for alignment, thereby improving the redundancy of the alignment of the semiconductor structure.

[0081] It should be further noted that the width dimension of the cutting lane regions 200C should not be too large or too small. If the width dimension of the cutting lane regions 200C is too large, it is easy to occupy too much of the effective use area of the chip regions 200A, so that the number of device layers provided in a unit area of the semiconductor structure is too small, which affects the performance of the semiconductor structure; if the width dimension of the cutting lane regions 200C is too small, in the formation process of the alignment marks, the process difficulty of forming the alignment marks in the cutting lane regions 200C is increased, so that the process window for forming the alignment marks is too small, and the probability that the device layers formed in the chip regions 200A are damaged is increased. Therefore, in this embodiment, the width dimension of the cutting lane regions 200C is 60 microns to 80 microns.

[0082] Reference is made to Figures 6 to 10 wherein, Figure 6 is a top view, Figure 7 is Figure 6 is a sectional view along the AA direction,​Figure 7 and FIG. 4 is an enlarged view of the alignment slot. A device layer is formed on the substrate 206 of the chip area 200A, the device layer including a plurality of devices 207, an interconnection structure 204 electrically connected to the devices 207, and a first dielectric layer 203 covering the devices 207 and the interconnection structure 204; and an alignment mark 270 is formed on the substrate 206 of the dicing lane area 200C.

[0083] Specifically, the plurality of devices 207 includes transistors, resistors, capacitors, and other electronic devices 207.

[0084] The plurality of devices 207 and the interconnection structure 204 constitute an integrated circuit.

[0085] It should be noted that the first dielectric layer 203 serves as an electrical isolation for the plurality of devices 207 and the interconnection structure 204.

[0086] In this embodiment, the material of the first dielectric layer 203 includes a dielectric material, which includes one or more of titanium oxide, zirconium oxide, hafnium oxide, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride.

[0087] It should be noted that during the formation of the multi-layer semiconductor structure, the pattern of each layer needs to be accurately aligned with the pattern of the next layer. The alignment mark 270 serves as a reference point to help the alignment system ensure that the pattern of each layer is set at the correct position.

[0088] It should also be noted that the alignment mark 270 is formed on the substrate 206 of the dicing lane area 200C, which reduces the probability of the alignment mark 270 occupying the effective area of the chip area 200A, increases the effective use area of the device layer on the chip area 200A, and enables more device layers to be set in the same unit area, thereby improving the performance and product yield of the semiconductor structure.

[0089] As an example, the step of forming the alignment mark 270 includes: forming a second dielectric layer 202 on the substrate 206 of the dicing lane area 200C; forming an alignment slot 210 in the second dielectric layer 202; forming an alignment material layer (not shown) in the alignment slot 210, and taking the alignment material layer in the alignment slot 210 as the alignment mark 270.

[0090] Specifically, the second dielectric layer 202 provides a process basis for forming the alignment mark 270.

[0091] In the embodiment, the material of the second dielectric layer 202 comprises a dielectric material, which comprises one or more of titanium oxide, zirconium oxide, hafnium oxide, silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride.

[0092] Specifically, the alignment groove 210 provides a spatial position for forming the alignment mark 270.

[0093] In the embodiment, in the step of forming the alignment mark 270, the alignment groove 210 comprises a plurality of first sub-alignment grooves 211 distributed at different positions of the scribe lane region 200C.

[0094] It should be noted that the plurality of first sub-alignment grooves 211 distributed at different positions of the scribe lane region 200C can provide more geometric constraints, which can help the alignment system to calculate more accurate relative positional relationships through these geometric constraints, thereby improving the alignment accuracy of the alignment system (such as binocular microscope alignment) and the semiconductor structure.

[0095] In the embodiment, in the step of forming the alignment mark 270, part of the first sub-alignment grooves 211 are located in the first scribe lane region 200B, and the remaining first sub-alignment grooves 211 are located in the second scribe lane region 200D.

[0096] It should be noted that the extension direction of the first sub-alignment grooves 211 distributed in the first scribe lane region 200B and the extension direction of the first sub-alignment grooves 211 distributed in the second scribe lane region 200D are perpendicular to each other, and correspondingly, after forming the alignment mark 270, in the process of aligning the semiconductor structure, the alignment mark 270 in the first direction and the alignment mark 270 in the second direction can improve the alignment accuracy, and at the same time, even if the alignment mark 270 in one direction cannot be correctly identified, the alignment mark 270 in the other direction can still be used for alignment, thereby improving the redundancy of aligning the semiconductor structure.

[0097] In the embodiment, the first sub-alignment grooves 211 located in the first scribe lane region 200B comprise a plurality of second sub-alignment grooves 212 extending along the second direction and arranged at intervals along the first direction; the first sub-alignment grooves 211 located in the second scribe lane region 200D comprise a plurality of second sub-alignment grooves 212 extending along the first direction and arranged at intervals along the second direction.

[0098] Specifically, the second sub-alignment grooves 212 arranged at intervals can produce obvious diffraction patterns, and the diffraction patterns can provide strong signals, thereby facilitating the identification and processing of the alignment system.

[0099] It should be noted that the second sub-alignment groove 212 extends along the first direction and the second direction, can provide alignment information in different directions for the alignment system, and helps the alignment system to accurately align in the first direction and the second direction, thereby improving the alignment accuracy.

[0100] In this embodiment, the second sub-alignment groove 212 is rectangular in shape.

[0101] It should be noted that the rectangular second sub-alignment groove 212 can provide clear geometric edges, which facilitates the alignment system to recognize and measure through an image processing algorithm, thereby determining the accurate position of the alignment mark 270.

[0102] In this embodiment, the number of the first sub-alignment grooves 211 in the first cutting track area 200B is equal to the number of the first sub-alignment grooves 211 in the second cutting track area 200D.

[0103] Specifically, the number of the first sub-alignment grooves 211 in the first cutting track area 200B is equal to the number of the first sub-alignment grooves 211 in the second cutting track area 200D, which means that the number of the first sub-alignment grooves 211 in the first direction is equal to the number of the first sub-alignment grooves 211 in the second direction. The equal number of the first sub-alignment grooves 211 in the first direction and the second direction can provide uniform alignment reference, ensure the consistency of the alignment process of the semiconductor structure, and at the same time, the equal number of the first sub-alignment grooves 211 in the first direction and the second direction can simplify the alignment algorithm and reduce the complexity of the alignment system, thereby improving the production efficiency.

[0104] In this embodiment, in the step of forming the alignment mark 270, the number of the first sub-alignment grooves 211 is at least greater than 2.

[0105] Specifically, more than 2 first sub-alignment grooves 211 make the number of the subsequently formed alignment marks 270 also more than two, which can improve the alignment accuracy of the alignment system in a two-dimensional space during the alignment process. As an example, Figure 6 four first sub-alignment grooves 211 are shown in the middle.

[0106] In this embodiment, the material of the alignment mark 270 includes one or both of titanium nitride and silicon oxide.

[0107] Specifically, titanium nitride and silicon oxide have a relatively high refractive index, which helps to improve the recognition in the alignment system.

[0108] Although the present application is disclosed as above, the present application is not limited thereto. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various changes and modifications, and therefore the protection scope of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes multiple chip regions arranged in an array and dicing channels located between adjacent chip regions; A device layer, located on the substrate of the chip region, includes a plurality of devices, interconnect structures electrically connected to the devices, and a first dielectric layer covering the devices and interconnect structures; Alignment marks are located on the base of the cutting channel area.

2. The semiconductor structure as described in claim 1, characterized in that, The alignment marks include multiple first sub-alignment marks distributed at different locations in the cutting channel area.

3. The semiconductor structure as described in claim 2, characterized in that, The cutting channel area includes a first cutting channel area and a second cutting channel area orthogonal to it. The first cutting channel area extends along a first direction and is spaced apart along a second direction. The second cutting channel area extends along the second direction and is spaced apart along the first direction. The first direction is perpendicular to the second direction. A portion of the first sub-alignment marks are located in the first cutting channel area, and the remaining first sub-alignment marks are located in the second cutting channel area.

4. The semiconductor structure as described in claim 3, characterized in that, The first sub-alignment mark located in the first cutting channel area includes a plurality of second sub-alignment marks that extend along the second direction and are spaced apart along the first direction; The first sub-alignment mark located in the second cutting channel area includes a plurality of second sub-alignment marks that extend along the first direction and are spaced apart along the second direction.

5. The semiconductor structure as described in claim 3, characterized in that, The number of first sub-alignment marks located in the first cutting channel area is equal to the number of first sub-alignment marks located in the second cutting channel area.

6. The semiconductor structure as described in claim 2, characterized in that, The number of the first sub-alignment markers is at least greater than 3.

7. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a second dielectric layer located on the substrate of the dicing region, and the alignment mark is located in the second dielectric layer.

8. The semiconductor structure as described in claim 1, characterized in that, The alignment mark is made of one or both of titanium nitride and silicon oxide.

9. The semiconductor structure as described in claim 1, characterized in that, The width of the cutting channel is 60 to 80 micrometers.

10. The semiconductor structure as claimed in claim 1, characterized in that, The area enclosed by the alignment marks includes a rectangle; The diagonal of the rectangle coincides with and is perpendicular to the center point of the base.

11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a plurality of chip regions arranged in an array and dicing channels located between adjacent chip regions; A device layer is formed on the substrate of the chip region. The device layer includes a plurality of devices, interconnect structures electrically connected to the devices, and a first dielectric layer covering the devices and interconnect structures. Alignment marks are formed on the substrate of the cutting channel area.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming the alignment mark includes: forming a second dielectric layer on the substrate of the cut channel area; forming an alignment groove in the second dielectric layer; forming an alignment material layer in the alignment groove, and using the alignment material layer located in the alignment groove as the alignment mark.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of forming the alignment mark, the alignment groove includes a plurality of first sub-alignment grooves distributed at different positions in the cutting channel area.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of providing the substrate, the cutting channel area includes a first cutting channel area and a second cutting channel area orthogonal to it. The first cutting channel area extends along a first direction and is spaced apart along a second direction. The second cutting channel area extends along the second direction and is spaced apart along the first direction. The first direction is perpendicular to the second direction. In the step of forming the alignment mark, a portion of the first sub-alignment groove is located in the first cutting channel area, and the remaining first sub-alignment groove is located in the second cutting channel area.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of forming the alignment mark, the first sub-alignment groove located in the first cutting channel area includes a plurality of second sub-alignment grooves that extend along the second direction and are spaced apart along the first direction. In the step of forming the alignment mark, the first sub-alignment groove located in the second cutting channel area includes a plurality of second sub-alignment grooves extending along the first direction and spaced apart along the second direction.

16. The method for forming a semiconductor structure as described in claim 14, characterized in that, In the step of forming the alignment mark, the number of first sub-alignment slots located in the first cutting channel area is equal to the number of first sub-alignment slots located in the second cutting channel area.

17. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming the alignment mark, the number of the first sub-alignment slots is at least greater than 3.

18. The method for forming a semiconductor structure as described in claim 11, characterized in that, The alignment mark is made of one or both of titanium nitride and silicon oxide.

19. The method for forming a semiconductor structure as described in claim 11, characterized in that, The width of the cutting channel is 60 to 80 micrometers.

Images