Low-insertion-loss high-harmonic-suppression LTCC band-pass filter equivalent circuit and filter thereof

Abstract

The invention discloses a low-insertion-loss high-harmonic-suppression LTCC (Low Temperature Co-fired Ceramic) band-pass filter equivalent circuit and a filter thereof, which are based on an LTCC (Low Temperature Co-fired Ceramic) technology and adopt a four-order cross-coupled filter lumped parameter model design to realize special electrical performance requirements of a novel laminated band-pass filter. According to the LTCC multi-layer band-pass filter, the characteristics of the LTCC multi-layer band-pass filter are effectively achieved, and the LTCC multi-layer band-pass filter has the advantages of being low in loss, high in harmonic suppression, small in size, high in reliability, low in cost, suitable for large-scale production and the like and further adapts to the development trend of integration and miniaturization of new electronic elements.

Description

TECHNICAL FIELD

[0001] The application discloses an equivalent circuit of a low-insertion-loss high-harmonic-suppression LTCC band-pass filter and a filter thereof, which can be used for wireless connection of mobile phones, tablets, automobile electronics and other various communication devices. BACKGROUND

[0002] LTCC (Low Temperature Co-fired Ceramic) technology is an advanced multilayer ceramic integration technology. After the ceramic green sheet is finely processed through punching, hole filling, wiring and the like, and then stacked in a specific order, a whole structure is formed by co-firing at a low temperature. In this multilayer structure, various passive components such as capacitors and inductors can be integrated to realize high integration and miniaturization of passive components. At the same time, the LTCC material has excellent high-frequency characteristics, can effectively reduce signal loss during high-frequency signal transmission, and has high mechanical strength and thermal stability, can adapt to complex and changeable working environments, and has very high reliability.

[0003] The band-pass filter based on the LTCC technology is designed by using the multilayer structure characteristics and integration advantages of the LTCC. By reasonably designing the internal circuit layout and component parameters, the band-pass filter can accurately filter signals in a specific frequency range and effectively suppress signals of other frequencies. This band-pass filter is more compact in structure, greatly saves space compared with traditional filters, has low insertion loss in the passband, and has good suppression performance outside the passband, and can meet the high-precision requirements of modern communication systems for signal processing.

[0004] In a 5G smartphone terminal, the space is extremely limited, and traditional filters often have difficulty in meeting the performance requirements while realizing miniaturized layout. The LTCC filter, by virtue of its unique technical process, integrates multiple passive components in a multilayer ceramic structure, greatly reducing the size of the device. Compared with other forms of filters, the miniaturization advantage is particularly prominent, which can easily adapt to the compact space structure of the mobile phone, and then realize accurate filtering of 5G frequency band signals, effectively improve the data transmission rate, video playback smoothness and voice call clarity of the mobile phone. SUMMARY

[0005] The application provides a novel low-insertion-loss high-harmonic-suppression LTCC band-pass filter, aiming at realizing high-performance frequency selection and suppression functions through innovative design. The filter adopts an LTCC process, constructs a four-order filter structure, and enhances the distinction of signals inside and outside the passband through a clever cross-coupling mechanism, thereby significantly improving the out-of-band suppression capability, and effectively meeting the urgent needs of modern communication systems for high selectivity, low loss and high out-of-band suppression filters. The application adopts the technical scheme that a novel dielectric microwave LTCC multilayer band-pass filter comprises an LTCC ceramic base, a wiring terminal head arranged on the outer side of the base and a circuit layer arranged in the base, and the circuit layer in the base is in a laminated structure.

[0006] The application first provides a low-insertion-loss high-harmonic-suppression LTCC band-pass filter equivalent circuit, which comprises an input port and an output port, wherein a first channel and a second channel are arranged between the input port and the output port; the first channel comprises a fifth capacitor C5, a fifth inductor L5 and a sixth capacitor C6 which are sequentially connected between the input port and the output port, wherein a first grounding inductor L1 is connected between the input port and the fifth capacitor C5, a second grounding inductor L2 and a second grounding capacitor C2 are sequentially connected between the fifth capacitor C5 and the fifth inductor L5, a third grounding capacitor C3 and a third grounding inductor L3 are sequentially connected between the fifth inductor L5 and the sixth capacitor C6, a fourth grounding inductor L4 is connected between the sixth capacitor C6 and the output port, the first grounding inductor L1, the fourth grounding inductor L4, the fifth capacitor C5 and the sixth capacitor C6 form an LC high-pass filter circuit, and the second grounding inductor L2 and the third grounding inductor L3 form two LC parallel resonators; the second channel comprises a first coupling capacitor C1 and a fourth coupling capacitor C4 which are sequentially connected between the input port and the output port, and a seventh grounding capacitor C7 is arranged between the first coupling capacitor C1 and the fourth coupling capacitor C4.

[0007] A low-insertion-loss high-harmonic-suppression LTCC band-pass filter, which comprises a ceramic body, a circuit structure layer arranged in the ceramic body, and the circuit structure layer comprises:

[0008] A first layer, a first layer first metal pattern, a first layer second metal pattern and a first layer third metal pattern are printed on the ceramic dielectric substrate; the first layer first metal pattern and the first layer second metal pattern are respectively an input port and an output port, and are connected with a fourth layer first metal plane and a fourth layer second metal plane through a first connecting point column and a second connecting point column; the first layer third metal pattern is a first layer grounding plane, which is connected with a second layer first metal pattern through a third grounding point column;

[0009] The second layer, the second layer first metal pattern is printed on the ceramic dielectric substrate, and the second layer first metal pattern is connected with the eighth layer third metal plane and the eighth layer fourth metal plane through the fourth connecting point column and the fifth connecting point column respectively, and is connected with the eighth layer sixth metal plane and the eighth layer seventh metal plane through the sixth connecting point column and the seventh connecting point column;

[0010] The third layer, the third layer first metal plane and the third layer second metal plane are printed on the ceramic dielectric substrate, and the third layer first metal plane and the third layer second metal plane are connected with the eighth layer sixth metal plane and the eighth layer seventh metal plane insulated from each other of the eighth layer through the eighth connecting point column and the ninth connecting point column respectively; the third layer first metal plane and the second layer first metal pattern form the second ground capacitance C2 and the third ground capacitance C3 of the two LC parallel resonators;

[0011] The fourth layer, the fourth layer first metal plane and the fourth layer second metal plane are printed on the ceramic dielectric substrate, and the fourth layer first metal plane and the fourth layer second metal plane are connected with the eighth layer first metal plane and the eighth layer second metal plane through the tenth connecting point column and the eleventh connecting point column respectively, and are connected with the first layer first metal pattern and the first layer third metal pattern through the first connecting point column and the second connecting point column; the first metal plane and the fourth layer second metal plane form the fifth capacitance C5 and the sixth capacitance C6 of the inter-stage coupling with the third layer first metal plane and the third layer second metal plane respectively;

[0012] The fifth layer, the fifth layer first metal plane is printed on the ceramic dielectric substrate, and the fifth layer first metal plane forms the first inter-stage coupling capacitance C1 and the fourth coupling capacitance C4 with the fourth layer first metal plane and the fourth layer second metal plane respectively, and forms the seventh ground capacitance C7 with the second layer first metal pattern;

[0013] The sixth layer, the sixth layer first metal plane and the sixth layer second metal plane are printed on the ceramic dielectric substrate, and the sixth layer first metal plane is connected with the metal plane conductor of the seventh layer through the twelfth connecting point column and the thirteenth connecting point column, and the sixth layer second metal plane is connected with the seventh layer second metal plane through the fourteenth connecting point column and the fifteenth connecting point column;

[0014] The seventh layer, the seventh layer first metal plane and the seventh layer second metal plane are printed on the ceramic dielectric substrate, and the seventh layer first metal plane is connected with the eighth layer first metal plane and the eighth layer third metal plane through the sixteenth connecting point column and the seventeenth connecting point column respectively; and the seventh layer second metal plane is connected with the eighth layer second metal plane and the eighth layer fourth metal plane through the eighteenth connecting point column and the nineteenth connecting point column respectively;

[0015] The eighth layer, the eighth layer first metal plane, the eighth layer second metal plane, the eighth layer third metal plane, the eighth layer fourth metal plane, the eighth layer fifth metal plane, the eighth layer sixth metal plane and the eighth layer seventh metal plane are printed on the ceramic medium substrate; the eighth layer first metal plane is connected to the fourth layer first metal plane through the tenth connecting point column; the eighth layer second metal plane is connected to the fourth layer second metal plane and the seventh layer second metal plane through the eleventh connecting point column and the eighteenth connecting point column; the eighth layer third metal plane is connected to the second layer first metal pattern and the seventh layer first metal plane through the fourth connecting point column and the seventeenth connecting point column; the eighth layer fourth metal plane is connected to the second layer first metal pattern and the seventh layer second metal plane through the fifth connecting point column and the nineteenth connecting point column; the eighth layer fifth metal plane, the eighth layer sixth metal plane and the eighth layer seventh metal plane are connected to each other, wherein the eighth layer fifth metal plane is connected to the second layer first metal pattern through the sixth connecting point column and the seventh connecting point column, the eighth layer sixth metal plane is connected to the second layer first metal pattern and the third layer metal plane conductor through the sixth connecting point column and the eighth connecting point column, and the eighth layer seventh metal plane is connected to the second layer first metal pattern and the third layer second metal plane through the seventh connecting point column and the ninth connecting point column.

[0016] The sixth layer first metal plane, the seventh layer first metal plane, the eighth layer first metal plane, the eighth layer third metal plane, the fourth connecting point column, the tenth connecting point column, the twelfth connecting point column, the thirteenth connecting point column, the sixteenth connecting point column and the seventeenth connecting point column constitute a first ground inductance L1; the sixth layer second metal plane, the seventh layer second metal plane, the eighth layer second metal plane, the eighth layer fourth metal plane and the fifth connecting point column, the eleventh connecting point column, the fourteenth connecting point column, the fifteenth connecting point column, the eighteenth connecting point column and the nineteenth connecting point column constitute a second ground inductance L2; the eighth layer seventh metal plane, the seventh connecting point column and the ninth connecting point column constitute a third ground inductance L3 of a second-order LC parallel resonator; and the spatial coupling between the second ground inductance L2 and the third ground inductance L3 forms a fifth coupling inductance L5 between the two LC parallel resonators.

[0017] Further, a direction identification pattern is printed on the surface of the ceramic body.

[0018] Further, the phase difference caused by the inter-stage capacitance is +90°, the phase difference caused by the ground capacitance is -90°, the phase difference caused by the inter-stage inductance is -90°, and the phase difference caused by the LC parallel resonator is -90° when the frequency is lower than the resonant frequency and is +90° when the frequency is higher than the resonant frequency.

[0019] The beneficial effect of the present application is that the present application is based on LTCC (low temperature co-fired ceramic) technology, and adopts a four-stage cross-coupling filter lumped parameter model to design and realize the special electrical performance requirements of the novel laminated chip band-pass filter. The present application effectively realizes the characteristics of the LTCC multilayer band-pass filter, and has the advantages of low loss, high harmonic suppression, small size, high reliability, low cost and suitability for large-scale production, and in addition, it also adapts to the development trend of new electronic component integration and miniaturization. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 It is an equivalent circuit schematic diagram of the novel laminated chip LTCC band-pass filter of the present application.

[0021] Figure 2 It is a node model of the equivalent circuit diagram of the novel laminated chip LTCC band-pass filter of the present application.

[0022] Figure 3 It is a three-dimensional schematic diagram of the appearance structure of the novel laminated chip LTCC band-pass filter of the present application.

[0023] Figure 4 It is a schematic diagram of the internal structure of the novel laminated chip LTCC band-pass filter of the present application.

[0024] Figure 5 It is a schematic diagram of the first layer plane structure of the present application.

[0025] Figure 6 It is a schematic diagram of the second layer circuit plane structure of the present application.

[0026] Figure 7 It is a schematic diagram of the third layer circuit plane structure of the present application.

[0027] Figure 8 It is a schematic diagram of the fourth layer circuit plane structure of the present application.

[0028] Figure 9 It is a schematic diagram of the fifth layer circuit plane structure of the present application.

[0029] Figure 10 It is a schematic diagram of the sixth layer circuit plane structure of the present application.

[0030] Figure 11 It is a schematic diagram of the seventh layer circuit plane structure of the present application.

[0031] Figure 12 It is a schematic diagram of the eighth layer circuit plane structure of the present application.

[0032] Figure 13is the product electrical frequency response curve, the new type of laminated chip LTCC band pass filter operating frequency band is 0.69GHz~15GHz, wherein the passband frequency band is 3.3GHz~5GHz. The figure contains the electrode 1 to electrode 2 port signal transmission curve S(2,1) and the return loss curve S(1,1) of electrode 1. DETAILED DESCRIPTION

[0033] The present case is further explained and described below in conjunction with the accompanying drawings.

[0034] Figure 1 is the equivalent circuit diagram of low insertion loss and high harmonic suppression LTCC band pass filter.

[0035] The new type of laminated chip band pass filter circuit is a four-order LC filter circuit, which contains two LC parallel resonators and two LC high pass filter circuits. The two LC high pass filter circuits are composed of the first ground inductance L1, the fourth ground inductance L4 and the fifth capacitor C5, the sixth capacitor C6; the two LC parallel resonators are composed of the second ground inductance L2, the third ground inductance L3 and the second ground capacitor C2, the third ground capacitor C3; in addition, the fifth inductance L5 is equivalent to the coupling inductance between the two LC parallel resonators, the fifth capacitor C5 and the sixth capacitor C6 are the coupling capacitors between the input and output ports, and the seventh ground capacitor C7 is the ground capacitor.

[0036] Figure 2 is the node model of the equivalent circuit diagram of the new type of low insertion loss and high harmonic suppression LTCC band pass filter, and there are two paths from the input port to the output port. The first path passes through the fifth capacitor C5, the LC parallel resonator ①, the fifth inductance L5, the LC parallel resonator ②, the sixth capacitor C6 to the output port, and the second path passes through the first coupling capacitor C1, the seventh ground capacitor C7, the fourth coupling capacitor C4 to the output port. Among them, the phase difference caused by the inter-stage capacitor is +90°, the phase difference caused by the ground capacitor is -90°, the phase difference caused by the inter-stage inductance is -90°, and the phase difference caused by the LC parallel resonator is ±90° (when lower than the resonance frequency, it is -90°, and when higher than the resonance frequency, it is +90°). When the input signal frequency is lower than the resonance frequency, the phase difference caused by the path (1) is +90°-90°-90°-90°+90°=-90°; when the input signal frequency is higher than the resonance frequency, the phase difference caused by the path (1) is +90°+90°-90°+90°+90°=+270°, and the phase difference caused by the signal passing through the path (2) is +90°-90°+90°=+90°. Therefore, no matter whether the input signal is lower or higher than the resonance frequency, the phase difference between the signals passing through the path (1) and the path (2) will be 180°, and through this ingenious design, a transmission zero point can be formed in the upper and lower sidebands of the filter.

[0037] Figure 3 The appearance structure of the new low insertion loss and high harmonic suppression LTCC band-pass filter, 40 is the direction mark of the product, 41 is the ceramic body of the product, mainly composed of alumina (Al2O3), calcium oxide (CaO), magnesium oxide (MgO) and silicon oxide (SiO2);

[0038] The internal structure of the new laminated chip LTCC band-pass filter is shown in Figure 4 The circuit structure is distributed inside the ceramic substrate. The circuit structure has twelve layers in total, please refer to Figures 5-12 The internal structure of the product from bottom to top is as follows:

[0039] The first layer, the first layer first metal pattern 1, the first layer second metal pattern 2 and the first layer third metal pattern 3 are printed on the ceramic medium substrate. The first layer first metal pattern 1 and the first layer second metal pattern 2 are the input and output ports of the filter, which are connected with the fourth layer first metal plane 16 and the fourth layer second metal plane 17 through the first connecting point column 4 and the second connecting point column 5 respectively; the first layer third metal pattern 3 is the ground plane of the first layer as the product, which is connected with the second layer first metal pattern 7 through the third connecting point column 6.

[0040] The second layer, the second layer first metal pattern 7 is printed on the ceramic medium substrate, which is connected with the eighth layer third metal plane 35 and the eighth layer fourth metal plane 36 which are insulated with each other through the fourth connecting point column 8 and the fifth connecting point column 9 respectively, and is connected with the eighth layer sixth metal plane 38 and the eighth layer seventh metal plane 39 which are insulated with each other through the sixth connecting point column 10 and the seventh connecting point column 11 respectively.

[0041] The third layer, the third layer first metal plane 12 and the third layer second metal plane 13 are printed on the ceramic medium substrate, which are connected with the eighth layer sixth metal plane 38 and the eighth layer seventh metal plane 39 which are insulated with each other through the eighth connecting point column 14 and the ninth connecting point column 15 respectively. The third layer first metal plane 12 and the second layer first metal pattern 7 form the second ground capacitance C2 and the third ground capacitance C3 of two LC parallel resonators.

[0042] The fourth layer, two mutually insulated metal planes are printed on the ceramic dielectric substrate, which are the fourth layer first metal plane 16 and the fourth layer second metal plane 17, which are connected to the mutually insulated eighth layer first metal plane 33 and the eighth layer second metal plane 34 of the eighth layer through the tenth connecting point column 18 and the eleventh connecting point column 19, and are connected to the first layer first metal pattern 1 and the first layer third metal pattern 3 through the first connecting point column 4 and the second connecting point column 5. The first metal plane 16 and the fourth layer second metal plane 17 form the fifth capacitor C5 and the sixth capacitor C6 with the third layer first metal plane 12 and the third layer second metal plane 13 respectively.

[0043] The fifth layer, the fifth layer first metal plane 20 is printed on the ceramic dielectric substrate, which forms the first inter-stage coupling capacitor C1 and the fourth coupling capacitor C4 with the fourth layer first metal plane 16 and the fourth layer second metal plane 17 respectively. It forms the seventh ground capacitor C7 with the second layer first metal pattern 7.

[0044] The sixth layer, two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, which are the sixth layer first metal plane 21 and the sixth layer second metal plane 22, and the sixth layer first metal plane 21 is connected to the metal plane conductor 27 of the seventh layer through the twelfth connecting point column 23 and the thirteenth connecting point column 25, and the sixth layer second metal plane 22 is connected to the seventh layer second metal plane 28 through the fourteenth connecting point column 24 and the fifteenth connecting point column 26.

[0045] The seventh layer, two mutually insulated metal plane conductors are printed on the ceramic dielectric substrate, which are the seventh layer first metal plane 27 and the seventh layer second metal plane 28, and the seventh layer first metal plane 27 is connected to the mutually insulated eighth layer first metal plane 33 and the eighth layer third metal plane 35 of the eighth layer through the sixteenth connecting point column 29 and the seventeenth connecting point column 31, and is connected to the sixth layer first metal plane 21 through the twelfth connecting point column 23 and the thirteenth connecting point column 25. The seventh layer second metal plane 28 is connected to the mutually insulated eighth layer second metal plane 34 and the eighth layer fourth metal plane 36 of the eighth layer through the eighteenth connecting point column 30 and the nineteenth connecting point column 32, and is connected to the sixth layer second metal plane 22 through the fourteenth connecting point column 24 and the fifteenth connecting point column 26.

[0046] The eighth layer, seven metal plane conductors are printed on the ceramic dielectric substrate, which are the eighth layer first metal plane 33, the eighth layer second metal plane 34, the eighth layer third metal plane 35, the eighth layer fourth metal plane 36, the eighth layer fifth metal plane 37, the eighth layer sixth metal plane 38 and the eighth layer seventh metal plane 39. The eighth layer first metal plane 33 is connected to the fourth layer first metal plane 16 and the seventh layer first metal plane 27 through the tenth connecting point column 18 and the sixteenth connecting point column 29 respectively. The eighth layer second metal plane 34 is connected to the fourth layer second metal plane 17 and the seventh layer second metal plane 28 through the eleventh connecting point column 19 and the eighteenth connecting point column 30 respectively. The eighth layer third metal plane 35 is connected to the second layer first metal pattern 7 and the seventh layer first metal plane 27 through the fourth connecting point column 8 and the seventeenth connecting point column 31 respectively. The eighth layer fourth metal plane 36 is connected to the second layer first metal pattern 7 and the seventh layer second metal plane 28 through the fifth connecting point column 9 and the nineteenth connecting point column 32 respectively. The eighth layer fifth metal plane 37, the eighth layer sixth metal plane 38 and the eighth layer seventh metal plane 39 are connected to each other, wherein the eighth layer fifth metal plane 37 is connected to the second layer first metal pattern 7 through the sixth connecting point column 10 and the seventh connecting point column 11. The eighth layer sixth metal plane 38 is connected to the second layer first metal pattern 7 and the third layer metal plane conductor 12 through the sixth connecting point column 10 and the eighth connecting point column 14 respectively. The eighth layer seventh metal plane 39 is connected to the second layer first metal pattern 7 and the third layer second metal plane 13 through the seventh connecting point column 11 and the ninth connecting point column 15 respectively. The sixth layer first metal plane 21, the seventh layer first metal plane 27, the eighth layer first metal plane 33, the eighth layer third metal plane 35 and the fourth connecting point column 8, the tenth connecting point column 18, the twelfth connecting point column 23, the thirteenth connecting point column 25, the sixteenth connecting point column 29 and the seventeenth connecting point column 31 together constitute a first ground inductance L1. The sixth layer second metal plane 22, the seventh layer second metal plane 28, the eighth layer second metal plane 34, the eighth layer fourth metal plane 36 and the fifth connecting point column 9, the eleventh connecting point column 19, the fourteenth connecting point column 24, the fifteenth connecting point column 26, the eighteenth connecting point column 30 and the nineteenth connecting point column 32 together constitute a second ground inductance L2. The eighth layer sixth metal plane 38 and the sixth connecting point column 10, the eighth connecting point column 14 constitute a second ground inductance L2 of a first order LC parallel resonator.

[0047] The eighth layer seventh metal plane 39 and the seventh connecting point column 11, the ninth connecting point column 15 constitute a third ground inductance L3 of a second order LC parallel resonator. The space coupling between the second ground inductance L2 and the third ground inductance L3 forms a coupling inductance L5 between the two LC parallel resonators, and the coupling inductance L5 can be enhanced by connecting the two inductances L2 and L3 through the eighth layer fifth metal plane 37.

Claims

1. An equivalent circuit of a low insertion loss high harmonic rejection LTCC bandpass filter, said equivalent circuit comprising an input port and an output port, characterized in that, The first passageway comprises a fifth capacitor C5, a fifth inductor L5 and a sixth capacitor C6 connected in series between the input port and the output port, wherein a first grounding inductor L1 is connected between the input port and the fifth capacitor C5, a second grounding inductor L2 and a second grounding capacitor C2 are connected in series between the fifth capacitor C5 and the fifth inductor L5, a third grounding capacitor C3 and a third grounding inductor L3 are connected in series between the fifth inductor L5 and the sixth capacitor C6, a fourth grounding inductor L4 is connected between the sixth capacitor C6 and the output port, the first grounding inductor L1, the fourth grounding inductor L4 and the fifth capacitor C5 and the sixth capacitor C6 form an LC high-pass filter circuit, and the second grounding inductor L2 and the third grounding inductor L3 and the second grounding capacitor C2 and the third grounding capacitor C3 form two LC parallel resonators; the second passageway comprises a first coupling capacitor C1 and a fourth coupling capacitor C4 connected in series between the input port and the output port, and a seventh grounding capacitor C7 is arranged between the first coupling capacitor C1 and the fourth coupling capacitor C4.

2. A filter implementing the equivalent circuit of the low insertion loss high harmonic suppression LTCC bandpass filter as claimed in claim 1, characterized in that, The filter comprises a ceramic body, a circuit structure layer arranged in the ceramic body, and the circuit structure layer comprises: A first layer, a first layer first metal pattern (1), a first layer second metal pattern (2) and a first layer third metal pattern (3) are printed on the ceramic medium substrate; the first layer first metal pattern (1) and the first layer second metal pattern (2) are respectively input ports and output ports, and are connected with a fourth layer first metal plane (16) and a fourth layer second metal plane (17) through a first connecting point column (4) and a second connecting point column (5); the first layer third metal pattern (3) is a first layer grounding plane, which is connected with a second layer first metal pattern (7) through a third connecting point column (6); A second layer, a second layer first metal pattern (7) is printed on the ceramic medium substrate, and the second layer first metal pattern (7) is connected with an eighth layer third metal plane (35) and an eighth layer fourth metal plane (36) through a fourth connecting point column (8) and a fifth connecting point column (9), and is connected with an eighth layer sixth metal plane (38) and an eighth layer seventh metal plane (39) through a sixth connecting point column (10) and a seventh connecting point column (11); A third layer, a third layer first metal plane (12) and a third layer second metal plane (13) are printed on the ceramic medium substrate, and the third layer first metal plane (12) and the third layer second metal plane (13) are connected with the eighth layer sixth metal plane (38) and the eighth layer seventh metal plane (39) of the eighth layer which are insulated from each other through an eighth connecting point column (14) and a ninth connecting point column (15); the third layer first metal plane (12) and the second layer first metal pattern (7) form a second grounding capacitor C2 and a third grounding capacitor C3 of two LC parallel resonators; The fourth layer, the fourth layer first metal plane (16) and the fourth layer second metal plane (17) are printed on the ceramic dielectric substrate, the fourth layer first metal plane (16) and the fourth layer second metal plane (17) are connected with the eighth layer first metal plane (33), the eighth layer second metal plane (34) through the tenth connecting point column (18), the eleventh connecting point column (19), and are connected with the first layer first metal pattern (1) and the first layer third metal pattern (3) through the first connecting point column (4), the second connecting point column (5) respectively; the first metal plane (16) and the fourth layer second metal plane (17) form the fifth capacitor C5 and the sixth capacitor C6 with the third layer first metal plane (12), the third layer second metal plane (13) respectively; The fifth layer, the fifth layer first metal plane (20) is printed on the ceramic dielectric substrate, the fifth layer first metal plane (20) forms the first coupling capacitor C1 and the fourth coupling capacitor C4 with the fourth layer first metal plane (16), the fourth layer second metal plane (17) respectively, and forms the seventh ground capacitor C7 with the second layer first metal pattern (7); The sixth layer, the sixth layer first metal plane (21) and the sixth layer second metal plane (22) are printed on the ceramic dielectric substrate, the sixth layer first metal plane (21) is connected with the seventh layer metal plane conductor (27) through the twelfth connecting point column (23), the thirteenth connecting point column (25), and the sixth layer second metal plane (22) is connected with the seventh layer second metal plane (28) through the fourteenth connecting point column (24), the fifteenth connecting point column (26); The seventh layer, the seventh layer first metal plane (27) and the seventh layer second metal plane (28) are printed on the ceramic dielectric substrate, the seventh layer first metal plane (27) is connected with the eighth layer first metal plane (33), the eighth layer third metal plane (35) through the sixteenth connecting point column (29), the seventeenth connecting point column (31) respectively; the seventh layer second metal plane (28) is connected with the eighth layer second metal plane (34), the eighth layer fourth metal plane (36) through the eighteenth connecting point column (30), the nineteenth connecting point column (32) respectively; The eighth layer, the eighth layer first metal plane (33), the eighth layer second metal plane (34), the eighth layer third metal plane (35), the eighth layer fourth metal plane (36), the eighth layer fifth metal plane (37), the eighth layer sixth metal plane (38) and the eighth layer seventh metal plane (39) are printed on the ceramic dielectric substrate; the eighth layer first metal plane (33) is connected with the fourth layer first metal plane (16) through the tenth connecting point column (18) respectively; the eighth layer second metal plane (34) is connected with the fourth layer second metal plane (17) and the seventh layer second metal plane (28) through the eleventh connecting point column (19) and the eighteenth connecting point column (30) respectively; the eighth layer third metal plane (35) is connected with the second layer first metal pattern (7) and the seventh layer first metal plane (27) through the fourth connecting point column (8) and the seventeenth connecting point column (31) respectively; the eighth layer fourth metal plane (36) is connected with the second layer first metal pattern (7) and the seventh layer second metal plane (28) through the fifth connecting point column (9) and the nineteenth connecting point column (32) respectively; the eighth layer fifth metal plane (37), the eighth layer sixth metal plane (38) and the eighth layer seventh metal plane (39) are connected with each other, wherein the eighth layer fifth metal plane (37) is connected with the second layer first metal pattern (7) through the sixth connecting point column (10) and the seventh connecting point column (11), the eighth layer sixth metal plane (38) is connected with the second layer first metal pattern (7) and the third layer metal plane conductor (12) through the sixth connecting point column (10) and the eighth connecting point column (14) respectively, and the eighth layer seventh metal plane (39) is connected with the second layer first metal pattern (7) and the third layer second metal plane (13) through the seventh connecting point column (11) and the ninth connecting point column (15) respectively; The sixth layer first metal plane (21), the seventh layer first metal plane (27), the eighth layer first metal plane (33), the eighth layer third metal plane (35) and the fourth connecting point column (8), the tenth connecting point column (18), the twelfth connecting point column (23), the thirteenth connecting point column (25), the sixteenth connecting point column (29), the seventeenth connecting point column (31) constitute a first ground inductance L1; the sixth layer second metal plane (22), the seventh layer second metal plane (28), the eighth layer second metal plane (34), the eighth layer fourth metal plane (36) and the fifth connecting point column (9), the eleventh connecting point column (19), the fourteenth connecting point column (24), the fifteenth connecting point column (26), the eighteenth connecting point column (30), the nineteenth connecting point column (32) constitute a second ground inductance L2; the eighth layer seventh metal plane (39), the seventh connecting point column (11), the ninth connecting point column (15) constitute a third ground inductance L3 of a second order LC parallel resonator; the spatial coupling between the second ground inductance L2 and the third ground inductance L3 forms a fifth coupling inductance L5 between the two LC parallel resonators.

3. The filter of claim 2, wherein, The surface of the ceramic body is printed with a directional identification pattern.

4. The filter of claim 2, wherein, Wherein the phase difference caused by the inter-stage capacitor is +90°, the phase difference caused by the ground capacitor is -90°, the phase difference caused by the inter-stage inductor is -90°, and the phase difference caused by the LC parallel resonator is -90° when lower than the resonant frequency and +90° when higher than the resonant frequency.

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