Communication method and communication device

Abstract

A communication method and a communication apparatus based on an LDPC code, and a device can perform encoding or decoding based on an LDPC check matrix, the LDPC check matrix being determined based on an LDPC basis matrix and a second translation value of the basis matrix, the second translation value of the basis matrix being determined based on a first sequence and a first translation value of the basis matrix, and the first sequence being a sequence of the first sequence and the first translation value of the basis matrix. The first sequence indicates an association relationship between a row i of the basis matrix and a row theta (i) of the basis matrix, and a first translation value of the basis matrix is a predefined translation value. According to the method, more types of communication can be realized on the premise of not increasing a base graph and a corresponding translation value.

Description

Technical Field

[0001] This application relates to the field of coding, and more specifically, to a communication method and a communication device. Background Technology

[0002] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity check matrix, they can be encoded using simple feedback shift registers, reducing the coding complexity of LDPC codes.

[0003] Currently, the base graphs (BGs) of QC-LDPC codes described in the standard include BG1 and BG2. Future communication networks may have more diverse communication scenarios, such as high-throughput, low-power, ultra-reliable low-latency communication (URLLC) scenarios. Specifying the base graph and corresponding shift values ​​for each LDPC code separately would lead to cumbersome storage and complex standard descriptions. Summary of the Invention

[0004] Embodiments of this application provide a communication method and a communication device that can realize more types of communication without increasing the base map and the corresponding translation value.

[0005] In a first aspect, a communication method is provided, which can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0006] The method includes: acquiring an information bit sequence; determining an LDPC parity check matrix, wherein the LDPC parity check matrix is ​​determined based on an LDPC base matrix and a second shift value of the base matrix, wherein the second shift value of the base matrix is ​​determined based on a first sequence and a first shift value of the base matrix, the first sequence indicating the association between row i of the base matrix and row θ(i) of the base matrix, and the first shift value of the base matrix being a predefined shift value; encoding the information bit sequence according to the LDPC parity check matrix to obtain a codeword sequence; and outputting the codeword sequence.

[0007] In the above technical solution, different LDPC parity-check matrices can be generated based on the capabilities of the first sequence matching decoder or the requirements of the scenario, in order to achieve more types of communication, such as high-throughput communication or low-complexity communication.

[0008] Secondly, a communication method is provided, which can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the receiving device itself (e.g., a network device, a terminal device), a component in the receiving device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the receiving device.

[0009] The method includes: acquiring a codeword sequence; determining an LDPC parity-check matrix, wherein the LDPC parity-check matrix is ​​determined based on an LDPC base matrix and a second shift value of the base matrix, wherein the second shift value of the base matrix is ​​determined based on a first sequence and a first shift value of the base matrix, the first sequence indicating the association between row i of the base matrix and row θ(i) of the base matrix, and the first shift value of the base matrix being a predefined shift value; and decoding the codeword sequence according to the LDPC parity-check matrix to obtain an information bit sequence.

[0010] For the beneficial effects of the second aspect, please refer to the description of the first aspect, which will not be repeated here.

[0011] In some implementations of the first or second aspect, row i of the basis matrix is ​​not associated with any row of the basis matrix, and the second translation value of the element in row i is determined based on the first translation value of the element in row i.

[0012] In some implementations of the first or second aspect, the second translation value of the element (i,j) in row i and column j of the basis matrix is ​​equal to the first translation value of the element (i,j).

[0013] In some implementations of the first or second aspect, row i of the basis matrix is ​​associated with row θ(i) of the basis matrix, and the second translation value of the element in row i is determined based on the first translation value of the element in row θ(i) or the second translation value of the element in row θ(i).

[0014] In some implementations of the first or second aspect, the second translation value of an element in row i is determined based on the first translation value of an element in row θ(i) and the first translation value of an element in row i, or the second translation value of an element in row i is determined based on the second translation value of an element in row θ(i) and the first translation value of an element in row i.

[0015] In some implementations of the first or second aspect, if any row in the basis matrix satisfies that row i of the basis matrix is ​​associated with row θ(i) of the basis matrix, and row θ(i) of the basis matrix is ​​not associated with any row in the basis matrix, then the second shift value of the element in row i is determined based on the first shift value of the element in row θ(i).

[0016] In the above technical solution, the advantage of obtaining the second translation value is that the implementation complexity is low, the second translation values ​​of different rows of the basis matrix can be obtained in parallel, and the additional latency is small.

[0017] In some implementations of the first or second aspect, the first translation value of the element (θ(i),j) in row θ(i) and column j of the basis matrix and the first translation value of the element (i,j) in row i and column j of the basis matrix are not equal to the first value. The second translation value of the element (i,j) is determined based on the first translation value of the element (θ(i),j). The first value indicates that there is no translation value. The first translation value of the element (θ(i),j) or the first translation value of the element (i,j) is equal to the first value. The second translation value of the element (i,j) is determined based on the first translation value of the element (i,j).

[0018] In some implementations of the first or second aspect, if there exists a row i in the basis matrix such that row i is associated with row θ(i) of the basis matrix, and row θ(i) in the basis matrix is ​​associated with row θ(θ(i)), then the second shift value of the element in row i is determined based on the second shift value of the element in row θ(i).

[0019] In the above technical solution, the advantage of obtaining the second translation value is that the design of the first sequence and the basis matrix has more space, allowing the parent node to have multiple splits, resulting in better actual performance.

[0020] In some implementations of the first or second aspect, the second translation value of the element (θ(i),j) in row θ(i) and column j of the basis matrix and the first translation value of the element (i,j) in row i and column j of the basis matrix are both not equal to the first value. The second translation value of the element (i,j) is determined based on the second translation value of the element (θ(i),j). The first value indicates that there is no translation value. The second translation value of the element (θ(i),j) or the first translation value of the element (i,j) is equal to the first value. The second translation value of the element (i,j) is determined based on the first translation value of the element (i,j).

[0021] In some implementations of the first or second aspect, the first translation value of element (i,j) is equal to the first value, and the second translation value of element (i,j) is determined based on the first translation value of element (i,j), including: the second translation value of element (i,j) is equal to the first value.

[0022] In some implementations of the first or second aspect, the second shift value of the element in row i is determined based on the first or second shift value of the element in row θ(i), and a predefined numerical value k(i) associated with row i, where k(i) is an integer.

[0023] In some implementations of the first or second aspect, k(i) is determined based on the first translation value of the element (i, c(i)) in row i and column c(i) of the basis matrix, where column c(i) is the extended check column associated with row i.

[0024] In some implementations of the first or second aspect, before determining the LDPC parity check matrix, the method further includes: determining the LDPC parity check matrix using a second translation value of the base matrix based on first information, wherein the first information includes the coding code rate and / or the number of matrix rows corresponding to the coding code rate, the number of matrix rows corresponding to the coding code rate is the number of rows remaining in the rows corresponding to the first matrix excluding the core rows, and the first matrix is ​​the region in the base matrix corresponding to the coding code rate.

[0025] In the above technical solution, the encoding chain can have two branches. The main characteristic of the different branches lies in the different shift values ​​used to determine the LDPC parity check matrix. That is, the transmitting device can determine the LDPC parity check matrix based on the second shift value of the base matrix described in this application, or it can directly determine the LDPC parity check matrix based on the first shift value of the base matrix. The advantage of this implementation is that it is compatible with existing communication protocols and existing communication equipment, and can select a more suitable communication scheme according to different scenarios, requirements, and equipment capabilities, ensuring optimal performance in every bit rate range.

[0026] In some implementations of the first or second aspect, determining the LDPC parity check matrix using a second translation value of the base matrix based on first information includes: determining the LDPC parity check matrix using a second translation value based on a first association relationship and the first information, wherein the first association relationship indicates that any one of a plurality of code rate intervals supported by the base matrix is ​​associated with the first translation value or the second translation value of the base matrix, wherein associating a code rate interval with the first translation value indicates determining the coding matrix based on the first translation value of the base matrix, and associating a code rate interval with the second translation value indicates determining the coding matrix based on the second translation value of the base matrix, wherein the coding code rate is located in a first code rate interval of the plurality of code rate intervals, and the first code rate interval is associated with the second translation value of the base matrix.

[0027] In some implementations of the first or second aspect, determining the LDPC parity check matrix using a second translation value of the base matrix based on the first information includes: determining the LDPC parity check matrix using a second translation value of the base matrix based on a first rule and the first information, wherein the first rule indicates that among all rows associated with the number of rows of the matrix corresponding to the coding code rate, there exists at least one row m associated with row θ(m) of the base matrix, then the second translation value of the base matrix is ​​used to determine the coding matrix; and each row among all rows associated with the number of rows of the matrix corresponding to the coding code rate is not associated with any row of the base matrix, then the first translation value of the base matrix is ​​used to determine the coding matrix, wherein at least one row m among the rows associated with the number of rows of the matrix corresponding to the coding code rate is associated with row θ(m) of the base matrix.

[0028] In some implementations of the first or second aspect, determining the LDPC parity check matrix using a second shift value of the base matrix based on the first information includes: determining the LDPC parity check matrix using a second shift value of the base matrix based on a first code rate threshold and the first information; if the coding code rate is less than the first code rate threshold, then the coding matrix is ​​determined using the second shift value of the base matrix; otherwise, the coding matrix is ​​determined using the first shift value of the base matrix, wherein the coding code rate is less than the first code rate threshold.

[0029] In some implementations of the first or second aspect, before determining the LDPC parity check matrix, the method further includes: determining the LDPC parity check matrix using a second shift value of the base matrix based on a second rule, wherein the second rule instructs that the coding matrix be determined using the second shift value of the base matrix in a high-throughput scenario, otherwise, the coding matrix is ​​determined using a first shift value of the base matrix.

[0030] In some implementations of the first or second aspect, the high throughput scenario is a communication scenario that satisfies at least one of the following conditions: the coding code rate is greater than or equal to the code rate threshold, the modulation order is greater than or equal to the order threshold, the coding modulation scheme (MCS) is greater than or equal to the level threshold, the length of the transport block (TB) of the entire communication is greater than or equal to the length threshold, the number of coded blocks (CB) is greater than or equal to the number threshold, the number of streams in multiple-input multiple-output (MIMO) is greater than or equal to the number of streams threshold, and finite buffer rate matching (LBRM) is enabled.

[0031] In some implementations of the first or second aspect, row i of the basis matrix is ​​associated with row θ(i) of the basis matrix, and row i satisfies a first condition: the first condition is α(i)≤α0, where α(i) is the number of columns j in which the element (i, j) of column j in row i of the basis matrix is ​​1 and the element (θ(i), j) of column j in row θ(i) of the basis matrix is ​​0, and α0 is a threshold; or, the first condition is α(i)≤α1*w(i), where w(i) is the number of elements in row i that are 1, and α1 is a threshold; or, the first condition is α(i)≤α2*w(θ(i)), where w(θ(i)) is the number of elements in row θ(i) that are 1, and α2 is a threshold.

[0032] In some implementations of the first or second aspect, α0 takes the value of 0, 1 or 2, α1 takes the value of 0≤α1≤2 / w(i) or 0≤α1≤1 / w(i), and α2 takes the value of 0≤α2≤2 / w(θ(i)) or 0≤α2≤1 / w(θ(i)).

[0033] In some implementations of the first or second aspect, the basis matrix is ​​a base. Figure 1 or base Figure 2 ,base Figure 1 The first translation value is shown in Table 3, based on Figure 2 The first translation value is shown in Table 4.

[0034] In some implementations of the first or second aspect, the fixed number of punched columns in the basis matrix is ​​P, where 0 ≤ P ≤ 2.

[0035] Thirdly, a communication apparatus is provided for performing the method provided by any of the above aspects or their implementations. Specifically, the apparatus may include units and / or modules for performing the method provided by any of the above aspects or their implementations, such as processing units and / or transceiver units.

[0036] In one implementation, the device is either a transmitting device or a receiving device. When the device is a transmitting device or a receiving device, the transceiver unit can be a transceiver, an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0037] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device. When the device is a chip, chip system, or circuit used in a transmitting or receiving device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0038] Fourthly, a communication device is provided, comprising: a memory for storing a program; and at least one processor for executing the computer program or instructions stored in the memory to perform the method provided in any of the foregoing aspects or their implementations.

[0039] In one implementation, the device is either a transmitting device or a receiving device.

[0040] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device.

[0041] Fifthly, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to obtain a computer program or instructions stored in a memory via the communication interface to execute the method provided in any of the foregoing aspects or their implementations. The communication interface may be implemented in hardware or software.

[0042] In one implementation, the device further includes the memory.

[0043] Sixthly, a processor is provided for executing the methods provided in the above aspects.

[0044] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0045] In a seventh aspect, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including methods for performing any of the foregoing aspects or their implementations.

[0046] Eighthly, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method provided in any of the foregoing aspects or their implementations.

[0047] Ninthly, a chip is provided, comprising a processor and a communication interface. The processor reads instructions stored in a memory through the communication interface and executes the methods provided in any of the above aspects or their implementations. The communication interface can be implemented in hardware or software.

[0048] Optionally, as one implementation, the chip also includes a memory that stores computer programs or instructions. The processor is used to execute the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to perform the methods provided by any of the above aspects or their implementations.

[0049] When the method provided in this application is executed by a chip, this application does not limit the specific number of chips implementing the method. For example, it can be executed by one chip, or by two or more chips. Furthermore, when the number of chips implementing the method is two or more, the chip manufacturers are not limited; they can be from the same manufacturer or different manufacturers.

[0050] In a tenth aspect, a computer program is provided that, when run on a computer, causes the methods provided by any of the foregoing aspects or their implementations to be executed.

[0051] Eleventhly, a communication system is provided, including at least one of the transmitting end device or receiving end device described above. Attached Figure Description

[0052] Figure 1 This is a schematic diagram of a network architecture that can be applied to embodiments of this application.

[0053] Figure 2 This is a schematic diagram of the parity check matrix H of an LDPC.

[0054] Figure 3 This is a Tanner plot of the parity-check matrix H of an LDPC.

[0055] Figure 4 This is a schematic diagram of the structure of the parity check matrix.

[0056] Figure 5 This is a schematic diagram of the information transmission process.

[0057] Figure 6 This is a schematic flowchart of a communication method 600 provided in this application.

[0058] Figure 7 and Figure 8 This is a schematic diagram of the first and second translation values ​​of the basis matrix in scenario one.

[0059] Figure 9 and Figure 10This is a schematic diagram of the first and second translation values ​​of the basis matrix in scenario two.

[0060] Figure 11 This is a performance simulation diagram of the LDPC code determined based on the second translation value proposed in this application and the LDPC code determined based on the first translation value.

[0061] Figure 12 This is a schematic block diagram of the communication device 1000 provided in the embodiments of this application.

[0062] Figure 13 A schematic block diagram of a communication device 1100 provided in an embodiment of this application. Detailed Implementation

[0063] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0064] The terms "for indicating" or "instruction" can include both direct and indirect indication, or they can be explicit and / or implicit. The various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words "exemplary," "for example," "exemplary," "as another example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, while "more" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element A sending messages, information, or data to network element B, and network element B receiving messages, information, or data from network element A, aim to specify which network element the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when," "under the circumstances," "if," and "if" indicate that the device will take corresponding action under certain objective conditions, not that there is a time limit, nor do they require the device to perform a judgment action during implementation, nor do they imply any other limitations.

[0065] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0066] The following describes a communication system to which embodiments of this application can be applied.

[0067] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, long term evolution-advanced (LTE-A) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0068] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0069] Figure 1 This is a schematic diagram of a network architecture applicable to embodiments of this application. For example... Figure 1 As shown, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 This document uses only uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as examples. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application to other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0070] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0071] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home-evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, or RAN equipment including CU and DU nodes, or RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes. Alternatively, network equipment may also be a radio controller, relay station, vehicle-mounted equipment, or wearable device in a cloud radio access network (CRAN) scenario. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future communication networks, or equipment performing base station functions in future communication systems. A base station may support networks with the same or different access technologies, without limitation.

[0072] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0073] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0074] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, ultra-reliable low-latency communication (URLLC) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0075] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0076] 1. LDPC code

[0077] LDPC codes are a type of linear block code. Linear block codes divide the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving equipment decodes the received signal to determine the original information bits.

[0078] The parity-check matrix H of an LDPC is a sparse matrix. The number of zero elements in the parity-check matrix H is far greater than the number of non-zero elements; in other words, the row weight (or column weight) of the parity-check matrix is ​​far less than the number of elements in each row (or column) of the LDPC matrix. Specifically, an LDPC code with an information bit sequence length of q and a code length of n can be uniquely determined by its parity-check matrix H.

[0079] Tanner represented the parity-check matrix H graphically in 1981; this type of graph is now called a Tanner graph. There is a one-to-one correspondence between Tanner graphs and parity-check matrices. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes; the other type consists of parity nodes, representing parity constraints. Each parity node represents a parity constraint. The following section will discuss this in conjunction with... Figure 2 and Figure 3 Please provide an explanation.

[0080] Figure 2 This is a schematic diagram of the parity check matrix H of an LDPC.

[0081] Figure 2 In the middle, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CN). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. Figure 2 In the diagram, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner diagram.

[0082] Figure 3 The Tanner plot of the parity-check matrix H of an LDPC.

[0083] like Figure 3As shown, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph consists of interconnected vertices. The cycle starts and ends at one vertex in this group of vertices and passes through each node only once. The length of a cycle is defined as the number of edges it contains, while the perimeter of the graph, also known as the circumference, is defined as the minimum cycle length in the graph. Figure 3 In the middle, the circumference is 4, such as Figure 3 The diagram shows the black lines connecting the variable nodes in the Tanner graph. Variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. Parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to the parity bits in the LDPC. The connection between two types of nodes corresponds to the value of an element in the H matrix. If there is a connection between the i-th parity node and the j-th variable node, the element (i, j) in the H matrix has a value of 1; otherwise, the corresponding element is 0. The connection between a variable node and a parity node can also be called an edge. A connection between a parity node and a variable node can also be described as: there is a connection or an edge between the parity node and the variable node. The edge relationship between a parity node and a variable node can include either the presence of an edge or the absence of an edge. Furthermore, in the Tanner graph, a cycle is a closed loop formed by connecting variable nodes, parity nodes, and edges end-to-end.

[0084] 2. QC-LDPC code

[0085] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be implemented using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented using a base graph (BG), where elements are either 0 or 1. Expanding the 1s and 0s in the BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, the BG can be written in matrix form, which can be referred to as the base matrix H in this application. BG Basis matrix H BGAn element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The expansion process of the base matrix is ​​described below.

[0086] Based on the basis matrix and the boosting value Z c (Lifting size) allows the basis matrix to be expanded into a complete parity-check matrix for encoding or decoding. In this application, Z... c It can also be called the expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The expansion process involves lifting all elements in the basis matrix to a Z-shape. c ×Z c A square matrix, in which 0 is promoted to Z. c ×Z c The zero matrix is ​​promoted to an identity matrix, and then cyclically shifted based on the shifting value (SV) corresponding to the 1. This cyclic shift can be to the left or right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values ​​are 0, 1, and 3, the cyclically shifted matrix after shifting to the right is as follows:

[0087] (1) When the translation value is 0 (i.e., remains unchanged), the corresponding cyclically shifted matrix is:

[0088] (2) When the translation value is 1, the corresponding cyclically shifted matrix is:

[0089] (3) When the translation value is 3, the corresponding cyclically shifted matrix is:

[0090] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the array corresponds to a Z. c ×Z c The submatrix is ​​represented by an exponential matrix H, where each element indicates the number of times the corresponding submatrix has been cyclically shifted by the identity matrix. This significantly reduces the storage space required for the complete parity check matrix H. b The elements in it can also be called QC blocks.

[0091] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0092]

[0093] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the array represents a Z. c Square matrix of order Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0094] For example, As shown below:

[0095]

[0096] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0097] It is understandable that the above exponent matrix H... b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are then expanded into a cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained.

[0098] 3. Increase value Z c (Lifting Size) and (Shifting Value)

[0099] The storage content of the 5G LDPC code regarding shifting values ​​includes: (1) a list of lifting sizes; and (2) a list of shifting values ​​that correspond one-to-one with the rows of the lifting size list.

[0100] For example, the list of Lifting Sizes is shown in Table 1.

[0101] Table 1

[0102] Promotion Index Promotion value set 0 {2,4,8,16,32,64,128,256} 1 {3,6,12,24,48,96,192,384} 2 {5,10,20,40,80,160,320} 3 {7,14,28,56,112,224} 4 {9,18,36,72,144,288} 5 {11,22,44,88,176,352} 6 {13,26,52,104,208} 7 {15,30,60,120,240}

[0103] The j-th row of the Lifting Size list includes Where a j ∈{2,3,5,7,9,11,13,15}, max(k j)∈{7,7,6,5,5,5,4,4}; The row index of Lifting Size corresponds one-to-one with the column index of Shifting Value, that is, the lifting size in each row of the Lifting Size list corresponds to a set of Shifting Values.

[0104] For example, the list of Shifting Values ​​is shown in Table 2.

[0105] Table 2

[0106]

[0107] It is understandable that the basis matrix H BG The elements in the matrix include 0 and 1, meaning all elements are either 0 or 1. Table 2 stores all rows of the base matrix and the associated columns for each row. If an associated column exists, it indicates that the value at that position in the base matrix is ​​1; otherwise, it is 0.

[0108] For a fixed lift index, a non-zero position in the base matrix corresponds to one translation value. For example, H... BG The shift value corresponding to row 0, column 0 when the promotion index is 0 is 211, H BG The shift value corresponding to the 6th column of the 1st row in the middle when the lifting index = 3 is 66, H BG The shift value corresponding to the second row and ninth column of the middle column when the promotion index is 7 is 206.

[0109] It's understandable that LDPC encoding requires first determining the lift value, and then constructing a parity check matrix based on the corresponding shift value. For example, if the determined lift value is 40, and the lift value index corresponding to 40 in Table 1 is 2, then the parity check matrix can be constructed based on the shift value in the column corresponding to lift value index = 2 in Table 2.

[0110] 4. Column weight and row weight

[0111] For a given column of a matrix, column weight refers to the number of non-zero elements contained in that column. For a given row of a matrix, row weight refers to the number of non-zero elements contained in that row. It can be understood that the matrix involved in the descriptions of row and column weights is the parity check matrix H.

[0112] 5. Structure of the basis matrix

[0113] Figure 4 This is a schematic diagram of the structure of the parity check matrix.

[0114] like Figure 4As shown in (a), the parity-check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include... Figure 4 Parts A and B are shown in (b) above. Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest bit rate, or a parity where all degrees are greater than or equal to 2, or a parity node corresponding to the set of rows with the highest row weight (row weight significantly higher than other rows). A region of all zeros can correspond to... Figure 4 In (b) of the matrix, part C is an all-zero matrix. The incremental redundancy region can correspond to... Figure 4 Part D of (b) in the diagram. The Laptian-like region can correspond to... Figure 4 The E part of (b) can be an identity matrix, corresponding to the parity bits of the low code rate extension.

[0115] Figure 4 The parity-check matrix of the LDPC code shown adopts a "raptor-like" structure, which can be gradually extended to low code rates from a high-rate core matrix. In practical use, such as... Figure 4 As shown in (a), the first X rows and first Y columns of the parity check matrix can be extracted. As the bitrate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0116] It should be noted that the parity check matrix can be represented by the LDPC basis matrix. Therefore, the structure of the LDPC basis matrix is ​​similar to that of the parity check matrix, and will not be described in detail here.

[0117] 6. Information column and validation column

[0118] The columns of the LDPC base matrix consist of information columns and check columns.

[0119] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to part A.

[0120] Check columns: Corresponding to check bits (or check digits, etc.), these can include core check columns and extended check columns. The core check columns are the columns corresponding to part B, and the extended check columns are the columns corresponding to part C or part E. Extended check columns can also be called raptor-like columns.

[0121] 7. Core rows, core columns, core matrix, and core check columns

[0122] Core rows: The core rows of the LDPC base matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or the rows corresponding to parts A, B, or C.

[0123] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to part A plus part B.

[0124] The kernel matrix is ​​a matrix region consisting of all the kernel rows and columns of the LDPC base matrix. In other words, the kernel matrix is ​​the high-rate region of the LDPC base matrix, or the part consisting of part A and part B.

[0125] Core check columns: N columns following the information columns in the LDPC base matrix, where N equals the number of rows corresponding to the core rows. For example, the information columns are 1 to K. b If the column is K, then the core verification column is K. b +1 to K b +N columns.

[0126] 8. Message length, code length, and code rate

[0127] The information length is the length of the bit sequence of information to be sent (i.e., the number of bits contained therein). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0128] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0129] Code rate refers to the ratio of the length of the bit sequence of information to be transmitted to the code length.

[0130] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, media access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS).

[0131] 9. Information Transmission Process

[0132] Figure 5This is a schematic diagram illustrating the information transmission process applicable to this application. For example... Figure 5 As shown, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery before reaching the destination, completing the transmission of information from the source to the destination. Among these processes, Figure 5 The upper-layer processing (including source coding, channel coding, and modulation) is performed at the transmitting end device, while the lower-layer processing (including demodulation, channel decoding, and source recovery) is performed at the receiving end device. The embodiments of this application mainly relate to... Figure 5 The diagram shows source coding, channel coding, channel decoding, and source recovery.

[0133] Currently, the 5G communication protocol standard describes two base maps: BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or less than or equal to 3840 and the code rate is less than or equal to 2 / 3, or less than or equal to 0.25; otherwise, BG1 is used. It can be understood that the BG1 (or BG2) described in this application refers to 5G's BG1 (or BG2), or NR's BG1 (or BG2). Future communication networks may have more communication scenarios, such as high throughput, low power consumption, and URLLC. If the base map and corresponding shift amount of the LDPC code are specified separately for each scenario, the number of base maps will be very large, and the standard description will be complex.

[0134] In view of this, this application proposes a communication method based on LDPC codes, which can effectively solve the above-mentioned technical problems.

[0135] Figure 6 This is a schematic flowchart of a communication method 600 based on LDPC codes provided in this application. The method includes the following steps.

[0136] It is understood that method 600 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to implement this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0137] S610, the transmitting device obtains the information bit sequence.

[0138] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, then the sending device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0139] The process of the transmitting device acquiring the information bit sequence can refer to: the transmitting device performing source encoding on the source symbols to generate the information bit sequence; or, the transmitting device acquiring the information bit sequence can also refer to: the transmitting device receiving the information bit sequence from other communication devices. This application does not limit the method of acquiring the information bit sequence.

[0140] S620, the transmitting device determines the LDPC check matrix.

[0141] The LDPC parity check matrix is ​​determined based on the LDPC basis matrix (hereinafter referred to as the basis matrix) and the second translation value of the basis matrix. The second translation value of the basis matrix is ​​determined based on the first sequence and the first translation value of the basis matrix. The first sequence indicates the relationship between row i of the basis matrix and row θ(i) of the basis matrix. The first translation value of the basis matrix is ​​a predefined translation value.

[0142] The following section provides a detailed explanation of each part used to determine the LDPC parity-check matrix.

[0143] (1) The first translation value of the basis matrix, wherein the first translation value of the basis matrix is ​​a predefined translation value.

[0144] Optionally, the basis matrix can be BG1 or BG2. The fixed number of punched columns in BG1 or BG2 is P, where 0 ≤ P ≤ 2.

[0145] Optionally, the first shift value of BG1 and BG2 can be the shift value of BG1 and BG2 defined in the 5G standard. Specifically, the shift values ​​of BG1 and BG2 defined in the 5G standard are shown in Table 3 and Table 4, respectively.

[0146] Table 3

[0147]

[0148]

[0149]

[0150]

[0151]

[0152]

[0153] Table 4

[0154]

[0155]

[0156]

[0157]

[0158] Optionally, the first translation value of BG1 is the translation value corresponding to the translation values ​​in Table 3 after partial modification. For example, the first translation value of BG1 includes 8 sets of translation values ​​corresponding to lifting indexes 0 to 7. Among them, the translation values ​​corresponding to some lifting indexes are consistent with Table 3, while the translation values ​​corresponding to the remaining lifting indexes can be different from Table 3. Another example is that the first translation value of BG1 includes 8 sets of translation values ​​corresponding to lifting indexes 0 to 7, where the basis matrix H corresponding to BG1... BG1 The translation value corresponding to region #1 is consistent with that in Table 3. For example, region #1 includes part A and part B; or, region #1 can be part A, part B, and part H. BG1 The D portion refers to rows whose line numbers are less than a certain threshold. For information on portions A, B, and D, please refer to [link to relevant documentation]. Figure 4 The description in (b) of the text.

[0159] Similarly, the first translation value table for BG2 is the translation value corresponding to the translation values ​​in Table 4 after some modifications. Examples will not be provided here.

[0160] (2) The first sequence θ, where the first sequence θ indicates the relationship between row i of the basis matrix and row θ(i) of the basis matrix. It can also be understood as the first sequence being used to indicate the relationship between rows of the basis matrix.

[0161] In one possible implementation, the first sequence θ includes m elements, where m is equal to the number of rows in the basis matrix. The m elements correspond one-to-one with the m rows of the basis matrix. It can be understood that the element among the m elements that corresponds to row i of the basis matrix is ​​θ(i).

[0162] For example, if the row numbers of the basis matrix start from 1, the value of element θ(i) in the first sequence can be the first character or a positive integer, where the first character is not equal to any positive integer. When θ(i) is a positive integer, it is less than i, meaning the value of θ(i) is less than the row number of the current row. For example, when θ(i) is a positive integer, it means that row i of the basis matrix is ​​associated with row θ(i); when θ(i) is the first character, it means that row i of the basis matrix is ​​not associated with any row in the basis matrix. The first character can be a number, letter, or symbol, etc., and this application does not limit this. For example, in this example, the first character can be 0.

[0163] It is understandable that if the row numbers of the base matrix start from row 0, then the first character cannot be 0, but can be other characters, such as -1, -2, etc. For ease of description, the following embodiments will be described with the row and column numbers of the base matrix starting from 1, and the first character being 0, that is, the element θ(i) in the first sequence has a value of 0 or a positive integer.

[0164] The implementation is illustrated with an example. The base matrix has m = 17 rows, and the first sequence θ has 17 elements, θ = {0,0,0,0,0,0,0,3,1,4,0,0,0,0,2,7,6}, which correspond one-to-one with rows 1 to 17 of the base matrix. Among them, θ(i) corresponding to rows i = 1,2,3,4,5,6,7,11,12,13,14 of the base matrix in the first sequence is 0, θ(8) corresponding to row 8 of the base matrix is ​​3 < 8, and θ(9) corresponding to row 9 of the base matrix is ​​1 < 9.

[0165] In another possible implementation, the first sequence θ only includes the row number i corresponding to the element θ(i) ≠ 0, and θ(i). Based on the example of the first sequence above, the information stored in the first sequence in this implementation is shown in Table 5.

[0166] Table 5

[0167] i 8 9 10 15 16 17 θ(i) 3 1 4 2 7 6

[0168] Optionally, if θ(i) ≠ 0 for row i indicated by the first sequence, then row i may satisfy the first condition.

[0169] One possible implementation is that the first condition is α(i) ≤ α0, where α(i) is the number of columns j where the element (i, j) in row i and column j of the basis matrix is ​​1 and the element (θ(i), j) in row θ(i) and column j of the basis matrix is ​​0, and α0 is the threshold #1. For example, α0 is an integer, and its specific value can be 0, 1, or 2.

[0170] For example, the range of j includes all columns of the base matrix, or the range of j includes the core column of the base matrix.

[0171] Another possible implementation is that the first condition is α(i)≤α1*w(i), where w(i) is the number of elements with a value of 1 in row i, and α1 is the threshold #2.

[0172] For example, w(i) is the number of elements (i, j) in the basis matrix that have a value of 1, where the range of j includes all columns of the basis matrix, or the range of j includes the core column of the basis matrix.

[0173] For example, 0≤α1≤1, and the range of α1 is 0≤α1≤2 / w(i), or 0≤α1≤1 / w(i).

[0174] Another possible implementation is that the first condition is α(i)≤α2*w(θ(i)), where w(θ(i)) is the number of elements with a value of 1 in row θ(i), and α2 is the threshold #3.

[0175] For example, w(θ(i)) is the number of elements (θ(i), j) of the basis matrix that have a value of 1, where the range of j includes all columns of the basis matrix, or the range of j includes the core column of the basis matrix.

[0176] For example, 0≤α2≤1, the range of α2 is 0≤α2≤2 / w(θ(i)), or 0≤α2≤1 / w(θ(i)).

[0177] (3) The second translation value of the basis matrix, wherein the second translation value of the basis matrix is ​​determined based on the first sequence and the first translation value of the basis matrix.

[0178] a) If the first sequence indicates that row i of the basis matrix is ​​not associated with any row of the basis matrix (i.e., θ(i) = 0), the second shift value of the element in row i is determined based on the first shift value of the element in row i. For example, the second shift value of the element (i,j) in row i and column j of the basis matrix is ​​equal to the first shift value of the element (i,j).

[0179] b) If the first sequence indicates that row i of the basis matrix is ​​associated with row θ(i) of the basis matrix (i.e., θ(i) ≠ 0), the second shift value of the element in row i is determined based on either the first shift value of the element in row θ(i) or the second shift value of the element in row θ(i). Examples are given below for different scenarios.

[0180] Scene 1

[0181] In this scenario, any row in the basis matrix satisfies that row i of the basis matrix is ​​associated with row θ(i), and row θ(i) of the basis matrix is ​​not associated with any row in the basis matrix (i.e., for any row i where θ(i) ≠ 0, θ(θ(i)) = 0). Then, the second shift value of the element in row i is determined based on the first shift value of the element in row θ(i).

[0182] Optionally, in the above scenario, the second translation value of the element in row i is determined based on the first translation value of the element in row θ(i) and the first translation value of the element in row i. The following explains how to determine the second translation value of the element in row i in different cases, where the element (a,b) of the basis matrix represents the element in row a and column b of the basis matrix, SV1(a,b) represents the first translation value of element (a,b), and SV2(a,b) represents the second translation value of element (a,b).

[0183] Scenario 1

[0184] If neither the first translation value of element (θ(i),j) nor the first translation value of element (i,j) of the basis matrix is ​​equal to the first value, the second translation value of element (i,j) is determined based on the first translation value of element (θ(i),j), where the first value indicates that no translation value exists (e.g., the first value is equal to -1). For example, the second translation value of element (i,j) is equal to the first translation value of element (θ(i),j), i.e., SV2(i,j) = SV1(θ(i),j).

[0185] It can be understood that if the translation value of an element in the basis matrix does not exist, then the value of that element is 0, or the element is empty.

[0186] Optionally, the second shift value of element (i,j) is determined based on the first shift value of element (θ(i),j) and a predefined value k(i) associated with row i, where k(i) is an integer. For example, SV2(i,j) = SV1(θ(i),j) + k(i).

[0187] In one possible implementation, k(i) is determined based on the first translation value of the element (i, c(i)) of the basis matrix. For example, column c(i) is the extended check column associated with row i, or column c(i) is the column with the largest column number among all columns associated with row i, or column c(i) is the column with the largest column number in row i. Figure 4 The column associated in part E of (b) is either the column c(i) associated with row i and has a weight of 1.

[0188] For example, k(i) = SV1(i,c(i)), or k(i) = -SV1(i,c(i)), or k(i) = Zc - SVi(i,c(i)), where Zc is the lift value corresponding to the first translation value of the basis matrix.

[0189] In another possible implementation, k(i) is always equal to 0.

[0190] Scenario 2

[0191] If the first translation value of element (θ(i),j) of the basis matrix or the first translation value of element (i,j) of the basis matrix is ​​equal to the first value, the second translation value of element (i,j) is determined based on the first translation value of element (i,j).

[0192] It can be understood that if the first translation value of element (i,j) equals the first value, then the second translation value of element (i,j) equals the first value, that is, SV2(i,j)=SV1(θ(i),j)=the first value. That is, if the first translation value of element (i,j) does not exist (for example, equal to -1), then the second translation value of element (i,j) is also considered to not exist.

[0193] Optionally, if the first translation value of element (θ(i),j) is equal to the first value, but the first translation value of element (i,j) is not equal to the first value, then the second translation value of element (i,j) is equal to the first translation value of element (i,j); or, the second translation value of element (i,j) is determined based on the first translation value of element (i,j) and the predefined value k(i) associated with row i, for example, SV2(i,j) = SV1(i,j) + k(i).

[0194] In this scenario, for any row i where θ(i)≠0, θ(θ(o))=0. Therefore, the advantage of obtaining the second translation value in this scenario is that the implementation complexity is low, the second translation values ​​of different rows can be obtained in parallel, and the additional latency is small.

[0195] For example, based on the descriptions of cases one and two, one possible pseudocode for scenario one is shown below:

[0196] Obtain the first translation value SV1(i,j) of the basis matrix.

[0197] For any i∈1,…,m

[0198]

[0199] The following is combined Figure 7 and Figure 8 Let's take scenario one as an example. Figure 7 This is a schematic diagram showing the first translation value of the basis matrix, where, Figure 7 Each value in the pseudocode represents the first translation value of the element at the corresponding position in the basis matrix. A translation value of -1 indicates that the element at that position has no translation value. For example, the first sequence indicates that θ(i) = 0 for rows 1 to 8 of the basis matrix, and θ(9) = 1 for row 9 of the basis matrix, meaning that row 9 of the basis matrix is ​​associated with row 1. Based on the above pseudocode (k(i) = 0 in this example), we can obtain the following: Figure 8 The second translation value of the basis matrix shown is explained here, but only the second translation value corresponding to some elements in the 9th row of the basis matrix is ​​explained.

[0200] For example, for the element (9,2) of the basis matrix, SV1(9,2) and SV1(1,2) are not equal to -1, so SV2(9,2) = SV1(1,2) = 19. For another example, for the element (9,3) of the basis matrix, since SV1(9,3) is equal to -1, SV2(9,3) = SV1(9,3) = -1. For yet another example, for the element (9,25) of the basis matrix, SV1(1,25) is equal to -1, so SV2(9,25) = SV1(9,25) = 170. These details will not be elaborated further here.

[0201] Scene 2

[0202] In this scenario, there exists a row i in the basis matrix that is related to row i and row θ(i) of the basis matrix, and row θ(i) in the basis matrix is ​​related to row θ(θ(i)) of the basis matrix (i.e., there exists a row i where θ(i)≠0 and θ(θ(i))≠0). Then the second shift value of the element in row i is determined based on the second shift value of the element in row θ(i).

[0203] It is understandable that in this scenario, the second translation value is determined by nesting the row numbers of the base matrix in ascending order. Nesting means that the second translation value of the entire base matrix is ​​determined by looping through the row numbers only once. The second translation value of the larger row number will not affect the second translation value of the smaller row number, while the second translation value of the smaller row number will affect the second translation value of the larger row number.

[0204] Optionally, in the above scenario, the second translation value of the element in row i is determined based on the second translation value of the element in row θ(i) and the first translation value of the element in row i. The following explains how to determine the second translation value of the element in row i in different cases, where the element (a,b) of the base matrix represents the element in row a and column b of the base matrix, SV1(a,b) represents the first translation value of element (a,b), and SV2(a,b) represents the second translation value of element (a,b).

[0205] Scenario 1

[0206] If neither the second translation value of the element (θ(i),j) of the basis matrix nor the first translation value of the element (i,j) of the basis matrix is ​​equal to the first value, the second translation value of the element (i,j) is determined based on the second translation value of the element (θ(i),j), and the first value indicates that no translation value exists. For example, the second translation value of the element (i,j) is equal to the second translation value of the element (θ(i),j), that is, SV2(i,j) = SV2(θ(i),j).

[0207] Optionally, the second shift value of element (i,j) is determined based on the second shift value of element (θ(i),j) and a predefined value k(i) associated with row i, where k(i) is an integer. For example, SV2(i,j) = SV2(θ(o),j) + k(o). See the description above for k(i), which will not be repeated here.

[0208] Scenario 2

[0209] If the second shift value of the element (θ(i),j) of the basis matrix, or the first shift value of the element (i,j) of the basis matrix, is equal to the first value, the second shift value of the element (i,j) is determined based on the first shift value of the element (i,j).

[0210] It can be understood that if the first translation value of element (i,j) equals the first value, then the second translation value of element (i,j) equals the first value, that is, SV2(i,j)=SV1(θ(i),j)=the first value. That is, if the first translation value of element (i,j) does not exist (for example, equal to -1), then the second translation value of element (i,j) is also considered to not exist.

[0211] Optionally, if the second translation value of element (θ(i),j) is equal to the first value, but the first translation value of element (i,j) is not equal to the first value, then the second translation value of element (i,j) is equal to the first translation value of element (i,j). Alternatively, the second translation value of element (i,j) is determined based on the first translation value of element (i,j) and the predefined value k(i) associated with row i. For example, SV2(i,j) = SV1(i,j) + k(i).

[0212] The advantage of obtaining the second translation value in this scenario is that the design of the first sequence and the basis matrix has more space, allowing the parent node to have multiple splits, resulting in better actual performance.

[0213] For example, based on the descriptions of Case 1 and Case 2, one possible pseudocode for Scenario 2 is shown below:

[0214]

[0215] The following is combined Figure 9 and Figure 10 Let's take a second scenario as an example. Figure 9 This is a schematic diagram showing the first translation value of the basis matrix, where, Figure 9 Each value in the pseudocode represents the first translation value of the element at the corresponding position in the base matrix, and -1 indicates that the element at that position has no translation value. For example, the first sequence indicates that θ(i) = 0 for rows 1 to 9, 11, 12, and 14 to 16 of the base matrix, θ(10) = 4 for row 10, and θ(13) = 10 for row 13. That is, row 10 is associated with row 4, and row 13 is associated with row 10. Based on the above pseudocode (k(i) = 0 in this example), we can obtain the following... Figure 10 The second translation value of the basis matrix shown.

[0216] It is understandable that, since θ(10) = 4, θ(4) = 0, and θ(θ(10)) = 0, the method for obtaining the second translation value of the element in the 10th row is described in Scenario 1. Specifically, the second translation value of the element in the 10th row is as follows: Figure 10 As shown in row 10 of the matrix. Here, we only explain the second translation values ​​corresponding to some elements in row 13 of the basis matrix.

[0217] As can be seen from the above, θ(θ(13))=4≠0. The 13th row is related to the 10th row. For example, for the element (13,2) of the basis matrix, SV1(13,2)=63 and SV2(10,2)=8 are not equal to -1, so SV2(13,2)=SV2(10,2)=8. For another example, for the element (13,12) of the basis matrix, since SV1(13,12) is equal to -1, then SV2(13,12)=SV1(13,12)=-1. For another example, for the element (13,4) of the basis matrix, SV2(10,4)=-1, then SV2(13,4)=SV1(13,4)=111. This will not be elaborated further here.

[0218] Scene 3

[0219] In this scenario, there exists a row i in the basis matrix that is related to row i and row θ(i) of the basis matrix, and row θ(i) in the basis matrix is ​​related to row θ(θ(i)) of the basis matrix (i.e., there exists a row i where θ(i)≠0 and θ(θ(i))≠0). Then the second shift value of the element in row i is determined based on the second shift value of the element in row θ(i).

[0220] It is understandable that in this scenario, the second translation value is determined by nesting the row numbers of the base matrix in ascending order. Nesting means that the second translation value of the entire base matrix is ​​determined by looping through the row numbers only once. The first translation value of the larger row number may affect the second translation value of the smaller row number, but it is not necessary to loop back to the part of the smaller row number to make changes. At the same time, the second translation value of the smaller row number will affect the second translation value of the larger row number.

[0221] The description of Case 1 in this scenario is the same as that of Case 1 in Scenario 2. The difference is that in Case 2 of this scenario, the second shift value of the larger line number may affect the second shift value of the smaller line number.

[0222] For example, one possible pseudocode for scenario three is shown below:

[0223]

[0224] It is understandable that, based on the above pseudocode, in case two, if the second translation value of element (θ(i),j) of the basis matrix, or the first translation value of element (i,j) of the basis matrix, is equal to the first value, the second translation value of element (i,j) is determined based on the first translation value of element (i,j); if the first translation value of element (i,j) is not equal to the first value and the second translation value of element (θ(i),j) is equal to the first value, then the second translation value of element (θ(i),j) will be determined by the first translation value of element (i,j).

[0225] The preceding text has described in detail how to obtain the second translation value of the base matrix. In practical applications, the coding chain can have two branches, the main characteristic of which lies in the different translation values ​​used to determine the LDPC parity-check matrix. That is, the transmitting device can determine the LDPC parity-check matrix using the second translation value of the base matrix based on the method provided in this application embodiment, or it can directly determine the LDPC parity-check matrix based on the first translation value of the base matrix. The advantage of this implementation is that it is compatible with existing communication protocols and existing communication equipment, and can select a more suitable communication scheme according to different scenarios, requirements, and equipment capabilities, ensuring optimal performance in every bit rate range. The following is an example of how to determine which coding chain branch to use.

[0226] Implementation Method 1

[0227] The transmitting device can determine the LDPC parity check matrix using a first shift value or a second shift value of the base matrix based on the first information. The first information includes the coding rate and / or the number of matrix rows corresponding to the coding rate. The number of matrix rows corresponding to the coding rate is the number of rows remaining in all rows of the first matrix excluding the core rows. The first matrix is ​​the region in the base matrix corresponding to the coding rate. Alternatively, the first matrix can also be defined as a matrix obtained by truncating the first X rows and the first Y columns of the base matrix based on the coding rate. The first matrix is ​​as follows: Figure 4 As shown in (a) in the figure.

[0228] For example, the coding rate R and the number of rows i in the matrix corresponding to the coding rate can be converted as follows: R = kb / (kb + iP), where P is the fixed number of punctures in the base matrix and kb is the number of columns of the information column corresponding to the base matrix.

[0229] Example 1: The transmitting device determines the LDPC parity-check matrix using a first shift value or a second shift value of the base matrix based on first information and a first association relationship. The first association relationship indicates that any one of the multiple code rate intervals supported by the base matrix is ​​associated with the first shift value or the second shift value of the base matrix. The association of a code rate interval with the first shift value indicates that the encoding matrix is ​​determined based on the first shift value of the base matrix, and the association of a code rate interval with the second shift value indicates that the encoding matrix is ​​determined based on the second shift value of the base matrix.

[0230] For example, the code rates supported by the basis matrix can be divided into multiple code rate intervals (r1, r2], (r2, r3], ..., (r...). k-1 ,r k ], where r i <r i+1For each segment, its relationship with the shift value is specified. The association between the bit rate interval and the shift value type can be: directly specifying the shift value type used for each bit rate interval, or setting an ID for the two branches of the coding chain, with each bit rate interval corresponding to an ID.

[0231] It is understood that in this application, the transmitting device uses the second shift value of the base matrix to determine the LDPC parity matrix. Therefore, the encoded code rate is located in the first code rate interval of multiple code rate intervals, and the first code rate interval is related to the second shift value of the base matrix.

[0232] Example 2: The transmitting device determines the LDPC parity check matrix using either a first shift value or a second shift value of the base matrix based on the first information and a first rule. The first rule indicates that among all rows associated with the matrix row number corresponding to the coding code rate, there exists at least one row m associated with row θ(m) of the base matrix (i.e., θ(m) ≠ 0). In this case, the second shift value of the base matrix is ​​used to determine the coding matrix. If each row among all rows associated with the matrix row number corresponding to the coding code rate is not associated with any row of the base matrix, then the first shift value of the base matrix is ​​used to determine the coding matrix.

[0233] It can be understood that all rows associated with the number of matrix rows corresponding to the coding bitrate are the remaining rows in the first matrix excluding the core rows.

[0234] It can also be understood that in this application, the transmitting device uses the second translation value of the base matrix to determine the LDPC parity matrix. Therefore, at least one row m in the row associated with the number of rows of the matrix corresponding to the coding code rate is associated with row θ(m) of the base matrix.

[0235] Example 3: The transmitting device determines the LDPC parity-check matrix based on the first information and the first code rate threshold, using either the first or second shift value of the base matrix. If the coding code rate is less than the first code rate threshold, the second shift value of the base matrix is ​​used to determine the coding matrix; otherwise, the first shift value of the base matrix is ​​used to determine the coding matrix.

[0236] It is understood that in this application, the transmitting device uses the second shift value of the base matrix to determine the LDPC parity matrix, therefore, the coding rate is less than the first code rate threshold.

[0237] Optionally, the coding rate in this implementation can also be replaced with the quadrature amplitude modulation (QAM) order or the MCS table ID. An MCS table ID can directly correspond to a coding rate and a modulation order, and a modulation order and a coding rate can also be correlated through the MCS ID. Therefore, the above scheme is equally applicable to the MCS table ID or the QAM order.

[0238] Implementation Method Two

[0239] The transmitting device can determine the LDPC parity matrix using either the first or second shift value of the base matrix based on a second rule. The second rule indicates that the encoding matrix is ​​determined using the second shift value of the base matrix in high-throughput scenarios; otherwise, the encoding matrix is ​​determined using the first shift value of the base matrix.

[0240] For example, a high-throughput scenario can satisfy at least one of the following definitions:

[0241] a) The coding rate is greater than or equal to the code rate threshold, and the modulation order is greater than or equal to the order threshold. For example, the code rate threshold can be any value among 22 / 24, 22 / 25, 22 / 26, 948 / 1024, 910 / 1024, and 873 / 1024.

[0242] b) The modulation order is higher than or equal to the order threshold. For example, the order threshold can be any value among quadrature amplitude modulation (QAM) 64, QAM 256, and QAM 1024.

[0243] c) The MCS is greater than or equal to the grading threshold. For example, the grading threshold can be any value among 26, 27, and 28.

[0244] d) The length of the entire communication's transmission block (TB) is greater than or equal to a length threshold. For example, the length threshold is any one of the following values: 8448, 16896, 25344, 33792, and 42240.

[0245] e) The number of code blocks (CBs) is greater than or equal to a number threshold. For example, the number threshold is any value among 2, 3, 4, and 5.

[0246] f) The number of multiple-input multiple-output (MIMO) streams is greater than or equal to a stream count threshold. For example, the stream count thresholds are 12, 24, 36, or 108.

[0247] g) When limited buffer rate matching (LBRM) is enabled.

[0248] S630: The transmitting device encodes the information bit sequence according to the LDPC parity check matrix to obtain the codeword sequence.

[0249] S640, the transmitting device sends a codeword sequence to the receiving device. Correspondingly, the receiving device receives the codeword sequence from the transmitting device.

[0250] It should be noted that, since channel noise may be introduced during the transmission of the codeword sequence, the LDPC codeword sequence output or transmitted by the transmitting device may be different from the LDPC codeword sequence received by the receiving device.

[0251] In S650, the receiving device decodes the codeword sequence according to the LDPC parity check matrix to obtain the information bit sequence.

[0252] The LDC parity check matrix used for decoding by the receiving device is the same as the LDPC parity check matrix used for encoding by the sending device. The specific method by which the receiving device determines the LDPC parity check matrix can be found in the description on the sending device side, and will not be detailed here.

[0253] This scheme can generate different LDPC parity-check matrices based on the capabilities of the first sequence matching decoder or the requirements of the scenario, in order to achieve more types of communication, such as high-throughput communication or low-complexity communication.

[0254] Figure 11 This is a performance simulation diagram of the LDPC code determined based on the second translation value proposed in this application and the LDPC code determined based on the first translation value. Among them, Figure 11 The horizontal axis represents the signal-to-noise ratio (SNR), and the vertical axis represents the block error rate (BLER).

[0255] like Figure 11 As shown, the figure includes three lines #1 and three lines #2. Lines #1 and #2 with the same shape correspond to a set of simulation results. All three sets of simulation results were obtained under a maximum iteration complexity of 5 rounds. In each set, line #1 represents the simulation result of the LDPC parity-check matrix obtained based on the second translation value of the 5G base map, and line #2 represents the simulation result of the LDPC parity-check matrix obtained based on the first translation value of the 5G base map. Specifically, line #1 marked with "×" corresponds to N = 32 * Zc, line #1 marked with "O" corresponds to N = 33 * Zc, and line #1 marked with "*" corresponds to N = 34 * Zc, where N is the code length, Zc is the boost value, and 32, 33, and 34 are the column numbers of the base map corresponding to the transmitted bits. Based on the simulation results, line #2 in each set shows a performance gain compared to line #1 at code rates of 22 / 32, 22 / 33, and 22 / 34.

[0256] Optionally, in this application, a generator matrix can be determined first, and the information bit sequence can be LDPC encoded based on the generator matrix. The method for determining the generator matrix is ​​the same as that proposed in this application, and will not be repeated here.

[0257] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0258] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0259] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (transmitting device or receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0260] The above text combined Figures 1 to 11 The present application provides a detailed description of the method embodiments, which will be discussed below in conjunction with... Figure 12 and Figure 13 This describes an embodiment of the apparatus described in this application. It is understood that, in order to achieve the functions described in the above embodiments, Figure 12 and Figure 13 The apparatus includes hardware structures and / or software modules corresponding to perform various functions. Those skilled in the art will readily recognize that, based on the units and method steps described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0261] Figure 12 and Figure 13 The diagram illustrates the possible structures of apparatuses provided for embodiments of this application. These apparatuses can be used to implement the functions of the transmitting or receiving devices in the above method embodiments, and thus also achieve the beneficial effects of the above method embodiments.

[0262] Figure 12 This is a schematic block diagram of the communication device 1000 provided in an embodiment of this application. Figure 12 As shown, the device 1000 may include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside world, and the processing unit 1020 is used for data processing. The communication unit 1010 may also be referred to as a communication interface or a transceiver unit.

[0263] In one possible design, the device 1000 can implement the steps or processes corresponding to those performed by the transmitting device in the above method embodiments, wherein the processing unit 1020 is used to perform processing-related operations of the transmitting device in the above method embodiments, and the communication unit 1010 is used to perform transmission-related operations of the transmitting device in the above method embodiments.

[0264] In another possible design, the device 1000 can implement the steps or processes corresponding to those performed by the receiving device in the above method embodiments, wherein the communication unit 1010 is used to perform the receiving-related operations of the receiving device in the above method embodiments, and the processing unit 1020 is used to perform the processing-related operations of the receiving device in the above method embodiments.

[0265] It is understood that the device 1000 here is embodied in the form of a functional unit. The term "unit" here can refer to an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, integrated logic circuitry, and / or other suitable components supporting the described functions. In an alternative example, those skilled in the art will understand that the device 1000 may specifically be the transmitting end device in the above embodiments, used to execute the various processes and / or steps corresponding to the transmitting end device in the above method embodiments; or, the device 1000 may specifically be the receiving end device in the above embodiments, used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiments. To avoid repetition, further details are omitted here.

[0266] The apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting device in the above-described method, or the apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the receiving device in the above-described method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, respectively executing the transmission and reception operations and related processing operations in each method embodiment.

[0267] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In embodiments of this application, Figure 12The device mentioned can be the receiving or transmitting device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on a chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitations are imposed here.

[0268] Figure 13 This is a schematic block diagram of a communication device 1100 provided in an embodiment of this application. The device 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is used to execute instructions to control the transceiver 1120 to transmit and / or receive signals.

[0269] Optionally, the device 1100 may further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 via an internal connection path. The memory 1130 stores instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In one possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the transmitting device in the above method embodiments. In another possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the receiving device in the above method embodiments.

[0270] Optionally, the memory 1130 may be integrated into the processor 1110.

[0271] In one possible scenario, device 1100 includes at least one processor with integrated memory, and other memory besides the memory integrated on the processor.

[0272] It is understood that the device 1100 can specifically be the transmitting or receiving device in the above embodiments, or it can be a chip or a chip system. Correspondingly, the transceiver 1120 can be the transceiver circuit of the chip, which is not limited here. Specifically, the device 1100 can be used to execute the various steps and / or processes corresponding to the transmitting or receiving device in the above method embodiments.

[0273] Optionally, the memory 1130 may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may include non-volatile random access memory. For example, the memory may also store device type information. The processor 1110 may be used to execute instructions stored in the memory, and when the processor 1110 executes instructions stored in the memory, the processor 1110 is used to perform the various steps and / or processes of the method embodiments corresponding to the transmitting or receiving devices described above.

[0274] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0275] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor in the embodiments of this application can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0276] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0277] Optionally, the memory (e.g., 1130) in this embodiment may be integrated into the processor (e.g., 1110).

[0278] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0279] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0280] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by a transmitting or receiving device in any method embodiment are performed.

[0281] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0282] In addition, this application also provides a communication system, including the transmitting end device and the receiving end device in the embodiments of this application.

[0283] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0284] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0285] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0286] It is understood that the term "embodiment" used throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, various embodiments throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0287] It can also be understood that in this application, "when," "if," and "if" all refer to the network element making corresponding processing under certain objective circumstances, and are not time-limited, nor do they require the network element to make a judgment when it is implemented, nor do they mean that there are other limitations.

[0288] It can also be understood that in the various embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it can also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

Claims

1. A communication method based on low-density parity-check (LDPC) codes, characterized in that, The method includes: Obtain the information bit sequence; The LDPC parity check matrix is ​​determined based on the LDPC base matrix and a second translation value of the base matrix. The second translation value of the base matrix is ​​determined based on a first sequence and a first translation value of the base matrix. The first sequence indicates the association between row i of the base matrix and row () of the base matrix. The first translation value of the base matrix is ​​a predefined translation value. The information bit sequence is encoded according to the LDPC parity check matrix to obtain a codeword sequence; Output the codeword sequence.

2. A communication method, characterized in that, Obtain the codeword sequence; The LDPC parity-check matrix is ​​determined based on the LDPC base matrix and a second translation value of the base matrix. The second translation value of the base matrix is ​​determined based on a first sequence and a first translation value of the base matrix. The first sequence indicates the relationship between row i of the base matrix and row θ(i) of the base matrix. The first translation value of the base matrix is ​​a predefined translation value. The codeword sequence is decoded according to the LDPC parity check matrix to obtain the information bit sequence.

3. The method according to claim 1 or 2, characterized in that, Row i of the base matrix is ​​not associated with any row of the base matrix, and the second translation value of the element in row i is determined based on the first translation value of the element in row i.

4. The method according to claim 3, characterized in that, The second translation value of the element (i,j) in row i and column j of the basis matrix is ​​equal to the first translation value of the element (i,j).

5. The method according to any one of claims 1 to 4, characterized in that, Row i of the basis matrix is ​​associated with row θ(i) of the basis matrix, and the second translation value of the element in row i is determined based on the first translation value of the element in row θ(i) or the second translation value of the element in row θ(i).

6. The method according to claim 5, characterized in that, The second translation value of the element in row i is determined based on the first translation value of the element in row θ(i) and the first translation value of the element in row i. or, The second translation value of the element in row i is determined based on the second translation value of the element in row θ(i) and the first translation value of the element in row i.

7. The method according to claim 5 or 6, characterized in that, If any row in the basis matrix satisfies the condition that row i of the basis matrix is ​​associated with row θ(i) of the basis matrix, and row θ(i) of the basis matrix is ​​not associated with any row in the basis matrix, then the second translation value of the element in row i is determined based on the first translation value of the element in row θ(i).

8. The method according to claim 7, characterized in that, The first translation value of the element (θ(i),j) in row θ(i) and column j of the base matrix and the first translation value of the element (i,j) in row i and column j of the base matrix are both not equal to the first value. The second translation value of the element (i,j) is determined based on the first translation value of the element (θ(i),j). The first value indicates that there is no translation value. The first translation value of the element (θ(i),j) or the first translation value of the element (i,j) is equal to the first value, and the second translation value of the element (i,j) is determined based on the first translation value of the element (i,j).

9. The method according to claim 5 or 6, characterized in that, If there exists a row i in the basis matrix such that row i is associated with row θ(i) of the basis matrix, and row θ(i) of the basis matrix is ​​associated with row θ(θ(i)), then the second translation value of the element in row i is determined based on the second translation value of the element in row θ(i).

10. The method according to claim 9, characterized in that, The second translation value of the element (θ(i),j) in row θ(i) and column j of the base matrix and the first translation value of the element (i,j) in row i and column j of the base matrix are both not equal to the first value. The second translation value of the element (i,j) is determined based on the second translation value of the element (θ(i),j). The first value indicates that there is no translation value. The second translation value of the element (θ(i),j) or the first translation value of the element (i,j) is equal to the first value, and the second translation value of the element (i,j) is determined based on the first translation value of the element (i,j).

11. The method according to claim 8 or 10, characterized in that, The first translation value of element (i,j) is equal to the first numerical value, and the second translation value of element (i,j) is determined based on the first translation value of element (i,j), including: The second translation value of the element (i,j) is equal to the first value.

12. The method according to any one of claims 5 to 11, characterized in that, include: The second translation value of the element in row i is determined based on the first or second translation value of the element in row θ(i), and a predefined numerical value k(i) associated with row i, where k(i) is an integer.

13. The method according to claim 12, characterized in that, The k(i) is determined based on the first translation value of the element (i, c(i)) of the i-th row and c(i) of the base matrix, where the column c(i) is the extended check column associated with the i-th row.

14. The method according to any one of claims 1 to 13, characterized in that, Before determining the LDPC parity-check matrix, the method further includes: Based on the first information, the second translation value of the base matrix is ​​used to determine the LDPC parity-check matrix, wherein the first information includes the coding rate and / or the number of matrix rows corresponding to the coding rate, the number of matrix rows corresponding to the coding rate is the number of rows remaining in the rows corresponding to the first matrix excluding the core rows, and the first matrix is ​​the region in the base matrix corresponding to the coding rate.

15. The method according to claim 14, characterized in that, The step of determining the LDPC parity-check matrix based on the first information and using the second translation value of the base matrix includes: Based on the first correlation and the first information, the second translation value is used to determine the LDPC parity-check matrix. The first association indicates that any one of the multiple code rate intervals supported by the base matrix is ​​associated with a first shift value or a second shift value of the base matrix, wherein associating a code rate interval with the first shift value indicates determining the encoding matrix based on the first shift value of the base matrix, and associating a code rate interval with the second shift value indicates determining the encoding matrix based on the second shift value of the base matrix. The coding rate is located in the first code rate interval of the plurality of code rate intervals, and the first code rate interval is related to the second translation value of the base matrix.

16. The method according to claim 14, characterized in that, The step of determining the LDPC parity-check matrix based on the first information and using the second translation value of the base matrix includes: Based on the first rule and the first information, the second translation value of the basis matrix is ​​used to determine the LDPC parity-check matrix. If, according to the first rule, at least one row m in all rows associated with the matrix row number corresponding to the coding bitrate is associated with row () of the base matrix, then the coding matrix is ​​determined using the second shift value of the base matrix. If each row in all rows associated with the matrix row number corresponding to the coding bitrate is not associated with any row of the base matrix, then the coding matrix is ​​determined using the first shift value of the base matrix. Wherein, at least one row m of the matrix row number associated with the coding code rate is associated with row () of the base matrix.

17. The method according to claim 14, characterized in that, The step of determining the LDPC parity-check matrix based on the first information and using the second translation value of the base matrix includes: Based on a first code rate threshold and the first information, the second shift value of the base matrix is ​​used to determine the LDPC parity-check matrix. If the coding code rate is less than the first code rate threshold, the second shift value of the base matrix is ​​used to determine the coding matrix; otherwise, the first shift value of the base matrix is ​​used to determine the coding matrix. Wherein, the encoding code rate is less than the first code rate threshold.

18. The method according to any one of claims 1 to 13, characterized in that, Before determining the LDPC parity-check matrix, the method further includes: Based on the second rule, the second translation value of the basis matrix is ​​used to determine the LDPC parity-check matrix, wherein... The second rule instructs that the encoding matrix be determined using the second translation value of the base matrix in high-throughput scenarios; otherwise, the encoding matrix is ​​determined using the first translation value of the base matrix.

19. The method according to claim 18, characterized in that, The high throughput scenario is a communication scenario that satisfies at least one of the following conditions: The coding rate is greater than or equal to the code rate threshold, the modulation order is greater than or equal to the order threshold, the coding modulation scheme (MCS) is greater than or equal to the level threshold, the length of the transport block (TB) of the entire communication is greater than or equal to the length threshold, the number of coded blocks (CB) is greater than or equal to the number threshold, the number of streams in multiple-input multiple-output (MIMO) is greater than or equal to the number threshold, and finite buffer rate matching (LBRM) is enabled.

20. The method according to any one of claims 1 to 19, characterized in that, Row i of the basis matrix is ​​associated with row θ() of the basis matrix, and row i satisfies the first condition: The first condition is α(i)≤α0, where α(i) is the number of columns j in which the element (i, j) of row i and column j of the basis matrix is ​​1 and the element (θ(i), j) of row θ(i) and column j of the basis matrix is ​​0, and α0 is a threshold. or, The first condition is α(i)≤α1*(i), where w(i) is the number of elements with a value of 1 in row i, and α1 is the threshold. or, The first condition is α(i)≤α2*w(()), where w(θ(i)) is the number of elements with a value of 1 in the row θ(i), and α2 is the threshold.

21. The method according to claim 20, characterized in that, The value of α0 is 0, 1, or 2. The value range of α1 is 0≤α1≤2 / (i), or 0≤α1≤1 / (i). The value range of α2 is 0≤α2≤2 / (θ(i)), or 0≤α2≤1 / (θ(i)).

22. The method according to any one of claims 1 to 21, characterized in that, The basis matrix is ​​either basis graph 1 or basis graph 2. The first translation value of basis graph 1 is shown in Table 3, and the first translation value of basis graph 2 is shown in Table 4.

23. The method according to claim 22, characterized in that, The fixed number of punched columns in the base matrix is ​​P, where 0 ≤ P ≤ 2.

24. A communication device, characterized in that, The device includes at least one processor and an interface circuit, the interface circuit being configured to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, the processor causing the method as described in any one of claims 1 to 23 to be implemented via logic circuits or executing code instructions.

25. The communication device according to claim 24, characterized in that, The communication device is a chip or chip system.

26. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed, cause the method as described in any one of claims 1 to 23 to be implemented.

27. A computer program product, characterized in that, Includes a computer program that, when run, causes the method as described in any one of claims 1 to 23 to be implemented.

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