Semiconductor memory device

Abstract

The invention relates to a semiconductor memory device. The semiconductor memory device includes: a plurality of source channels penetrating a source selection line; a gate stack structure overlapping the source selection line; a connection pattern disposed between the source selection line and the gate stack structure, the connection pattern being commonly connected to the plurality of source channels; and a plurality of vertical channels penetrating the gate stack structure, the plurality of vertical channels being commonly connected to the connection pattern.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202110399181.X (application date: April 14, 2021, invention title: semiconductor memory device and method of manufacturing semiconductor memory device). Technical Field

[0002] This disclosure generally relates to semiconductor memory devices and methods for manufacturing such semiconductor memory devices, and more specifically, to a three-dimensional semiconductor memory device and a method for manufacturing such a three-dimensional semiconductor memory device. Background Technology

[0003] Semiconductor memory devices include memory cells capable of storing data. Three-dimensional semiconductor memory devices include memory cells arranged in three dimensions, thereby reducing the area occupied by the memory cells per unit area of ​​the substrate. Summary of the Invention

[0004] A semiconductor memory device according to embodiments of the present disclosure may include: a plurality of source channels penetrating a source select line; a gate stack structure overlapping the source select line; a connection pattern disposed between the source select line and the gate stack structure, the connection pattern being connected to the plurality of source channels; and a plurality of vertical channels penetrating the gate stack structure, the plurality of vertical channels being connected to the connection pattern.

[0005] A semiconductor memory device according to embodiments of the present disclosure may include: a first source channel and a second source channel extending parallel to each other; a first source select line surrounding the first source channel; a second source select line surrounding the second source channel; a gate stack structure overlapping the first source select line, the gate stack structure extending to overlap the second source select line; and a first vertical channel penetrating a first region of the gate stack structure overlapping the first source select line. The second vertical channel penetrates a second region of the gate stack structure that overlaps with the second source select line; a first connection pattern connects the first source channel and the first vertical channel between the first source select line and the gate stack structure; a second connection pattern connects the second source channel and the second vertical channel between the second source select line and the gate stack structure; and a source-side slit disposed between the first source select line and the second source select line, extending between the first connection pattern and the second connection pattern.

[0006] A semiconductor memory device according to embodiments of the present disclosure may include: a plurality of source channels penetrating a source select line; a gate stack structure overlapping the source select line; a plurality of vertical channels penetrating the gate stack structure; and a connection pattern disposed between the source select line and the gate stack structure to connect the plurality of vertical channels to the plurality of source channels, wherein the thickness of each of the plurality of vertical channels is different from the thickness of each of the plurality of source channels.

[0007] A method for manufacturing a semiconductor memory device according to embodiments of the present disclosure may include the following steps: forming a preliminary gate stack structure having a plurality of interlayer insulating layers and a plurality of conductive patterns alternately stacked on a first region of a sacrificial substrate, wherein the preliminary gate stack structure is penetrated by a memory layer and a plurality of vertical channels; forming a conductive layer connected to the plurality of vertical channels on the preliminary gate stack structure; forming a first insulating layer and a select gate layer on the conductive layer; and forming a source-side slit penetrating the first insulating layer, the select gate layer, and the conductive layer, such that the select gate layer is isolated into a plurality of source select lines, and the conductive layer is isolated into a plurality of interconnect patterns. Attached Figure Description

[0008] In the accompanying drawings, dimensions may be exaggerated for clarity. It will be understood that when an element is referred to as being "between" two elements, it may be the only element between those two elements, or there may be one or more intermediate elements. Similar reference numerals always indicate similar elements.

[0009] Figure 1 This is a circuit diagram showing a memory block of a semiconductor memory device according to an embodiment of the present disclosure.

[0010] Figure 2 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figures 3A to 3C The layout of the source select line, gate stack structure, and bit lines of a semiconductor memory device according to an embodiment of the present disclosure is shown.

[0012] Figure 4A and Figure 4B The diagram illustrates the gate stack structure and bit line layout of a semiconductor memory device according to embodiments of the present disclosure.

[0013] Figures 5A to 5C This is a plan view illustrating various implementations of the source channel.

[0014] Figures 6A to 6C This is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figures 7A to 7B This is an enlarged view showing the cross-section of the vertical channel and the cross-section of the source channel according to an embodiment of the present disclosure.

[0016] Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 11 , Figure 12A , Figure 12B and Figure 12C This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 13 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure.

[0018] Figure 14 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0019] The specific structural or functional descriptions disclosed herein are merely illustrative in order to describe embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the specific embodiments set forth herein.

[0020] In the following text, the terms "first" and "second" are used to distinguish one component from another and are not intended to imply a specific number or order of components. These terms can be used to describe various components, but components are not limited to these terms.

[0021] Furthermore, it will be understood that when a component is referred to as "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0022] The embodiments provide a semiconductor memory device and a method for manufacturing the semiconductor memory device, which can improve the stability of the manufacturing process of the three-dimensional semiconductor memory device and improve the operational reliability of the three-dimensional semiconductor memory device.

[0023] Figure 1 This is a circuit diagram showing the memory block BLK of a semiconductor memory device according to an embodiment of the present disclosure.

[0024] Reference Figure 1 A semiconductor memory device may include multiple memory blocks BLK. Each memory block BLK may include multiple memory cell strings MS1 and MS2 connected to a common source layer CSL and a bit line BL.

[0025] Multiple memory cell strings MS1 and MS2 can be connected to a common source layer CSL via source select transistor SST. Multiple memory cell strings MS1 and MS2 can be connected to bit line BL via drain select transistor DST. Each of memory cell strings MS1 and MS2 may include multiple memory cells MC connected in series.

[0026] The gate of the source select transistor SST can be connected to isolated source select lines SSL1 and SSL2. The gate of the drain select transistor DST can be connected to isolated drain select lines DSL1 and DSL2. The gates of multiple memory cells MC can be connected to multiple word lines WL. The word lines WL can be set at different heights, and the gates of memory cells MC set at the same height can be connected to a single word line WL.

[0027] The present disclosure will be described below primarily based on an embodiment in which the storage block BLK includes a first source select line SSL1 and a second source select line SSL2 isolated from each other, and a first drain select line DSL1 and a second drain select line DSL2 isolated from each other. However, the present disclosure is not limited thereto, and the storage block BLK may include three or more source select lines and three or more drain select lines isolated from each other.

[0028] Multiple memory cell strings MS1 and MS2 can be connected to each word line WL. The multiple memory cell strings MS1 and MS2 may include a first group and a second group, selectable individually via a first source select line SSL1 and a second source select line SSL2. The first group may include the first memory cell string MS1, and the second group may include the second memory cell string MS2.

[0029] The first memory cell string MS1 can be connected to the bit line BL via the drain select transistor DST connected to the first drain select line DSL1. The second memory cell string MS2 can be connected to the bit line BL via the drain select transistor DST connected to the second drain select line DSL2. In other words, a pair of first memory cell strings MS1 and second memory cell strings MS2 can be connected to the bit line BL corresponding to the pair of first memory cell strings MS1 and second memory cell strings MS2.

[0030] The first memory cell string MS1 can be connected to the common source layer CSL via a source select transistor SST connected to the first source select line SSL1, and the second memory cell string MS2 can be connected to the common source layer CSL via a source select transistor SST connected to the second source select line SSL2. Therefore, multiple memory cell strings MS1 and MS2 can be simultaneously isolated into multiple groups, and these groups can be individually selected for each of the source select lines SSL1 and SSL2 during read or verification operations. In an embodiment, during a read or verification operation, one of the first source select line SSL1 and the second source select line SSL2 is selected such that one of the first group of the first memory cell string MS1 and the second group of the second memory cell string MS2 can be connected to the common source layer CSL. Therefore, in this disclosure, the channel resistance can be reduced compared to when the first memory cell string MS1 and the second memory cell string MS2 are simultaneously connected to the common source layer CSL during read or verification operations. Therefore, in this disclosure, read disturbances can be reduced.

[0031] Figure 2 This is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0032] Reference Figure 2 The semiconductor memory device may include: source select lines SSL1[A], SSL2[A], SSL1[B], and SSL2[B], which are isolated from each other by source-side slits SS1 and SS2; source channels SC1[A], SC2[A], SC1[B], and SC2[B], which penetrate the source select lines SSL1[A], SSL2[A], SSL1[B], and SSL2[B]; and connecting patterns CP1[A], CP2[A], CP1[B], and CP2[B]. [B], which overlap with source selection lines SSL1[A], SSL2[A], SSL1[B] and SSL2[B] respectively; vertical channels VC1[A], VC2[A], VC1[B] and VC2[B], which are in contact with connection patterns CP1[A], CP2[A], CP1[B] and CP2[B]; and gate stack structures GST[A] and GST[B], which surround vertical channels VC1[A], VC2[A], VC1[B] and VC2[B].

[0033] The semiconductor memory device may include a first gate stack structure GST[A] and a second gate stack structure GST[B] that are isolated from each other by a slit SI.

[0034] The first gate stack structure GST[A] may include multiple word lines WL[A] and drain select lines that overlap with the multiple word lines WL[A] and are isolated from each other by drain-side slits SD.

[0035] In an embodiment, the first gate stack structure GST[A] may include a first drain select line DSL1[A] overlapping a first region R1 of multiple word lines WL[A] and a second drain select line DSL2[A] overlapping a second region R2 of multiple word lines WL[A]. The multiple word lines WL[A] may include a third region R3. The third region R3 may be disposed between the first region R1 and the second region R2 and may connect the first region R1 and the second region R2 to each other. A drain-side slit SD may be disposed between the first drain select line DSL1[A] and the second drain select line DSL2[A] and may overlap with the third region R3 of the word lines WL[A].

[0036] The first region R1 of the first drain selection line DSL1[A] and the word line WL[A] can be penetrated by a plurality of first vertical channels VC1[A] extending in the first direction D1. The second region R2 of the second drain selection line DSL2[A] and the word line WL[A] can be penetrated by a plurality of second vertical channels VC2[A] extending in the first direction D1.

[0037] Each of the word line WL[A], the first drain selection line DSL1[A], and the second drain selection line DSL2[A] may extend along a plane intersecting the first direction D1. In an embodiment, each of the word line WL[A], the first drain selection line DSL1[A], and the second drain selection line DSL2[A] may extend in the second direction D2 and the third direction D3. The slit SI and the drain-side slit SD may extend in the second direction D2. The first drain selection line DSL1[A] and the second drain selection line DSL2[A] may be adjacent to each other in the third direction D3. The first direction D1, the second direction D2, and the third direction D3 may correspond to the directions facing the X-axis, Y-axis, and Z-axis in the XYZ coordinate system, respectively.

[0038] The third region R3 of the word line WL[A] can be penetrated by multiple dummy channels DVC[A]. The dummy channels DVC[A] can be arranged in a row along the second direction D2. The drain-side slit SD can overlap with the dummy channels DVC[A]. In another embodiment, the dummy channels DVC[A] can be omitted. Figure 2 Compared to the implementation shown, in the implementation that omits the dummy channel DVC[A], the distance between the first drain selection line DSL1[A] and the second drain selection line DSL2[A] on the third-direction D3 can be narrowed.

[0039] Similar to the first gate stack structure GST[A], the second gate stack structure GST[B] may include multiple word lines WL[B] and a first drain select line DSL1[B] and a second drain select line DSL2[B] isolated from each other by drain-side slits SD. Additionally, similar to the first gate stack structure GST[A], the second gate stack structure GST[B] may be penetrated by multiple first vertical channels VC1[B], multiple second vertical channels VC2[B], and multiple dummy channels DVC[B].

[0040] The first gate stack structure GST[A] and the second gate stack structure GST[B] may overlap with the source select lines SSL1[A], SSL2[A], SSL1[B], and SSL2[B]. The source select lines SSL1[A], SSL2[A], SSL1[B], and SSL2[B] may be isolated from each other at substantially the same height. The source select lines SSL1[A], SSL2[A], SSL1[B], and SSL2[B] may include a first group of first source select lines SSL1[A] and second source select lines SSL2[A] and a second group of first source select lines SSL2[A] and second source select lines SSL2[B]. The first group of first source select lines SSL1[A] and second source select lines SSL2[A] may be disposed between the first gate stack structure GST[A] and the common source layer CSL. The first source select line SSL2[A] and the second source select line SSL2[B] of the second group can be set between the second gate stack structure GST[B] and the common source layer CSL.

[0041] The multiple word lines WL[A] of the first gate stack structure GST[A] can extend to overlap with the first source select line SSL1[A] and the second source select line SSL2[A] of the first group. The first region R1 of the word line WL[A] can overlap with the first source select line SSL1[A] of the first group, and the second region R2 of the word line WL[A] can overlap with the second source select line SSL2[A] of the first group. The first source select line SSL1[A] of the first group can be spaced apart from the second source select line SSL2[A] of the first group by a first source-side slit SS1 extending in the second direction D2.

[0042] Similar to the first gate stack structure GST[A], the multiple word lines WL[B] of the second gate stack structure GST[B] can overlap with the first source select lines SSL1[B] and the second source select lines SSL2[B] of the second group, which are spaced apart from each other. The first source select lines SSL1[A] and the second source select lines SSL2[A] of the first group can be spaced apart from the first source select lines SSL1[B] and the second source select lines SSL2[B] of the second group through a second source-side slit SS2 extending in the second direction D2.

[0043] The source channels SC1[A], SC2[A], SC1[B] and SC2[B] may include the first group of source channels SC1[A] and SC2[A] and the second group of source channels SC1[B] and SC2[B].

[0044] The first group of source channels SC1[A] and SC2[A] may include multiple first source channels SC1[A] and multiple second source channels SC2[A]. The multiple first source channels SC1[A] may be surrounded by a first source selection line SSL1[A] of the first group. The multiple second source channels SC2[A] may be surrounded by a second source selection line SSL2[A] of the first group.

[0045] Similar to the source channels SC1[A] and SC2[A] of the first group, the source channels SC1[B] and SC2[B] of the second group may include a plurality of first source channels SC1[B] surrounded by the first source selection line SSL1[B] of the second group and a plurality of second source channels SC2[B] surrounded by the second source selection line SSL2[B] of the second group.

[0046] The source channels SC1[A], SC2[A], SC1[B] and SC2[B] of the first and second groups can extend in the first direction D1 to connect together to the common source layer CSL.

[0047] The first source-side slit SS1 and the second source-side slit SS2 may extend between the connecting patterns CP1[A], CP2[A], CP1[B], and CP2[B]. The connecting patterns CP1[A], CP2[A], CP1[B], and CP2[B] may be positioned at substantially the same height. The connecting patterns CP1[A], CP2[A], CP1[B], and CP2[B] may include a first connecting pattern CP1[A] and a second connecting pattern CP2[A] of a first group, and a first connecting pattern CP1[B] and a second connecting pattern CP2[B] of a second group.

[0048] The first connection pattern CP1[A] of the first group can be disposed between the first source select line SSL1[A] and the first gate stack structure GST[A] of the first group. The second connection pattern CP2[A] of the first group can be disposed between the second source select line SSL2[A] and the first gate stack structure GST[A] of the first group. The first connection pattern CP1[A] and the second connection pattern CP2[A] of the first group can extend parallel to the first source select line SSL1[A] and the second source select line SSL2[A] of the first group.

[0049] Multiple first source channels SC1[A] may extend to contact a first connection pattern CP1[A]. Multiple first vertical channels VC1[A] may be commonly connected to the first connection pattern CP1[A], and may be connected to multiple first source channels SC1[A] through the first connection pattern CP1[A]. Multiple second source channels SC2[A] may extend to contact a second connection pattern CP2[A]. Multiple second vertical channels VC2[A] may be commonly connected to the second connection pattern CP2[A], and may be connected to multiple second source channels SC2[A] through the second connection pattern CP2[A].

[0050] The first connection pattern CP1[B] and the second connection pattern CP2[B] of the second group may have a structure similar to that of the first connection pattern CP1[A] and the second connection pattern CP2[A] of the first group. The slit SI may extend between the first connection pattern CP1[A] and the second connection pattern CP2[A] of the first group and the first connection pattern CP1[B] and the second connection pattern CP2[B] of the second group, and the slit SI may be connected to the second source-side slit SS2.

[0051] Figures 3A to 3C The layout of the source select line, gate stack structure, and bit lines of a semiconductor memory device according to an embodiment of the present disclosure is shown.

[0052] Figure 3A This is a plan view showing an implementation of the first source selection line SSL1[A] and the second source selection line SSL2[A] of the first group and the first source selection line SSL[B] of the second group.

[0053] Reference Figure 3A Source select lines SSL1[A], SSL2[A], and SSL1[B] may surround source channels SC1[A], SC2[A], and SC1[B] extending in the first direction D1, respectively. The sidewalls of each of the source channels SC1[A], SC2[A], and SC1[B] may be surrounded by a gate insulating layer GI. In other words, the gate insulating layer GI may be disposed between each of the source select lines SSL1[A], SSL2[A], and SSL1[B] and each of the source channels SC1[A], SC2[A], and SC1[B].

[0054] The first source-side slit SS1 and the second source-side slit SS2 may extend in the second direction D2. Each of the first source-side slit SS1 and the second source-side slit SS2 may have various shapes such as wavy shapes and linear shapes.

[0055] Figure 3B It is shown that... Figure 3AThe first gate stack structure GST[A] shown in the first group, where the first source select line SSL1[A] and the second source select line SSL2[A] overlap, and the first gate stack structure GST[A] and the first gate stack structure GST[A] shown in the first group, are intersected. Figure 3A The plan view of the second gate stack structure GST[B] with the first source selection line SSL1[B] overlapping in the second group is shown.

[0056] Reference Figure 3B The multiple word lines WLA and drain select lines DSL1[A] and DSL2[A] of the first gate stack structure GST[A] are spaced apart from the multiple word lines WL[B] and drain select lines DSL1[B] of the second gate stack structure GST[B] through a slit SI. The drain-side slit SD, which overlaps with the word lines (e.g., WL[A]), may overlap with a dummy channel (e.g., DVC[A]).

[0057] Each of the slit SI and the drain-side slit SD can have various shapes, such as wavy shapes and linear shapes. In an embodiment, each of the slit SI and the drain-side slit SD can have a linear shape.

[0058] Word lines WL[A] and WL[B], and drain select lines DSL1[A], DSL2[A], and DSL1[B], may surround vertical channels VC1[A], VC2[A], and VC1[B]. The sidewalls of each of vertical channels VC1[A], VC2[A], and VC1[B] may be surrounded by a memory layer ML. In other words, the memory layer ML may be disposed between each of word lines WL[A] and WL[B], and drain select lines DSL1[A], DSL2[A], and DSL1[B], and each of vertical channels VC1[A], VC2[A], and VC1[B].

[0059] The cross-sectional area of ​​each of the source channels SC1[A], SC2[A], and SC1[B] may be wider than the cross-sectional area of ​​each of the vertical channels VC1[A], VC2[A], and VC1[B]. The central axes of some of the vertical channels VC1[A], VC2[A], and VC1[B] may not overlap with the central axes of the source channels SC1[A], SC2[A], and SC1[B], but may be misaligned with them. Some of the vertical channels VC1[A], VC2[A], and VC1[B] may not overlap with the source channels SC1[A], SC2[A], and SC1[B]. Two or more of the vertical channels VC1[A], VC2[A], and VC1[B] may overlap with some of the source channels SC1[A], SC2[A], and SC1[B].

[0060] The dummy channel DVC[A] may not overlap with the source channels SC1[A], SC2[A], and SC1[B]. The dummy channel DVC[A] can be arranged in a row along the extension direction of the drain-side slit SD.

[0061] Figure 3C It is shown that... Figure 3B The diagram shows the plan view of the bit line BL where the vertical channels VC1[A], VC2[A] and VC1[B] overlap.

[0062] Reference Figure 3C Each bit line BL can be connected to the reference via contact plug CT. Figure 3B The vertical channels VC1[A], VC2[A], and VC1[B] are described. The vertical channels VC1[A], VC2[A], and VC1[B] connected to a single bit line can be individually controlled by different drain selection lines DSL1[A], DSL2[A], and DSL1[B], such as... Figure 3B As shown.

[0063] Figure 4A and Figure 4B The diagram illustrates the gate stack structure and bit line layout of a semiconductor memory device according to embodiments of the present disclosure.

[0064] Figure 4A This is a plan view showing the first gate stack structure GST[A] and the second gate stack structure GST[B]. Figure 4A The layout of multiple word lines WL[A] and drain select lines DSL1[A] and DSL2[A] of the first gate stack structure GST[A] and multiple word lines WL[B] and drain select lines DSL1[B] of the second gate stack structure GST[B] is shown.

[0065] Reference Figure 4A The drain-side slit SD, which overlaps with multiple word lines (e.g., WL[A]), may have a different shape than the slit SI between the first gate stack structure GST[A] and the second gate stack structure GST[B]. In an embodiment, the slit SI may extend in a linear shape in the second direction D2, and the drain-side slit SD may extend in a wavy shape in the second direction D2.

[0066] The first gate stack structure GST[A] and the second gate stack structure GST[B] can be penetrated by the vertical channels VC1[A], VC2[A] and VC1[B] surrounded by the memory layer ML. The vertical channels VC1[A], VC2[A] and VC1[B] can be arranged in a sawtooth pattern. The drain-side slit SD can have a wavy sidewall corresponding to the sidewall shape of the adjacent vertical channels (e.g., VC1[A] and VC2[A]), and the drain-side slit SD is inserted between the vertical channels (VC1[A] and VC2[A]).

[0067] Figure 4B It is shown that... Figure 4A The diagram shows the plan view of the bit line BL where the vertical channels VC1[A], VC2[A] and VC1[B] overlap.

[0068] Reference Figure 4B Each bit line BL can be connected to the reference via contact plug CT. Figure 4A The vertical channels VC1[A], VC2[A], and VC1[B] are described. The vertical channels VC1[A], VC2[A], and VC1[B] connected to a single bit line can be individually controlled by different drain selection lines DSL1[A], DSL2[A], and DSL1[B], such as... Figure 4A As shown.

[0069] Figures 5A to 5C This is a plan view showing various implementations of the source channel CS.

[0070] Reference Figures 5A to 5C Each source channel SC can be surrounded by a source select line SSL, with a gate insulating layer GI interposed between them. The source channels SC can have various layouts.

[0071] Reference Figures 5A to 5C Each source channel SC may extend in the first direction D1 and have an elliptical cross-sectional shape. The cross-sectional shape of each source channel SC is not limited to an elliptical shape and may have various shapes such as circular and polygonal shapes.

[0072] Reference Figure 5A In this embodiment, the minor and major axes of the elliptical shape may be parallel to the axis extending in the second direction D2 and the axis extending in the third direction D3, respectively. (Refer to...) Figure 5B and Figure 5C In another embodiment, the minor axis and major axis of the elliptical shape may be oriented relative to the tilt direction of the axis extending in the second direction D2 and the axis extending in the third direction D3, respectively.

[0073] Reference Figures 5A to 5C The source channel SC may include a row of channels arranged along the second direction D2. In an implementation, such as Figure 5A and Figure 5C As shown, the source channel SC may include a channel array. In another embodiment, as... Figure 5B As shown, the source channel SC may include two channel columns. However, this disclosure is not limited thereto, and the source channel SC may include three or more channel columns.

[0074] Figures 6A to 6C This is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure. Figure 6A and Figure 6C This shows the cell array region of a semiconductor memory device. Figure 6B The connection area of ​​the semiconductor memory device is shown.

[0075] Reference Figures 6A to 6C The semiconductor memory device may include: a peripheral circuit structure 10; a gate stack structure GST that overlaps with the peripheral circuit structure 10 and surrounds a plurality of vertical channels VC1 and VC2; a common source layer CSL disposed between the gate stack structure GST and the peripheral circuit structure 10; source select lines SSL1 and SSL2 disposed at substantially the same height between the common source layer CSL and the gate stack structure GST and spaced apart from each other; connection patterns CP1 and CP2 disposed at substantially the same height between the source select lines SSL1 and SSL2 and the gate stack structure GST and spaced apart from each other; and a bit line BL that overlaps with the connection patterns CP1 and CP2, with the gate stack structure GST interposed between them.

[0076] The gate stack structure GST may include interlayer insulating layers 51 and conductive patterns 53 alternately stacked in a first direction D1 extending vertical channels VC1 and VC2. The conductive patterns 53 may be formed of various conductive materials. The conductive patterns 53 may include drain select lines DSL1 and DSL2 overlapping source select lines SSL1 and SSL2 respectively, and word lines WL disposed between and spaced apart from the drain select lines DSL1 and DSL2 and the source select lines SSL1 and SSL2.

[0077] The gate stack structure GST can be penetrated by vertical channels VC1 and VC2. Each of the vertical channels VC1 and VC2 may include a vertical core insulating layer 43 and a vertical channel layer 41. The vertical channel layer 41 may extend along the sidewall of the vertical core insulating layer 43 and may extend along the surface of the vertical core insulating layer 43 facing the bit line BL. The vertical channel layer 41 may include a semiconductor layer that can be used as a channel for a memory cell string. In an embodiment, the vertical channel layer 41 may include silicon.

[0078] The sidewalls of each of the vertical channels VC1 and VC2 may be surrounded by a memory layer ML. A portion of the memory layer ML may be used as a data storage area. A portion of the memory layer ML may be defined at the intersection of each of the vertical channels VC1 and VC2 with the word line WL.

[0079] Bit line BL can be formed of various conductive materials. Bit line BL can be spaced apart from gate stack structure GST. In an embodiment, bit line BL can be insulated from gate stack structure GST through a first upper insulating layer 83 and a second upper insulating layer 87. The first upper insulating layer 83 and the second upper insulating layer 87 can extend between bit line BL and gate stack structure GST. Bit line BL can be connected to vertical channels VC1 and VC2 through contact plugs CT formed of conductive material. Each contact plug CT can penetrate the upper insulating layers 83 and 87 and the memory layer ML between vertical channel layer 41 and bit line BL and can contact vertical channel layer 41 and bit line BL.

[0080] Each of the connecting patterns CP1 and CP2 may include a doped semiconductor layer 47. In one embodiment, the doped semiconductor layer 47 may include a doped silicon layer. The doped semiconductor layer 47 may include a conductive impurity. In one embodiment, the doped semiconductor layer 47 may include an n-type impurity such as phosphorus. The doped semiconductor layer 47 may include a line portion 47A extending parallel to each of the source select lines SSL1 and SSL2, and a protrusion 47B projecting from the line portion 47A toward the vertical core insulating layer 43. The protrusion 47B of the doped semiconductor layer 47 may have sidewalls surrounded by the vertical channel layer 41.

[0081] The vertical channel layer 41 may protrude further than the vertical core insulating layer 43 toward the line portion 47A of the doped semiconductor layer 47 to surround the sidewall of the protrusion 74B of the doped semiconductor layer 47. The vertical channel layer 41 may contact the protrusion 47B of the doped semiconductor layer 47. Since the protrusion 47B includes a conductive dopant, the resistivity of the protrusion 47B may be lower than that of the undoped semiconductor layer. Because the vertical channel layer 41 contacts the protrusion 47B with low resistivity, the channel current in the vertical channel layer 41 may be improved.

[0082] Source select lines SSL1 and SSL2 can be formed of various conductive materials. Source select lines SSL1 and SSL2 can be spaced apart from connection patterns CP1 and CP2 and the common source layer CSL. In one embodiment, source select lines SSL1 and SSL2 can be insulated from connection patterns CP1 and CP2 by a first insulating layer 55, and from the common source layer CSL by a second insulating layer 59. The first insulating layer 55 can extend between connection patterns CP1 and CP2 and source select lines SSL1 and SSL2. The second insulating layer 59 can extend between source select lines SSL1 and SSL2 and the common source layer CSL.

[0083] The first insulating layer 55, source select lines SSL1 and SSL2, and the second insulating layer 59 are permeable by source channels SC1 and SC2. Each of the source channels SC1 and SC2 may include a source core insulating layer 63 and a source channel layer 61. The source channel layer 61 may extend along the sidewalls of the source core insulating layer 63 and along the surface of the source core insulating layer 63 facing the connection patterns CP1 and CP2. The source channel layer 61 may include a semiconductor layer that can be used as a channel for a source select transistor. In an embodiment, the source channel layer 61 may include silicon. The sidewalls of each of the source channels SC1 and SC2 facing the source select lines SSL and SSL2 may be surrounded by a gate insulating layer GI.

[0084] The common source layer CSL may include a line portion 67A extending parallel to the source select lines SSL1 and SSL2, and a protrusion 67B projecting from the line portion 67A toward the source core insulating layer 63. The common source layer CSL may include a doped semiconductor layer. In one embodiment, the common source layer CSL may include a doped silicon layer. The doped semiconductor layer of the common source layer CSL may include a conductivity type impurity. In one embodiment, the doped semiconductor layer of the common source layer CSL may include an n-type impurity such as phosphorus. The protrusion 67B of the common source layer CSL may have sidewalls surrounded by the source channel layer 61.

[0085] The source channel layer 61 may protrude further than the source core insulating layer 63 toward the line portion 67A of the common source layer CSL to surround the sidewall of the protrusion 67B of the common source layer CSL. The source channel layer 61 may contact the protrusion 67B of the common source layer CSL. Since the protrusion 67B includes a conductive dopant, the resistivity of the protrusion 67B may be lower than that of the undoped semiconductor layer. Because the source channel layer 61 contacts the protrusion 67B with low resistivity, the channel current in the source channel layer 61 may be improved.

[0086] The first bonding insulating layer 71 may be disposed between the common source layer CSL and the peripheral circuit structure 10. The first bonding insulating layer 71 may protrude further in the second direction D2 than each of the gate stack structure GST, source select lines SSL1 and SSL2, and the common source layer CSL, such as... Figure 6B As shown. The space between the portion of the first upper insulating layer 83 and the first bonding insulating layer 71 that protrudes further than the common source layer CSL in the second direction D2 can be filled by the first insulating structure 90, as shown. Figure 6B As shown.

[0087] The peripheral circuit structure 10 may include: a substrate 1 including a plurality of transistors 20; a second insulating structure 31 covering the first substrate 1; a plurality of interconnect structures 29 embedded in the second insulating structure 31; and a second bonding insulating layer 33 covering the plurality of interconnect structures 29 and the second insulating structure 31. The interconnect structures 29 may be connected to the transistors 20 and may transmit electrical signals.

[0088] The substrate 1 may be a semiconductor substrate such as a silicon substrate or a germanium substrate. The first substrate 1 may include active regions separated by an isolation layer 3. Transistors 20 may be disposed on the active regions. Each transistor 20 may include a gate insulating layer 11 and a gate electrode 13 stacked on the active regions of the substrate 1, and a junction 15 defined in the substrate 1 on both sides of the gate electrode 13. The junction 15 may be defined when at least one of p-type impurities and n-type impurities is doped in the active regions of the substrate 1.

[0089] Multiple transistors 20 may be included in peripheral circuitry to control the operation of the semiconductor memory device. In one embodiment, at least one transistor 20 may be included in a source control circuit 5. The source control circuit 5 is connected to a common source layer CSL via interconnect structures 29 and can control the discharge of the common source layer CSL. In one embodiment, the interconnect structures 29 connected to the source control circuit 5 may include a lower contact structure 21, an interconnect line 23, and an upper contact structure 25. The lower contact structure 21 may be connected to a junction 15 of the source control circuit 5, such as... Figure 6A As shown. The lower contact structure 21 may include patterns 21A, 21B, and 21C sequentially stacked on the junction 15. The upper contact structure 25 may be disposed in the connection area. The interconnect 23 may be connected to... Figure 6A The lower contact structure 21 shown is in contact and can extend to... Figure 6B The connection area shown is in contact with the upper contact structure 25. In other words, the lower contact structure 21 and the upper contact structure 25 can be connected to each other via the interconnect 23.

[0090] The second insulating structure 31 may include multiple insulating layers, each comprising two or more layers.

[0091] The first bonding insulating layer 71 and the second bonding insulating layer 33 can be bonded to each other to form a bonding structure BS.

[0092] Figure 6A This is a cross-sectional view of a semiconductor memory device taken along a line intersecting the bit line BL, and corresponding to... Figure 4B The cross-sectional view taken by line A-A' is shown.

[0093] Reference Figure 6AThe source channels SC1 can be connected to the connection pattern CP1 in the same region at a lower density than the vertical channels VC1. In an embodiment, the number of source channels SC1 connected to the connection pattern CP1 can be less than the number of vertical channels VC1 connected to the connection pattern CP1.

[0094] The source channel layer 61 may include a semiconductor layer having a contact pattern 61A and a pillar 61B. The contact pattern 61A may be connected to a connection pattern CP1. The pillar 61B may extend from the edge of the contact pattern 61A toward the common source layer CSL in a first direction D1. The sidewalls of the source core insulating layer 63 may be surrounded by the pillar 61B of the source channel layer 61 between the contact pattern 61A and the common source layer CSL. The pillar 61B of the source channel layer 61 may extend to surround a protrusion 67B of the common source layer CSL.

[0095] Impurities in the doped semiconductor layer 47 can diffuse into the contact pattern 61A, and impurities in the common source layer CSL can diffuse into the portion of pillar 61B that contacts the protrusion 67B of the common source layer CSL. Pillar 61B may include an undoped region UA. The undoped region UA ​​of pillar 61B can be defined as the region to which impurities in the doped semiconductor layer 47 and the common source layer CSL have not diffused. More specifically, a portion of pillar 61B may be retained as the undoped region UA ​​at the height between the connection pattern CP1 and the common source layer CSL. In an embodiment, the undoped region UA ​​of pillar 61B may be retained at the height at which the source select line SSL1 is set. The cutoff characteristics of the source select transistor connected to the source select line SSL1 can be improved by the undoped region UA ​​of pillar 61B.

[0096] The vertical core insulating layer 43 may include a first surface SU1 and a second surface SU2 facing opposite directions. The first surface SU1 may face the connection pattern CP1, and the second surface SU2 may face the bit line BL. The vertical channel layer 41 may extend along the second surface SU2 of the vertical core insulating layer 43 and may extend between the vertical core insulating layer 43 and the gate stack structure GST.

[0097] The bit line BL can be arranged in the second direction D2 at a narrower spacing than that of the vertical channel VC1. The bit line BL can penetrate the third upper insulating layer 99 and can make contact with the contact plug CT.

[0098] Figure 6B Show Figure 6A The ends of the source selection line SSL and the common source layer CSL are shown. Figure 6B This is a cross-sectional view of the common source layer CSL and the source selection line SSL1 taken along a line parallel to the second direction D2.

[0099] Reference Figure 6BThe common source layer CSL and the source selection line SSL1 may extend in the second direction D2. The ends of the source selection line SSL1 and the ends of the common source layer CSL may form a stepped structure. More specifically, the common source layer CSL may include a contact region CTA that protrudes further into the second direction D2 than the source selection line SSL1.

[0100] The common source layer (CSL) can be connected to the interconnect structure 29 via a first vertical contact plug 85A, an upper conductive pattern (UCP), and a second vertical contact plug 85B. The first vertical contact plug 85A can contact the contact region (CTA) of the common source layer (CSL), and the second vertical contact plug 85B can contact the interconnect structure 29. The upper conductive pattern (UCP) connects the first vertical contact plug 85A and the second vertical contact plug 85B to each other.

[0101] The first vertical contact plug 85A and the second vertical contact plug 85B may extend parallel to each other to penetrate the first insulating structure 90 and the first upper insulating layer 83, and may be formed of various conductive materials. The first insulating structure 90 may include multiple insulating layers. In an embodiment, the first insulating structure 90 may include a first filling insulating layer 91, a second filling insulating layer 95, and a third filling insulating layer 97. The first filling insulating layer 91 may be as follows: Figure 6A The third insulating layer 97 is disposed at the same height as the gate layer GST and can extend to the height of the line portion 47A of the doped semiconductor layer 47. The second insulating layer 95 can be disposed at the same height as the stacked structure of the source select line SSL1 and the first insulating layer 55. The third insulating layer 97 can be disposed at the same height as the stacked structure of the second insulating layer 59 and the common source layer CSL.

[0102] The first vertical contact plug 85A may extend in a first direction D1 to penetrate the first upper insulating layer 83, the first filler insulating layer 91, the second filler insulating layer 95, and the second insulating layer 59. The first vertical contact plug 85A may include a surface that contacts the contact region CTA of the common source layer CSL.

[0103] The second vertical contact plug 85B may extend in the first direction D1 to penetrate the first upper insulating layer 83, the first filler insulating layer 91, the second filler insulating layer 95, the third filler insulating layer 97, and the bonding structure BS. The second vertical contact plug 85B may include a surface that contacts the upper contact structure 25 of the interconnect structure 29. The upper contact structure 25 may be a portion of the interconnect structure 29 connected to the source control circuit 5, such as... Figure 6A As shown. The upper contact structure 25 may include a through-hole plug that contacts the interconnect 23 and a pad pattern 25B disposed between the through-hole plug 25A and the second vertical contact plug 85B.

[0104] The upper conductive pattern UCP can be connected to the first vertical contact plug 85A and the second vertical contact plug 85B via the first through-hole plug 89A and the second through-hole plug 89B. The first through-hole plug 89A and the second through-hole plug 89B can be formed of the same conductive material as the contact plug CT, such as... Figure 6A As shown. The first through-hole plug 89A and the second through-hole plug 89B can penetrate the second upper insulating layer 87 and can contact the first vertical contact plug 85A and the second vertical contact plug 85B, respectively. The upper conductive pattern UCP can penetrate the third insulating layer 99 and can extend from the first through-hole plug 89A toward the second through-hole plug 89B.

[0105] Figure 6C It is a cross-sectional view of a semiconductor memory device taken along a line parallel to the bit line BL. Figure 6C Corresponding to along Figure 4B The cross-sectional view taken by line B-B' is shown.

[0106] Reference Figure 6C Source channels SC1 and SC2 may include a first source channel SC1 and a second source channel SC2 that extend parallel to each other.

[0107] Source select lines SSL1 and SSL2 may include a first source select line SSL1 and a second source select line SSL2 isolated from each other by a source side slit SS. The first source select line SSL1 may surround the sidewall of the first source channel SC1, and the second source select line SSL2 may surround the sidewall of the second source channel SC2.

[0108] Vertical channels VC1 and VC2 may include a first vertical channel VC1 and a second vertical channel VC2. The first vertical channel VC1 may overlap with the first source select line SSL1. The second vertical channel VC2 may overlap with the second source select line SSL2.

[0109] The connection patterns CP1 and CP2 may include a first connection pattern CP1 and a second connection pattern CP2 isolated from each other by a source-side slit SS. The first connection pattern CP1 may connect a first source channel SC1 and a first vertical channel VC1 between a first source select line SSL1 and a gate stack structure GST. The second connection pattern CP2 may connect a second source channel SC2 and a second vertical channel VC2 between a second source select line SSL2 and a gate stack structure GST.

[0110] The second insulating layer 59 may extend to fill the source-side slit SS. In one embodiment, the second insulating layer 59 may be disposed between the first source select line SSL1 and the second source select line SSL2. Additionally, the second insulating layer 59 may penetrate the first insulating layer 55 and may extend between the first connection pattern CP1 and the second connection pattern CP2.

[0111] Drain select lines DSL1 and DSL2 may include a first drain select line DSL1 and a second drain select line DSL2 isolated from each other by a drain-side slit SD. The first drain select line DSL1 may overlap with a first source select line SSL1 and surround a first vertical channel VC1. The second drain select line DSL2 may overlap with a second source select line SSL2 and surround a second vertical channel VC2.

[0112] Each conductive pattern 53 used as a word line WL may surround a first vertical channel VC1 between a first drain select line DSL1 and a first connection pattern CP1. Each conductive pattern 53 used as a word line WL may extend between a second drain select line DSL2 and a second connection pattern CP2 to surround a second vertical channel VC2.

[0113] The first upper insulating layer 83 may extend to fill the drain-side slit SD. In one embodiment, the first upper insulating layer 83 may penetrate an interlayer insulating layer adjacent to the first upper insulating layer 83 within the interlayer insulating layer 51, and may extend between the first drain select line DSL1 and the second drain select line DSL2. The first vertical channel VC1 and the second vertical channel VC2 may extend into the interior of the first upper insulating layer 83.

[0114] Bit line BL can extend in the third direction D3 to overlap with the first connection pattern CP1 and the second connection pattern CP2. Bit line BL can be connected to a pair of first vertical channels VC1 and second vertical channels VC2 corresponding to bit line BL via contact plugs CT.

[0115] Figures 7A to 7B This is an enlarged view showing the cross-section of the vertical channel VC and the source channel SC according to an embodiment of the present disclosure.

[0116] Reference Figure 7A The vertical channel VC may be surrounded by a conductive pattern 53, and the memory layer ML is interposed between the vertical channel VC and the conductive pattern 53. The memory layer ML may include a tunnel insulating layer TI, a data storage layer DS, and a barrier insulating layer BI.

[0117] The tunnel insulation layer TI may extend along the surface of the vertical trench layer 41. The tunnel insulation layer TI may include a charge-tunable insulating material. In one embodiment, the tunnel insulation layer TI may include a silicon oxide layer.

[0118] The data storage layer DS may extend along the surface of the tunnel insulation layer TI. The data storage layer DS may include a material layer capable of storing data. In one embodiment, the data storage layer DS may include a nitride layer capable of storing data altered by the Fowler-Nordheim tunneling.

[0119] The barrier insulating layer BI may extend along the surface of the data storage layer DS. The barrier insulating layer BI may include an oxide layer.

[0120] The vertical core insulating layer 43 of the vertical channel VC can be separated from the memory layer ML by the vertical channel layer 41.

[0121] Reference Figure 7B The source core insulating layer 63 of the source channel SC can be separated from the source select line SSL by the gate insulating layer GI and the source channel layer 61. The pillar 61B of the source channel layer 61 can be surrounded by the source select line SSL, and the gate insulating layer GI is inserted between the pillar 61B and the source select line SSL.

[0122] Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 10E , Figure 10F , Figure 11 , Figure 12A , Figure 12B and Figure 12C This is a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0123] Figure 8A and Figure 8B This is a cross-sectional view showing the process of forming the preliminary gate stack structure 110, the conductive layer 137, and the select gate layer 143.

[0124] Reference Figure 8A A preliminary gate stack structure 110, penetrating the memory layer 123 and a plurality of vertical channels 130, can be formed on the sacrificial substrate 101, which includes a first region A1 and a second region A2. The sacrificial substrate 101 may be a silicon substrate.

[0125] A preliminary gate stack structure 110 may be formed on a first region A1 of the sacrificial substrate 101. The preliminary gate stack structure 110 may be penetrated by a plurality of vertical channel vias 121 extending in a first direction D1. The plurality of vertical channel vias 121 may extend into the first region A1 of the sacrificial substrate 101.

[0126] The memory layer 123 may extend along the surface of each vertical channel via 121. The memory layer 123 may include... Figure 7A The barrier insulation layer BI, data storage layer DS, and tunnel insulation layer TI are shown.

[0127] Each vertical channel 130 may include a vertical channel layer 131 and a vertical core insulating layer 133. The vertical channel layer 131 may extend along the surface of the memory layer 123, and a central region of the vertical channel via 121 may be open. The vertical channel layer 131 may include a semiconductor layer. In one embodiment, the vertical channel layer 131 may include undoped silicon. The vertical core insulating layer 133 may be disposed in the central region of the vertical channel via 121 open through the vertical channel layer 131.

[0128] The initial gate stack structure 110 may include interlayer insulating layers 111 and conductive patterns 113 alternately stacked on a first region A1 of the sacrificial substrate 101. The interlayer insulating layers 111 and conductive patterns 113 may surround a plurality of vertical channels 130, and the memory layer 123 is interposed between the plurality of vertical channels 130 and each of the interlayer insulating layers 111 and conductive patterns 113. The plurality of vertical channels 130 may include a first vertical channel 130A and a second vertical channel 130B.

[0129] Subsequently, a conductive layer 137 connected to the plurality of vertical channels 130 may be formed on the initial gate stack structure 110. The conductive layer 137 may include a doped semiconductor layer. In an embodiment, the conductive layer 137 may include a doped silicon layer, and the doped silicon layer may include an n-type impurity. The conductive layer 137 may extend toward the central region of each vertical channel via 121.

[0130] In one embodiment, the process of forming the conductive layer 137 may include etching a portion of the vertical core insulating layer 133 to define a first recessed region 135 in the central region of the vertical channel via 121, and forming a doped semiconductor layer on the initial gate stack 110 to fill the first recessed region 135. A portion of the inner wall of the vertical channel layer 131 may be exposed through the first recessed region 135.

[0131] The conductive layer 137 and the initial gate stack structure 110 may be patterned to not overlap with the second region A2 of the sacrificial substrate 101. The second region A2 may be a region extending from the first region A1 of the sacrificial substrate 101. In an example, the second region A2 may extend from the first region A1 in a second direction D2 intersecting with the plurality of vertical channels 130.

[0132] Subsequently, a first filler insulating layer 115 may be formed. The first filler insulating layer 115 may cover the second region A2 of the sacrificial substrate 101 that is opened through the conductive layer 137 and the initial gate stack structure 110. The first filler insulating layer 115 may extend to the height of the conductive layer 137.

[0133] Reference Figure 8BA first insulating layer 141 and a select gate layer 143 may be formed on the conductive layer 137. The first insulating layer 141 and the select gate layer 143 may extend to cover the first filler insulating layer 115. The select gate layer 143 may be formed of various conductive materials.

[0134] Figure 9A and Figure 9B It is shown in the reference Figure 8B A cross-sectional view of the process for forming the source selection line 143S, which continues after the described process. Figure 9A It is a cross-sectional view taken along an axis parallel to one of the source selection lines 143S. Figure 9B It is a cross-sectional view taken along the axis intersecting the source selection line 143S.

[0135] Reference Figure 9A and Figure 9B Through-holes can be formed by etching the selective gate layer 143, the first insulating layer 141, and the conductive layer 137. Figure 8B The source-side slit 145 of the select gate layer 143, the first insulating layer 141, and the conductive layer 137 is shown. Therefore, the select gate layer 143 can be isolated into multiple source select lines 143S, and the conductive layer 137 can be isolated into multiple connection patterns 137CP.

[0136] Multiple source select lines 143S may include a first source select line and a second source select line, and multiple connection patterns 137CP may include a first connection pattern and a second connection pattern. The first connection pattern may contact the first vertical channel 130A, and the second connection pattern may contact the second vertical channel 130B. For example... Figure 9B As shown, the first source selection line may overlap with the first vertical channel 130A, and the second source selection line may overlap with the second vertical channel.

[0137] Each source selection line 143S may include an end EG[S] that overlaps with the first filler insulating layer 115.

[0138] Figures 10A to 10F It is shown in the reference Figure 9A and Figure 9B A cross-sectional view of the process that continues after the described process. Figures 10A to 10F Each of these is a cross-sectional view taken along an axis parallel to one of the source selection lines 143S.

[0139] Reference Figure 10A A second filling insulating layer 151 covering the end EG[S] of the source selection line 143S can be formed on the first filling insulating layer 115.

[0140] Subsequently, a second insulating layer 153 may be formed. The second insulating layer 153 may cover the source selection line 143S. The second insulating layer 153 may extend to cover the second filler insulating layer 151.

[0141] Subsequently, source channel vias 157 can be formed. Source channel vias 157 can penetrate the second insulating layer 153, the source select line 143S, and the first insulating layer 141, and can expose the connection pattern 137CP. Subsequently, gate insulating layers 155 can be formed on the sidewalls of the source select line 143S exposed through the respective source channel vias 157.

[0142] In one embodiment, the gate insulating layer 155 can be formed by an oxidation process. During the oxidation process of forming the gate insulating layer 155, the oxide layer formed on the surface of the connection pattern 137CP can be removed by an etch-back process.

[0143] Reference Figure 10B They can be filled with source channels 160 respectively. Figure 10A The source channel hole 157 is shown. The source channel 160 can contact the connection pattern 137CP.

[0144] The process of forming the source channel 160 may include along... Figure 10A The process of forming an undoped semiconductor layer 161 on the surface of each source channel via 157 shown, and the process of forming a source core insulating layer 163 on the undoped semiconductor layer 161 are illustrated. In an embodiment, the undoped semiconductor layer 161 may include undoped silicon. The undoped semiconductor layer 161 may be spaced apart from the source select line 143S by a gate insulating layer 155. The source core insulating layer 163 may be filled with... Figure 10A The central region of each source channel hole 157 shown.

[0145] Subsequently, a portion of the source core insulating layer 163 can be etched to define a second recessed region 165. A portion of the inner wall of the undoped semiconductor layer 161 can be exposed through the second recessed region 165.

[0146] Reference Figure 10C A doped semiconductor layer can be formed on the second insulating layer 153 to achieve the following: Figure 10B The second recessed region 165 is shown to be filled. In an embodiment, the doped semiconductor layer may include an n-type impurity and may include a doped silicon layer.

[0147] Subsequently, the doped semiconductor layer and the second insulating layer 153 can be etched. Thus, the doped semiconductor layer can be retained as a common source layer 167L connected to the source channel 160.

[0148] The common source layer 167L may include an end EG[C] overlapping with the second filler insulating layer 151. The end EG[C] of the common source layer 167L may protrude further in the second direction D2 than the end EG[S] of the source selection line 143S.

[0149] The common source layer 167L may include a line portion 167A and a protrusion 167B. The line portion 167A may be parallel to the source selection line 143S. The protrusion 167B may extend from the line portion 167A toward the source core insulating layer 163. Figure 10B The second recessed region 165 shown can be filled by a protrusion 167B corresponding to the second recessed region 165. In addition, the protrusion 167B corresponding to the second recessed region 165 can contact the inner wall of the undoped semiconductor layer 161.

[0150] Reference Figure 10D A third filling insulating layer 169 may be formed on the second filling insulating layer 151. The third filling insulating layer 169 may cover the end EG[C] of the common source layer 167L.

[0151] Subsequently, a first bonding insulating layer 171 may be formed. The first bonding insulating layer 171 may cover the common source layer 167L. The first bonding insulating layer 171 may extend to cover the third filler insulating layer 169.

[0152] Reference Figure 10E It can provide a peripheral circuit structure 200 formed through a separate process. See reference... Figure 6A and Figure 6B As described, the peripheral circuit structure 200 may include a substrate 201 having a plurality of transistors 210, an insulating structure 231 covering the substrate 201, a plurality of interconnect structures buried in the insulating structure 231, and a second bonding insulating layer 233 covering the plurality of interconnect structures and the insulating structure 231.

[0153] Transistors 210 may be insulated from each other by an isolation layer 203 formed in substrate 201. At least one transistor 210 may be included in source control circuit 205. Interconnection structures connected to source control circuit 205 may include a lower contact structure 221, an upper contact structure 225, and an interconnect line 223. The lower contact structure 221 may be connected to transistor 210 of source control circuit 205. The upper contact structure 225 may not overlap with transistor 210 of source control circuit 200. Interconnect line 223 may connect lower contact structure 221 and upper contact structure 225. Lower contact structure 221 may include patterns 221A, 221B, and 221C sequentially stacked between transistor 210 of source control circuit 205 and interconnect line 223. Transistor 210 of source control circuit 205 may be connected to interconnect line 223 via lower contact structure 221. Interconnect line 223 may extend toward upper contact structure 225 in a second direction D2. The upper contact structure 225 may include a through-hole plug 225A and a pad pattern 225B. The through-hole plug 225A may contact the interconnect 223. The pad pattern 225B may be disposed on the through-hole plug 225A.

[0154] The sacrificial substrate 101 may overlap with the peripheral circuit structure 200, such that the first bonding insulating layer 171 faces the second bonding insulating layer 233 of the peripheral circuit structure 200. Subsequently, a process may be formed to bond the first bonding insulating layer 171 and the second bonding insulating layer 233 to each other.

[0155] Reference Figure 10F It can remove Figure 10E The sacrificial substrate 101 is shown. Therefore, the memory layer 123 penetrating the initial gate stack structure 110 is exposed. Subsequently, conductive impurities can be implanted into the ends of each vertical channel 130. In this embodiment, n-type impurities can be implanted into the ends of the vertical channel 130.

[0156] Figure 11 It is shown in the reference Figure 10F A cross-sectional view of the process for forming the drain selection line 113D, which continues after the described process. Figure 11 It is a cross-sectional view taken along the axis intersecting the source selection line 143S.

[0157] Reference Figure 11 This can form a drain-side slit 181. The drain-side slit 181 can penetrate... Figure 10F A portion of the preliminary gate stack structure 110 shown makes Figure 10F At least one conductive pattern in the conductive pattern 113 of the preliminary gate stack structure 110 shown is isolated into a drain select line 113D. The drain select line 113D may overlap with the source select line 143S. Therefore, the gate stack structure 110G can be defined.

[0158] The drain-side slit 181 can be extended to penetrate as... Figure 10F At least one conductive pattern among the conductive patterns 113 of the preliminary gate stack structure 110 shown.

[0159] The conductive patterns stacked between the drain select line 113D and the source select line 143S, spaced apart from each other, are not penetrated by the drain-side slit 181, but can be retained as word lines 113W. The drain select line 113D may include a first drain select line surrounding a first vertical channel 130A and a second drain select line surrounding a second vertical channel 130B.

[0160] Figures 12A to 12C This is shown in the execution reference. Figure 11 A cross-sectional view of an implementation of a process that continues after the described process. Figures 12A to 12C Each of these is a cross-sectional view taken along an axis parallel to one of the source selection lines 143S.

[0161] Reference Figure 12A A first upper insulating layer 183 may be formed. The first upper insulating layer 183 may cover the gate stack structure 110G and the memory layer 123. The first upper insulating layer 183 may extend to overlap with the peripheral circuit structure 200, and a first filling insulating layer 115, a second filling insulating layer 151 and a third filling insulating layer 169 are interposed between the first upper insulating layer 183 and the peripheral circuit structure 200.

[0162] Subsequently, vertical contact plugs 185A and 185B can be formed. Vertical contact plugs 185A and 185B can penetrate the first upper insulating layer 183, the first filler insulating layer 115, and the second filler insulating layer 151. Vertical contact plugs 185A and 185B may include a first vertical contact plug 185A and a second vertical contact plug 185B.

[0163] A first vertical contact plug 185A may extend toward the common source layer 167L. The first vertical contact plug 185A may extend to penetrate the second insulating layer 153 disposed between the common source layer 167L and the second fill insulating layer 151. The first vertical contact plug 185A may contact the common source layer 167L. A second vertical contact plug 185B may extend toward the pad pattern 225B connected to the source control circuit 205. The second vertical contact plug 185B may extend to penetrate the third fill insulating layer 169, the first bonding insulating layer 171, and the second bonding insulating layer 233 disposed between the pad pattern 225B and the second fill insulating layer 151. The second vertical contact plug 185B may contact the pad pattern 225B.

[0164] Reference Figure 12BA second upper insulating layer 187 may be formed on the first upper insulating layer 183. The second upper insulating layer 187 may extend to cover the first vertical contact plug 185A and the second vertical contact plug 185B.

[0165] Subsequently, contact holes 189A and 189B can be formed. Contact holes 189A and 189B can penetrate the second upper insulating layer 187. Contact holes 189A and 189B may include a first contact hole 189A and a second contact hole 189B.

[0166] The first contact holes 189A may extend toward the vertical channel 130. Each first contact hole 189A may extend to penetrate the first upper insulating layer 183 and the memory layer 123 disposed between the vertical channel layer 131 and the second upper insulating layer 187. The vertical channel layer 131 may be exposed through the first contact holes 189A.

[0167] A second contact hole 189B can be formed to expose the first vertical contact plug 185A and the second vertical contact plug 185B.

[0168] Reference Figure 12C Conductive materials can be used to fill it. Figure 12A Each of the first contact hole 189A and the second contact hole 189B shown. Thus, a contact plug 191A and a through-hole plug 191B can be formed.

[0169] Each contact plug 191A can be set to Figure 12A The first contact hole 189A shown is in contact with the channel layer 131 of the vertical channel 130. A through-hole plug 191B can be provided. Figure 12A The second contact hole 189B shown can contact the first vertical contact plug 185A and the second vertical contact plug 185B respectively.

[0170] Subsequently, subsequent processes can be carried out to form bit lines and conductive patterns.

[0171] Figure 13 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0172] Reference Figure 13 The memory system 1100 includes a memory device 1120 and a memory controller 1110.

[0173] The memory device 1120 may include a source channel that penetrates the source select line, a gate stack structure that overlaps with the source select line, a connection pattern disposed between the source select line and the gate stack structure, and a vertical channel that is connected to the source channel and penetrates the gate stack structure through the connection pattern.

[0174] The memory device 1120 may be a multi-chip package configured with multiple flash memory chips.

[0175] The storage controller 1110 controls the storage device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory for the CPU 1112, which performs overall control operations for data exchange with the storage controller 1110. The host interface 1113 includes a data exchange protocol for a host connected to the storage system 1100. The error correction block 1114 detects and corrects errors included in data read from the storage device 1120. The memory interface 1115 interfaces with the storage device 1120. The storage controller 1110 may also include a read-only memory (ROM) for storing code data, etc., used for interfacing with the host.

[0176] Figure 14 This is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0177] Reference Figure 14 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. The computing system 1200 may be a mobile device.

[0178] The memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 may include a source channel penetrating the source select line, a gate stack structure overlapping the source select line, a connection pattern disposed between the source select line and the gate stack structure, and a vertical channel connected to the source channel and penetrating the gate stack structure through the connection pattern.

[0179] According to this disclosure, the vertical channel penetrating the gate stack structure and the source channel penetrating the source select line can be connected to each other through a connection pattern disposed between the gate stack structure and the source select line. Therefore, the process load for ensuring the alignment margin between the vertical channel and the source channel can be reduced.

[0180] According to this disclosure, the source channel can be aligned on a connection pattern extending parallel to the gate stack structure. Therefore, the stability of the process for aligning the source channel on the connection pattern can be improved, and the arrangement freedom of the source channel can be improved.

[0181] According to this disclosure, for each source select line isolated from each other by a source-side slit, the memory cell string can be divided into groups that can be selected simultaneously and individually. Therefore, read disturbances can be reduced, thereby improving the operational reliability of the semiconductor memory device.

[0182] Cross-references to related applications

[0183] This application claims priority to Korean Patent Application No. 10-2020-0110556, filed with the Korean Intellectual Property Office on August 31, 2020, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Multiple source channels, wherein the multiple source channels penetrate the source selection line; A gate stack structure that overlaps with the source select line; A connection pattern is disposed between the source select line and the gate stack-up structure, and the connection pattern is collectively connected to the plurality of source channels; as well as Multiple vertical channels penetrate the gate stack structure and are collectively connected to the connection pattern. Wherein, the plurality of source channels and the plurality of vertical channels do not penetrate the connection pattern, such that the connection pattern extends continuously through the plurality of source channels and the plurality of vertical channels.

2. The semiconductor memory device according to claim 1, wherein, The cross-sectional area of ​​each of the source channels is wider than the cross-sectional area of ​​each of the vertical channels.

3. The semiconductor memory device according to claim 1, wherein, There exists at least one case where one of the plurality of source channels overlaps with two or more of the plurality of vertical channels.

4. The semiconductor memory device according to claim 1, wherein, At least one of the plurality of vertical channels does not overlap with the plurality of source channels.

5. The semiconductor memory device according to claim 1, wherein, The number of source channels connected to the connection pattern is less than the number of vertical channels connected to the connection pattern.

6. The semiconductor memory device according to claim 1, further comprising: A common source layer is connected to the plurality of source channels. The common source layer overlaps with the connection pattern, and the plurality of source channels are interposed between the common source layer and the connection pattern. as well as Multiple bit lines are connected to the vertical channels respectively, the bit lines overlap with the connection pattern, and the multiple vertical channels are inserted between the bit lines and the connection pattern.

7. The semiconductor memory device according to claim 1, wherein, The gate stack structure includes multiple interlayer insulating layers and multiple conductive patterns alternately stacked in the direction of the multiple vertical channel extensions, and The conductive pattern includes: A drain selection line that overlaps with the source selection line; and A word line is provided between the drain select line and the source select line.

8. The semiconductor memory device of claim 1, further comprising: A common source layer, which is connected to the plurality of source channels; A substrate, overlapping the gate stack structure, wherein the common source layer is interposed between the substrate and the gate stack structure, the substrate including a transistor; and A bonding structure is disposed between the substrate and the common source layer.

9. The semiconductor memory device according to claim 1, wherein, The connection pattern extends parallel to the source selection line.

10. The semiconductor memory device of claim 1, further comprising a common source layer commonly connected to the plurality of source channels. in, The common source layer includes a contact region that extends further than the source selection line in the direction intersecting the plurality of vertical channels.

11. The semiconductor memory device of claim 10, further comprising: A first vertical contact plug contacts the contact region of the common source layer and extends in the direction in which the plurality of vertical channels extend. A source control circuit, which overlaps with the gate stack structure, and a common source layer is inserted between the source control circuit and the gate stack structure. The source control circuit includes a transistor. An interconnect structure connected to the source control circuit; A second vertical contact plug is connected to the interconnect structure and extends parallel to the first vertical contact plug; as well as An upper conductive pattern is provided, which connects the first vertical contact plug and the second vertical contact plug.

12. The semiconductor memory device of claim 1, further comprising: A gate insulating layer disposed between each of the source channels and the source select line; as well as A memory layer is disposed between each of the vertical channels and the gate stack structure.

13. The semiconductor memory device of claim 1, further comprising a common source layer commonly connected to the plurality of source channels. in, Each of the aforementioned source channels includes: A semiconductor layer, comprising a contact pattern connected to the connection pattern and pillars extending from the edge of the contact pattern toward the common source layer; and A source core insulating layer, which is surrounded by pillars of the semiconductor layer between the contact pattern of the semiconductor layer and the common source layer.

14. The semiconductor memory device according to claim 13, wherein, Each of the source channels includes an undoped region defined at a height between the contact pattern and the common source layer.

15. The semiconductor memory device according to claim 13, wherein, The common source layer includes a doped semiconductor layer, and The doped semiconductor layer of the common source layer includes: A line portion extending parallel to the source selection line; and A protrusion, which is surrounded by pillars of the semiconductor layer between the wire portion and the source core insulating layer.

16. The semiconductor memory device according to claim 1, wherein, Each of the vertical channels includes: A vertical core insulating layer having a first surface facing the connection pattern and a second surface facing a direction opposite to the first surface, the vertical core insulating layer penetrating the gate stack structure; and A semiconductor layer extending along the second surface of the vertical core insulating layer, the semiconductor layer extending between the gate stack and the vertical core insulating layer.

17. The semiconductor memory device of claim 16, wherein, The connection pattern includes a doped semiconductor layer, and The doped semiconductor layer includes: A line portion extending parallel to the source selection line; and A protrusion extending from the wire portion toward the vertical core insulating layer, the protrusion being surrounded by the semiconductor layer.

18. A semiconductor memory device, the semiconductor memory device comprising: A first source channel and a second source channel, the first source channel and the second source channel extending parallel to each other; A first source selection line surrounds the first source channel; A second source selection line surrounds the second source channel; A gate stack structure that overlaps with the first source select line and extends to overlap with the second source select line; A first vertical channel penetrates a first region of the gate stack structure that overlaps with the first source selection line; A second vertical channel penetrates the second region of the gate stack structure that overlaps with the second source select line; A first connection pattern connects the first source channel and the first vertical channel between the first source selection line and the gate stack-up structure, wherein the first source channel and the first vertical channel do not penetrate the first connection pattern so that the first connection pattern extends continuously through the first source channel and the first vertical channel. A second connection pattern connects the second source channel and the second vertical channel between the second source select line and the gate stack structure, wherein the second source channel and the second vertical channel do not penetrate the second connection pattern such that the second connection pattern extends continuously through the second source channel and the second vertical channel; and A source-side slit is disposed between the first source selection line and the second source selection line, and extends between the first connection pattern and the second connection pattern.

19. The semiconductor memory device of claim 18, further comprising a common source layer overlapping the gate stack, wherein the first source select line and the second source select line are interposed between the common source layer and the gate stack, the common source layer being connected to the first source channel and the second source channel.

20. The semiconductor memory device of claim 18, further comprising a bit line overlapping the first connection pattern and the second connection pattern, the gate stack structure being interposed between the bit line and the first connection pattern and the second connection pattern, the bit line being connected to the first vertical channel and the second vertical channel.

21. The semiconductor memory device according to claim 18, wherein, The gate stack structure includes multiple interlayer insulating layers and multiple conductive patterns alternately stacked in the directions extending from the first vertical channel and the second vertical channel, and The conductive pattern includes: A first drain selection line, which overlaps with the first connection pattern, and which surrounds the first vertical channel; A second drain selection line, which overlaps with the second connection pattern, surrounds the second vertical channel; and A word line that surrounds the first vertical channel between the first drain select line and the first connection pattern, and the word line that extends between the second drain select line and the second connection pattern to surround the second vertical channel.

22. The semiconductor memory device of claim 21, further comprising a wavy slit extending between the first drain select line and the second drain select line in a direction intersecting the first vertical channel and the second vertical channel, the wavy slit overlapping the word line.

23. The semiconductor memory device of claim 21, further comprising: A drain-side slit extends between the first drain selection line and the second drain selection line in a direction intersecting the first vertical channel and the second vertical channel; as well as A dummy channel is provided, which overlaps with the drain-side slit and penetrates the word line.

24. A semiconductor memory device, the semiconductor memory device comprising: Multiple source channels, wherein the multiple source channels penetrate the source selection line; A gate stack structure that overlaps with the source select line; Multiple vertical channels, the multiple vertical channels penetrating the gate stack structure; as well as A connection pattern is disposed between the source select line and the gate stack to connect the plurality of vertical channels to the plurality of source channels, wherein the thickness of each of the plurality of vertical channels is different from the thickness of each of the plurality of source channels. Wherein, the plurality of source channels and the plurality of vertical channels do not penetrate the connection pattern, such that the connection pattern extends continuously through the plurality of source channels and the plurality of vertical channels.

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