A semiconductor device and a method of fabricating the same

Abstract

The application relates to the technical field of semiconductor device preparation, in particular to a semiconductor device and a preparation method thereof, which comprises a semiconductor substrate, a first transistor and a second transistor, the first transistor and the second transistor are sequentially arranged above the semiconductor substrate along the thickness direction of the semiconductor substrate, the first transistor and / or the second transistor is a ring-gate transistor, the ring-gate transistor comprises an inner side wall between a gate stack structure and a source-drain, an isolation structure is arranged between the gate stack structure of the first transistor and the gate stack structure of the second transistor, a first gate side wall is arranged above the gate stack structure of the second transistor and extends to both sides of the channel of the second transistor, a second gate side wall is arranged on both sides of the gate stack structures of the first transistor and the second transistor along the width direction of the channel, and the second gate side wall is below the first gate side wall. The application reduces the high aspect ratio problem of gate etching, improves the device integration and reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, and in particular to a gate etching method for nanosheet gate-around transistors and complementary field-effect transistors. Background Technology

[0002] As semiconductor technology nodes continue to shrink to below 3nm, traditional FinFETs are gradually being replaced by Nanosheet-Gate-All-Around FETs (GAAFETs) and Complementary Field-Effect Transistors (CFETs) due to the limitations of short-channel effect (SCE). These new devices employ a gate-all-around (GAA) structure, which provides better gate control, thereby improving device performance and reducing leakage current.

[0003] However, with the evolution of technology nodes, the manufacturing of CFET and GAA transistors faces the following challenges: Gate pitch reduction: At nodes of 3nm and below, the pitch between gates continues to decrease, resulting in a significant increase in the aspect ratio (AR) of gate etching and a narrowing of the process window.

[0004] Increased gate height: CFET devices have a higher gate height than GAA devices, requiring a thicker hard mask to support high AR etching, which increases process complexity.

[0005] Sidewall etching damage: When removing the sidewall dielectric in the source and drain regions, the gate pitch is extremely small, requiring a large over-etching process, which leads to severe damage to the gate hard mask and sidewalls, greatly increasing the requirements for the etching process.

[0006] Currently, the industry mainly uses the following methods to address the above problems: Increasing the thickness of the hard mask to withstand high AR etching, but this will further increase the etching difficulty and may affect subsequent processes (such as metal filling).

[0007] Optimize the etching process: such as using more advanced reactive ion etching or atomic layer etching, but it is still difficult to completely avoid over-etching damage to the gate and sidewalls.

[0008] In view of this, the present invention is proposed. Summary of the Invention

[0009] The purpose of this invention is to provide a method for fabricating semiconductor devices, which aims to reduce the high aspect ratio problem of gate etching, reduce over-etching damage of the outer wall dielectric, and improve device integration and reliability.

[0010] In a first aspect, the present invention provides a semiconductor device, including a semiconductor substrate; A first transistor and a second transistor are sequentially disposed above the semiconductor substrate along the thickness direction of the semiconductor substrate. The first transistor and / or the second transistor are gate-around transistors, and the gate-around transistor includes an inner wall located between the gate stack structure and the source and drain. An isolation structure is disposed between the gate stack structure of the first transistor and the gate stack structure of the second transistor; The first gate sidewall is disposed on both sides of the upper part of the gate stack structure of the second transistor and extends to both sides of the channel of the second transistor; The second gate sidewall is disposed on both sides of the gate stack structure of the first transistor and the second transistor along the width direction of the channel; The second gate sidewall is located below the first gate sidewall.

[0011] As a preferred embodiment of this technical solution, the inner wall and the isolation structure are made of at least some different materials.

[0012] As a preferred embodiment of this technical solution, the second gate sidewall is integrally formed with the isolation structure.

[0013] As a preferred embodiment of this technical solution, in a cross-section that passes downward through the first gate sidewall and is perpendicular to the channel, the second gate sidewall and the isolation structure form an H-shaped structure.

[0014] As a preferred embodiment of this technical solution, in a cross-section that passes downward through the first gate sidewall and is perpendicular to the channel, the inner sidewall connects the second gate sidewall located on both sides of the channel.

[0015] As a preferred embodiment of this technical solution, the inner wall includes a first inner wall and a second inner wall, wherein the first inner wall is the lowest inner wall between the gate stack structure and the source drain of the first transistor, and the second inner wall is all the inner walls except the first inner wall. In the direction perpendicular to the channel, the height of the first inner wall is Y, and the height of the isolation structure is X, where X / Y is greater than 1.

[0016] As a preferred embodiment of this technical solution, the inner wall includes a first inner wall and a second inner wall, wherein the first inner wall is the lowest inner wall between the gate stack structure and the source drain of the first transistor, and the second inner wall is all the inner walls except the first inner wall. In the direction perpendicular to the channel, the height of the first inner wall is Y, and the height of the second inner wall is Z, where Z / Y is greater than 2.

[0017] As a preferred embodiment of this technical solution, the medium of the isolation structure includes any one of low-k carbon-doped silicon oxyoxide, low-k carbon-doped silicon oxynitride, silicon oxynitride, porous organosilicon glass, and atomic layer deposited oxide.

[0018] In some embodiments of the present invention, the first gate sidewall may be above the top surface of the topmost channel region of the second transistor.

[0019] In other embodiments of the invention, the first gate sidewall may extend below the top surface of the topmost channel region of the second transistor.

[0020] Secondly, the present invention also provides a method for fabricating the above-mentioned semiconductor device, comprising the following steps: A fin stack is formed on a semiconductor substrate by sequentially stacking a channel sacrificial layer and a channel layer. The fin stack includes an upper fin stack and a lower fin stack, which are isolated from each other by an isolation structure sacrificial layer. A false grid is formed on the exposed fin stack surface; A first sidewall dielectric is deposited on both sides of the dummy gate and anisotropically etched to form the first gate sidewall; Using the dummy gate and the first gate sidewall as a mask, the fin stack is etched to form a nanowire stack; The isolation structure sacrificial layer is removed and the isolation dielectric integrated layer is filled to form an isolation structure, and a second gate sidewall is formed on both sides of the channel and below the first gate sidewall. Laterally etch the sacrificial layer of the channel to form a groove, and form an inner sidewall in the groove; Source and drain regions are formed at both ends of the nanowire stack; Isotropic etching of the sacrificial layer forms trenches, releasing nanowires; An alternative gate stack is formed in the trench.

[0021] As a preferred embodiment of this technical solution, the formation of the first gate sidewall includes the following steps: Anisotropic etching of the dummy gate stops at the top of the upper fin stack; First sidewall dielectric is deposited on both sides of the dummy gate and anisotropically etched to form the first gate sidewall.

[0022] As a preferred embodiment of this technical solution, the formation of the second gate sidewall includes the following steps: Using the dummy gate and the first gate sidewall as a mask, the fin stack is etched to form a nanowire stack, and the nanowire stack below the first gate sidewall is etched inward to form a lateral concavity. Remove the isolation structure sacrificial layer and fill it with an isolation dielectric integrated layer to form a second gate sidewall on both sides of the channel and below the first gate sidewall.

[0023] As a preferred embodiment of this technical solution, the formation of the first gate sidewall includes the following steps: Anisotropic etching of the dummy gate is performed and stopped at the bottom of the lower fin stack; After depositing a first sacrificial layer on both sides of the dummy gate and selectively etching the first sacrificial layer until the top of the upper fin stack is just exposed, a first sidewall dielectric is deposited on both sides of the dummy gate and anisotropically etched to form the first gate sidewall.

[0024] As a preferred embodiment of this technical solution, the formation of the second gate sidewall includes the following steps: Remove the first sacrificial layer to form a lateral concave stack of nanowires below the first gate sidewall; Remove the isolation structure sacrificial layer and fill it with an isolation dielectric integrated layer to form a second gate sidewall on both sides of the channel and below the first gate sidewall.

[0025] Thirdly, the present invention also provides an electronic device including the above-mentioned semiconductor device, the electronic device including a smartphone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank.

[0026] The semiconductor device of the present invention has at least the following beneficial effects: The semiconductor device of this invention improves integration density through three-dimensional stacking of the first and second transistors, enhances gate control capability through the ring-gate structure of the first and second transistors, and cleverly solves the manufacturing challenges of high aspect ratios and parasitic capacitance issues through split sidewalls (first gate sidewall and second gate sidewall). Simultaneously, the reliability and stability of the device are ensured by the isolation structure and inner sidewalls. Therefore, this invention provides key technical support for the efficient mass production of nanosheet ring-gate transistors and complementary field-effect transistors at 3nm and below nodes.

[0027] The method for fabricating the semiconductor device of the present invention has at least the following beneficial effects: In the semiconductor device fabrication method of the present invention, the first sidewall is formed by an outer sidewall process and the second sidewall is formed by an isolation dielectric integrated layer process. The semiconductor device obtained by the present invention through optimizing the gate etching method can reduce the over-etching amount of the outer sidewall, reduce the AR ratio of the gate etching, thereby reducing the hard mask thickness, reducing the etching difficulty, protecting the gate sidewall, improving device reliability, simplifying process integration, and improving mass production feasibility. Attached Figure Description

[0028] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0029] Figure 1 This is a top view of the semiconductor device of the present invention; Figure 2 This is a schematic cross-sectional view of the semiconductor device prepared according to the present invention (DD'). Figure 3 This is a schematic cross-sectional view of BB' of the SiGe / Si stacked superlattice layer epitaxially grown on the substrate according to the present invention. Figure 4 This invention uses SiGe / Si multilayer superlattice layers to form multiple periodically distributed fin stacks, and forms shallow trench isolation regions between two adjacent fin stacks. (AA' cross-sectional schematic diagram) Figure 5 This is a schematic cross-sectional view of BB', in which a dummy gate layer and a dummy gate hard mask layer are sequentially formed on the exposed fin stack surface of the present invention. Figure 6 This is a schematic cross-sectional view of BB', showing the anisotropic etching of the dummy gate and stopping at the top of the fin in this invention. Figure 7 This is a schematic cross-sectional view of BB' showing the deposition of the first sidewall medium and the etching of the sidewalls in this invention. Figure 8 This is a schematic cross-sectional view of DD', showing the deposition of the first sidewall medium and the etching of the sidewalls in this invention. Figure 9 This is a schematic diagram of the CC' cross-section at the bottom of the anisotropic etched dummy gate of the present invention; Figure 10 This is a schematic cross-sectional view of the DD' section at the bottom of the anisotropic etched dummy gate of the present invention; Figure 11 This is a schematic cross-sectional view of EE' at the bottom of the anisotropic etched dummy gate of the present invention; Figure 12 This is a schematic cross-sectional view of the DD' that forms a laterally concave shape according to the present invention; Figure 13 This is a schematic cross-sectional view of the laterally concave EE' formed in this invention; Figure 14 This is a schematic diagram of the CC' cross-section of the dummy gate directly etched to the bottom in this invention; Figure 15 This is a schematic cross-sectional view of DD', which is directly etched to the bottom of the dummy gate according to the present invention; Figure 16This is a schematic cross-sectional view of the CC' section of the first sacrificial layer deposited in this invention; Figure 17 This is a schematic cross-sectional view of the first sacrificial layer deposited in this invention. Figure 18 This is a schematic cross-sectional view of BB' of the first sidewall medium deposited according to the present invention; Figure 19 This is a schematic cross-sectional view of the DD' section of the first sidewall medium deposited according to the present invention; Figure 20 This is a schematic cross-sectional view of EE' of the first sidewall medium deposited according to the present invention; Figure 21 This is a schematic cross-sectional view of BB' for removing the fin stacking in the source / drain region according to the present invention; Figure 22 This is a schematic cross-sectional view of BB', showing the removal of the sacrificial layer of the isolation structure in this invention. Figure 23 This is a schematic cross-sectional view of BB', which is the integrated layer of the filling isolation medium of the present invention. Figure 24 This is a schematic cross-sectional view of the DD' section of the integrated layer filled with the isolation medium of the present invention; Figure 25 This is a schematic cross-sectional view of EE', which is the integrated layer of the filling isolation medium of the present invention. Figure 26 This is a schematic cross-sectional view of BB' formed by the transverse groove of the present invention; Figure 27 This is a schematic cross-sectional view of BB' showing the formation of the inner wall of the present invention; Figure 28 This is a schematic cross-sectional view of the EE' section showing the formation of the inner wall of the present invention; Figure 29 This is a schematic cross-sectional view of the semiconductor device prepared according to the present invention.

[0030] Figure label: 1: Semiconductor substrate; 2: First transistor; 3: Second transistor; 4: Inner sidewall; 5: Isolation structure; 6: First gate sidewall; 7: Second gate sidewall; 8: Fin stack; 9: First sacrificial layer; 10: Source / drain region; 11: Outer sidewall; 12: Gate; 13: Dummy gate stack; 14: Hard mask layer; 15: Isolation structure sacrificial layer; 16: Groove. Detailed Implementation

[0031] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "installed," "connected," and "linked" should be interpreted broadly; for example, they may refer to a fixed connection, a detachable connection, or an integral connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection or an indirect connection through an intermediate medium; and they may refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0034] Example 1 like Figure 1-2 and Figure 29 As shown, this embodiment provides a semiconductor device, including a semiconductor substrate 1; The first transistor 2 and the second transistor 3 are sequentially disposed above the semiconductor substrate 1 along the thickness direction of the semiconductor substrate 1. The first transistor 2 and / or the second transistor 3 are gate ring transistors. The gate ring transistor includes an inner wall 4 located between the gate stack structure and the source drain to isolate the gate stack structure during the epitaxial growth of the source drain and prevent the epitaxial material from growing on the gate 12 and causing a short circuit. An isolation structure 5 is disposed between the gate stack structure of the first transistor 2 and the gate stack structure of the second transistor 3 to effectively isolate the gates 12 of the upper and lower transistors, prevent signal crosstalk and leakage current between the upper and lower layers, and ensure the normal function and stability of the device. The first gate sidewall 6 is disposed on both sides of the upper part of the gate stack structure of the second transistor 3 and extends to both sides of the channel of the second transistor 3; the "upper part of the gate stack structure" mentioned here refers to the gate stack portion located above the top channel region, that is, the uppermost part of the gate stack structure of the second transistor 3. The second gate sidewall 7 is disposed on both sides of the gate stack structure of the first transistor 2 and the second transistor 3 along the width direction of the channel; The second gate sidewall 7 is located below the first gate sidewall 6.

[0035] The separate structure of the first gate sidewall 6 and the second gate sidewall 7 successfully solved the etching problem caused by the high aspect ratio structure.

[0036] Furthermore, the fact that the second gate sidewall 7 is located below the first gate sidewall 6 further illustrates that the second gate sidewall 7 can be made of a different material than the first gate sidewall 6. For example, the second gate sidewall 7 can be made of an ultra-low-k dielectric material, while the first gate sidewall 6 still uses conventional silicon nitride (SiN) or similar materials for mechanical support. This design can significantly reduce the parasitic capacitance between the gate 12 and the source / drain, thereby directly improving the device switching speed and reducing power consumption.

[0037] Based on the above technical solution, preferably, the inner wall 4 and the isolation structure 5 are made of at least some different materials.

[0038] The main function of the isolation structure 5 is electrical isolation. Therefore, an ultra-low k dielectric (such as porous SiCOH, k<2.5) can be selected alone to minimize this parasitic capacitance. The inner wall 4 does not need to be concerned with the k value and can continue to use traditional but reliable high etching selectivity materials (such as SiN, SiBCN, etc.).

[0039] Based on the above technical solution, it is further preferred that the second gate sidewall 7 is integrally formed with the isolation structure 5.

[0040] The second gate sidewall 7 of the present invention is integrated with the isolation structure 5 in the MDI process, which can effectively reduce the AR ratio of the gate 12 etching, thereby reducing the hard mask thickness, reducing the etching difficulty, protecting the gate 12 sidewall, improving device reliability, simplifying process integration, and improving mass production feasibility.

[0041] like Figure 28 As shown, based on the above technical solution, in a cross-section (EE' direction) that passes downward through the first gate sidewall 6 and is perpendicular to the channel, the second gate sidewall 7 and the isolation structure 5 form an H-shaped structure.

[0042] like Figure 28As shown, based on the above technical solution, in a cross-section (EE' direction) that passes downward through the first gate sidewall 6 and is perpendicular to the channel, the inner sidewall 4 connects the second gate sidewall 7 located on both sides of the channel.

[0043] Based on the above technical solution, the inner wall 4 includes a first inner wall and a second inner wall. The first inner wall is the lowest inner wall 4 between the gate stack structure and the source drain of the first transistor 2, and the second inner wall is all the inner walls 4 except for the first inner wall. In the direction perpendicular to the channel, the height of the first inner wall is Y, which is the thickness of the channel sacrificial layer, and the height of the isolation structure 5 is X, which is the thickness of the isolation structure sacrificial layer 15, wherein X / Y is greater than 1.

[0044] Based on the above technical solution, it is further preferred that X / Y is any value between 2 and 5.

[0045] Based on the above technical solution, the inner wall 4 further includes a first inner wall and a second inner wall. The first inner wall is the lowest inner wall 4 between the gate stack structure and the source drain of the first transistor 2, and the second inner wall is all the inner walls 4 except for the first inner wall. In the direction perpendicular to the channel, the height of the first inner wall is Y, which is the thickness of the channel sacrificial layer, and the height of the second inner wall is Z, which is the bottom sacrificial layer of the device, wherein Z / Y is greater than 2.

[0046] Based on the above technical solution, Z / Y is further defined as any value between 2 and 8, and preferably between 2 and 4.

[0047] More preferably, based on the above technical solution, the medium of the isolation structure 5 includes any one of low-k carbon-doped silicon oxyoxide, low-k carbon-doped silicon oxynitride, silicon oxynitride, porous organosilicon glass, and atomic layer deposited oxide.

[0048] Example 2 To address the problem of over-etching damage to the outer spacer 11 caused by high AR gate 12 etching in GAA / CFET manufacturing, this embodiment provides a method for fabricating the aforementioned semiconductor device, specifically including the following steps: First, SiGe / Si stacked superlattice layers are epitaxially grown sequentially on the substrate. Then, the SiGe / Si stacked superlattice layers are stacked into multiple periodically distributed fins, and shallow trench isolation (STI) regions are formed between two adjacent fins. Based on the above technical solution, further, a dummy gate and a dummy gate hard mask layer 14 are sequentially formed on the exposed fin stack 8 surface; Based on the above technical solution, in order to reduce over-etching of the outer wall 11 and lower the gate etching AR ratio, this invention adopts a split sidewall design, that is, the outer wall 11 is divided into a first gate sidewall 6 and a second gate sidewall 7. The second gate sidewall 7 is integrated with the MDI process, reducing the etching difficulty. Specific embodiments include, but are not limited to, the following two fabrication methods: Method 1: Step-by-step etching of dummy gate and sidewall integration First, anisotropic etching of the dummy gate is performed and stopped at the top of the upper fin stack 8. Then, the first sidewall dielectric is deposited on both sides of the dummy gate and anisotropic etching is performed to form the first gate sidewall 6. Using the dummy gate and the first gate sidewall 6 as a mask, the fin stack 8 is etched to form a nanowire stack, and the nanowire stack below the first gate sidewall 6 is etched inward to form a lateral concavity. Remove the isolation structure sacrificial layer 15 and fill it with an isolation dielectric integrated layer to form a second gate sidewall 7 on both sides of the channel and below the first gate sidewall 6.

[0049] This method avoids deep trench etching of the outer wall 11 by etching the dummy gate in stages. The second gate sidewall 7 (the lower half of the outer wall 11) is formed by isotropic etching and is naturally connected to the MDI medium, which reduces the etching difficulty.

[0050] Method 2: One-step etching of dummy gate and sacrificial layer for assistance Anisotropic etching of the dummy gate is performed and stopped at the bottom of the lower fin stack 8; After depositing a first sacrificial layer 9 on both sides of the dummy gate and selectively etching the first sacrificial layer 9 until the top of the upper fin stack 8 is just exposed, a first sidewall dielectric is deposited on both sides of the dummy gate and anisotropically etched to form a first gate sidewall 6. Remove the first sacrificial layer 9 so that the nanowire stack below the first gate sidewall 6 forms a lateral concave shape; Remove the isolation structure sacrificial layer 15 and fill it with an isolation dielectric integrated layer to form a second gate sidewall 7 on both sides of the channel and below the first gate sidewall 6.

[0051] After filling the first sacrificial layer 9 and recessing, the sidewall etching only needs to process the first gate sidewall 6, which effectively reduces the over-etching of the outer sidewall 11. The second gate sidewall 7 (the lower half of the outer sidewall 11) is naturally formed by the MDI process and does not require additional etching.

[0052] The semiconductor device prepared by the present invention using two optimized etching methods for the gate 12 can reduce the amount of over-etching of the outer wall 11 and reduce the AR ratio of the gate 12 etching, thereby reducing the hard mask thickness, reducing the etching difficulty, protecting the sidewall of the gate 12, improving device reliability, simplifying process integration, and improving mass production feasibility.

[0053] Based on the two optimized gate 12 etching methods mentioned above, the channel sacrificial layer is further etched laterally to form a groove 16, and an inner sidewall 4 is formed in the groove 16.

[0054] Based on the above technical solution, source / drain regions 10 are further formed at both ends of the nanowire stack, and then an isolation layer medium is deposited on the source / drain regions 10. The isolation layer medium is then chemically and mechanically polished to planarize it, thereby obtaining the isolation layer.

[0055] Based on the above technical solution, the sacrificial layer of the isotropic etching channel is further used to form trenches and release nanowires.

[0056] Based on the above technical solution, a replacement gate stack is further formed in the trench and CMP is performed to form a metal gate surrounding the nanosheet channel. Then, front-end interconnect, back-end interconnect and back-side interconnect processes are performed to realize the electrical connection between various parts inside the device and between the device and external circuits.

[0057] The following provides a detailed description of two embodiments for the fabrication of the semiconductor device of the present invention: Example 3 In step S1, as Figure 3 As shown, SiGe / Si stacked superlattice layers are first grown sequentially on the substrate via epitaxy. The superlattice structures of the bottom and top layers can be deposited periodically, with the number of periods of the Si layer being ≥1. The low-Ge-concentration SiGe layer serves as the channel sacrificial layer with a thickness of Y, which is the height of the first inner sidewall in the semiconductor device. The high-Ge-concentration SiGe layer serves as the structural isolation sacrificial layer for the upper and lower transistors of the CFET device with a thickness of X, which is the height of the isolation structure 5 in the semiconductor device. The SiGe layer above the silicon substrate serves as the bottom sacrificial layer of the device with a thickness of Z, which is the height of the second inner sidewall in the semiconductor device. Based on the above technical solution, preferably, the X / Y ratio is greater than 1, and more preferably, X / Y is any value between 2 and 5; the Z / Y ratio is greater than 2, and more preferably, any value between 2 and 8. The thickness of the high-Ge-concentration SiGe isolation sacrificial layer is greater than the thickness of the low-Ge-concentration SiGe channel sacrificial layer. The high-Ge-concentration SiGe, as the structural isolation sacrificial layer for the upper and lower transistors, needs a sufficiently large thickness (X) to prevent crosstalk or short circuits between the channel regions (low-Ge-concentration SiGe) of the upper and lower transistors during subsequent processes (such as epitaxy and etching). Furthermore, when selectively etching the low-Ge-concentration SiGe (channel sacrificial layer) to form a nanosheet channel, a thicker structural isolation sacrificial layer (X>Y) can prevent accidental penetration of the isolation sacrificial layer due to over-etching, thus avoiding damage to the lower device structure. The SiGe bottom sacrificial layer thickness is greater than twice the SiGe channel sacrificial layer thickness. The SiGe bottom sacrificial layer is located between the substrate and the bottommost transistor and needs to withstand the mechanical stress of subsequent multilayer stacking (such as epitaxial growth, CMP, etc.). Z>2Y can prevent substrate deformation or defects from extending to the channel region due to stress concentration. In addition, when removing low-Ge concentration SiGe sacrificial layers, the thicker bottom sacrificial SiGe layer can serve as an etch stop layer to avoid the etching process penetrating too deep into the substrate and affecting the electrical performance of the device.

[0058] Based on the above, such as Figure 4 As shown, further, the SiGe / Si superlattice layer is used to form multiple periodically distributed fin stacks 8, and shallow trench isolation regions (STIs) are formed between two adjacent fin stacks 8. Specifically, firstly, a hard mask layer 14 is deposited above the topmost channel layer. After patterning, the epitaxially grown superlattice layer is etched into multiple periodically distributed fins, with the etching stopping at or below the substrate. Then, an insulating dielectric material is deposited and planarized to expose the hard mask layer 14. The hard mask layer 14 is then removed by wet or dry etching. The insulating dielectric material is then selectively etched back to expose the three-dimensional fin stack structure 8. Shallow trench isolation regions are formed between adjacent fin stacks 8. The upper surface of the shallow trench isolation region is generally flush with the interface between the superlattice layer structure in the fin stack 8 and the substrate monocrystalline silicon, or it may be higher or lower than the interface level.

[0059] In step 2, as Figure 5 As shown, a dummy gate stack 13 and a dummy gate hard mask layer 14 are sequentially formed on the exposed fin stack 8 surface. Specifically, an oxide layer and polysilicon (or amorphous silicon) are sequentially deposited above the shallow trench isolation region, and CMP is performed, followed by the deposition of the dummy gate hard mask layer 14.

[0060] The material of the dummy gate hard mask layer 14 can be oxide, carbide, organic material, etc.

[0061] In step S3, as Figure 6 As shown, anisotropic etching of amorphous or polycrystalline dummy gates is performed and stopped at the top of the fin stack 8. After etching, the dummy gate hard mask layer 14 above the dummy gate structure is retained.

[0062] In step S4, as Figure 7-8 As shown, the dielectric of the first gate sidewall 6 is deposited on both sides of the dummy gate structure, and then the dielectric of the first gate sidewall 6 in the horizontal direction is etched, leaving only the dielectric of the dummy gate and the hard mask layer 14 sidewall to form the first gate sidewall 6.

[0063] In step S5, as Figure 9-11 As shown, anisotropic etching of the amorphous or polycrystalline dummy gate is used to the bottom (the oxide layer above the shallow trench isolation region). Further, as... Figure 12-13 As shown, isotropic etching is used to perform lateral recess on polycrystalline or amorphous dummy gates, forming a lateral concavity. The dielectric material of the first gate sidewall 6 can be silicon nitride, nitrogen-doped silicon oxide, nitrogen-doped silicon carbide, etc. During etching, the integrity of the channel layer can be guaranteed because the sacrificial layer and the channel layer have a large etching selectivity.

[0064] In step S6, the interface oxide layer (i.e., the oxide layer above the shallow trench isolation area) on the surface of the source / drain fin stack 8 is removed, for example, by cleaning with diluted HF to ensure the cleanliness of the surface of the source / drain fin stack 8.

[0065] Based on the above, further, such as Figure 21 As shown, a protective hard mask (such as SiN) is covered on the isolation dielectric integrated layer, exposing only the source / drain fin stack 8 region that needs to be etched. The source / drain fin stack 8 is then removed using anisotropic etching. Specifically, a high-selectivity reactive ion etching process can be used, and vertical etching is ensured by adjusting the bias voltage. After etching, residual polymer is removed using low-temperature O2 plasma cleaning, metal contamination is removed using dilute sulfuric acid / hydrogen peroxide cleaning, and lattice damage is repaired by rapid thermal annealing.

[0066] In step S7, as Figure 22 As shown, the isolation structure sacrificial layer 15 (high Ge concentration SiGe sacrificial layer) is removed, and the isolation dielectric integration layer is filled and isotropically etched (e.g., ...) is performed. Figure 23-25 Specifically, selective etching can be used to remove the sacrificial layer 15 of the isolation structure, retaining the surrounding dielectric layer. Then, SiO2 or a low-k material (such as SiOC) is deposited to fill the cavity, and polished to expose the hard mask of the gate 12, forming a flat plane to achieve isolation between the gate 12 and the source / drain region 10, providing a planarization basis for subsequent metal interconnects.

[0067] In step S8, as Figure 26 As shown, isotropic etching is performed to precisely etch the inner wall 4 cavity of low-Ge-concentration SiGe, i.e., selectively etching low-Ge-concentration SiGe to protect high-Ge-concentration SiGe and the surrounding dielectric layer, achieving isotropic etching and forming controllable lateral grooves 16. Specifically, this can be achieved using wet etching or pure gaseous isotropic etching processes. Then, following conventional methods, such as... Figure 27-28 As shown, the inner sidewall 4 medium is deposited and etched to form the inner sidewall 4, exposing the channel material.

[0068] In step S9, firstly, the source / drain region 10 is epitaxially grown using methods such as metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, or combinations thereof. The source / drain region 10 can also be doped simultaneously. For example, for a P-type FET, the material of the source / drain region 10 is boron-doped SiGe (SiGe:B), and for an N-type FET, the material of the source / drain region 10 is phosphorus-doped silicon (Si:P). After forming the source / drain region 10, an isolation layer dielectric is deposited on the source / drain region 10, and the isolation layer dielectric is chemically mechanically polished to planarize it, thus obtaining the isolation layer.

[0069] Based on the above, the fake gate hard mask layer 14 is further removed to expose the fake gate layer.

[0070] Based on the above, dummy gates are further removed.

[0071] In step S10, the gate dielectric layer on the surface of the source / drain fin stack 8 is removed to provide a clean interface for the subsequent formation of the metal gate, ensuring good electrical contact and interface characteristics between the metal gate and the fin stack 8, reducing the leakage current of the gate 12, and improving the reliability and performance of the device. Furthermore, the sacrificial layer in the superlattice stack is selectively etched to release the SiGe nanowire channel, providing space for the subsequent filling of the metal gate. When the device is in operation, this channel structure helps to improve the electrical performance of the device, such as increasing carrier mobility.

[0072] Specifically, plasma etching technology can be used (by adjusting the gas ratio according to the characteristics of the gate dielectric material) to etch the gate dielectric layer on the surface of the fin stack 8 under precisely controlled process conditions. By adjusting parameters such as plasma energy, density, and etching time, selective removal of the gate dielectric layer can be achieved while minimizing damage to the silicon material of the fin stack 8 and the surrounding structure. After dry etching, some etching products and impurities may remain on the surface of the fin stack 8. These can be further removed by wet cleaning with a chemical cleaning solution (such as diluted hydrofluoric acid solution) to remove surface residues and achieve a highly clean surface, preparing it for subsequent processes.

[0073] In step S11, a high-k metal gate is deposited and CMP is performed to form a metal gate surrounding the nanowire channel.

[0074] Based on the above, further front-end interconnect, back-end interconnect and rear-side interconnect processes are carried out to realize the electrical connection between various parts inside the device and between the device and external circuits, transmit the electrical signals of the device to the required places, and build a complete integrated circuit system. This part of the process can refer to the existing technology and will not be described in detail here.

[0075] Example 4 In step T1, as Figure 3 As shown, SiGe / Si stacked superlattice layers are first grown sequentially on the substrate via epitaxy. The superlattice structures of the bottom and top layers can be deposited periodically, with the number of periods of the Si layer being ≥1. The low-Ge-concentration SiGe layer serves as the channel sacrificial layer with a thickness of Y, which is the height of the first inner sidewall in the semiconductor device. The high-Ge-concentration SiGe layer serves as the structural isolation sacrificial layer for the upper and lower transistors of the CFET device with a thickness of X, which is the height of the isolation structure 5 in the semiconductor device. The SiGe layer above the silicon substrate serves as the bottom sacrificial layer of the device with a thickness of Z, which is the height of the second inner sidewall in the semiconductor device. Based on the above technical solution, preferably, the X / Y ratio is greater than 1, and more preferably, X / Y is any value between 2 and 5; the Z / Y ratio is greater than 2, and more preferably, any value between 2 and 8. The thickness of the high-Ge-concentration SiGe isolation sacrificial layer is greater than the thickness of the low-Ge-concentration SiGe channel sacrificial layer. The high-Ge-concentration SiGe, as the structural isolation sacrificial layer for the upper and lower transistors, needs a sufficiently large thickness (X) to prevent crosstalk or short circuits between the channel regions (low-Ge-concentration SiGe) of the upper and lower transistors during subsequent processes (such as epitaxy and etching). Furthermore, when selectively etching the low-Ge-concentration SiGe (channel sacrificial layer) to form a nanosheet channel, a thicker structural isolation sacrificial layer (X>Y) can prevent accidental penetration of the isolation sacrificial layer due to over-etching, thus avoiding damage to the lower device structure. The SiGe bottom sacrificial layer thickness is greater than twice the SiGe channel sacrificial layer thickness. The SiGe bottom sacrificial layer is located between the substrate and the bottommost transistor and needs to withstand the mechanical stress of subsequent multilayer stacking (such as epitaxial growth, CMP, etc.). Z>2Y can prevent substrate deformation or defects from extending to the channel region due to stress concentration. In addition, when removing low-Ge concentration SiGe sacrificial layers, the thicker bottom sacrificial SiGe layer can serve as an etch stop layer to avoid the etching process penetrating too deep into the substrate and affecting the electrical performance of the device.

[0076] Based on the above, such as Figure 4As shown, further, the SiGe / Si superlattice layer is used to form multiple periodically distributed fin stacks 8, and shallow trench isolation (STI) regions are formed between two adjacent fin stacks 8. Specifically, firstly, a hard mask layer 14 is deposited above the topmost channel layer. After patterning, the epitaxially grown superlattice layer is etched into multiple periodically distributed fins, with the etching stopping at or below the substrate. Then, an insulating dielectric material is deposited and planarized to expose the hard mask layer 14. The hard mask layer 14 is then removed by wet or dry etching. The insulating dielectric material is then selectively etched back to expose the three-dimensional fin stack structure 8. Shallow trench isolation regions are formed between adjacent fin stacks 8. The upper surface of the shallow trench isolation region is generally flush with the interface between the superlattice layer structure in the fin stack 8 and the substrate monocrystalline silicon, or it may be higher or lower than the interface level.

[0077] In step 2, as Figure 5 As shown, a dummy gate stack 13 and a dummy gate hard mask layer 14 are sequentially formed on the exposed fin stack 8 surface. Specifically, an oxide layer and polysilicon (or amorphous silicon) are sequentially deposited above the shallow trench isolation region, and CMP is performed, followed by the deposition of the dummy gate hard mask layer 14.

[0078] The material of the dummy gate hard mask layer 14 can be oxide, carbide, organic material, etc.

[0079] In step T3, as Figure 14-15 As shown, the dummy gate is directly anisotropically etched in one step and stopped at the bottom of the lower fin stack 8. Specifically, before etching, the etching equipment needs to be calibrated and the process parameters optimized to determine the optimal etching gas flow rate, power, pressure and other parameters. During the etching process, the etching rate and etching depth are monitored in real time. The changes in the gas composition generated during the etching process can be monitored by techniques such as optical emission spectroscopy (OES) to determine the etching progress. After the etching is completed, SEM is used to check whether the dummy gate has been completely removed and whether the fin surface is damaged.

[0080] In step T4, as Figure 16-17 As shown, a first sacrificial layer 9 is deposited and selectively etched to the point where the top of the fin stack 8 is just exposed. Specifically, during the deposition of the first sacrificial layer 9, it is important to control the deposition rate and film quality to avoid film defects. Before performing the selective etching recess process, the etching equipment must be calibrated to ensure etching accuracy. After recess, the remaining height of the first sacrificial layer 9 is measured using an atomic force microscope (AFM) or SEM to ensure it meets design requirements.

[0081] The medium of the first sacrificial layer 9 includes any one of amorphous silicon, amorphous carbon, phosphosilicate glass and organic spin-coating materials, and is preferably amorphous silicon. Amorphous silicon can accurately achieve the Recess height, has strong process controllability, and has strong interface compatibility with media such as SiN / SiO2 / MDI.

[0082] In step T5, as Figure 18-20 As shown, a first gate sidewall dielectric is deposited and anisotropic outer sidewall 11 is etched, then the first sacrificial layer 9 is removed. Specifically, the first gate sidewall dielectric material is usually selected from materials with good insulation properties and etching selectivity, such as silicon nitride or silicon oxide. The first gate sidewall dielectric can be deposited using CVD or ALD methods, and the horizontal first gate sidewall dielectric can be etched away using plasma etching technology, leaving the vertical sidewall to form the first gate sidewall 6, which isolates the gate 12 from the source / drain region 10 to prevent leakage. After etching, the first sacrificial layer 9 is removed using wet etching or dry etching to form a laterally concave (e.g., Figure 12-13 When wet etching, an etching solution with high selectivity for the first sacrificial layer 9 material should be selected to avoid damage to other materials.

[0083] In other embodiments of the present invention, when removing the first sacrificial layer 9, the first sacrificial layer 9 located below the first gate sidewall 6 can be completely removed, or a small portion can be retained below the first gate sidewall 6, such that the bottom of the first gate sidewall 6 in the final device is slightly lower than the top surface of the topmost nanowire of the second transistor 3. When etching away the first sacrificial layer 9, a portion of the first gate sidewall 6 can also be removed, resulting in the bottom of the first gate sidewall 6 being higher than the top surface of the topmost nanowire of the second transistor 3.

[0084] In step T6, the interface oxide layer (i.e., the oxide layer above the shallow trench isolation area) on the surface of the source / drain fin stack 8 is removed, for example, by cleaning with diluted HF to ensure the cleanliness of the surface of the source / drain fin stack 8.

[0085] Based on the above, further, such as Figure 21 As shown, a protective hard mask (such as SiN) is covered on the isolation dielectric integrated layer, exposing only the source / drain fin stack 8 region that needs to be etched. The source / drain fin stack 8 is then removed using anisotropic etching. Specifically, a high-selectivity reactive ion etching process can be used, and vertical etching is ensured by adjusting the bias voltage. After etching, residual polymer is removed using low-temperature O2 plasma cleaning, metal contamination is removed using dilute sulfuric acid / hydrogen peroxide cleaning, and lattice damage is repaired by rapid thermal annealing.

[0086] In step T7, as Figure 22As shown, the isolation structure sacrificial layer 15 (high Ge concentration SiGe sacrificial layer) is removed, and the isolation dielectric integration layer is filled and isotropically etched (e.g., ...) is performed. Figure 23-25 Specifically, selective etching can be used to remove the sacrificial layer 15 of the isolation structure, retaining the surrounding dielectric layer. Then, SiO2 or a low-k material (such as SiOC) is deposited to fill the cavity, and polished to expose the hard mask of the gate 12, forming a flat plane to achieve isolation between the gate 12 and the source / drain region 10, providing a planarization basis for subsequent metal interconnects.

[0087] In step T8, as Figure 26 As shown, isotropic etching is performed to precisely etch the inner wall 4 cavity of low-Ge-concentration SiGe, i.e., selectively etching low-Ge-concentration SiGe to protect high-Ge-concentration SiGe and the surrounding dielectric layer, achieving isotropic etching and forming controllable lateral grooves 16. Specifically, this can be achieved using wet etching or pure gaseous isotropic etching processes. Then, following conventional methods, such as... Figure 27-28 As shown, the inner sidewall 4 medium is deposited and etched to form the inner sidewall 4, exposing the channel material.

[0088] In step T9, firstly, the source / drain regions 10 are epitaxially grown using methods such as metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, or combinations thereof. The source / drain regions 10 can also be doped simultaneously. For example, for a P-type FET, the material of the source / drain regions 10 is boron-doped SiGe (SiGe:B), and for an N-type FET, the material of the source / drain regions 10 is phosphorus-doped silicon (Si:P). After forming the source / drain regions 10, an isolation layer dielectric is deposited on the source / drain regions 10, and the isolation layer dielectric is chemically mechanically polished to planarize it, thus obtaining the isolation layer.

[0089] Based on the above, the fake gate hard mask layer 14 is further removed to expose the fake gate layer.

[0090] Based on the above, dummy gates are further removed.

[0091] In step T10, the gate dielectric layer on the surface of the source / drain fin stack 8 is removed to provide a clean interface for the subsequent formation of the metal gate, ensuring good electrical contact and interface characteristics between the metal gate and the fin stack 8, reducing the leakage current of the gate 12, and improving the reliability and performance of the device. Furthermore, the sacrificial layer in the superlattice stack is selectively etched to release the SiGe nanowire channel, providing space for the subsequent filling of the metal gate. When the device is in operation, this channel structure helps to improve the electrical performance of the device, such as increasing carrier mobility.

[0092] Specifically, plasma etching technology can be used (by adjusting the gas ratio according to the characteristics of the gate dielectric material) to etch the gate dielectric layer on the surface of the fin stack 8 under precisely controlled process conditions. By adjusting parameters such as plasma energy, density, and etching time, selective removal of the gate dielectric layer can be achieved while minimizing damage to the silicon material of the fin stack 8 and the surrounding structure. After dry etching, some etching products and impurities may remain on the surface of the fin stack 8. These can be further removed by wet cleaning with a chemical cleaning solution (such as diluted hydrofluoric acid solution) to remove surface residues and achieve a highly clean surface, preparing it for subsequent processes.

[0093] In step T11, a high-k metal gate is deposited and CMP is performed to form a metal gate surrounding the nanowire channel.

[0094] Based on the above, further front-end interconnect, back-end interconnect and rear-side interconnect processes are carried out to realize the electrical connection between various parts inside the device and between the device and external circuits, transmit the electrical signals of the device to the required places, and build a complete integrated circuit system. This part of the process can refer to the existing technology and will not be described in detail here.

[0095] The above description does not provide detailed explanations of the technical aspects of each layer's patterning and etching. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to create the same structure, those skilled in the art can design methods that are not entirely identical to those described above.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, Including semiconductor substrates; A first transistor and a second transistor are sequentially disposed above the semiconductor substrate along the thickness direction of the semiconductor substrate. The first transistor and / or the second transistor are gate-around transistors, and the gate-around transistor includes an inner wall located between the gate stack structure and the source and drain. An isolation structure is disposed between the gate stack structure of the first transistor and the gate stack structure of the second transistor; The first gate sidewall is disposed on both sides of the upper part of the gate stack structure of the second transistor and extends to both sides of the channel of the second transistor; The second gate sidewall is disposed on both sides of the gate stack structure of the first transistor and the second transistor along the width direction of the channel; The second gate sidewall is located below the first gate sidewall.

2. The semiconductor device according to claim 1, characterized in that, The inner wall and the isolation structure are made of at least some different materials.

3. The semiconductor device according to claim 1, characterized in that, The second gate sidewall is integrally formed with the isolation structure.

4. The semiconductor device according to claim 1, characterized in that, In a cross-section that extends downward through the first gate sidewall and is perpendicular to the channel, the second gate sidewall and the isolation structure form an H-shaped structure.

5. The semiconductor device according to claim 1, characterized in that, In a cross-section that passes downward through the first gate sidewall and is perpendicular to the channel, the inner sidewall connects the second gate sidewall located on both sides of the channel.

6. The semiconductor device according to claim 1, characterized in that, The medium of the isolation structure includes any one of low-k carbon-doped silicon oxyoxide, low-k carbon-doped silicon oxynitride, silicon oxynitride, porous organosilicon glass, and atomic layer deposited oxide.

7. The semiconductor device according to claim 1, characterized in that, The first gate sidewall also extends below the top surface of the topmost channel region of the second transistor.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, The inner wall includes a first inner wall and a second inner wall. The first inner wall is the lowest inner wall between the gate stack structure and the source drain of the first transistor. The second inner wall is all the inner walls except the first inner wall. In the direction perpendicular to the channel, the height of the first inner wall is Y, and the height of the isolation structure is X, where X / Y is greater than 1.

9. The semiconductor device according to any one of claims 1 to 7, characterized in that, The inner wall includes a first inner wall and a second inner wall. The first inner wall is the lowest inner wall between the gate stack structure and the source drain of the first transistor. The second inner wall is all the inner walls except the first inner wall. In the direction perpendicular to the channel, the height of the first inner wall is Y, and the height of the second inner wall is Z, where Z / Y is greater than 2.

10. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A fin stack is formed on a semiconductor substrate by sequentially stacking a channel sacrificial layer and a channel layer. The fin stack includes an upper fin stack and a lower fin stack, which are isolated from each other by an isolation structure sacrificial layer. A false grid is formed on the exposed fin stack surface; A first sidewall dielectric is deposited on both sides of the dummy gate and anisotropically etched to form the first gate sidewall; Using the dummy gate and the first gate sidewall as a mask, the fin stack is etched to form a nanowire stack; The isolation structure sacrificial layer is removed and the isolation dielectric integrated layer is filled to form an isolation structure, and a second gate sidewall is formed on both sides of the channel and below the first gate sidewall. Laterally etch the sacrificial layer of the channel to form a groove, and form an inner sidewall in the groove; Source and drain regions are formed at both ends of the nanowire stack; Isotropic etching of the sacrificial layer forms trenches, releasing nanowires; An alternative gate stack is formed in the trench.

11. The preparation method according to claim 10, characterized in that, The formation of the first gate sidewall includes the following steps: Anisotropic etching of the dummy gate stops at the top of the upper fin stack; First sidewall dielectric is deposited on both sides of the dummy gate and anisotropically etched to form the first gate sidewall.

12. The preparation method according to claim 11, characterized in that, The formation of the second gate sidewall includes the following steps: Using the dummy gate and the first gate sidewall as a mask, the fin stack is etched to form a nanowire stack, and the nanowire stack below the first gate sidewall is etched inward to form a lateral concavity. Remove the isolation structure sacrificial layer and fill it with an isolation dielectric integrated layer to form a second gate sidewall on both sides of the channel and below the first gate sidewall.

13. The preparation method according to claim 10, characterized in that, The formation of the first gate sidewall includes the following steps: Anisotropic etching of the dummy gate is performed and stopped at the bottom of the lower fin stack; After depositing a first sacrificial layer on both sides of the dummy gate and selectively etching the first sacrificial layer until the top of the upper fin stack is just exposed, a first sidewall dielectric is deposited on both sides of the dummy gate and anisotropically etched to form the first gate sidewall.

14. The preparation method according to claim 13, characterized in that, The formation of the second gate sidewall includes the following steps: Remove the first sacrificial layer to form a lateral concave stack of nanowires below the first gate sidewall; Remove the isolation structure sacrificial layer and fill it with an isolation dielectric integrated layer to form a second gate sidewall on both sides of the channel and below the first gate sidewall.

15. An electronic device, characterized in that, Includes the semiconductor device according to any one of claims 1-9; The electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

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