Semiconductor structure and manufacturing method thereof, memory and memory system

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, a memory and a memory system. The semiconductor structure comprises a first stack structure comprising first dielectric layers and first conductive layers which are alternately arranged; a first conductive pillar extending along a stacking direction in the first stacking structure; the storage layers and the isolation layers are alternately arranged and located between the first conductive columns and the first stacking structures; wherein the first conductive layer and the first conductive column are both in contact with the storage layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and more particularly, to a semiconductor structure, a memory, a memory system, and a manufacturing method of the semiconductor structure. BACKGROUND

[0002] With the development of big data, AI technology, and high-performance chips, the demand for computing power is increasing, and the development of high-density data storage technology is growing rapidly. High-density data storage technology refers to a technology that can store more data in smaller storage media, and plays an important role in the field of data storage technology. SUMMARY

[0003] The present application provides a semiconductor structure, a memory, a memory system, and a manufacturing method of the semiconductor structure.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor structure. The semiconductor structure includes: a first stack structure including first dielectric layers and first conductive layers arranged alternately; a first conductive pillar extending in a stacking direction in the first stack structure; and storage layers and isolation layers arranged alternately between the first conductive pillar and the first stack structure; wherein the first conductive layers and the first conductive pillar are both in contact with the storage layers.

[0005] In an example embodiment, the material of the isolation layers includes an insulating material.

[0006] In an example embodiment, the insulating material includes a high dielectric constant material.

[0007] In an example embodiment, the number of storage layers is a plurality.

[0008] In an example embodiment, the material of the storage layers includes a ferroelectric material or an anti-ferroelectric material.

[0009] In an example embodiment, the storage layers and the isolation layers are arranged alternately in a direction away from the outer wall of the first conductive pillar.

[0010] In an example embodiment, the semiconductor structure further includes: a second conductive layer located at one side of the first stack structure; a first channel layer penetrating through the second conductive layer and connected with the first conductive pillar; and a first gate dielectric layer penetrating through the second conductive layer and surrounding the sidewall of the first channel layer.

[0011] In an example embodiment, the isolation layers and the storage layers arranged alternately are located in the first stack structure and surround the end of the first conductive pillar away from the second conductive layer.

[0012] In an example embodiment, the semiconductor structure further comprises: a third dielectric layer on a side of the first stack structure away from the second conductive layer, wherein an end of the first conductive pillar extending out of the first stack structure extends into the third dielectric layer; a third conductive layer on a side of the third dielectric layer away from the first stack structure; a second conductive pillar penetrating through the third conductive layer and the third dielectric layer and connected with the first conductive pillar; a second gate dielectric layer penetrating through the third conductive layer and the third dielectric layer and surrounding a sidewall of the second conductive pillar; and a second channel layer penetrating through the third conductive layer and surrounding a sidewall of the second gate dielectric layer.

[0013] In an example embodiment, the semiconductor structure further comprises: a fourth dielectric layer on a side of the third conductive layer away from the third dielectric layer, wherein the second channel layer further penetrates through the fourth dielectric layer; an isolation structure inside the second channel layer and at an end of the second conductive pillar away from the first conductive pillar; and a channel plug inside the second channel layer and at an end of the isolation structure away from the second conductive pillar.

[0014] In a second aspect, some embodiments of the present application provide a memory. The memory comprises: the semiconductor structure as mentioned in any of the embodiments above; and a peripheral circuit coupled with the semiconductor structure.

[0015] In a third aspect, some embodiments of the present application provide a memory system. The memory system comprises: the memory as mentioned in any of the embodiments above; and a controller coupled with the memory and configured to control the memory to store data.

[0016] In a fourth aspect, some embodiments of the present application provide a method for manufacturing a semiconductor structure. The method comprises: forming a first hole extending along a stacking direction in a first stack structure, wherein the first stack structure comprises first dielectric layers and first conductive layers arranged alternately; forming storage layers and isolation layers alternately on an inner wall of the first hole; and forming a first conductive pillar inside the storage layers.

[0017] In an example embodiment, the method further comprises: forming a second conductive layer on a side of the first stack structure; forming a first channel hole penetrating through the second conductive layer to the first conductive pillar; and forming a first gate dielectric layer on a sidewall of the first channel hole and forming a first channel layer inside the first gate dielectric layer.

[0018] In an example embodiment, the manufacturing method further includes: removing the isolation layer and a portion of the storage layer from a side of the first stack structure facing away from the second conductive layer to expose the first conductive pillar; forming a third dielectric layer covering the first conductive pillar on the side of the first stack structure facing away from the second conductive layer; forming a third conductive layer on a side of the third dielectric layer facing away from the first stack structure; forming an initial second channel hole through the third conductive layer to the third dielectric layer and forming a second channel layer on an inner wall of the initial second channel hole; deepening the initial second channel hole to the first conductive pillar to form a second channel hole; and forming a second gate dielectric layer on a sidewall of the second channel hole and forming a second conductive pillar on an inner side of the second gate dielectric layer.

[0019] In an example embodiment, the material of the isolation layer includes an insulating material.

[0020] In an example embodiment, the insulating material includes a high dielectric constant material.

[0021] In an example embodiment, the number of the storage layers is multiple.

[0022] In an example embodiment, the material of the storage layer includes a ferroelectric material or an anti-ferroelectric material. BRIEF DESCRIPTION OF DRAWINGS

[0023] Other features, objects, and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments thereof as taken in conjunction with the accompanying drawings. In the drawings:

[0024] FIG. 1A is a schematic cross-sectional view of a semiconductor structure provided by an embodiment of the application;

[0025] FIG. 1B is a circuit schematic of a memory cell in the semiconductor structure provided by an embodiment of the application;

[0026] FIG. 2A is a schematic cross-sectional view of a semiconductor structure provided by another embodiment of the application;

[0027] FIG. 2B is a circuit schematic of a memory cell in the semiconductor structure provided by another embodiment of the application;

[0028] FIG. 3 is a flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of the application;

[0029] FIG. 4A to FIG. 4I is a schematic cross-sectional view of a semiconductor structure in a manufacturing process provided by an embodiment of the application;

[0030] FIG. 5 is a schematic block diagram of a memory provided by an embodiment of the application; and

[0031] FIG. 6 is a schematic block diagram of a system having a memory system provided by an embodiment of the present application. DETAILED DESCRIPTION

[0032] For a better understanding of the present application, various aspects of the present application will be described in greater detail below with reference to the accompanying drawings. It is to be noted that these detailed descriptions are merely descriptive of exemplary embodiments of the present application and are not intended in any way to limit the scope of the present application. Throughout the specification, like drawing reference numerals refer to like elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0033] It should be noted that the expressions first, second, third and the like in this description merely serve to distinguish one feature from another feature, without implying any order or sequence of the features. Thus, the first conductive layer discussed in the present application can also be referred to as the second conductive layer, and vice versa, without departing from the teachings of the present application.

[0034] In the drawings, the thicknesses of components, sizes, and shapes can have been slightly adjusted for the sake of convenience in explanation. The drawings are merely examples for illustration and are not strictly drawn to scale. As used in this document, the terms "substantially", "approximately", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in a measuring or calculating process that are recognized by those of ordinary skill in the art.

[0035] It should also be understood that expressions such as "include", "including", "have", "has", "contain" and / or "containing" and the like, are open-ended expressions that are used to specify the presence of stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or combinations of them. Furthermore, when such expressions as "at least one of", "one or more of", and / or the like are followed by a list of elements, the expression is intended to cover all of the individual elements in the list, as well as any combination of two or more of the elements. In addition, when describing embodiments of the present application, the use of "can" means "one or more embodiments of the present application". Also, the use of the term "exemplary" is intended to present examples or illustrations.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an overly formal or overly literal sense unless expressly so defined herein.

[0037] It should be noted that the embodiments and features of the present application can be combined with each other, as long as there is no conflict. In addition, the specific steps in the methods described in the present application are not necessarily limited to the order described, but can be performed in any order or in parallel, unless otherwise explicitly limited or derived from the context.

[0038] In addition, when "connected" or "coupled" is used in the present application, it can mean direct contact or indirect contact between the corresponding components, unless there is an explicit definition or it can be derived from the context.

[0039] The present application will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0040] Some embodiments of the present application provide a semiconductor structure. FIG. 1A is a schematic diagram of a cross section of a semiconductor structure provided by embodiments of the present application. FIG. 1B is a schematic diagram of a circuit of a memory cell in a semiconductor structure provided by embodiments of the present application.

[0041] It should be noted that in the following, the x direction, the y direction and the z direction in the various drawings show the spatial relationship of the components in the semiconductor structure. For example, the z direction is the stacking direction of the first stack structure, and the x direction and the y direction are two directions intersecting (e.g., perpendicular to) each other in a plane intersecting (e.g., perpendicular to) the stacking direction. The same concept will be used throughout the present application to describe the spatial relationship of the components in the semiconductor structure.

[0042] As shown in FIG. 1A , the semiconductor structure 100 includes a first stack structure 111, a first conductive pillar 112, a memory layer 113 and an isolation layer 114. The first stack structure 111 includes first dielectric layers 1111 and first conductive layers 1112 arranged alternately. The first conductive pillar 112 extends in the z direction in the first stack structure 111. The memory layer 113 and the isolation layer 114 are arranged alternately and are located between the first conductive pillar 112 and the first stack structure 111. The first conductive layer 1112 is in contact with the memory layer 113, and the first conductive pillar 112 is in contact with the memory layer 113.

[0043] According to the semiconductor structure 100 provided in the above embodiments, one of the first conductive layers 1112 can serve as a first electrode of a storage capacitor C, the first conductive pillars 112 can serve as second electrodes of the storage capacitor C, the storage layers 113 and the isolation layers 114 arranged alternately are located between the first conductive layer 1112 and the first conductive pillars 112, and both the first conductive layer 1112 and the first conductive pillars 112 are in contact with the storage layers 113. Based on the characteristic that the electric field intensity of the radiation-type electric field has a gradient characteristic in the direction perpendicular to the z direction (for example, the radial direction of the first conductive pillars 112), the storage layers 113 at different positions can store different bit information, thereby being capable of providing a storage capacitor C for storing multiple bits with a simple structure. In addition, multiple storage capacitors C are arranged in the z direction, which can expand the storage bit information capacity of a single memory cell MC (see FIG. 1B ) and is beneficial to improving the storage density and enhancing the capacity of large-capacity information storage.

[0044] In some embodiments, the first dielectric layers 1111 and the first conductive layers 1112 both extend along the x direction and the y direction. For example, the outermost layers of the first stack structure 111 in the z direction are both the first dielectric layers 1111. Each of the first dielectric layers 1111 can have the same or different thicknesses from each other, and each of the first conductive layers 1112 can also have the same or different thicknesses from each other, which are not specifically limited in the present application. The material of the first dielectric layers 1111 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other appropriate insulating material. For example, the material of the first dielectric layers 1111 can be silicon oxide (SiO2). The material of the first conductive layers 1112 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO) or any other appropriate conductive material. For example, the material of the first conductive layers 1112 can be polysilicon (Poly-Si).

[0045] It should be noted that, although FIG. 1A four first conductive layers 1112 are shown in the first stack structure 111, in other alternative embodiments, the first stack structure 111 can also include two, three or more first conductive layers 1112, which are not specifically limited in the present application.

[0046] In some embodiments, the first conductive pillar 112 can be substantially a columnar structure, for example, the columnar structure can have an inclined angle. The material of the first conductive pillar 112 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. For example, the material of the first conductive pillar 112 is tungsten (W). In other embodiments, the first conductive pillar 112 can be substantially a cylindrical structure (not shown), for example, the cylindrical structure can have an inclined angle. In this case, the semiconductor structure 100 can further include an insulating pillar (not shown) inside the cylindrical first conductive pillar 112.

[0047] In some embodiments, the storage layers 113 and the isolation layers 114 are alternately arranged along a direction away from the outer wall of the first conductive pillar 112. For example, the storage layers 113 are arranged outside the first conductive pillar 112, and the isolation layers 114 are arranged between adjacent storage layers 113. Each of the storage layers 113 can have the same or different thicknesses from each other, and each of the isolation layers 114 can also have the same or different thicknesses from each other, which are not specifically limited in the present application.

[0048] It should be noted that, although FIG. 1A It is shown that the number of the storage layers 113 is three, and the number of the isolation layers 114 is two, in other alternative embodiments, the number of the storage layers 113 can be more (for example, greater than three), and the number of the isolation layers 114 can also be more (for example, greater than two), which are not specifically limited in the present application.

[0049] In some embodiments, the material of the storage layer 113 can include a ferroelectric material. The ferroelectric material can include one or more of zirconium oxide (Zr02), hafnium oxide (Hf02), aluminum (Al)-doped Hf02, silicon (Si)-doped Hf02, zirconium (Zr)-doped Hf02, lanthanum (La)-doped Hf02, yttrium (Y)-doped Hf02, and other element-doped ferroelectric materials. When an electric field is applied to the ferroelectric material layer, the central atoms stay in a low-energy state along the direction of the electric field, and when the electric field is reversed, the central atoms move in the crystal along the direction of the electric field and stay in another low-energy state. The movement of a large number of central atoms in the crystal unit cell is coupled to form ferroelectric domains, and the ferroelectric domains form a polarization charge under the action of the electric field. The polarization charge formed by the ferroelectric domains under the electric field is higher, and the polarization charge formed by the ferroelectric domains without reversal under the electric field is lower. The binary stable state of such ferroelectric material makes it possible to store logical information as the storage layer 113. In other embodiments, the material of the storage layer 113 can include an anti-ferroelectric material. The anti-ferroelectric material can include lead zirconate (PbZr03), lead hafnate (PbHf03), sodium niobate (NaNb03), ammonium dihydrogen phosphate (NH4H2P04), ammonium iodate (NH4IO3), tungsten trioxide (W03), etc. The anti-ferroelectric material has better stability, and its application to the memory can bring better data retention characteristics. For example, in the case where the material of the storage layer 113 is a ferroelectric material or an anti-ferroelectric material, the semiconductor structure 100 can be part of a ferroelectric random access memory (FRAM).

[0050] In some embodiments, the material of the isolation layer 114 can include an insulating material. For example, the insulating material can include one or more of silicon oxide (Si02), silicon nitride (Si3N4), silicon oxynitride (SiOxNy), or any other suitable insulating material. For another example, the insulating material can also include a high dielectric constant material such as aluminum oxide (AI2O3), titanium oxide (Ti02), tantalum oxide (Ta203), hafnium oxide (Hf02), etc. In the case where the isolation layer 114 is prepared using a high dielectric constant material, it is beneficial to improve the isolation effect of the isolation layer 114 between adjacent storage layers 113, reduce the risk of charge leakage between adjacent storage layers 113, and improve the accuracy of stored information. x N y ) or other any suitable insulating material. For another example, the insulating material can also include a high dielectric constant material such as aluminum oxide (AI2O3), titanium oxide (Ti02), tantalum oxide (Ta203), hafnium oxide (Hf02), etc. In the case where the isolation layer 114 is prepared using a high dielectric constant material, it is beneficial to improve the isolation effect of the isolation layer 114 between adjacent storage layers 113, reduce the risk of charge leakage between adjacent storage layers 113, and improve the accuracy of stored information.

[0051] In some embodiments, the semiconductor structure 100 can further include a second conductive layer 115, a first channel layer 117, and a first gate dielectric layer 118. The second conductive layer 115 can be located on one side of the first stack structure 111. The first channel layer 117 can extend through the second conductive layer 115 and be connected (e.g., in contact) with the first conductive pillar 112. The first gate dielectric layer 118 can extend through the second conductive layer 115 and surround the sidewall of the first channel layer 117.

[0052] In some embodiments, the second conductive layer 115 can extend along the x- and y-directions. The material of the second conductive layer 115 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. For example, the material of the second conductive layer 115 can be polysilicon (Poly-Si).

[0053] In some embodiments, the semiconductor structure 100 can further include a second dielectric layer 116. The second dielectric layer 116 can be located on opposite sides of the second conductive layer 115 in the z-direction. The second dielectric layer 116 can also extend along the x- and y-directions. For example, one second dielectric layer 116 can be located between and in contact with the first stack structure 111 and the second conductive layer 115. Another second dielectric layer 116 can be located on the surface of the second conductive layer 115 facing away from the first stack structure 111. The material of the second dielectric layer 116 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or any other suitable insulating material. For example, the material of the second dielectric layer 116 can be silicon oxide (SiO2). It should be noted that in the case where the material of the second dielectric layer 116 is the same as the material of the first dielectric layer 1111, there is no distinct interface between the two and they can be a unitary structure. x N y ) or any other suitable insulating material. For example, the material of the second dielectric layer 116 can be silicon oxide (SiO2). It should be noted that in the case where the material of the second dielectric layer 116 is the same as the material of the first dielectric layer 1111, there is no distinct interface between the two and they can be a unitary structure.

[0054] In some embodiments, the first channel layer 117 can have a substantially cylindrical outer profile. For example, in the case where the semiconductor structure 100 includes the second dielectric layer 116, the first channel layer 117 can also extend through the two second dielectric layers 116. The material of the first channel layer 117 can include one or more of polysilicon (poly-Si), amorphous silicon (a-Si), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), or any other suitable semiconductor material.

[0055] In some embodiments, the first gate dielectric layer 118 can be substantially a tubular structure. For example, in the case that the semiconductor structure 100 includes the second dielectric layer 116, the first gate dielectric layer 118 can also penetrate through two second dielectric layers 116. The material of the first gate dielectric layer 118 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), high dielectric constant material, or any other suitable insulating material. The high dielectric constant material can include, but is not limited to, aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O3), hafnium oxide (HfO2), etc.

[0056] In some embodiments, the alternatingly arranged storage layers 113 and isolation layers 114 are located in the first stack structure 111 and surround the end of the first conductive pillar 112 away from the second conductive layer 115. For example, the storage layers 113 can be substantially a cylindrical structure, and the isolation layers 114 can also be substantially a cylindrical structure. The closed ends of the cylindrical storage layers 113 and the isolation layers 114 are located in the first stack structure 111 (e.g., the first dielectric layer 1111).

[0057] As described above, the first channel layer 117, the first gate dielectric layer 118, and the portion of the second conductive layer 115 in contact with the first gate dielectric layer 118 can constitute the first transistor T1. The first transistor T1 can be referred to as a vertical channel transistor. For example, as shown in FIGS. 1A and IB, the end of the first channel layer 117 away from the first conductive pillar 112 can serve as one of the source and drain of the first transistor T1 and can be used to connect with the first bit line BL1. The end of the first channel layer 117 close to the first conductive pillar 112 can serve as the other of the source and drain of the first transistor T1 and can be connected with the second electrode (i.e., the first conductive pillar 112) of the plurality of storage capacitors C. The portion of the second conductive layer 115 in contact with the first gate dielectric layer 118 can serve as the control electrode (e.g., the gate) of the first transistor T1, and the other portion of the second conductive layer 115 can serve as the first word line WL1. FIG. 1A and FIG. 1B As described above, the first channel layer 117, the first gate dielectric layer 118, and the portion of the second conductive layer 115 in contact with the first gate dielectric layer 118 can constitute the first transistor T1. The first transistor T1 can be referred to as a vertical channel transistor. For example, as shown in FIGS. 1A and IB, the end of the first channel layer 117 away from the first conductive pillar 112 can serve as one of the source and drain of the first transistor T1 and can be used to connect with the first bit line BL1. The end of the first channel layer 117 close to the first conductive pillar 112 can serve as the other of the source and drain of the first transistor T1 and can be connected with the second electrode (i.e., the first conductive pillar 112) of the plurality of storage capacitors C. The portion of the second conductive layer 115 in contact with the first gate dielectric layer 118 can serve as the control electrode (e.g., the gate) of the first transistor T1, and the other portion of the second conductive layer 115 can serve as the first word line WL1.

[0058] The plurality of storage capacitors C are arranged in the z direction, the second electrodes of the storage capacitors C share the first conductive pillar 112 to achieve connection between each other, and the second electrodes (i.e., the first conductive pillar 112) of the storage capacitors C are also connected with one of the source and drain of the first transistor T1. The first transistor T1 and the plurality of storage capacitors C can constitute a memory cell MC, the plurality of storage capacitors C can be used to store more bits of data, and the first transistor T1 can serve as a switch to access the stored data.

[0059] In some embodiments, the semiconductor structure 100 can further include an insulating capping layer 119. For example, the insulating capping layer 119 can extend along the x- and y-directions and be located on a side of the second conductive layer 115 facing away from the first stack structure 111 (e.g., a surface of the second dielectric layer 116). The material of the insulating capping layer 119 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiOxNy), or any other suitable insulating material. For example, the material of the insulating capping layer 119 can be silicon oxide (SiO2). It should be noted that in the case where the material of the second dielectric layer 116 is the same as the material of the insulating capping layer 119, there is no apparent interface between the two and they can be a monolithic structure. x N y ) or any other suitable insulating material. For example, the material of the insulating capping layer 119 can be silicon oxide (SiO2). It should be noted that in the case where the material of the second dielectric layer 116 is the same as the material of the insulating capping layer 119, there is no apparent interface between the two and they can be a monolithic structure.

[0060] In some embodiments, the semiconductor structure 100 can further include a first contact structure 120. The first contact structure 120 can extend through the insulating capping layer 119 and be connected (e.g., in contact) with the first channel layer 117. For example, the first contact structure 120 can be substantially a columnar structure, which can have an inclined angle. The first contact structure 120 can be used to lead out the first channel layer 117 (e.g., one of the source and drain of the first transistor T1) in the z-direction. The material of the first contact structure 120 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0061] In some embodiments, the first contact structure 120 can include a first adhesion layer 1201 and a first conductive body 1202. The first conductive body 1202 can be substantially a columnar structure, the first adhesion layer 1201 can surround the sidewall of the first conductive body 1202, and the first conductive body 1202 can be close to the end surface of the first channel layer 117. The material of the first adhesion layer 1201 can include, but is not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The material of the first conductive body 1202 can include, but is not limited to, metal materials such as tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), etc. The first adhesion layer 1201 can be used to improve the bonding performance between the first conductive body 1202 and the insulating capping layer 119.

[0062] In some embodiments, the semiconductor structure 100 can further include a second contact structure 121. The second contact structure 121 can penetrate through the insulating cap layer 119 and extend to (e.g., inside of) the second conductive layer 115. For example, the second contact structure 121 can be substantially a columnar structure, which can have a tilt angle. The second contact structure 121 can be used to lead out the second conductive layer 115 (e.g., the control electrode of the first transistor T1) in the z direction. The material of the second contact structure 121 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0063] In some embodiments, the second contact structure 121 can include a second adhesion layer 1211 and a second conductive body 1212. The second conductive body 1212 can be substantially a columnar structure, the second adhesion layer 1211 can surround the sidewall of the second conductive body 1212, and the second conductive body 1212 can be close to the end surface of the second conductive layer 115. The material of the second adhesion layer 1211 can include, but is not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The material of the second conductive body 1212 can include, but is not limited to, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), etc. The second adhesion layer 1211 can be used to improve the bonding performance between the second conductive body 1212 and the insulating cap layer 119 and the second dielectric layer 116, respectively.

[0064] In some embodiments, the semiconductor structure 100 can further include a substrate 122. The substrate 122 can be located on the side of the first stack structure 111 away from the second conductive layer 115. The substrate 122 can include a semiconductor substrate. For example, the material of the substrate 122 can include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP), etc. For another example, the substrate 122 can include a silicon-on-insulator (SOI) or a germanium-on-insulator (GeOI) substrate, etc. For example, the substrate 122 can serve as a support.

[0065] FIG. 2A is a cross-sectional schematic view of a semiconductor structure provided by another embodiment of the present application. FIG. 2B is a circuit schematic view of a memory cell in a semiconductor structure provided by another embodiment of the present application. For the purpose of brief description, the same content as the previous embodiment, the present application will not be described here.

[0066] As FIG. 2AAs shown, the semiconductor structure 200 includes a first stack structure 211, a first conductive pillar 212, a storage layer 213, and an isolation layer 214. The first stack structure 211 includes first dielectric layers 2111 and first conductive layers 2112 arranged alternately. The first conductive pillar 212 extends in the z direction in the first stack structure 211. The storage layer 213 and the isolation layer 214 are arranged alternately and are located between the first conductive pillar 212 and the first stack structure 211. The first conductive layers 2112 are in contact with the storage layer 213, and the first conductive pillar 212 is in contact with the storage layer 213.

[0067] In some embodiments, the semiconductor structure 200 can further include a second conductive layer 215, a first channel layer 217, and a first gate dielectric layer 218. The second conductive layer 215 is located on one side of the first stack structure 211. The first channel layer 217 penetrates the second conductive layer 215 and is connected (e.g., in contact) with the first conductive pillar 212. The first gate dielectric layer 218 penetrates the second conductive layer 215 and surrounds the sidewall of the first channel layer 217.

[0068] In some embodiments, on the side of the first stack structure 211 away from the second conductive layer 215, the first conductive pillar 212 protrudes from the first stack structure 211. For example, the storage layer 213 can be substantially a tubular structure, and the isolation layer 214 can also be substantially a tubular structure. The tubular storage layer 213 and the isolation layer 214 are sleeved outside the portion of the first conductive pillar 212 located in the first stack structure 211.

[0069] In some embodiments, the semiconductor structure 200 can further include a third dielectric layer 223, a third conductive layer 224, a second conductive pillar 225, a second gate dielectric layer 226, and a second channel layer 227. The third dielectric layer 223 can be located on the side of the first stack structure 211 away from the second conductive layer 215. The first conductive pillar 212 extends to the third dielectric layer 223 from the end of the first stack structure 211 protruding. The third conductive layer 224 can be located on the side of the third dielectric layer 223 away from the first stack structure 211. The second conductive pillar 225 can penetrate the third conductive layer 224 and the third dielectric layer 223 and be connected with the first conductive pillar 212. The second gate dielectric layer 226 can penetrate the third conductive layer 224 and the third dielectric layer 223 and surround the sidewall of the second conductive pillar 225. The second channel layer 227 can penetrate the third conductive layer 224 and surround the sidewall of the second gate dielectric layer 226.

[0070] In some embodiments, the third dielectric layer 223 can extend along the x- and y-directions and cover a surface of the first stack structure 211 facing away from the second conductive layer 215. For example, the outermost layer of the first stack structure 211 near the second conductive layer 215 is the first dielectric layer 2111, and the outermost layer of the first stack structure 211 facing away from the second conductive layer 215 is the first conductive layer 2112. Thus, the third dielectric layer 223 can be in contact with the first conductive layer 2112 that is the outermost layer facing away from the second conductive layer 215. Alternatively, the outermost layers on both sides of the first stack structure in the z-direction are the first dielectric layer (not shown), which is not limited in the present application. Thus, the third dielectric layer can be in contact with the first dielectric layer that is the outermost layer facing away from the second conductive layer. The material of the third dielectric layer 223 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material.

[0071] It should be noted that, in the case where the outermost layers of the first stack structure are the first dielectric layer, and the material of the third dielectric layer is the same as that of the first dielectric layer, there is no obvious interface between the third dielectric layer and the first dielectric layer that is the outermost layer facing away from the second conductive layer, and they can be an integrated structure.

[0072] In some embodiments, the third conductive layer 224 can extend along the x- and y-directions and be located on a surface of the third dielectric layer 223 facing away from the first stack structure 211. The material of the third conductive layer 224 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO) or any other suitable conductive material. For example, the material of the third conductive layer 224 can be polysilicon (Poly-Si).

[0073] In some embodiments, the second conductive pillar 225 can have a substantially columnar structure and extend into the first conductive pillar 212 along the z-direction. The material of the second conductive pillar 225 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. In some examples, the second conductive pillar 225 can include an adhesion material layer 2251 and a body portion 2252. The body portion 2252 can have a substantially columnar structure, and the adhesion material layer 2251 can surround the sidewall of the body portion 2252 and be proximate to the end of the body portion 2252 that is proximate to the first conductive pillar 212. The material of the adhesion material layer 2251 can include, but is not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The material of the body portion 2252 can include, but is not limited to, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), etc. The adhesion material layer 2251 can be used to improve the bonding performance between the body portion 2252 and the second gate dielectric layer 226.

[0074] In some embodiments, the second gate dielectric layer 226 can have a substantially tubular structure and extend into the first conductive pillar 212 along the z-direction. The tubular second gate dielectric layer 226 can be disposed around the second conductive pillar 225, and the inner wall of the second gate dielectric layer 226 can be in contact with the outer wall of the second conductive pillar 225 (e.g., the adhesion material layer 2251). The material of the second gate dielectric layer 226 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), a high-k material, or any other suitable insulating material. The high-k material can include, but is not limited to, aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O3), hafnium oxide (HfO2), etc.

[0075] In some embodiments, the second channel layer 227 can have a substantially tubular structure and extend into the third dielectric layer 223 away from the surface of the first stack structure 211 along the z-direction. The tubular second channel layer 227 can be disposed around the second gate dielectric layer 226, and the inner wall of the second channel layer 227 can be in contact with the outer wall of the second gate dielectric layer 226. The material of the second channel layer 227 can include one or more of polysilicon (poly-Si), amorphous silicon (a-Si), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), or any other suitable semiconductor material.

[0076] In some embodiments, the semiconductor structure 200 can further include a fourth dielectric layer 228, an isolation structure 229, and a channel plug 230. The fourth dielectric layer 228 can be located on a side of the third conductive layer 224 facing away from the third dielectric layer 223. The second channel layer 227 can further extend through the fourth dielectric layer 228. The isolation structure 229 can be located inside the second channel layer 227 and at an end of the second conductive pillar 225 facing away from the first conductive pillar 212. The channel plug 230 can be located inside the second channel layer 227 and at an end of the isolation structure 229 facing away from the second conductive pillar 225. In this embodiment, the channel plug 230 can be used to increase the area of the second channel layer 227 at the end facing away from the second conductive pillar 225, and the isolation structure 229 can serve to electrically isolate the second conductive pillar 225 and the channel plug 230.

[0077] In some embodiments, the fourth dielectric layer 228 can extend along the x- and y-directions and be located on a surface of the third conductive layer 224 facing away from the third dielectric layer 223. The material of the fourth dielectric layer 228 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), or any other suitable insulating material. For example, the second conductive pillar 225 and the second gate dielectric layer 226 can extend into the fourth dielectric layer 228 but not through the fourth dielectric layer 228. For another example, in the z-direction, the second gate dielectric layer 226 can have a greater extension length than the second conductive pillar 225.

[0078] In some embodiments, the isolation structure 229 can be substantially a columnar structure and be located in a space surrounded by an inner wall of a portion of the second gate dielectric layer 226 protruding from the second conductive pillar 225 and an end surface of the second conductive pillar 225 facing away from the first conductive pillar 212. The material of the isolation structure 229 can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), or any other suitable insulating material. It should be noted that in the case where the material of the isolation structure 229 is the same as the material of the second gate dielectric layer 226, there is no clear interface between the two and they can be a unitary structure.

[0079] In some embodiments, the channel plug 230 can be substantially a columnar structure and be located in a space surrounded by an inner wall of a portion of the second channel layer 227 protruding from the isolation structure 229 and an end surface of the isolation structure 229 facing away from the second conductive pillar 225. The material of the channel plug 230 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0080] As described above, the second conductive pillar 225, the second gate dielectric layer 226, and the second channel layer 227 can constitute the second transistor T2. The second transistor T2 can be referred to as a ring channel (CAA) field effect transistor. For example, as shown in FIG. 2B, the second channel layer 227 can be in contact with the third conductive layer 224, and the third conductive layer 224 can be in contact with the second conductive pillar 225. The second channel layer 227 can be in contact with the first conductive pillar 212. FIG. 2A and FIG. 2B As shown in FIG. 2B, a portion of the second channel layer 227 in contact with the third conductive layer 224 can serve as one pole (e.g., one of a source and a drain) of the second transistor T2, and can be used to connect with the third conductive layer 224 as the second word line WL2. An end of the second channel layer 227 away from the first conductive pillar 212 can serve as another pole (e.g., another of the source and the drain) of the second transistor T2, and can be used to connect with the second bit line BL2. The second conductive pillar 225 can serve as a control pole (e.g., a gate) of the second transistor T2, and can be connected with the second electrode (i.e., the first conductive pillar 212) of the plurality of storage capacitors C.

[0081] The first transistor T1, the second transistor T2, and the plurality of storage capacitors C can constitute one memory cell MC, the plurality of storage capacitors C can be used to store more bits of data, and the first transistor T1 and the second transistor T2 can serve as switches to access the stored data. For example, the first word line WL1 can be a write word line, and the first bit line BL1 can be a write bit line. The second word line WL2 can be a read word line, and the second bit line BL2 can be a read bit line. The plurality of storage capacitors C can share the two transistors T1 and T2, so that the number of transistors configured per memory cell MC can be reduced, thereby helping to improve the storage density.

[0082] In some embodiments, the semiconductor structure 200 can further include a third contact structure 231. The third contact structure 231 can extend through the fourth dielectric layer 228 and to the third conductive layer 224 (e.g., inside the third conductive layer 224). For example, the third contact structure 231 can be substantially a pillar structure, which can have an inclined angle. The third contact structure 231 can be used to lead out the third conductive layer 224 (e.g., the second word line WL2) in the z direction. The material of the third contact structure 231 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material.

[0083] In some embodiments, the third contact structure 231 may include a third adhesive layer 2311 and a third conductive body 2312. The third conductive body 2312 may be generally columnar, and the third adhesive layer 2311 may surround the sidewalls of the third conductive body 2312 and the end face of the third conductive body 2312 near the third conductive layer 224. The material of the third adhesive layer 2311 may include, but is not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc. The material of the third conductive body 2312 may include, but is not limited to, tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), etc. The third adhesive layer 2311 can be used to improve the bonding performance between the third conductive body 2312 and the fourth dielectric layer 228.

[0084] Some embodiments of this application also provide a method for manufacturing a semiconductor structure. FIG. 3 This is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this application. FIG. 3 As shown, the semiconductor structure manufacturing method 300 (hereinafter referred to as manufacturing method 300) may include the following steps.

[0085] S310, a first hole extending along the stacking direction is formed in the first stacked structure, wherein the first stacked structure includes an alternately arranged first dielectric layer and a first conductive layer.

[0086] S320, a storage layer and an isolation layer are alternately formed on the inner wall of the first hole.

[0087] S330, a first conductive pillar is formed inside the storage layer.

[0088] According to the manufacturing method provided in the embodiments of this application, a storage capacitor capable of storing multi-bit information can be formed through the above steps, and the manufacturing method is simple. Furthermore, multiple storage capacitors arranged in the z-direction can be formed, which can increase the storage bit information capacity of a single storage cell, thereby improving storage density and enhancing the capacity for large-capacity information storage.

[0089] FIG. 4A to FIG. 4I This is a cross-sectional schematic diagram of the semiconductor structure provided in the embodiments of this application during the manufacturing process. The following is in conjunction with... FIG. 4A to FIG. 4I A manufacturing method 300 including steps S310 to S330 will be described by way of example.

[0090] S310

[0091] FIG. 4A An intermediate structure 400a containing a first stacked structure 411 is shown. FIG. 4B The intermediate structure 400b is shown after the formation of the first hole 441.

[0092] likeFIG. 4A As shown, the first dielectric layer 4111 and the first conductive layer 4112 can be formed alternately using thin film deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the first stacked structure 411. For example, the outermost layer of the first stacked structure 411 is always the first dielectric layer 4111.

[0093] In some embodiments, the material of the first dielectric layer 4111 may include silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiO2). x N y The first dielectric layer 4111 may be made of one or more of the following materials: tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. For example, the first conductive layer 4112 may be made of polysilicon (Poly-Si).

[0094] In some embodiments, the first stacked structure 411 may be formed on one side (e.g., the surface) of the substrate 422. The substrate 422 may include a semiconductor substrate. For example, the material of the substrate 422 may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). As another example, the substrate 422 may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) substrate. The substrate 422 may serve a supporting function.

[0095] like FIG. 4B As shown, an etching process (e.g., dry etching and / or wet etching) can be used to form a first hole 441 extending in the z-direction in the first stacked structure 411. The first hole 441 can extend from the side of the first stacked structure 411 away from the substrate 422 along the negative z-direction and stop inside the first dielectric layer 4111 closest to the substrate 422 in the first stacked structure 411.

[0096] S320

[0097] FIG. 4C An intermediate structure 400c is shown after the formation of the storage layer 413, the isolation layer 414, and the first conductive pillar 412.

[0098] like FIG. 4B and FIG. 4CAs shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to form the storage layers 413 and the isolation layers 414 alternatively on the inner wall of the first hole 441. For example, a storage layer 413 can be formed first on the inner wall of the first hole 441, and then an isolation layer 414 can be formed on the inner wall of the storage layer 413. Subsequently, the above process can be repeated, and then a storage layer 413 can be formed again on the inner wall of the isolation layer 414 farthest from the inner wall of the first hole 441. In this way, the storage layer 413 formed first is in contact with the first conductive layer 4112 exposed by the first hole 441, and the storage layer 413 formed last is exposed.

[0099] It should be noted that although FIG. 4C Although three storage layers 413 and two isolation layers 414 are shown, in other alternative embodiments, a larger number (e.g., more than three) of storage layers 413 and a larger number (e.g., more than two) of isolation layers 414 can be formed, which are not specifically limited in the present application.

[0100] In some embodiments, the material of the storage layer 413 can include a ferroelectric material. The ferroelectric material can include one or more of zirconium oxide (ZrO2), hafnium oxide (HfO2), aluminum (Al) doped HfO2, silicon (Si) doped HfO2, zirconium (Zr) doped HfO2, lanthanum (La) doped HfO2, yttrium (Y) doped HfO2, and other element doped ferroelectric materials. In other embodiments, the material of the storage layer 413 can include an anti-ferroelectric material. The anti-ferroelectric material can include lead zirconate (PbZrO3), lead hafnate (PbHfO3), sodium niobate (NaNbO3), ammonium dihydrogen phosphate (NH4H2PO4), ammonium iodate (NH4IO3), tungsten trioxide (WO3), etc.

[0101] In some embodiments, the material of the isolation layer 414 can include an insulating material. For example, the insulating material can include one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For another example, the insulating material can include a high dielectric constant material such as aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O3), hafnium oxide (HfO2), etc. In the case where the isolation layer 414 is made of a high dielectric constant material, it is beneficial to improve the isolation effect of the isolation layer 414 between adjacent storage layers 413, reduce the risk of charge leakage between adjacent storage layers 413, and improve the accuracy of stored information.

[0102] S330

[0103] As FIG. 4CAs shown, the first conductive pillar 412 can be formed inside the storage layer 413 by a thin film deposition process of CVD, PVD, ALD or any combination thereof. For example, the first conductive pillar 412 can be formed in the space inside the last formed storage layer 413. Alternatively, the first conductive pillar 412 can be formed on the inner wall of the last formed storage layer 413, and an insulating pillar (not shown) can be formed in the space inside the first conductive pillar 412. In this way, the last formed storage layer 413 can be in contact with the first conductive pillar 412.

[0104] In some embodiments, the material of the first conductive pillar 412 can include one or more of tungsten (W), molybdenum (Mo), copper (Cu), aluminum (Al), ruthenium (Ru), titanium (Ti), titanium nitride (TiN), polysilicon (Poly-Si), indium tin oxide (ITO), or any other suitable conductive material. For example, the material of the first conductive pillar 412 is tungsten (W).

[0105] According to the manufacturing method of the semiconductor structure provided by the above embodiments, the storage capacitor capable of storing multi-bit information can be formed, and the manufacturing method is simple. In addition, a plurality of storage capacitors arranged in the z direction can also be formed, the capacity of storing bit information of a single storage unit can be expanded, the storage density can be improved, and the capacity of storing large amount of information can be improved.

[0106] In some embodiments, the manufacturing method 300 further includes the following steps: forming a second conductive layer on one side of the first stack structure; forming a first channel hole penetrating through the second conductive layer to the first conductive pillar; and forming a first gate dielectric layer on the sidewall of the first channel hole, and forming a first channel layer inside the first gate dielectric layer.

[0107] FIG. 4D and FIG. 4E are cross-sectional structure diagrams during the execution of the above process steps. Among them, FIG. 4D Fig. 400d shows the intermediate structure 400d after the formation of the second conductive layer 415 and the first channel hole 442. FIG. 4E Fig. 400e shows the intermediate structure 400e after the formation of the first gate dielectric layer 418 and the first channel layer 417. The above process steps are illustrated below in combination with FIG. 4D and FIG. 4E The above process steps are illustrated below in combination with

[0108] In some embodiments, as shown in Fig. 400a, the first stack structure 400a includes a plurality of storage layers 413 and a plurality of first conductive pillars 412. FIG. 4DAs shown, a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof, can be used to form a second dielectric layer 416, a second conductive layer 415, and another second dielectric layer 416 in sequence on the side of the first stack structure 411 away from the substrate 422. As a result, the second conductive layer 415 can be formed on the side of the first stack structure 411, with one of the second dielectric layers 416 located between the first stack structure 411 and the second conductive layer 415.

[0109] In some embodiments, as shown in FIG. 4B, a first trench hole 442 can be formed through the second dielectric layer 416 and the second conductive layer 415 to expose the first conductive pillar 412. FIG. 4D

[0110] In some embodiments, as shown in FIG. 4C, a first gate dielectric layer 418 can be formed on the sidewall of the first trench hole 442. Further, a first channel layer 417 can be formed inside the first gate dielectric layer 418. For example, the first channel layer 417 can be formed on the inner wall of the first gate dielectric layer 418, and the space surrounded by the first channel layer 417 can be filled with an insulating material. As another example, the first channel layer 417 can be formed in the space surrounded by the first gate dielectric layer 418. FIG. 4D FIG. 4E

[0111] In some embodiments, as shown in FIG. 4D, the manufacturing method 300 can further include a step of forming an insulating cap layer 419. For example, a thin film deposition process, such as CVD, PVD, ALD, or any combination thereof, can be used to form the insulating cap layer 419 on the side of the second conductive layer 415 away from the first stack structure 411 (e.g., the surface of the second dielectric layer 416). FIG. 4E

[0112] In some embodiments, as shown in FIG. 4E, a second gate dielectric layer 428 can be formed on the sidewall of the first trench hole 442. Further, a second channel layer 427 can be formed inside the second gate dielectric layer 428. For example, the second channel layer 427 can be formed on the inner wall of the second gate dielectric layer 428, and the space surrounded by the second channel layer 427 can be filled with an insulating material. As another example, the second channel layer 427 can be formed in the space surrounded by the second gate dielectric layer 428. FIG. 4E ​​​​As shown, the manufacturing method 300 further includes steps of forming the first contact structure 420 and the second contact structure 421. For example, first, an etching (e.g., wet etching and / or dry etching) process can be employed to form a first contact hole (corresponding to the outer profile of the first contact structure 420) and a second contact hole (corresponding to the outer profile of the second contact structure 421), respectively. Among others, the first contact hole can penetrate through the insulating cap layer 419 and expose the first channel layer 417, and the second contact hole can penetrate through the insulating cap layer 419 and the second dielectric layer 416 and extend into the second conductive layer 415. Then, a thin film deposition process of CVD, PVD, ALD, or any combination thereof can be employed to form a first adhesive layer 4201 and a second adhesive layer 4211 on the inner walls of the first contact hole and the second contact hole, respectively. Next, a thin film deposition process of CVD, PVD, ALD, or any combination thereof can be employed to form a first conductive body 4202 and a second conductive body 4212 on the inner sides of the first adhesive layer 4201 and the second adhesive layer 4211, respectively. Among others, the first adhesive layer 4201 and the first conductive body 4202 can constitute the first contact structure 420, and the second adhesive layer 4211 and the second conductive body 4212 can constitute the second contact structure 421.

[0113] It is noted that in the step of forming the first contact structure 420 and the second contact structure 421, the step of forming the first adhesive layer 4201 and the second adhesive layer 4211 can be omitted, and after forming the first contact hole and the second contact hole, a conductive material can be filled in the first contact hole and the second contact hole, respectively, to form the first contact structure and the second contact structure.

[0114] In some embodiments, the manufacturing method 300 can further include the following steps: removing a portion of the isolation layer and the storage layer from the side of the first stack structure facing away from the second conductive layer to expose the first conductive pillar; forming a third dielectric layer covering the first conductive pillar on the side of the first stack structure facing away from the second conductive layer; forming a third conductive layer on the side of the third dielectric layer facing away from the first stack structure; forming an initial second channel hole penetrating through the third conductive layer to the third dielectric layer, and forming a second channel layer on the inner wall of the initial second channel hole; deepening the initial second channel hole to the first conductive pillar to form a second channel hole; and forming a second gate dielectric layer on the sidewall of the second channel hole, and forming a second conductive pillar on the inner side of the second gate dielectric layer.

[0115] FIG. 4F to FIG. 4I is a cross-sectional view of the intermediate structure during the process of forming the first contact structure 420 and the second contact structure 421. FIG. 4F shows the intermediate structure 400f after removing a portion of the storage layer 413 and the isolation layer 414 to expose the first conductive pillar 412. FIG. 4G shows the intermediate structure 400g after forming the third dielectric layer 423, the third conductive layer 424, and the second channel layer 427. FIG. 4HAn intermediate structure 400h after forming the second channel hole 443 is shown. FIG. 4I An intermediate structure 400i after forming the second gate dielectric layer 426 and the second conductive column 425 is shown. The following describes the process of forming the second channel hole 443 in the second gate dielectric layer 426 and the second conductive column 425 in detail. FIG. 4F to FIG. 4I The above process steps are illustrated by examples.

[0116] In some embodiments, as shown in FIG. 4A, a thin film deposition process of CVD, PVD, ALD, or any combination thereof can be used to form the third dielectric layer 423 covering the surface of the first stack structure 411 facing away from the second conductive layer 415 and covering the portion of the first conductive column 412 protruding from the first stack structure 411. FIG. 4E and FIG. 4F As shown in FIG. 4B, a chemical mechanical polishing (CMP) process and / or an etching (e.g., dry etching and / or wet etching) process can be used to sequentially remove the substrate 422, the outermost first dielectric layer 4111 of the first stack structure 411, and the protruding portions of the storage layer 413 and the isolation layer 414 alternately arranged from the remaining first stack structure 411, so that the first conductive column 412 is exposed. In this way, the first conductive column 412 protrudes from the remaining first stack structure 411.

[0117] In some embodiments, as shown in FIG. 4A, a thin film deposition process of CVD, PVD, ALD, or any combination thereof can be used to form the third dielectric layer 423 covering the surface of the first stack structure 411 facing away from the second conductive layer 415 and covering the portion of the first conductive column 412 protruding from the first stack structure 411. FIG. 4G In some embodiments, as shown in FIG. 4A, a thin film deposition process of CVD, PVD, ALD, or any combination thereof can be used to form the third dielectric layer 423 covering the surface of the first stack structure 411 facing away from the second conductive layer 415 and covering the portion of the first conductive column 412 protruding from the first stack structure 411.

[0118] FIG. 4G In some embodiments, as shown in FIG. 4A, a thin film deposition process of CVD, PVD, ALD, or any combination thereof can be used to form the third dielectric layer 423 covering the surface of the first stack structure 411 facing away from the second conductive layer 415 and covering the portion of the first conductive column 412 protruding from the first stack structure 411.

[0119] In some embodiments, as shown in FIG. 4A, a thin film deposition process of CVD, PVD, ALD, or any combination thereof can be used to form the third dielectric layer 423 covering the surface of the first stack structure 411 facing away from the second conductive layer 415 and covering the portion of the first conductive column 412 protruding from the first stack structure 411. FIG. 4G In some embodiments, as shown in FIG. 4B, an etching (e.g., wet etching and / or dry etching) process can be used to form an initial second channel hole 443’ sequentially penetrating the fourth dielectric layer 428 and the third conductive layer 424. The initial second channel hole 443’ can stop at the surface of the third dielectric layer 423 facing away from the first stack structure 411. For example, the initial second channel hole 443’ is substantially aligned with the first conductive column 412. Next, a thin film deposition process of CVD, PVD, ALD, or any combination thereof can be used to form the second channel layer 427 on the inner wall of the initial second channel hole 443’. For example, in this step, the second channel layer 427 can cover the sidewall and the bottom of the initial second channel hole 443’.

[0120] FIG. 4G and​​FIG. 4H As shown, an etching process (e.g., wet etching and / or dry etching) can be used to deepen the initial second channel hole 443' to the first conductive post 412. The deepened initial second channel hole 443' can be referred to as the second channel hole 443. For example, the second channel hole 443 can extend into the interior of the first conductive post 412. Furthermore, after this step, the portion of the second channel layer 427 located at the bottom of the initial second channel hole 443' is removed, while the portion of the second channel layer 427 located on the sidewall of the initial second channel hole 443' is retained.

[0121] In some implementations, such as FIG. 4H and FIG. 4I As shown, a second gate dielectric layer 426 can be formed on the sidewall of the second channel hole 443 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Next, an adhesive material layer 4251 can be formed on the inner sidewall of the second gate dielectric layer 426 and the bottom of the second channel hole 443 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and a main body portion 4252 is formed inside the adhesive material layer 4251. The adhesive material layer 4251 and the main body portion 4252 can constitute a second conductive pillar 425.

[0122] It should be noted that in the step of forming the second conductive pillar 425, the step of forming the adhesive material layer 4251 can be omitted, and after forming the second gate dielectric layer 426, conductive material is filled inside it to form the second conductive pillar.

[0123] In some implementations, such as FIG. 4I As shown, the manufacturing method 300 further includes the step of forming a third contact structure 431. For example, a third contact hole (corresponding to the outer contour of the third contact structure 431) may first be formed using an etching process (e.g., wet etching and / or dry etching). The third contact hole may penetrate the fourth dielectric layer 428 and extend into the interior of the third conductive layer 424. Then, a third adhesive layer 4311 may be formed on the inner wall of the third contact hole using a thin film deposition process of CVD, PVD, ALD, or any combination thereof. Next, a third conductive body 4312 may be formed inside the third adhesive layer 4311 using a thin film deposition process of CVD, PVD, ALD, or any combination thereof. The third adhesive layer 4311 and the third conductive body 4312 constitute the third contact structure 431.

[0124] It should be noted that in the step of forming the third contact structure 431, the step of forming the third adhesive layer 4311 can be omitted, and after forming the third contact hole, conductive material is filled into the third contact hole to form the third contact structure.

[0125] Some embodiments of this application also provide a memory. FIG. 5is a schematic block diagram of a memory provided by embodiments of the present application. As shown, the memory 50 can include a semiconductor structure 51 and a peripheral circuit 52. For example, the semiconductor structure 51 and the peripheral circuit 52 can be arranged in a z-direction to constitute the memory 50. FIG. 5

[0126] The semiconductor structure 51 can be implemented as the semiconductor structure described in any of the above embodiments (e.g., the semiconductor structure 100 shown in FIG. 1A or the semiconductor structure 200 shown in). In some embodiments, as described above, the semiconductor structure 51 can include a plurality of memory cells MC. In some examples, each memory cell MC can include one transistor T1 and a plurality of memory capacitors C. In other examples, each memory cell MC can include two transistors T1, T2 and a plurality of memory capacitors C. For example, the memory capacitors C can be ferroelectric capacitors. The semiconductor structure 51 can include a memory cell array constituted by the plurality of memory cells MC to implement data storage. FIG. 2A

[0127] The peripheral circuit 52 can be coupled to the semiconductor structure 51. The peripheral circuit 52 can include any suitable digital, analog, and / or mixed-signal peripheral circuitry for facilitating operation of a memory cell array in the semiconductor structure 51. For example, the peripheral circuit 52 can include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion of the above functional circuitry (e.g., a sub-circuit), or any active or passive components of the circuitry (e.g., a transistor, a diode, a resistor, or a capacitor).

[0128] Some embodiments of the present application also provide a memory system. FIG. 6 is a schematic block diagram of a system having a memory system provided by embodiments of the present application.

[0129] As shown, the system 60 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an argument reality (AR) device, or any other suitable electronic device having a memory system 62 located therein. As shown, the system 60 can include a host 68 and the memory system 62. The memory system 62 can have one or more memories 64 and a controller 66. Among others, the memory 64 can be implemented as the memory 50 described above (refer to FIG. 6 FIG. 6 FIG. 5 ​​​​The host 68 can be a processor of an electronic device, such as a central processing unit (CPU), or can be a system-on-chip (SoC), such as an application processor (AP). The host 68 can be configured to send or receive data to or from the memory 64.

[0130] In some embodiments, the controller 66 can be coupled to the memory 64 and the host 68, and configured to control the memory 64. For example, the controller 66 can be configured to control the memory 64 to perform operations such as reading, erasing, and programming. The controller 66 can also manage data stored in the memory 64 and communicate with the host 68. For example, the controller 66 can communicate with an external device (e.g., the host 68) according to a specific communication protocol.

[0131] The above description is merely illustrative of the embodiments of the present application and the principles thereof. Those skilled in the art shall understand that the scope of protection of the present application is not limited to the technical solutions formed by the specific combinations of the technical features described above, and shall also cover other technical solutions formed by any combinations of the technical features described above or their equivalent features without departing from the technical concepts. For example, the technical solutions formed by mutually replacing the above-described features with the technical features disclosed in the present application (but not limited to) having similar functions.

Claims

1. A semiconductor structure, wherein, include: The first stacked structure includes alternating first dielectric layers and first conductive layers; The first conductive post extends along the stacking direction in the first stacked structure; as well as Alternating storage and isolation layers are located between the first conductive pillar and the first stacked structure; Both the first conductive layer and the first conductive pillar are in contact with the storage layer.

2. The semiconductor structure according to claim 1, wherein, The material of the isolation layer includes insulating material.

3. The semiconductor structure according to claim 2, wherein, The insulating material includes materials with high dielectric constant.

4. The semiconductor structure according to claim 1, wherein, There are multiple storage layers.

5. The semiconductor structure according to claim 1, wherein, The material of the storage layer includes ferroelectric or antiferroelectric materials.

6. The semiconductor structure according to any one of claims 1 to 5, wherein, Along a direction away from the outer wall of the first conductive pillar, the storage layer and the isolation layer are alternately arranged.

7. The semiconductor structure according to any one of claims 1 to 5, wherein, The semiconductor structure also includes: The second conductive layer is located on one side of the first stacked structure; A first channel layer penetrates the second conductive layer and is connected to the first conductive pillar; and A first gate dielectric layer extends through the second conductive layer and surrounds the sidewalls of the first channel layer.

8. The semiconductor structure according to claim 7, wherein, The alternating isolation layer and storage layer are located in the first stacked structure and surround the end of the first conductive pillar away from the second conductive layer.

9. The semiconductor structure according to claim 7, wherein, On the side of the first stacked structure opposite to the second conductive layer, the first conductive pillar protrudes from the first stacked structure, and the semiconductor structure further includes: A third dielectric layer is located on the side of the first stacked structure opposite to the second conductive layer, wherein the first conductive post protrudes from the end of the first stacked structure and extends into the third dielectric layer; The third conductive layer is located on the side of the third dielectric layer that is away from the first stacked structure; The second conductive post penetrates the third conductive layer and the third dielectric layer, and is connected to the first conductive post; A second gate dielectric layer extends through the third conductive layer and the third dielectric layer, and surrounds the sidewall of the second conductive pillar; and The second channel layer penetrates the third conductive layer and surrounds the sidewalls of the second gate dielectric layer.

10. The semiconductor structure according to claim 9, wherein, Also includes: The fourth dielectric layer is located on the side of the third conductive layer opposite to the third dielectric layer, wherein the second channel layer also penetrates the fourth dielectric layer; An isolation structure is located inside the second channel layer and at the end of the second conductive post opposite to the first conductive post; and The channel plug is located inside the second channel layer and at the end of the isolation structure opposite to the second conductive post.

11. A memory, wherein, include: The semiconductor structure as described in any one of claims 1 to 10; as well as The peripheral circuit is coupled to the semiconductor structure.

12. A memory system, wherein, include: The memory as described in claim 11; as well as A controller, coupled to the memory, is used to control the memory to store data.

13. A method for manufacturing a semiconductor structure, wherein, The manufacturing method includes: A first hole extending along the stacking direction is formed in a first stacked structure, wherein the first stacked structure includes an alternately arranged first dielectric layer and a first conductive layer; A storage layer and an isolation layer are alternately formed on the inner wall of the first hole; and A first conductive pillar is formed inside the storage layer.

14. The manufacturing method according to claim 13, wherein, The manufacturing method further includes: A second conductive layer is formed on one side of the first stacked structure; Forming a first channel hole penetrating the second conductive layer to the first conductive pillar; and A first gate dielectric layer is formed on the sidewall of the first channel hole, and a first channel layer is formed inside the first gate dielectric layer.

15. The manufacturing method according to claim 14, wherein, The manufacturing method further includes: Remove a portion of the isolation layer and the storage layer from the side of the first stacked structure opposite to the second conductive layer to expose the first conductive pillar; A third dielectric layer is formed on the side of the first stacked structure opposite to the second conductive layer, covering the first conductive pillar; A third conductive layer is formed on the side of the third dielectric layer that is opposite to the first stacked structure; An initial second channel hole is formed, penetrating from the third conductive layer to the third dielectric layer, and a second channel layer is formed on the inner wall of the initial second channel hole; Deepen the initial second channel hole to the first conductive post to form a second channel hole; and A second gate dielectric layer is formed on the sidewall of the second channel hole, and a second conductive post is formed on the inner side of the second gate dielectric layer.

16. The manufacturing method according to any one of claims 13 to 15, wherein, The material of the isolation layer includes insulating material.

17. The manufacturing method according to claim 16, wherein, The insulating material includes materials with high dielectric constant.

18. The manufacturing method according to any one of claims 13 to 15, wherein, There are multiple storage layers.

19. The manufacturing method according to any one of claims 13 to 15, wherein, The material of the storage layer includes ferroelectric or antiferroelectric materials.

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