Preparation method of semiconductor structure, power device and electronic equipment
By forming a buffer doped region and a second doped region in the MOSFET device and dispersing the charge using a two-stage sidewall process, the gate oxide reliability problem caused by the HCI effect is solved, thereby optimizing device performance and simplifying the process.
Patent Information
- Application Number
- CN202511191207.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-25
- Publication Date
- 2025-11-18
AI Technical Summary
In the prior art, MOSFET devices with submicron or deep submicron channel lengths are prone to hot carrier injection (HCI effect), which leads to gate oxide reliability failure and affects device performance and lifespan.
By forming a buffer doped region and a second doped region within the substrate, and using two sidewall processes as masks, the charge is dispersed, the peak electric field is reduced, and the process flow is simplified, reducing the number of mask removals.
While reducing the channel length, the impact of HCI effect on the device is reduced, performance is optimized, manufacturing process is simplified, and cost and complexity are reduced.
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Figure CN120980904A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, and in particular to a method for fabricating a semiconductor structure, a power device, and an electronic device. Background Technology
[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used and high-performance power devices. Wide-bandgap semiconductor materials, such as silicon carbide (SiC), are ideal materials for fabricating high-performance power MOSFETs due to their excellent properties. On-resistance is a crucial performance indicator for SiC MOSFETs, and its magnitude determines the power device's losses. To obtain MOSFETs with low on-resistance, shorter channel lengths are typically used to reduce on-resistance.
[0003] However, submicron or deep submicron channel lengths cause localized hot spots to easily form near the channel at the MOSFET source due to concentrated current density, resulting in hot carrier injection (HCE or HCI). This exacerbates gate oxide reliability failures, causing device performance degradation or damage, thereby shortening device lifespan and reducing reliability. Summary of the Invention
[0004] Therefore, it is necessary to provide a method for fabricating semiconductor structures, power devices, and electronic devices to address the technical problems in the existing technology, at least to avoid or reduce the impact of the HCI effect on device performance.
[0005] In a first aspect, this application provides a method for fabricating a semiconductor structure for power devices with a channel length not exceeding the submicron level, the method comprising:
[0006] A substrate is provided; a first surface of the substrate includes mask layers spaced apart along a first direction and extending along a second direction; a side surface of the mask layers includes a first sidewall structure; the second direction is perpendicular to the first direction;
[0007] Based on the first sidewall structure, a buffer doping region is formed within the substrate;
[0008] A second sidewall structure is formed on the side surface of the first sidewall structure, and grooves are arranged at intervals between adjacent second sidewall structures along the second direction;
[0009] Based on the second sidewall structure, a first doped region is formed in the substrate at the bottom of the groove; the first doped region penetrates the buffer doped region along the direction toward the substrate;
[0010] After removing the first sidewall structure, the second sidewall structure, and the mask layer, a second doped region is formed in the substrate along the second direction between adjacent first doped regions.
[0011] In the semiconductor structure fabrication method described in the above embodiments, a buffer doped region is formed in the substrate through a first sidewall structure, creating a "buffer band" to disperse charge, reduce the maximum electric field intensity of the trench along the first direction, and decrease the probability of hot carriers appearing. Based on this, a second sidewall process is performed to form a second sidewall structure, which is then used as a mask to complete the fabrication of the first doped region. The two sidewall processes serve as masks for the buffer doped region and the first doped region, respectively, and the sidewall structure can be removed in a single operation, significantly reducing the number of mask removal operations. This optimizes the electrical performance of the device while simplifying the process, laying the foundation for reducing the process complexity and manufacturing cost of power devices.
[0012] In some embodiments, the substrate further includes a well region extending into the substrate via a first surface;
[0013] Forming a buffer doped region includes:
[0014] An ion implantation process is performed on the well region located adjacent to the first sidewall structure to form a buffer doped region extending into the well region via the first surface.
[0015] In some embodiments, the conductivity type of the buffer doped region is the same as that of the first doped region, and the doping concentration is less than that of the first doped region.
[0016] The conductivity type of the second doped region is the same as that of the well region, but opposite to that of the first doped region.
[0017] In some embodiments, the first doped region extends through the buffer doped region and into the well region via the first surface in a direction toward the substrate;
[0018] The second doped region extends through the buffer doped region via the first surface in the direction toward the substrate and into the well region.
[0019] In some embodiments, forming a second sidewall structure includes:
[0020] A sacrificial layer is formed covering the top surface of the buffer doped region, the mask layer, and the first sidewall structure;
[0021] Part of the sacrificial layer is removed to form a groove, and the remaining sacrificial layer is used to form the second sidewall structure.
[0022] In some embodiments, forming a groove includes:
[0023] A photoresist layer is formed on the top surface of the sacrificial layer;
[0024] forming a patterned photoresist layer, forming strip-shaped photoresist layers arranged in the second direction and extending in the first direction;
[0025] etching and removing the part of the sacrificial layer between the adjacent strip-shaped photoresist layers to form a groove.
[0026] In some embodiments, forming the second doped region comprises:
[0027] forming a mask material layer covering the first surface;
[0028] etching and removing part of the mask material layer to form a trench penetrating the mask material layer in a direction towards the substrate; the trench is arranged alternately with the first doped region in the second direction in the orthographic projection of the first surface;
[0029] forming the second doped region in the well region at the bottom of the groove.
[0030] In some embodiments, after forming the second doped region, the method further comprises:
[0031] forming strip-shaped gate electrodes on the first surface on both sides of the buffer doped region; the strip-shaped gate electrodes are arranged in the first direction and extend in the second direction;
[0032] The distance between the adjacent strip-shaped gate electrodes is not greater than the size of the well region in the first direction.
[0033] In a second aspect, the present application further provides a power device comprising the semiconductor structure prepared by the preparation method in any one of the above embodiments.
[0034] In a third aspect, the present application further provides an electronic device comprising the semiconductor structure prepared by the preparation method in any one of the above embodiments; or comprising the power device in the above embodiments.
[0035] In the power device and the electronic device in the above embodiments, the semiconductor structure prepared by the preparation method can reduce the influence of HCI effect on the reliability of the gate oxide of the device while reducing the cell size (PITCH), ensure that the device performance (such as breakdown voltage and switching efficiency) is maintained or even optimized, and simultaneously realize substantial simplification of the overall manufacturing process, meeting the needs of modern electronic devices for miniaturization and high performance.
[0036] The semiconductor structure preparation method, the power device and the electronic device provided by the present application have the following unexpected technical effects:
[0037] Compared with the conventional preparation process, the process step of preparing the buffer doped region is integrated into the traditional process flow by adjusting the process timing in the application, the two side wall processes are used as the masks of the buffer doped region and the first doped region respectively, and the side wall structure can be removed once subsequently, so that the operation times of mask removal are greatly reduced, while the channel length is reduced to the sub-micron level to reduce the on-resistance, the buffer doped region is used to disperse the electric charge on both sides of the channel to reduce the peak electric field, and the damage of the hot carrier to the gate oxide layer is reduced, so that the overall manufacturing process is effectively simplified, and the manufacturing cost and complexity are reduced. BRIEF DESCRIPTION OF DRAWINGS
[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0039] Figure 1 The flow chart of the semiconductor structure preparation method provided in an embodiment;
[0040] Figure 2 The cross-sectional schematic diagram of the structure obtained after forming the well region in step S102 in the semiconductor structure preparation method provided in an embodiment;
[0041] Figure 3 The cross-sectional schematic diagram of the structure obtained after forming the mask layer and the first side wall structure in an embodiment; Figure 2 The cross-sectional schematic diagram of the structure obtained after forming the mask layer and the first side wall structure in an embodiment;
[0042] Figure 4 The cross-sectional schematic diagram of the structure obtained after forming the buffer doped region in step S104 in the semiconductor structure preparation method provided in an embodiment;
[0043] Figure 5a The cross-sectional schematic diagram of the structure obtained after forming the sacrificial layer photoresist layer in step S106 in the semiconductor structure preparation method provided in an embodiment;
[0044] Figure 5b The cross-sectional schematic diagram of the structure obtained after forming the sacrificial layer photoresist layer in step S106 in the semiconductor structure preparation method provided in an embodiment;
[0045] Figure 6 The cross-sectional schematic diagram of the structure obtained after forming the second side wall structure in an embodiment; Figure 5a The cross-sectional schematic diagram of the structure obtained after forming the second side wall structure in an embodiment;
[0046] Figure 7 The cross-sectional schematic diagram of the structure obtained after forming the buffer doped region in step S108 in the semiconductor structure preparation method provided in an embodiment;
[0047] Figure 8a A cross-sectional schematic view of the structure obtained after removing the first side wall structure, the second side wall structure and the mask layer in step S110 of the method for manufacturing a semiconductor structure according to an embodiment;
[0048] Figure 8b A cross-sectional schematic view of the structure obtained after removing the first side wall structure, the second side wall structure and the mask layer in step S110 of the method for manufacturing a semiconductor structure according to an embodiment;
[0049] Figure 9a A cross-sectional schematic view of the structure obtained after forming the trench in step S120 of the method for manufacturing a semiconductor structure according to an embodiment; Figure 8a A cross-sectional schematic view of the structure obtained after forming the trench in step S120 of the method for manufacturing a semiconductor structure according to an embodiment;
[0050] Figure 9b A cross-sectional schematic view of the structure obtained after forming the trench in step S120 of the method for manufacturing a semiconductor structure according to an embodiment; Figure 8b A cross-sectional schematic view of the structure obtained after forming the trench in step S120 of the method for manufacturing a semiconductor structure according to an embodiment;
[0051] Figure 10 A cross-sectional schematic view of the structure obtained after forming the trench in step S120 of the method for manufacturing a semiconductor structure according to an embodiment; Figure 9a A cross-sectional schematic view of the structure obtained after forming the trench in step S120 of the method for manufacturing a semiconductor structure according to an embodiment; Figure 9b A cross-sectional schematic view of the structure obtained after forming the trench in step S120 of the method for manufacturing a semiconductor structure according to an embodiment.
[0052] Legend of reference signs:
[0053] 1, initial substrate; 2, well region; 10, substrate; 11, buffer doped region; 102, recess; 12, first doped region; 103, trench; 13, second doped region; 21, mask layer; 22, sacrificial layer; 23, mask material layer; 31, first side wall structure; 32, second side wall structure; 40, strip-shaped gate. DETAILED DESCRIPTION
[0054] In order to facilitate the understanding of the present application, a more full and comprehensive description of the present application will be made with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be realized in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0056] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section; for example, a first doped type could be termed a second doped type; and similarly, a second doped type could be termed a first doped type; a first doped type and a second doped type are different doped types, e.g., a first doped type can be p-type and a second doped type can be n-type, or the first doped type can be n-type and the second doped type can be p-type.
[0057] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other direction (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0058] The singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. In addition, use of the term "and / or" includes any and all combinations of associated items.
[0059] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of this application, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of this application.
[0060] Please see Figure 1 This application provides a method for fabricating a semiconductor structure for power devices with a channel length not greater than the submicron level, comprising: steps S102-S110.
[0061] Step S102: Provide a substrate; the first surface of the substrate includes mask layers spaced apart along a first direction and extending along a second direction; the side surface of the mask layers includes a first sidewall structure; the second direction is perpendicular to the first direction.
[0062] Step S104: Based on the first sidewall structure, a buffer doped region is formed in the substrate.
[0063] Step S106: Form a second sidewall structure located on the side surface of the first sidewall structure, and grooves located between adjacent second sidewall structures and spaced apart along the second direction.
[0064] Step S108: Based on the second sidewall structure, a first doped region is formed in the substrate at the bottom of the groove; the first doped region penetrates the buffer doped region along the direction toward the substrate.
[0065] Step S110: After removing the first sidewall structure, the second sidewall structure, and the mask layer, a second doped region is formed in the substrate along the second direction between adjacent first doped regions.
[0066] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1At least one of the steps in the method can include multiple steps or multiple stages, which are not necessarily performed at the same time, but can be performed at different times, and the order of the steps or stages is not necessarily sequential, but can be performed alternately or alternately with at least one of the other steps or steps in the step or stage.
[0067] The following will be described in detail Figures 2 to 10 The preparation method provided in the embodiments of the present application will be described in detail.
[0068] In the embodiments of the present application, in order to facilitate understanding, the substrate can include a first surface located on the front surface, and a back surface opposite to the front surface, i.e. a second surface. At the same time, the first direction is defined as the Y-axis direction, the second direction is defined as the X-axis direction, and the third direction is defined as the Z-axis direction.
[0069] Please refer to Figures 2-3 , Figure 2 The figure a in the step S102 is a cross-sectional view of the semiconductor structure along the line A-A' or the line B-B' provided by the present application, and the figure b is a top view of the semiconductor structure. It should be understood that the figure a and the figure b of the other views also correspond to the cross-sectional view and the top view of the device in the corresponding step respectively, and the following will not be described in detail. Step S102: providing a substrate 10; the first surface 10a of the substrate 10 includes a mask layer 21 which is arranged at intervals along the OY direction and extends along the OX direction; the side surface of the mask layer 21 includes a first side wall structure 31.
[0070] Specifically, an ion implantation process is used to form a well region 2 extending into the initial substrate 1 through the first surface 10a in the initial substrate 1, to obtain the substrate 10, and the specific structure is as shown in Figure 2 After the deposition process is used to form the mask layer 21 on the top surface of the first surface 10a of the substrate 10, a photoresist layer is coated, and a series of steps such as exposure and development are performed on the patterned photoresist layer, and then any one of dry etching or wet etching is used to form the first side wall structure 31, and the specific structure is as shown in Figure 3 .
[0071] For example, the initial substrate 1 can be a single-layer structure or a multi-layer structure, so the type of the initial substrate 1 should not limit the protection scope of the present disclosure. In addition, the initial substrate 1 can also include a shallow trench isolation structure and other structures, which are omitted because they are not related to the invention point of the present scheme. In addition, in the embodiment in which the substrate 10 includes a P-type initial substrate 1, N-type ions can be implanted to form the well region 2; and correspondingly, in the embodiment in which the substrate 10 includes an N-type initial substrate 1, P-type ions can be implanted to form the well region 2. In the present embodiment, the conductivity type of the initial substrate 1 is N-type, and the conductivity type of the well region 2 is P-type.
[0072] For example, the material of the mask layer 21 includes but is not limited to polysilicon.
[0073] For example, the material of the first side wall structure 31 includes but is not limited to polysilicon.
[0074] Referring to Figure 4 , in step S104, a buffer doped region 11 is formed in the substrate 10 based on the first side wall structure 31, and a structure as shown in Figure 4 is obtained.
[0075] Specifically, since the conductivity type of the initial substrate 1 is N type and the conductivity type of the well region 2 is P type in the embodiment, the buffer doped region 11 can be formed by a self-aligned process of injecting N type ions.
[0076] Referring to Figure 5a , Figures 5b-7 , in step S106, a second side wall structure 32 is formed on the side surface of the first side wall structure 31, and a groove 102 is formed between adjacent second side wall structures 32 and arranged along the OX direction.
[0077] Specifically, a deposition process is used to form a sacrificial layer 22 and a photoresist layer on the top surface of the buffer doped region 11, the mask layer 21 and the first side wall structure 31, and the photoresist layer is patterned to form a strip-shaped photoresist layer arranged along the OX direction, and a specific structure is as shown in Figures 5a-5b .
[0078] Subsequently, any etching method is used to remove the sacrificial layer 22 between adjacent strip-shaped photoresist layers to form the groove 102, and the remaining sacrificial layer 22 constitutes the second side wall structure 32, and a specific structure is as shown in Figure 6 .
[0079] Referring to Figure 7 , in step S108, a first doped region 12 is formed in the substrate at the bottom of the groove 102 based on the second side wall structure 32; the first doped region 12 penetrates the buffer doped region 11 along the ZO direction.
[0080] Specifically, a self-aligned ion implantation process is performed on the substrate 10 at the bottom of the groove 102 with the second side wall structure 32 as a mask to form the first doped region 12 by injecting N type ions, and a specific structure is as shown in Figure 7 .
[0081] For example, the material of the sacrificial layer 22 includes but is not limited to polysilicon.
[0082] For example, the doping concentration of the buffer doped region 11 is not greater than that of the first doped region 12.
[0083] In the above embodiment, the first side wall structure 31 and the second side wall structure 32 are simple in preparation process and strong in thickness controllability. After the doping process is completed, the two side wall structures can be removed simultaneously in subsequent processes.
[0084] Please refer to Figures 8a-8b , Figures 9a-9b Step S110: After the first side wall structure 31, the second side wall structure 32, and the mask layer 21 are removed, a second doped region 13 located between adjacent first doped regions 12 along the OY direction is formed in the substrate 10.
[0085] Specifically, the first side wall structure 31, the second side wall structure 32, and the mask layer 21 are removed by using a grinding process or other planarization process, and a structure as shown in FIGS. 11a and 11c is obtained. Figure 8a and Figure 8b The mask material layer 23 covering the first surface 10a is formed by using a deposition process, and part of the mask material layer 23 is etched to form a trench 103 penetrating the mask material layer 23 along the ZO direction. The substrate 10 at the bottom of the trench 103 is implanted with P-type ions to form the second doped region 13, and a structure as shown in FIGS. 12a and 12c is obtained. Figure 9a and Figure 9b The structure.
[0086] Please refer to Figure 10 , wherein, Figure 10 FIG. a in FIG. c is a sectional view of the semiconductor structure along the line A-A', and FIG. b is a sectional view of the semiconductor structure along the line B-B'.
[0087] The strip-shaped gate 40 is formed on the first surface 10a on both sides of the buffer doped region 11; the strip-shaped gate 40 is arranged at intervals along the OY direction and extends along the OX direction; the interval between adjacent strip-shaped gates 40 is not greater than the width (i.e., the size along the OY direction) of the well region, so as to ensure that the strip-shaped gate covers the channel.
[0088] In a second aspect, the present application also provides a power device comprising the semiconductor structure prepared by the preparation method in any one of the above embodiments.
[0089] In a third aspect, the present application also provides an electronic device comprising the semiconductor structure prepared by the preparation method in any one of the above embodiments or comprising the power device in the above embodiments.
[0090] Since the power device, the electronic device, and the semiconductor structure preparation method in the above embodiments are based on the same inventive concept, the power device and the electronic device prepared by using the semiconductor structure preparation method have all the advantages of the semiconductor structure preparation method provided by the present application, and thus, details are not described herein again
[0091] In the above embodiments, the unexpected technical effects of the present application are:
[0092] Compared with the conventional process, the application integrates the preparation of the buffer doped region into the traditional process by adjusting the timing, uses two sidewall processes as masks for the buffer doped region and the first doped region respectively, and removes the sidewall at one time, thereby greatly reducing the number of mask removals. Meanwhile, the channel is reduced to a sub-micron level to reduce the on-resistance, the buffer doped regions on both sides of the channel disperse the electric charge and reduce the peak electric field, the damage of hot carriers to the gate oxide is reduced, and the process is effectively simplified, the cost and complexity are reduced.
[0093] The technical features of the above-mentioned embodiments can be combined in any manner. In order to make the description simple, all possible combinations of the technical features of the above-mentioned embodiments are not described, but as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present disclosure.
[0094] The above-mentioned embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that for ordinary skilled persons in the art, some modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the patent protection scope of the present application should be subject to the appended claims.
Claims
1. A method of fabricating a semiconductor structure, comprising: A power device for channel length not more than sub-micron level, comprising: providing a substrate; a mask layer is included on a first surface of the substrate, the mask layer is arranged along a first direction and extends along a second direction; a first side wall structure is included on a side surface of the mask layer; the second direction is perpendicular to the first direction; forming a buffer doped region in the substrate based on the first side wall structure; forming a second side wall structure on a side surface of the first side wall structure, and forming a groove between adjacent second side wall structures and arranged along the second direction; forming a first doped region in the substrate at a bottom of the groove based on the second side wall structure; the first doped region penetrates the buffer doped region along a direction towards the substrate; after removing the first side wall structure, the second side wall structure and the mask layer, forming a second doped region in the substrate between adjacent first doped regions along the second direction.
2. The production method according to claim 1, characterized by, the substrate further comprises a well region extending into the substrate via the first surface; forming the buffer doped region comprises: performing ion implantation process on the well region between adjacent first side wall structures to form a buffer doped region extending into the well region via the first surface.
3. The preparation method according to claim 2, characterized in that, the buffer doped region has the same conductivity type as the first doped region and has a doping concentration less than that of the first doped region; the second doped region has the same conductivity type as the well region and has an opposite conductivity type to the first doped region.
4. The production method according to claim 3, characterized by, the first doped region penetrates the buffer doped region along a direction towards the substrate and extends into the well region via the first surface; the second doped region penetrates the buffer doped region along a direction towards the substrate and extends into the well region via the first surface.
5. The preparation method according to claim 3, characterized in that, forming the second side wall structure comprises: forming a sacrificial layer covering top surfaces of the buffer doped region, the mask layer and the first side wall structure; removing part of the sacrificial layer to form the groove, and the remaining sacrificial layer is used to form the second side wall structure.
6. The preparation method according to claim 5, characterized in that, forming the groove comprises: forming a photoresist layer on a top surface of the sacrificial layer; patterning the photoresist layer to form strip-shaped photoresist layers arranged along the second direction and extending along the first direction; etching and removing part of the sacrificial layer between adjacent strip-shaped photoresist layers to form the groove.
7. The preparation method according to claim 3, characterized in that, forming the second doped region comprises: forming a mask material layer covering the first surface; etching and removing part of the mask material layer to form a trench penetrating the mask material layer along a direction towards the substrate; a projection of the trench on the first surface and the first doped region are arranged alternately along the second direction; forming the second doped region in the well region at the bottom of the groove.
8. The method of any one of claims 2-7, wherein, after forming the second doped region, further comprising: forming strip-shaped gates on the first surface on both sides of the buffer doped region; the strip-shaped gates are arranged along the first direction and extend along the second direction; a distance between adjacent strip-shaped gates is not greater than a size of the well region along the first direction.
9. A power device, characterized by comprising: a semiconductor structure prepared by the preparation method of any one of claims 1-8.
10. An electronic device, comprising: comprising: A semiconductor structure produced by the production method according to any one of claims 1 to 8; or A power device according to claim 9.