Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate; the base comprises a substrate, a gate structure arranged on the substrate and sacrificial side walls located on the two sides of the gate structure; wherein metal silicides are respectively formed on the substrate and the gate structure; the surface of the substrate is provided with a gap region located between the gate structure and the metal silicide; based on a stress proximity technology, removing the sacrificial side wall, and arranging stress layers on the substrate and the gate structure; the thickness of the stress layer is greater than the width of the gap region; removing part of the stress layer to expose at least part of the surface of the metal silicide; the rest stress layer forms a grid side wall; wherein the gap region is covered by the gate side wall; a first interlayer dielectric layer is arranged on the surfaces of the metal silicide and the gate side wall; and etching the first interlayer dielectric layer corresponding to the position of the metal silicide to prepare a contact hole. Therefore, the problem of high contact resistance of the contact hole manufactured after the SPT process is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor manufacturing process, in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] SPT (Stress Proximity Technology) is a technology widely used in advanced semiconductor device manufacturing process in recent years. The technical principle is mainly as follows: after forming metal silicide at the gate and the source-drain region, the side wall is removed, and then the stress layer is deposited to more effectively transmit the stress to the channel region, thereby improving the mobility of the carriers. Subsequently, the contact hole is made at the position corresponding to the gate and the source-drain region.

[0003] However, the technical personnel found that the contact hole made after the SPT process is prone to high contact resistance problem. SUMMARY

[0004] Therefore, embodiments of the present application are devoted to providing a semiconductor structure and a manufacturing method thereof, which can reduce the high contact resistance problem of the contact hole made after the SPT process.

[0005] One embodiment of the present application provides a manufacturing method of a semiconductor structure, which comprises: providing a substrate; the substrate comprises a substrate, a gate structure arranged on the substrate, and a sacrificial side wall arranged on both sides of the gate structure; wherein the substrate and the gate structure are respectively formed with metal silicide; the surface of the substrate has a gap region between the gate structure and the metal silicide; based on the stress proximity technology, the sacrificial side wall is removed, and a stress layer is arranged on the substrate and the gate structure; wherein the thickness of the stress layer is greater than the width of the gap region; part of the stress layer is removed to expose at least part of the surface of the metal silicide; the remaining part of the stress layer forms a gate side wall; wherein the gap region is covered by the gate side wall; a first interlayer dielectric layer is arranged on the surface of the metal silicide and the gate side wall; and the first interlayer dielectric layer is etched to manufacture a contact hole at the position corresponding to the metal silicide.

[0006] Optionally, in the step of etching the first interlayer dielectric layer to manufacture a contact hole at the position corresponding to the metal silicide, the etching selectivity ratio of the first interlayer dielectric layer with respect to the gate side wall falls within the range of 6-15.

[0007] Optionally, the gate side wall is at least partially in direct contact with the metal silicide of the substrate to form a contact region; wherein the width of the contact region falls within the range of 120Å-160Å.

[0008] Optionally, the step of etching the first interlayer dielectric layer to form a contact hole corresponding to the location of the metal silicide includes: etching trenches on the first interlayer dielectric layer to form a second interlayer dielectric layer, based on the locations of the gate sidewall and the metal silicide formed on the substrate; wherein there is a height difference between the surface of the second interlayer dielectric layer on the metal silicide of the gate structure and the surface of the second interlayer dielectric layer on the metal silicide of the substrate; etching the second interlayer dielectric layer to form a corresponding contact hole at the location of the metal silicide.

[0009] Optionally, the depth of the trench falls within the range of 600 Å to 1000 Å.

[0010] Optionally, the height difference is consistent with the height of the gate structure relative to the substrate.

[0011] Optionally, the step of etching the second interlayer dielectric layer to form a corresponding contact hole at the location of the metal silicide includes: stacking an organic dielectric layer and a mask layer on the second interlayer dielectric layer; forming an opening defining the location of the contact hole in the organic dielectric layer and the mask layer using photolithography and etching processes according to the location of the metal silicide; wherein, the second interlayer dielectric layer is not etched during the etching of the organic dielectric layer; and etching the second interlayer dielectric layer along the opening location to form the contact hole.

[0012] Optionally, the method for fabricating the semiconductor structure further includes: filling the contact hole with a metal material and planarizing it to form a contact structure; wherein the metal material covers the metal silicide.

[0013] Optionally, the type of contact hole includes: a shared contact hole; the shared contact hole is located on both the metal silicide of the gate structure and the metal silicide of the substrate.

[0014] One embodiment of this application provides a semiconductor structure, which is prepared using the semiconductor structure preparation method described in any of the foregoing embodiments.

[0015] The various embodiments provided in this application offer the unexpected benefit of removing the stress layer on the metal silicide before the SPT process. This eliminates the need for a separate stress layer removal process after the first interlayer dielectric layer etching during subsequent contact hole fabrication, thus preventing damage to the gate sidewalls made of the same material. Furthermore, by setting the stress layer thickness in the SPT process to be greater than the width of the gap region, the gap region is prevented from being exposed after removing the stress layer on the metal silicide. This ensures that the fabricated gate sidewalls completely cover the gap region, preventing high contact resistance issues caused by the gap region being exposed at the bottom of the contact hole. Attached Figure Description

[0016] Figures 1-4 This is a schematic diagram of the contact hole preparation process after the SPT process in related technologies.

[0017] Figure 5 This is a schematic diagram of a method for fabricating a semiconductor structure provided in an embodiment of this application.

[0018] Figure 6 This is a schematic diagram of the substrate used in the method for fabricating the semiconductor structure provided in this application embodiment.

[0019] Figure 7 This is a schematic diagram of the removal of sacrificial sidewalls in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0020] Figure 8 This is a schematic diagram of the stress layer being set in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0021] Figure 9 This is a schematic diagram illustrating the removal of a portion of the stress layer in the method for fabricating a semiconductor structure provided in this application embodiment.

[0022] Figure 10 This is a schematic diagram of the first interlayer dielectric layer in the method for fabricating the semiconductor structure provided in the embodiments of this application.

[0023] Figures 11-12 This is a schematic diagram of etching trenches in the first interlayer dielectric layer in the method for fabricating the semiconductor structure provided in the embodiments of this application.

[0024] Figure 13 This is a schematic diagram illustrating the organic dielectric layer and mask layer in the method for fabricating a semiconductor structure provided in this application embodiment.

[0025] Figure 14 This is a schematic diagram of the formation of an opening in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0026] Figure 15 This is a schematic diagram of etching to form contact holes in the semiconductor structure fabrication method provided in the embodiments of this application.

[0027] Figure 16 This is a schematic diagram of the formation of a contact structure in the method for fabricating a semiconductor structure provided in the embodiments of this application.

[0028] Figure 17 This is a schematic diagram of the grinding amount of metal materials in related technologies.

[0029] Figure 18 This is a schematic diagram of the amount of metal material being ground in an embodiment of this application.

[0030] Explanation of reference numerals in the attached figures: 10. Substrate; 11. Substrate; 12. Metal silicide; 13. Gate structure; 31. Sacrificial sidewall; 32. Gap region; 14. Stress layer; 15. Gate sidewall; 16. First interlayer dielectric layer; 161. Second interlayer dielectric layer; 17. Mask layer; 18. Organic dielectric layer; 19. Metal material; 21. Contact region; 22. Trench; 23. Opening; 24. Contact hole; 25. Contact structure. Detailed Implementation

[0031] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0032] In this application, the accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features.

[0033] Unless otherwise stated, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0034] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0035] In the description of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. In other words, they should not be construed as limitations on this application.

[0036] In the description of this application, unless otherwise expressly defined, the terms "installation," "connection," "linking," "fixing," "setting," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can also refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0037] Please see Figures 1 to 4 . Figures 1-4 This diagram illustrates the main steps involved in fabricating contact holes after the SPT process in related technologies. Figure 1 As shown, a stress layer 104 is deposited on the substrate 101 and the gate structure 103 based on the SPT process. In the step of fabricating the contact hole 107, the stress layer 104 can serve as an etching stop layer. Specifically, the contact hole 107 is fabricated by covering the stress layer 104 with an interlayer dielectric layer 106, and performing photolithography and etching processes on the interlayer dielectric layer 106 corresponding to the positions of the metal silicide 102 on the gate structure 103 and the substrate 101. Figure 2 and Figure 3 This is a schematic diagram of the etching process. Since the bottom of the contact hole 107 needs to expose the metal silicide 102 for direct contact with the subsequently filled metal material, it undergoes the following etching process... Figure 2 and Figure 3 After the etching process shown, the stress layer 104 still covering the surface of the metal silicide 102 on the substrate 101 needs to be removed again to complete the process. Figure 4 The fabrication of the contact hole 107 shown is illustrated. The stress layer 104 on the side of the gate structure 103 can serve as the gate sidewall 105.

[0038] However, reference Figure 3 and Figure 4 Because the aspect ratio of the contact hole 107 is usually high, the stress layer 104 on the side of the gate structure 103 will also be damaged to some extent during the process of removing the stress layer 104 covering the surface of the metal silicide 102. As a result, when the stress layer 104 covering the surface of the metal silicide 102 is completely removed, the stress layer 104 on the side of the gate structure 103 is also almost removed. This results in the gate sidewall 105 being missing when the contact hole 107 is fabricated. Consequently, after the metal material is filled into the contact hole 107, some of the metal material will directly contact the gap region 108 between the gate structure and the metal silicide, resulting in high contact resistance and even easily causing open circuit problems, which will affect the electrical performance of the semiconductor structure.

[0039] To reduce gate sidewall defects during contact hole fabrication after the SPT process, ensuring complete coverage of the gap region and enabling full contact between the contact hole's metal material and the metal silicide, one embodiment of this application provides a semiconductor structure fabrication method. This method involves removing the stress layer covering the metal silicide beforehand during contact hole fabrication after the SPT process, exposing the metal silicide, and then covering it with an interlayer dielectric layer and performing an etching process to create the contact hole. This eliminates the need for additional removal of the remaining stress layer on the metal silicide after etching the interlayer dielectric layer, thus avoiding etching damage to the stress layer on the gate structure's sidewalls and preventing gate sidewall defects.

[0040] However, the semiconductor structures fabricated using the above methods still exhibit high contact resistance. Further analysis revealed that this is because, after removing the original sacrificial sidewalls of the gate structure using the SPT process, the deposited stress layer may be relatively thin to effectively transfer stress. This results in the exposure of gap regions after removing the stress layer on the metal silicide. Particularly, if the stress layer covering the sidewalls of the gate structure is thin, the gap regions cannot be covered by the formed gate sidewalls after the stress layer on the metal silicide is removed, easily leading to high contact resistance.

[0041] Therefore, it is necessary to provide a method for fabricating semiconductor structures that can prevent gap regions from being uncovered by the gate sidewalls during the fabrication of contact holes based on the SPT process. This allows the metal material subsequently filled into the contact holes to fully contact the metal silicide, avoiding high contact resistance or open circuit problems and improving the electrical performance of semiconductor structures fabricated based on the SPT process.

[0042] Please see Figures 5 to 18 One embodiment of this application provides a method for fabricating a semiconductor structure, which may include the following steps.

[0043] S110: Provides a substrate.

[0044] In this embodiment, as Figure 6 As shown, the substrate 10 may include: a substrate 11, a gate structure 13 disposed on the substrate 11, and sacrificial sidewalls 31 located on both sides of the gate structure 13; wherein, the substrate 11 and the gate structure 13 are respectively formed with metal silicide 12; the surface of the substrate 11 has a gap region 32 located between the gate structure 13 and the metal silicide 12.

[0045] The substrate 11 can serve as the basic structure of a semiconductor structure, not only providing mechanical support but also influencing the electrical properties of the semiconductor structure, such as threshold voltage and carrier mobility, through doping with ions. Specifically, the substrate 11 can be made of silicon (Si) or, depending on the requirements, other semiconductor materials such as silicon carbide (SiC) or gallium nitride (GaN).

[0046] The gate structure 13 can be used to influence the switching state of the MOS structure. Specifically, the gate structure 13 can be composed of a gate material and a gate oxide layer. As the gate electrode, the gate material can be polysilicon or a metal (such as aluminum, Al). The gate material can be isolated from the substrate 11 through the gate oxide layer. The gate oxide layer can specifically be silicon dioxide (SiO2). In some embodiments, the gate structure 13 may also include a work function adjustment layer. When a voltage is applied to the gate structure 13, it can attract or repel carriers in the channel region, thereby affecting the flow of carriers between the source and drain. In some embodiments, the gate structure 13 may also include oxide sidewalls located on both sides of the gate material, and sacrificial sidewalls 31 may be located on both sides of the oxide sidewalls.

[0047] The metal silicide 12 can be used as a contact connection between the metal material filling the contact hole and the substrate 11 to reduce contact resistance. Specifically, the metal silicide can be nickel silicide (NiSi), titanium silicide (TiSi2), cobalt silicide (CoSi2), etc. In some embodiments, the metal silicide 12 can be located on the gate material of the gate structure 13 to serve as a contact connection between the metal material disposed on the metal silicide 12 and the gate. The metal silicide 12 can also be located on the source / drain regions of the substrate 11 to serve as a contact connection between the metal material disposed on the metal silicide 12 and the source / drain.

[0048] The gap region 32 can be a surface region of the substrate 11 located between the gate structure 13 and the metal silicide 12. Specifically, in the fabricated semiconductor structure with contact holes, the gap region 32 needs to be covered by the gate sidewalls so that it does not come into direct contact with the metal material filling the contact holes.

[0049] S120: Based on stress proximity technology, the sacrificial sidewalls are removed, and a stress layer is formed on the substrate and gate structure; wherein the thickness of the stress layer is greater than the width of the gap region.

[0050] In this embodiment, as Figure 7 and Figure 8 As shown, by removing the sacrificial sidewall 31 and setting the stress layer 14 through deposition or other methods, stress is transferred to the channel, thereby improving the carrier mobility. It should be noted that the sacrificial sidewall 31 can be removed entirely or only partially.

[0051] In some embodiments, the stress layer 14 is used to form a stress field and transfer stress to the channel region through diffusion and mechanical coupling to change the band structure of the channel region, improve carrier mobility, and optimize the performance of the semiconductor structure. Specifically, a suitable material for the stress layer 14 can be selected according to the type of stress to be introduced. For example, the stress layer 14 can be made of silicon nitride or silicon carbide, or it can be titanium nitride, aluminum nitride, etc. In some embodiments, the stress layer 14 can also be used to form gate sidewalls in subsequent processes of the SPT process.

[0052] In some embodiments, if the thickness of the stress layer 14 is not uniform, the deposition thickness of a portion of the stress layer 14 located on the side of the gate structure 13 may exceed the width of the gap region 32.

[0053] S130: Remove part of the stress layer to expose at least a portion of the surface of the metal silicide; the remaining portion of the stress layer forms a gate sidewall; wherein the gap region is covered by the gate sidewall.

[0054] In this embodiment, please refer to the following: Figure 8 and Figure 9 The stress layer 14 covering the surface of the metal silicide 12 can be partially removed by an etch-back process, thereby exposing the metal silicide 12. The remaining stress layer 14 serves as the gate sidewall 15, meaning the gate sidewall 15 is fabricated in advance. It is understood that in this embodiment, the material of the gate sidewall 15 can be the same as the stress layer 14. In some embodiments, other processes can also be used to partially remove the stress layer 14; the choice can be flexible and depends on actual needs, and this application does not impose specific limitations on this.

[0055] In this embodiment, since the deposition thickness of the stress layer 14 is greater than the width of the gap region 32, the gap region 32 can still be covered by the gate sidewall 15 and will not be exposed after the stress layer 14 is partially removed by the etch-back process.

[0056] S140: A first interlayer dielectric layer is formed on the surface of the metal silicide and the gate sidewall.

[0057] In this embodiment, as Figure 10 As shown, a first interlayer dielectric layer 16 can be deposited on the surfaces of the metal silicide 12 and the gate sidewall 15 to provide isolation and insulation between the fabricated contact holes. Specifically, the interlayer dielectric layer 16 can be made of silicon dioxide (SiO2) or other low dielectric constant materials.

[0058] S150: At the location corresponding to the metal silicide, the first interlayer dielectric layer is etched to create a contact hole.

[0059] In this embodiment, for example, Figure 10 The structure shown allows etching of the first interlayer dielectric layer 16 to form contact holes that penetrate the first interlayer dielectric layer 16 and expose at least a portion of the surface of the metal silicide 12. Specifically, in the fabrication process of a MOS device, contact holes can include various types, such as gate contact holes located on the surface of the metal silicide of the gate structure, active region contact holes (AA CT) located on the metal silicide of the substrate as source / drain contacts, and shared contact holes (SCT) located on both the metal silicide of the gate structure and the metal silicide of the substrate as shared by the gate and source / drain electrodes. In this embodiment, the location of the contact hole to be fabricated can be determined according to the type of contact hole, and then etching can be performed according to the size (CT CD) of the contact hole.

[0060] In this embodiment, an unexpected effect is that by removing the stress layer 14 on the metal silicide 12 before the SPT process, it is not necessary to perform an additional stress layer removal process on the metal silicide 12 after the first interlayer dielectric layer 16 is etched during subsequent contact hole fabrication. This avoids damage to the gate sidewall 15 made of the same material. Furthermore, the thickness of the stress layer 14 in the SPT process is set to be greater than the width of the gap region 32, preventing the gap region 32 from being exposed after removing the stress layer 14 on the metal silicide 12. Thus, the fabricated gate sidewall 15 can completely cover the gap region 32, preventing high contact resistance caused by the gap region 32 being exposed at the bottom of the contact hole. Especially for shared contact holes and active region contact holes, related technologies often cause significant damage to the gate sidewall due to the removal of the etch stop layer before fabricating shared contact holes and active region contact holes. Therefore, this embodiment provides more significant protection for the gate sidewall when used to fabricate shared contact holes and active region contact holes.

[0061] In some embodiments, in the step of etching the first interlayer dielectric layer at the location corresponding to the metal silicide to form a contact hole, the etching selectivity of the first interlayer dielectric layer relative to the gate sidewall falls in the range of 6 to 15.

[0062] In some embodiments, please refer to Figure 10Because the contact hole has a high depth-to-width ratio, and the etching process of the first interlayer dielectric layer 16 also causes some etching damage to the gate sidewall 15 on the side of the gate structure 13, the etching selectivity of the first interlayer dielectric layer 16 relative to the gate sidewall 15 cannot be too high or too low. Controlling the etching selectivity of the first interlayer dielectric layer 16 relative to the gate sidewall 15 within the range of 6 to 15 can prevent open circuit problems caused by byproducts at the bottom of the contact hole, and can also control the etching damage to the gate sidewall 15 during the etching of the first interlayer dielectric layer 16 to a level that has a minimal impact on electrical performance. Specifically, for example, the etching selectivity of the interlayer dielectric layer 16 relative to the gate sidewall 15 can be 6, 15, or other values ​​such as 8, 10, or 12.

[0063] In some embodiments, the gate sidewall is at least partially in direct contact with the metal silicide of the substrate to form a contact region; wherein the width of the contact region falls in the range of 120 Å to 160 Å.

[0064] Please continue to refer to this. Figure 10 As mentioned earlier, during the etching of the first interlayer dielectric layer 16, due to the selectivity not being too high, etching damage to the gate sidewall 15 is unavoidable. Therefore, in conjunction with... Figure 8 and Figure 9 For reference, when setting the stress layer 14, the width of the stress layer 14 located on the side of the gate structure 13 (i.e., the gate sidewall subsequently formed) can be adjusted. For example, if the thickness of the stress layer 14 is deposited to be thicker, after the process of removing part of the stress layer 14 and forming the gate sidewall 15, the gate sidewall 15 can have direct contact with the metal silicide 12 of the substrate 11, and form a contact region 21 overlapping on the surface of the substrate 11. In this way, when... Figure 10 During the etching process of the first interlayer dielectric layer 16 shown, since the etching consumption of the gate sidewall located on the contact area 21 is reserved, even if part of the gate sidewall 15 is etched away in the width direction, the bottom of the contact hole will not be metal silicide 12, thus avoiding direct contact between the metal filled in the contact hole and the substrate surface where metal silicide 12 has not been formed.

[0065] In some embodiments, when the selectivity of etching the first interlayer dielectric layer 16 falls within the range of 6 to 15, by controlling the width of the contact area 21 within the range of 120 Å to 160 Å, the gate sidewall 15 can still cover the substrate surface between the gate structure 13 and the metal silicide 12 of the substrate 11 after the first interlayer dielectric layer 16 has been etched, thus preventing the bottom of the contact hole from not being metal silicide 12.

[0066] In some embodiments, the step of etching an interlayer dielectric layer to form a contact hole corresponding to the location of a metal silicide includes: etching trenches on the interlayer dielectric layer based on the locations of the gate sidewall and the metal silicide formed on the substrate to form a second interlayer dielectric layer; wherein there is a height difference between the surface of the second interlayer dielectric layer on the metal silicide of the gate structure and the surface of the second interlayer dielectric layer on the metal silicide of the substrate; etching the second interlayer dielectric layer to form a corresponding contact hole at the location of the metal silicide.

[0067] In some embodiments, such as Figure 10 As shown, since the first interlayer dielectric layer 16 covers the metal silicide 12 of the gate structure 13 and the substrate 11, its thickness is uneven. The thickness of the first interlayer dielectric layer 16 directly above the surface of the metal silicide 12 of the gate structure 13 is smaller than the thickness of the first interlayer dielectric layer 16 directly above the surface of the metal silicide 12 of the substrate 11. As a result, when etching the first interlayer dielectric layer 16, the first interlayer dielectric layer 16 on the metal silicide 12 of the substrate 11 has not been completely etched before the first interlayer dielectric layer 16 on the metal silicide 12 of the gate structure 13 has already been etched.

[0068] At this point, please refer to... Figure 2 and Figure 3 Taking related technologies as an example, the material covered by the interlayer dielectric layer 106 at the gate structure 103 will begin to be etched. When the interlayer dielectric layer 106 on the metal silicide 102 of the substrate 101 is completely etched, the metal silicide 102 of the gate structure 103 will be etched and damaged, thereby affecting the electrical performance. In some embodiments, a similar situation may occur during the etching of the first interlayer dielectric layer 16. Furthermore, referring to... Figure 10 If the stress layer 14 on the metal silicide 12 has been removed in advance, the metal silicide 12 of the gate structure 13 will be etched more severely due to the lack of protection from the stress layer 14.

[0069] In some embodiments, trenches 22 are etched on the first interlayer dielectric layer 16 at the corresponding positions of the metal silicide 12 to form a second interlayer dielectric layer 161. This allows for a height difference between the surface of the second interlayer dielectric layer 161 on the metal silicide 12 of the gate structure 13 and the surface of the second interlayer dielectric layer 161 on the metal silicide 12 of the substrate 11. This reduces the thickness difference between the first interlayer dielectric layer 16 on the metal silicide 12 of the gate structure 13 and the first interlayer dielectric layer 16 on the metal silicide 12 of the substrate 11. Consequently, the etching processes at the corresponding positions of the metal silicide 12 of the gate structure 13 and the corresponding positions of the metal silicide 12 of the substrate 11 tend to be synchronized, reducing damage to the metal silicide 12 caused by premature etching of the first interlayer dielectric layer 16 on the metal silicide 12 of the gate structure 13.

[0070] In some embodiments, such as Figure 11 and Figure 12 As shown, a mask layer 17 can be formed on the first interlayer dielectric layer 16, and a trench 22 corresponding to the gate sidewall 15 and the metal silicide 12 formed on the substrate 11 can be etched on the first interlayer dielectric layer 16 using a photolithography process. The remaining first interlayer dielectric layer 16 forms the second interlayer dielectric layer 161. The width of the trench 22 can be the same as the spacing width between adjacent gate structures 13. The depth of the trench 22 is the height difference h between the surface of the second interlayer dielectric layer 161 on the metal silicide 12 of the gate structure 13 and the surface of the second interlayer dielectric layer 161 on the metal silicide 12 of the substrate 11.

[0071] In some embodiments, the depth of trench 22 can fall within the range of 600 Å to 1000 Å. By controlling the height difference h within this range, the metal silicide 12 of the gate structure 13 is subjected to less or no etching damage during the etching of the second interlayer dielectric layer 161, and the electrical performance of the semiconductor structure is basically not affected.

[0072] In some embodiments, the height difference corresponds to the height of the gate structure relative to the substrate. (Reference) Figure 12 When the height difference h is the same as the height of the gate structure 13 relative to the substrate 11, the problem of inconsistent etching process caused by the uneven thickness of the first interlayer dielectric layer 16 on the metal silicide 12 of the gate structure 13 and the substrate 11 can be eliminated, thereby avoiding etching damage to the metal silicide 12 of the gate structure 13, which has a better effect.

[0073] In some embodiments, the step of etching a second interlayer dielectric layer to form a corresponding contact hole at the location of a metal silicide includes: stacking an organic dielectric layer and a mask layer on the second interlayer dielectric layer; forming an opening defining the location of the contact hole in the organic dielectric layer and the mask layer using photolithography and etching processes according to the location of the metal silicide; wherein the second interlayer dielectric layer is not etched during the etching of the organic dielectric layer; and etching the second interlayer dielectric layer along the opening location to form the contact hole.

[0074] In some embodiments, such as Figure 13 and Figure 14 As shown, an organic dielectric layer 18 and a mask layer 17 are disposed on the second interlayer dielectric layer 161. The positions of contact holes are defined using photolithography, and openings 23 are etched into the mask layer 17 and the organic dielectric layer 18. The positions of the openings 23 correspond to the positions of the contact holes, and the openings 23 may have stepped surfaces. Further, as... Figure 14 and Figure 15As shown, with the position of the opening 23 as a reference, the second interlayer dielectric layer 161 is etched to form a through contact hole 24.

[0075] By providing an organic dielectric layer 18 between the mask layer 17 and the second interlayer dielectric layer 161, the height difference h on the second interlayer dielectric layer 161 remains unchanged during the etching process of the opening 23, thus not affecting the subsequent etching.

[0076] In some embodiments, the method for fabricating the semiconductor structure further includes: filling a contact hole with a metal material and planarizing it to form a contact structure; wherein the metal material covers the metal silicide.

[0077] In some embodiments, such as Figure 15 and Figure 16 As shown, after filling the contact hole 24 with metal material 19, planarization can be performed using CMP process to complete the fabrication of the contact structure 25. Specifically, the metal material 19 can be tungsten, or other conductive metals such as aluminum, copper, etc.

[0078] In some embodiments, since the gap region 32 is covered by the gate sidewall 15, the bottom of the contact hole 24 is a metal silicide 12, and the metal material 19 can make full contact with the metal silicide 12, thereby reducing the contact resistance.

[0079] In some embodiments, the presence of the height difference h can also reduce the amount of metal material 19 being ground during the CMP process. (Reference) Figure 17 and Figure 18 Taking the active region contact hole as an example, Figure 17 This is a schematic diagram of the amount of metal material being ground during the CMP process in related technologies. The amount of grinding is V1 = (H-h1)*S+S*(1-a%)*h1+a%*s*h3. Figure 18 This diagram illustrates the amount of metal material 19 being polished during the CMP process in this embodiment. The polishing amount V2 = (H - h2) * S + S(1 - b%) * h2 + b% * S * h3. Here, a% and b% represent the mask aperture ratio, and S represents the wafer area. Since h2 > h1, b% > a%, and h3 = h2, and the polishing amount difference V1 - V2 = a% * (h2 - h1) * S > 0, the amount of metal material 19 being polished during the CMP process in the semiconductor structure fabrication method provided in this application is relatively small.

[0080] In some embodiments, an unexpected effect is that by removing the stress layer 14 on the metal silicide 12 in advance and etching the trench 22 on the first interlayer dielectric layer 16 during the etching process of the first interlayer dielectric layer 16, the problem of missing gate sidewall 15 can be avoided when fabricating shared contact holes, and the etching damage to the metal silicide 12 of the gate structure 13 can be reduced, resulting in a significant improvement in the electrical performance and reliability of the fabricated contact hole 24 and contact structure 25.

[0081] An embodiment of this application also provides a semiconductor structure, which is prepared using the semiconductor structure preparation method as described in any of the foregoing embodiments.

[0082] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of the invention.

[0083] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0084] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0085] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0086] The above description is merely a specific embodiment of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method for preparing the semiconductor structure includes: A substrate is provided; the substrate includes a substrate, a gate structure disposed on the substrate, and sacrificial sidewalls located on both sides of the gate structure; wherein, the substrate and the gate structure are respectively formed with metal silicide; the surface of the substrate has a gap region located between the gate structure and the metal silicide; Based on stress proximity technology, the sacrificial sidewall is removed, and a stress layer is formed on the substrate and the gate structure; wherein the thickness of the stress layer is greater than the width of the gap region; A portion of the stress layer is removed to expose at least a portion of the surface of the metal silicide; the remaining portion of the stress layer forms a gate sidewall; wherein the gap region is covered by the gate sidewall; A first interlayer dielectric layer is disposed on the surfaces of the metal silicide and the gate sidewall; Corresponding to the location of the metal silicide, the first interlayer dielectric layer is etched to create a contact hole.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The gate sidewall is at least partially in direct contact with the metal silicide of the substrate to form a contact region; wherein the width of the contact region falls within the range of 120 Å to 160 Å.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, In the step of etching the first interlayer dielectric layer to form a contact hole at the location corresponding to the metal silicide, the etching selectivity of the first interlayer dielectric layer relative to the gate sidewall falls in the range of 6 to 15.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The step of etching the first interlayer dielectric layer to create a contact hole at the location corresponding to the metal silicide includes: Based on the positions of the gate sidewall and the metal silicide formed on the substrate, trenches are etched on the first interlayer dielectric layer to form a second interlayer dielectric layer; wherein, there is a height difference between the surface of the second interlayer dielectric layer on the metal silicide of the gate structure and the surface of the second interlayer dielectric layer on the metal silicide of the substrate. The second interlayer dielectric layer is etched to form corresponding contact holes at the locations of the metal silicide.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, The depth of the trench falls within the range of 600 Å to 1000 Å.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, The height difference corresponds to the height of the gate structure relative to the substrate.

7. The method for preparing a semiconductor structure according to claim 4, characterized in that, The step of etching the second interlayer dielectric layer to form corresponding contact holes at the locations of the metal silicide includes: An organic dielectric layer and a mask layer are stacked on the second interlayer dielectric layer; Based on the location of the metal silicide, an opening defining the location of the contact hole is formed in the organic dielectric layer and the mask layer using photolithography and etching processes; wherein, during the etching of the organic dielectric layer, the second interlayer dielectric layer is not etched; The second interlayer dielectric layer is etched along the opening to form the contact hole.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The method for preparing the semiconductor structure further includes: The contact hole is filled with a metal material and planarized to form a contact structure; wherein the metal material covers the metal silicide.

9. The method for preparing a semiconductor structure according to any one of claims 1 to 8, characterized in that, The types of contact holes include: shared contact holes; the shared contact holes are located on both the metal silicide of the gate structure and the metal silicide of the substrate.

10. A semiconductor structure, characterized in that, The semiconductor structure is prepared using the semiconductor structure preparation method described in any one of claims 1 to 9.

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