Nitride semiconductor device and method for manufacturing nitride semiconductor device

Abstract

The invention provides a nitride semiconductor device capable of obtaining high withstand voltage and a method for manufacturing the nitride semiconductor device. A nitride semiconductor device includes: a first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis, and having a first surface intersecting the first axis; an insulating layer provided on the first surface and having a second surface facing the first surface and a third surface facing the second surface; and a second nitride semiconductor layer and a third nitride semiconductor layer, in which the channel layer and the barrier layer are disposed between the second nitride semiconductor layer and the third nitride semiconductor layer along a second axis intersecting the first axis, and in which the channel layer and the barrier layer are disposed between the second nitride semiconductor layer and the third nitride semiconductor layer in a cross-section including the first axis and the second axis. The second nitride semiconductor layer has a first covering portion covering a part of the third surface, and the third nitride semiconductor layer has a second covering portion covering a part of the third surface.

Description

Technical Field

[0001] This disclosure relates to nitride semiconductor devices and methods for manufacturing nitride semiconductor devices. Background Technology

[0002] A structure for regrowing nitride semiconductor layers containing high concentrations of impurities has been proposed to reduce contact resistance and other issues in nitride semiconductor devices.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2007-329350

[0006] Patent Document 2: Japanese Patent Publication No. 2007-538402

[0007] In recent years, the demand for higher pressure resistance has been increasing. Summary of the Invention

[0008] The purpose of this disclosure is to provide a nitride semiconductor device with high withstand voltage and a method for manufacturing the nitride semiconductor device.

[0009] The nitride semiconductor device disclosed herein comprises: a first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis, and having a first surface intersecting the first axis; an insulating layer disposed on the first surface, and having a second surface facing the first surface and a third surface facing the second surface; and a second nitride semiconductor layer and a third nitride semiconductor layer, wherein the channel layer and the barrier layer are disposed between the second nitride semiconductor layer and the third nitride semiconductor layer along a second axis intersecting the first axis, wherein, when viewed in a cross-section including the first axis and the second axis, the second nitride semiconductor layer has a first covered portion covering a portion of the third surface, and the third nitride semiconductor layer has a second covered portion covering a portion of the third surface.

[0010] Invention Effects

[0011] According to this disclosure, high pressure resistance can be obtained. Attached Figure Description

[0012] Figure 1 This is a cross-sectional view showing an embodiment of a nitride semiconductor device.

[0013] Figure 2 This is a top view showing the implementation of a nitride semiconductor device.

[0014] Figure 3This is a cross-sectional view (one of the embodiments) showing a method for manufacturing a nitride semiconductor device.

[0015] Figure 4 This is a cross-sectional view (second one) showing a method for manufacturing a nitride semiconductor device according to an embodiment.

[0016] Figure 5 This is a cross-sectional view (third one) showing a method for manufacturing a nitride semiconductor device according to an embodiment.

[0017] Figure 6 This is a cross-sectional view (fourth one) showing a method for manufacturing a nitride semiconductor device according to an embodiment.

[0018] Figure 7 This is a cross-sectional view (fifth) showing a method for manufacturing a nitride semiconductor device according to an embodiment.

[0019] Figure 8 This is a cross-sectional view (sixth) illustrating a method for manufacturing a nitride semiconductor device according to an embodiment.

[0020] Figure 9 This is a cross-sectional view (seventh) showing a method for manufacturing a nitride semiconductor device according to an embodiment.

[0021] Figure 10 This is a cross-sectional view (eighth) showing a method for manufacturing a nitride semiconductor device according to an embodiment.

[0022] Figure 11 This is a cross-sectional view (nine) showing a method for manufacturing a nitride semiconductor device according to an embodiment.

[0023] Figure 12 This is a cross-sectional view (tenth) showing a method for manufacturing a nitride semiconductor device according to an embodiment.

[0024] Figure 13 This is a cross-sectional view (eleventh of the embodiments) showing a method for manufacturing a nitride semiconductor device.

[0025] Figure 14 This is a cross-sectional view (twelfth of twelve) showing a method for manufacturing a nitride semiconductor device according to an embodiment.

[0026] Explanation of reference numerals in the attached figures

[0027] 44D: Drain electrode; 44S: Source electrode; 50: Gate electrode; 100: Nitride semiconductor device; 110: Substrate; 120: First nitride semiconductor layer; 122: Buffer layer; 124: Channel layer; 126: Barrier layer; 128: Cap layer; 130, 170, 172D, 172S: Insulating layers; 130D, 130G, 130S, 170D, 170S, 201, 202: Openings; 140D: Second recess; 1 40S: First recess; 142: Fourth nitride semiconductor layer; 142D: Third nitride semiconductor layer; 142S: Second nitride semiconductor layer; 144D: Second covered portion; 144S: First covered portion; 155: Channel region; 161, 163, 165, 166: Upper surface; 162, 164: Lower surface; 167: Recess; 200, 210D, 210S: Mask; L0: Reference distance; L1, L2: Distance. Detailed Implementation

[0028] [Description of embodiments of this disclosure]

[0029] First, the implementation plan disclosed herein will be listed for explanation.

[0030] [1] A nitride semiconductor device according to one aspect of the present disclosure has: a first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis and having a first surface intersecting the first axis; an insulating layer disposed on the first surface and having a second surface facing the first surface and a third surface facing the second surface; and a second nitride semiconductor layer and a third nitride semiconductor layer, wherein the channel layer and the barrier layer are disposed between the second nitride semiconductor layer and the third nitride semiconductor layer along a second axis intersecting the first axis, wherein, when viewed in a cross section including the first axis and the second axis, the second nitride semiconductor layer has a first covered portion covering a portion of the third surface, and the third nitride semiconductor layer has a second covered portion covering a portion of the third surface.

[0031] During the formation of the second and third nitride semiconductor layers, a nitride semiconductor layer that does not require polycrystalline inclusion is formed on the third surface. The second nitride semiconductor layer has a first coating portion, and the third nitride semiconductor layer has a second coating portion, thereby preventing the etchant from contacting the first nitride semiconductor layer during the removal of the unwanted nitride semiconductor layer. Therefore, the barrier layer and channel layer are not etched, enabling the nitride semiconductor device to achieve high breakdown voltage.

[0032] [2] In [1], the first nitride semiconductor layer may have a fourth surface opposite to the first surface, the first coated portion may have a fifth surface, the distance between the fifth surface and the fourth surface being greater than the reference distance between the first surface and the fourth surface, and the second coated portion may have a sixth surface, the distance between the sixth surface and the fourth surface being greater than the reference distance. In this case, it is easier to prevent the etching of the barrier layer and the channel layer.

[0033] [3] In [2], the distance between the third surface and the fifth surface may also be 10 nm or more and 100 nm or less, and the distance between the third surface and the sixth surface may also be 10 nm or more and 100 nm or less. These distances of 10 nm or more make it easier to prevent etching of the barrier layer and the channel layer. These distances of 100 nm or less make it easier to prevent excessive height differences.

[0034] [4] In any of [1] to [3], the first coated portion and the second coated portion may also be polycrystalline. The polycrystalline nature of the first coated portion and the second coated portion can also prevent the etching of the barrier layer and the channel layer.

[0035] [5] In any of [1] to [4], the first nitride semiconductor layer may also have a cap layer having the first surface. In this case, the barrier layer can be protected from damage by plasma or the like generated during the manufacturing process of the nitride semiconductor device.

[0036] [6] In any of [1] to [5], the length of the first coated portion along the direction of the second axis may be 50 nm or more and 300 nm or less, and the length of the second coated portion along the direction of the second axis may be 50 nm or more and 300 nm or less. These lengths of 50 nm or more make it easier to prevent etching of the barrier layer and the channel layer. These lengths of 300 nm or less make it easier to prevent short circuits between the gate electrode disposed between the second nitride semiconductor layer and the third nitride semiconductor layer.

[0037] [7] In any of [1] to [6], the channel layer may have a channel region containing a two-dimensional electron gas, and the resistance of the second nitride semiconductor layer and the resistance of the third nitride semiconductor layer are lower than the resistance of the channel region. In this case, the resistance between the electrodes disposed on the second nitride semiconductor layer and the third nitride semiconductor layer can be reduced.

[0038] [8] In any of [1] to [7], the second nitride semiconductor layer and the third nitride semiconductor layer may contain n-type impurities. In this case, the second nitride semiconductor layer and the third nitride semiconductor layer are readily made to have low resistance.

[0039] [9] In [8], the concentration of the impurity may also be 1 × 10⁻⁶. 20 cm -3 That's all. In this case, the second and third nitride semiconductor layers are more likely to have particularly low resistance.

[0040]

[10] In any of [1] to [9], the first nitride semiconductor layer may have a first recess and a second recess, with the channel layer and the barrier layer disposed between the first recess and the second recess along the second axis, the second nitride semiconductor layer disposed in the first recess, and the third nitride semiconductor layer disposed in the second recess. In this case, it is easy to form the second nitride semiconductor layer and the third nitride semiconductor layer.

[0041]

[11] Another aspect of the present disclosure describes a method for manufacturing a nitride semiconductor device comprising the following steps: preparing a first nitride semiconductor layer, the first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis, and having a first surface; forming a first insulating layer on the first surface, the first insulating layer having a second surface facing the first surface and a third surface facing the second surface; forming a first opening and a second opening in the first insulating layer, the first opening and the second opening being disposed between the channel layer and the barrier layer along a second axis intersecting the first axis when viewed from above; forming a first recess and a second recess in the first nitride semiconductor layer, the first recess being connected to the first opening and the second recess being connected to the second opening; and sputtering the first recess and the first opening, and the second recess and the second opening. A fourth nitride semiconductor layer is formed on the first insulating layer, the fourth nitride semiconductor layer comprising polycrystalline material on the first insulating layer; a second insulating layer and a third insulating layer are formed on the fourth nitride semiconductor layer, the second insulating layer covering portions of the first recess and the first opening of the fourth nitride semiconductor layer and portions of a portion of the first insulating layer, the third insulating layer covering portions of the second recess and the second opening of the fourth nitride semiconductor layer and portions of a portion of the first insulating layer; and portions of the fourth nitride semiconductor layer exposed from the second insulating layer and the third insulating layer are removed to form a second nitride semiconductor layer and a third nitride semiconductor layer, the second nitride semiconductor layer having a first covered portion covering a portion of the third surface, and the third nitride semiconductor layer having a second covered portion covering a portion of the third surface.

[0042] As described above, the etchant does not come into contact with the first nitride semiconductor layer when removing unwanted nitride semiconductor layers. Therefore, the barrier layer and channel layer are not etched, and the nitride semiconductor device can achieve high breakdown voltage.

[0043] [Details of the embodiments of this disclosure]

[0044] The embodiments of this disclosure will now be described in detail, but this disclosure is not limited to these embodiments. It should be noted that in this specification and accompanying drawings, sometimes repeated descriptions are omitted by using the same reference numerals to denote constituent elements that have substantially the same functional configuration. Furthermore, in the following description, the XYZ Cartesian coordinate system is used, but this coordinate system is set for illustrative purposes and is not intended to limit the orientation of the nitride semiconductor device. Additionally, the XY plane view is referred to as a top view; when viewed from any point, the +Z direction is sometimes referred to as above, upper side, or up, and the -Z direction is sometimes referred to as below, lower side, or down.

[0045] Embodiments of this disclosure relate to a nitride semiconductor device including a high electron mobility transistor (HEMT). Figure 1 This is a cross-sectional view showing an embodiment of a nitride semiconductor device. Figure 2 This is a top view showing the implementation of a nitride semiconductor device. Figure 1 Equivalent to along Figure 2 A sectional view of line I-I in the diagram.

[0046] like Figure 1 and Figure 2 As shown, the nitride semiconductor device 100 of the embodiment includes a substrate 110, a first nitride semiconductor layer 120, a second nitride semiconductor layer 142S, a third nitride semiconductor layer 142D, an insulating layer 130, a gate electrode 50, a source electrode 44S, a drain electrode 44D, an insulating layer 172S, and an insulating layer 172D.

[0047] The substrate 110 is, for example, a substrate for growing a gallium nitride (GaN) semiconductor layer, such as a semi-insulating silicon carbide (SiC) substrate. When the substrate 110 is a SiC substrate, its upper surface is a silicon (Si) polar surface. When the surface of the substrate 110 is a Si polar surface, the first nitride semiconductor layer 120 is grown using the gallium (Ga) polar surface as its growth surface.

[0048] The first nitride semiconductor layer 120 has a buffer layer 122, a channel layer 124, a barrier layer 126, and a cap layer 128. The buffer layer 122, channel layer 124, barrier layer 126, and cap layer 128 overlap along the Z-axis in the order described above. The first nitride semiconductor layer 120 has an upper surface 161 and a lower surface 164 intersecting the Z-axis. The upper surface 161 is present in the cap layer 128. The Z-axis is an example of a first axis. The upper surface 161 is an example of a first surface, and the lower surface 164 is an example of a fourth surface opposite to the first surface.

[0049] A buffer layer 122 is located above the substrate 110. The buffer layer 122 is, for example, an aluminum nitride (AlN) layer. The buffer layer 122 may also have an AlN layer and a GaN layer or an aluminum gallium nitride (AlGaN) layer above the AlN layer. A channel layer 124 is located above the buffer layer 122. The channel layer 124 is, for example, an undoped gallium nitride (GaN) layer. A barrier layer 126 is located above the channel layer 124. The barrier layer 126 is, for example, an n-type AlGaN layer. A channel region 155 containing a two-dimensional electron gas (2DEG) exists near the upper surface of the channel layer 124. A cap layer 128 is located above the barrier layer 126. The cap layer 128 is, for example, an n-type GaN layer.

[0050] A first recess 140S for the active electrode and a second recess 140D for the drain electrode are formed in a portion of the cap layer 128, the barrier layer 126, and the channel layer 124. The first recess 140S and the second recess 140D penetrate the cap layer 128 and the barrier layer 126 along the Z-axis and enter the channel layer 124. The channel layer 124 is exposed from the first recess 140S and the second recess 140D.

[0051] An insulating layer 130 is located above the cap layer 128. The insulating layer 130 is, for example, a silicon nitride (SiN) film. The thickness of the insulating layer 130 is, for example, 1 nm or more and 20 nm or less. The insulating layer 130 has an upper surface 163 and a lower surface 162 intersecting the Z-axis. An opening 130S for an active electrode and an opening 130D for a drain electrode are formed in the insulating layer 130. The opening 130S is connected to a first recess 140S, and the opening 130D is connected to a second recess 140D. The opening 130D is located on the +X side of the opening 130S. The lower surface 162 is an example of a second surface, and the upper surface 163 is an example of a third surface opposite to the second surface. The X-axis is an example of a second axis.

[0052] The second nitride semiconductor layer 142S is located above the channel layer 124 within the first recess 140S and opening 130S. When viewing a ZX section including the Z-axis and X-axis, the second nitride semiconductor layer 142S has a first covered portion 144S covering a portion of the upper surface 163. The first covered portion 144S may also contain polycrystalline material. The first covered portion 144S has an upper surface 165. Alternatively, the distance between the upper surface 165 and the lower surface 164 of the first nitride semiconductor layer 120 may be greater than the reference distance L0 between the upper surface 161 and the lower surface 164 of the first nitride semiconductor layer 120. It should be noted that, if the distance between the upper surface 161 and the lower surface 164 varies depending on their respective flatness according to their positions in the X-axis direction and Y-axis direction, the reference distance L0 may be set to the maximum value estimated from the distance values ​​at multiple different positions. For example, if the flatness of the upper surface 161 and the lower surface 164 is good, such that the difference between the average and maximum values ​​of the distance at multiple different locations is less than 0.5 nm, then the reference distance L0 can be set as this average value. The second nitride semiconductor layer 142S is in contact with the sidewalls of the opening 130S and the sidewalls of the first recess 140S. The upper surface 165 is an example of a fifth surface.

[0053] The third nitride semiconductor layer 142D lies above the channel layer 124 within the second recess 140D and the opening 130D. When viewed in a ZX section including the Z and X axes, the third nitride semiconductor layer 142D has a second covered portion 144D covering a portion of the upper surface 163. The second covered portion 144D may also contain polycrystalline material. The second covered portion 144D has an upper surface 166. Alternatively, the distance between the upper surface 166 and the lower surface 164 of the first nitride semiconductor layer 120 may be greater than the reference distance L0 between the upper surface 161 and the lower surface 164 of the first nitride semiconductor layer 120. The third nitride semiconductor layer 142D contacts the sidewalls of the opening 130D and the second recess 140D. The upper surface 166 is an example of a sixth surface.

[0054] The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are disposed along the X-axis between the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are, for example, n-type GaN layers. The resistance of the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D is lower than the resistance of the channel region 155.

[0055] An insulating layer 172S is located above the second nitride semiconductor layer 142S. The insulating layer 172S covers the upper surface 165 of the first coated portion 144S. An insulating layer 172D is located above the third nitride semiconductor layer 142D. The insulating layer 172D covers the upper surface 166 of the second coated portion 144D. The insulating layers 172S and 172D are, for example, silicon nitride (SiN) films. The thickness of the insulating layers 172S and 172D is, for example, 5 nm or more and 20 nm or less. An opening 170S for an active electrode is formed in the insulating layer 172S. The opening 170S reaches the second nitride semiconductor layer 142S. That is, the second nitride semiconductor layer 142S is exposed from the opening 170S. An opening 170D for a drain electrode is formed in the insulating layer 172D. The opening 170D reaches the third nitride semiconductor layer 142D. That is, the third nitride semiconductor layer 142D is exposed from the opening 170D. For example, the opening 170S is away from the first coated portion 144S, and the opening 170D is away from the second coated portion 144D.

[0056] The source electrode 44S is located inside the opening 170S, above the second nitride semiconductor layer 142S, and the drain electrode 44D is located inside the opening 170D, above the third nitride semiconductor layer 142D. The source electrode 44S is in direct contact with the second nitride semiconductor layer 142S, and the drain electrode 44D is in direct contact with the third nitride semiconductor layer 142D. The source electrode 44S has an ohmic contact with the second nitride semiconductor layer 142S, and the drain electrode 44D has an ohmic contact with the third nitride semiconductor layer 142D.

[0057] An opening 130G for a gate is formed in the insulating layer 130. The opening 130G is located along the X-axis between openings 130S and 130D. The gate electrode 50 is disposed on the insulating layer 130 and makes a Schottky contact with the first nitride semiconductor layer 120 via the opening 130G. The current flowing between the drain electrode 44D and the source electrode 44S via the channel region 155 varies according to the voltage applied to the gate electrode 50.

[0058] Next, the manufacturing method of the nitride semiconductor device 100 according to the embodiment will be described. Figures 3 to 14 This is a cross-sectional view showing a method for manufacturing a nitride semiconductor device 100 according to an embodiment. Figures 11 to 14 The images are enlarged and shown separately. Figures 6 to 9 Part of it.

[0059] First, such as Figure 3 As shown, a buffer layer 122, a channel layer 124, a barrier layer 126, and a cap layer 128 are formed on a substrate 110. The buffer layer 122, channel layer 124, barrier layer 126, and cap layer 128 can be formed, for example, by metal-organic chemical vapor deposition (MOCVD). Next, an insulating layer 130 is formed on the cap layer 128. The insulating layer 130 can be formed, for example, by CVD (chemical vapor deposition). In this way, a first nitride semiconductor layer 120 is obtained. The insulating layer 130 is an example of a first insulating layer.

[0060] Next, as Figure 4 As shown, a mask 200 is formed on the insulating layer 130. The mask 200 has an opening 201 for a first recess 140S and an opening 202 for a second recess 140D. For example, the mask 200 is formed of a photoresist.

[0061] Next, as Figure 5As shown, the insulating layer 130 is etched via openings 201 and 202 to form openings 130S connected to opening 201 and 130D connected to opening 202 in the insulating layer 130. For example, the etching of the insulating layer 130 is performed under conditions where lateral etching is unlikely. When viewed from above along the Z-axis, opening 130S is formed to be the same size as opening 201, and opening 130D is formed to be the same size as opening 202. For example, in the X-axis direction, the edge of opening 130S on the +X side coincides with the edge of opening 201 on the +X side, and the edge of opening 130D on the -X side coincides with the edge of opening 202 on the -X side. However, these edges do not need to be perfectly aligned; manufacturing errors or predetermined deviations are permissible. Openings 130S and 130D can be formed, for example, by using reactive ion etching (RIE) with a fluorine (F)-containing reactive gas. Opening 130S is an example of a first opening, and opening 130D is an example of a second opening.

[0062] Next, the first nitride semiconductor layer 120 is etched through openings 201 and 202 to form a first recess 140S connected to opening 130S and a second recess 140D connected to opening 130D. A portion of the channel layer 124 and a barrier layer 126 are disposed between the first recess 140S and the second recess 140D along the X-axis. The first recess 140S and the second recess 140D can be formed, for example, using a reactive etchant (RIE) containing chlorine (Cl). For example, the angle between the sidewalls of the first recess 140S and the sidewalls of the second recess 140D and the upper surface 161 of the first nitride semiconductor layer 120 is approximately 90 degrees. It should be noted that... Figure 5 In the ZX cross section shown in the figure, the angles formed by the sidewall of the first recess 140S and the upper surface 161 of the first nitride semiconductor layer 120, and the angles formed by the sidewall of the second recess 140D and the upper surface 161 of the first nitride semiconductor layer 120, can also be greater than 90 degrees.

[0063] Next, as Figure 6As shown, mask 200 is removed. Next, a fourth nitride semiconductor layer 142, which becomes the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D, is formed. The fourth nitride semiconductor layer 142 can be formed, for example, by sputtering. When the fourth nitride semiconductor layer 142 is formed by sputtering, nitrogen radicals can be continuously supplied while Ga and n-type impurities are intermittently supplied. The fourth nitride semiconductor layer 142 is formed in the first recess 140S and the opening 130S, in the second recess 140D and the opening 130D, and on the insulating layer 130. The portion within the first recess 140S and the opening 130S of the fourth nitride semiconductor layer 142 is epitaxially grown and contains a single crystal. The portion within the second recess 140D and the opening 130D of the fourth nitride semiconductor layer 142 is also epitaxially grown and contains a single crystal. The fourth nitride semiconductor layer 142 is in contact with the channel layer 124 at the bottom of the first recess 140S and the second recess 140D. On the other hand, the portion above the insulating layer 130 is not epitaxially grown and contains polycrystalline material.

[0064] In the case where the fourth nitride semiconductor layer 142 is formed by sputtering, such as Figure 11 As shown, sometimes a recess 167 is formed inside the opening 130S, near the sidewall of the opening 130S on the upper surface of the fourth nitride semiconductor layer 142. Similarly, sometimes a recess 167 is formed inside the opening 130D, near the sidewall of the opening 130D on the upper surface of the fourth nitride semiconductor layer 142. This is because a portion of the material flow ejected from the target is blocked by the fourth nitride semiconductor layer 142 already formed on the insulating layer 130. Furthermore, when observing the ZX cross-section, the shape and size of the recess 167 are not uniform along the Y-axis direction.

[0065] Next, as Figure 7 and Figure 12 As shown, an insulating layer 170 is formed on the fourth nitride semiconductor layer 142. The insulating layer 170 can be formed, for example, by CVD. The insulating layer 170 covers the recess 167.

[0066] Next, as Figure 8 and Figure 13As shown, masks 210S and 210D are formed on insulating layer 170. Mask 210S covers the area where insulating layer 172S is formed, and mask 210D covers the area where insulating layer 172D is formed. Mask 210S covers at least the edge of cap layer 128 on the -X side, and mask 210D covers at least the edge of cap layer 128 on the +X side. For example, masks 210S and 210D are formed using photoresist. For example, masks 210S and 210D are formed using photoresist similarly formed on insulating layer 170 in a manner that removes portions other than masks 210S and 210D by patterning. Next, the portions of insulating layer 170 exposed from masks 210S and 210D are etched to form insulating layer 172S and insulating layer 172D from insulating layer 170. The insulating layer 172S covers portions within the first recess 140S and opening 130S of the fourth nitride semiconductor layer 142, as well as portions on a portion of the insulating layer 130. The insulating layer 172D covers portions within the second recess 140D and opening 130D of the fourth nitride semiconductor layer 142, as well as portions on a portion of the insulating layer 130. Etching of the insulating layer 170 may be performed, for example, using a reactive gas containing fluorine (F) via RIE. Wet etching using buffered hydrofluoric acid may also be performed as etching of the insulating layer 170. The insulating layer 172S is an example of a second insulating layer, and the insulating layer 172D is an example of a third insulating layer.

[0067] Next, as Figure 9 As shown, masks 210S and 210D are removed. Next, the portion of the fourth nitride semiconductor layer 142 exposed from insulating layers 172S and 172D is removed, forming a second nitride semiconductor layer 142S and a third nitride semiconductor layer 142D from the fourth nitride semiconductor layer 142. The second nitride semiconductor layer 142S has a first covered portion 144S covering a portion of its upper surface 163, and the third nitride semiconductor layer 142D has a second covered portion 144D covering a portion of its upper surface 163. The portion of the fourth nitride semiconductor layer 142 exposed from insulating layers 172S and 172D, as described above, contains polycrystalline material. This portion can be removed, for example, using an alkaline etchant such as tetramethylammonium hydroxide (TMAH). The temperature of TMAH is, for example, 70°C or higher and 80°C or lower.

[0068] like Figure 14 As shown, when forming the second nitride semiconductor layer 142S, the recess 167 inside the opening 130S is covered by the insulating layer 172S. Similarly, when forming the third nitride semiconductor layer 142D, the recess 167 inside the opening 130D is covered by the insulating layer 172D.

[0069] Next, as Figure 10As shown, an opening 170S is formed in the insulating layer 172S, and an opening 170D is formed in the insulating layer 172D. The openings 170S and 170D can be formed, for example, using a reactive ion exchange (RIE) containing fluorine (F). Next, a source electrode 44S is formed inside the opening 170S on the second nitride semiconductor layer 142S, and a drain electrode 44D is formed inside the opening 170D on the third nitride semiconductor layer 142D. The source electrode 44S and drain electrode 44D can be formed, for example, by vapor deposition and stripping. The source electrode 44S is connected to the second nitride semiconductor layer 142S, and the drain electrode 44D is connected to the third nitride semiconductor layer 142D.

[0070] Next, an opening 130G is formed in the insulating layer 130. The opening 130G can be formed, for example, using a reactive ion exchange (RIE) containing fluorine (F). Next, a gate electrode 50 (see reference 130G) is formed on the insulating layer 130, which makes a Schottky contact with the first nitride semiconductor layer 120 via the opening 130G. Figure 1 ).

[0071] In this way, the nitride semiconductor device 100 of the embodiment can be manufactured.

[0072] In this embodiment, the second nitride semiconductor layer 142S has a first coated portion 144S, and the third nitride semiconductor layer 142D has a second coated portion 144D. Therefore, the removal (wet etching) of a portion of the fourth nitride semiconductor layer 142 used to form the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D is completed before the openings 130S and 130D are exposed. Therefore, the etchant such as TMAH used for wet etching does not reach the sidewalls of the openings 130S and 130D.

[0073] When the etchant reaches the sidewalls of openings 130S and 130D, the low-crystallinity portion near the recess 167 may be slightly etched. If the low-crystallinity portion contained in the second nitride semiconductor layer 142S is slightly etched, the cap layer 128 and the barrier layer 126 may be etched depending on the shape and size of the recess 167 when observing the ZX cross-section. Similarly, if the low-crystallinity portion contained in the third nitride semiconductor layer 142D is slightly etched, the cap layer 128 and the barrier layer 126 may be etched depending on the shape and size of the recess 167 when observing the ZX cross-section. Furthermore, the degree of etching of the barrier layer 126 is non-uniform along the Y-axis direction. Therefore, the concentration of 2DEG is non-uniform along the Y-axis direction, and the current tends to concentrate in the portion with high 2DEG concentration and low resistance. As a result, the breakdown voltage decreases.

[0074] In this embodiment, as described above, the etchant does not reach the sidewalls of opening 130S and opening 130D, and the etchant does not contact the first nitride semiconductor layer 120. Therefore, the cap layer 128, the barrier layer 126, and the channel layer 124 are not etched, and the nitride semiconductor device 100 can achieve high withstand voltage.

[0075] The distance between the upper surface 165 and the lower surface 164 is greater than the reference distance L0 between the upper surface 161 and the lower surface 164 of the first nitride semiconductor layer 120, thereby facilitating the prevention of etching of the barrier layer 126 and the channel layer 124 near the second nitride semiconductor layer 142S. The distance between the upper surface 166 and the lower surface 164 is greater than the reference distance L0 between the upper surface 161 and the lower surface 164 of the first nitride semiconductor layer 120, thereby facilitating the prevention of etching of the barrier layer 126 and the channel layer 124 near the third nitride semiconductor layer 142D.

[0076] The distance L1 between the upper surface 163 and the upper surface 165 is, for example, 10 nm or more and 100 nm or less. A distance L1 of 10 nm or more facilitates the prevention of etching of the barrier layer 126 and the channel layer 124 near the second nitride semiconductor layer 142S. Furthermore, a distance L1 of 100 nm or less facilitates the prevention of excessive height differences associated with the first coated portion 144S. The distance L1 can be 20 nm or more and 90 nm or less, or 30 nm or more and 80 nm or less.

[0077] The distance L2 between the upper surface 163 and the upper surface 166 is, for example, 10 nm or more and 100 nm or less. A distance L2 of 10 nm or more facilitates the prevention of etching of the barrier layer 126 and the channel layer 124 near the third nitride semiconductor layer 142D. Furthermore, a distance L2 of 100 nm or less facilitates the prevention of excessive height differences associated with the second coated portion 144D. The distance L2 can be 20 nm or more and 90 nm or less, or 30 nm or more and 80 nm or less.

[0078] The first nitride semiconductor layer 120 has a cap layer 128 with an upper surface 161, thereby protecting the barrier layer 126 from damage caused by plasma or the like generated during the manufacturing process of the nitride semiconductor device 100.

[0079] The length W1 of the first coated portion 144S in the X-axis direction is, for example, 50 nm or more and 300 nm or less. A length W1 of 50 nm or more facilitates the prevention of etching of the barrier layer 126 and the channel layer 124 near the second nitride semiconductor layer 142S. The length W1 is the X-axis length of the portion of the first coated portion 144S that is in contact with the upper surface 163 of the insulating layer 130, excluding the X-axis length of the portion of the first coated portion 144S that is not in contact with the upper surface 163 of the insulating layer 130. The length W1 can be set independently of the distance L1 between the upper surface 163 and the upper surface 165. Furthermore, a length W1 of 300 nm or less facilitates the prevention of short circuits between the gate electrode 50 and the second nitride semiconductor layer 142S. The length W1 can be 70 nm or more and 280 nm or less, or 100 nm or more and 250 nm or less.

[0080] The length W2 of the second coated portion 144D in the X-axis direction is, for example, 50 nm or more and 300 nm or less. A length W2 of 50 nm or more facilitates the prevention of etching of the barrier layer 126 and the channel layer 124 near the third nitride semiconductor layer 142D. The length W2 is the X-axis length of the portion of the second coated portion 144D that is in contact with the upper surface 163 of the insulating layer 130, excluding the X-axis length of the portion of the second coated portion 144D that is not in contact with the upper surface 163 of the insulating layer 130. The length W2 can be set independently of the distance L2 between the upper surface 163 and the upper surface 166. Furthermore, a length W2 of 300 nm or less facilitates the prevention of short circuits between the gate electrode 50 and the third nitride semiconductor layer 142D. The length W2 can be 70 nm or more and 280 nm or less, or 100 nm or more and 250 nm or less. The lengths W1 and W2 can be equal or different.

[0081] The resistance of the second nitride semiconductor layer 142S and the resistance of the third nitride semiconductor layer 142D are lower than the resistance of the channel region 155, thereby reducing the resistance between the source electrode 44S and the drain electrode 44D.

[0082] The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D contain n-type impurities, thereby easily achieving low resistance in the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D. The n-type impurities are not limited to germanium (Ge) and can also be silicon (Si). The concentration of the n-type impurities is, for example, 1 × 10⁻⁶. 20 cm -3 The above. The concentration of n-type impurities is 1×10⁻⁶. 20 cm -3 Therefore, the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D can easily achieve particularly low resistance. The concentration of n-type impurities can be 5 × 10⁻⁶.20 cm -3 The above can also be 1×10 21 cm -3 The above. The concentration of n-type impurities is 1×10⁻⁶. 20 cm -3 The second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D can be formed, for example, by sputtering, but are difficult to form by MOCVD. The concentration of n-type impurities can be determined by secondary ion mass spectrometry (SIMS).

[0083] When the second nitride semiconductor layer 142S is disposed in the first recess 140S and the third nitride semiconductor layer 142D is disposed in the second recess 140D, the second nitride semiconductor layer 142S and the third nitride semiconductor layer 142D are easily formed.

[0084] An insulating layer 130 is disposed on the upper surface 161 and contacts the first covered portion 144S and the second covered portion 144D, thereby protecting the first nitride semiconductor layer 120 through the insulating layer 130.

[0085] The embodiments have been described in detail above, but this disclosure is not limited to specific embodiments, and various modifications and alterations can be made within the scope of the claims.

Claims

1. A nitride semiconductor device, comprising: The first nitride semiconductor layer includes a channel layer and a barrier layer overlapping along a first axis, and has a first surface intersecting the first axis; An insulating layer is disposed on the first surface and has a second surface facing the first surface and a third surface facing the second surface; as well as A second nitride semiconductor layer and a third nitride semiconductor layer are provided, with the channel layer and the barrier layer disposed between the second nitride semiconductor layer and the third nitride semiconductor layer along a second axis intersecting the first axis. When observing the cross-section including the first axis and the second axis, The second nitride semiconductor layer has a first coating portion covering a portion of the third surface. The third nitride semiconductor layer has a second covered portion that covers a portion of the third surface.

2. The nitride semiconductor device according to claim 1, wherein, The first nitride semiconductor layer has a fourth side opposite to the first side. The first covered portion has a fifth surface, and the distance between the fifth surface and the fourth surface is greater than the reference distance between the first surface and the fourth surface. The second covering portion has a sixth surface, and the distance between the sixth surface and the fourth surface is greater than the reference distance.

3. The nitride semiconductor device according to claim 2, wherein, The distance between the third surface and the fifth surface is greater than 10 nm and less than 100 nm. The distance between the third surface and the sixth surface is greater than 10 nm and less than 100 nm.

4. The nitride semiconductor device according to any one of claims 1 to 3, wherein, The first coated portion and the second coated portion contain polycrystalline material.

5. The nitride semiconductor device according to any one of claims 1 to 3, wherein, The first nitride semiconductor layer has a cap layer having the first surface.

6. The nitride semiconductor device according to any one of claims 1 to 3, wherein, The length of the first coated portion along the direction of the second axis is 50 nm or more and 300 nm or less. The length of the second covered portion along the direction of the second axis is more than 50 nm and less than 300 nm.

7. The nitride semiconductor device according to any one of claims 1 to 3, wherein, The channel layer has a channel region containing a two-dimensional electron gas. The resistance of the second nitride semiconductor layer and the resistance of the third nitride semiconductor layer are lower than the resistance of the channel region.

8. The nitride semiconductor device according to any one of claims 1 to 3, wherein, The second nitride semiconductor layer and the third nitride semiconductor layer contain n-type impurities.

9. The nitride semiconductor device according to claim 8, wherein, The concentration of the impurity is 1×10 20 cm -3 above.

10. The nitride semiconductor device according to any one of claims 1 to 3, wherein, A first recess and a second recess are formed in the first nitride semiconductor layer, and the channel layer and the barrier layer are disposed between the first recess and the second recess along the second axis. The second nitride semiconductor layer is disposed in the first recess. The third nitride semiconductor layer is disposed in the second recess.

11. A method for manufacturing a nitride semiconductor device, comprising the following steps: Prepare a first nitride semiconductor layer, the first nitride semiconductor layer including a channel layer and a barrier layer overlapping along a first axis, and having a first surface; A first insulating layer is formed on the first surface, the insulating layer having a second surface facing the first surface and a third surface facing the second surface; A first opening and a second opening are formed in the first insulating layer, and the trench layer and the barrier layer are disposed between the first opening and the second opening along a second axis intersecting the first axis when viewed from above. A first recess and a second recess are formed in the first nitride semiconductor layer, wherein the first recess is connected to the first opening and the second recess is connected to the second opening; A fourth nitride semiconductor layer is formed in the first recess and the first opening, the second recess and the second opening, and on the first insulating layer by sputtering. The fourth nitride semiconductor layer contains polycrystalline material on the first insulating layer. A second insulating layer and a third insulating layer are formed on the fourth nitride semiconductor layer. The second insulating layer covers the portion of the first recess and the first opening of the fourth nitride semiconductor layer and a portion of the first insulating layer. The third insulating layer covers the portion of the second recess and the second opening of the fourth nitride semiconductor layer and a portion of the first insulating layer. as well as The portion of the fourth nitride semiconductor layer exposed from the second insulating layer and the third insulating layer is removed to form a second nitride semiconductor layer and a third nitride semiconductor layer. The second nitride semiconductor layer has a first covered portion covering a portion of the third surface, and the third nitride semiconductor layer has a second covered portion covering a portion of the third surface.

Images