Semiconductor structure

Abstract

The invention discloses a semiconductor structure. The semiconductor structure includes a substrate, a first well region, a second well region, a third well region, an isolation structure, a drain region, a source region and a gate structure. The first well region is in the substrate and has a first side surface. The second well region is in the substrate and has a second side surface. The third well region is in the substrate. The second well region is arranged between the first well region and the third well region. The isolation structure is in the substrate and between the first well region and the second well region. The drain region is in the first well region. The source region is in the third well region. The gate structure is on the substrate. A first side surface of the first well region faces a second side surface of the second well region. A first side surface of the first well region is separated from a second side surface of the second well region.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more particularly to metal-oxide-semiconductor structures. Background Technology

[0002] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are among the most widely used transistors in integrated circuits today. MOSFETs can be classified into three types based on their structure: planar MOSFETs, laterally diffused MOSFETs (LDMOS), and vertically diffused MOSFETs. Compared to the other two types, LDMOS can provide more current per unit area because its asymmetric structure provides a short channel between the drain and source. In existing LDMOS designs, the breakdown voltage is typically increased by reducing the doping concentration of the N-type well and / or P-type well regions beneath the isolation structure. However, reducing the doping concentration of the N-type well and / or P-type well regions requires more photomasks and more fabrication steps, resulting in high manufacturing costs and incompatibility with other fabrication processes, and the breakdown voltage is still insufficient to meet requirements. Summary of the Invention

[0003] The present invention provides a semiconductor structure in which a first side surface of a first well region and a second side surface of a second well region are separated to achieve a higher breakdown voltage.

[0004] According to some embodiments, a semiconductor structure is provided. The semiconductor structure includes a substrate, a first well region, a second well region, a third well region, an isolation structure, a drain region, a source region, and a gate structure. The first well region is in the substrate and has a first side surface. The second well region is in the substrate and has a second side surface. The third well region is in the substrate. The second well region is located between the first well region and the third well region. The isolation structure is in the substrate and is located between the first well region and the second well region. The drain region is in the first well region. The source region is in the third well region. The gate structure is on the substrate. The first side surface of the first well region faces the second side surface of the second well region. The first side surface of the first well region and the second side surface of the second well region are separated.

[0005] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0006] Figure 1 These are schematic diagrams of semiconductor structures in some embodiments;

[0007] Figure 2 These are schematic diagrams of semiconductor structures in some embodiments;

[0008] Figure 3 These are schematic diagrams of semiconductor structures in some embodiments;

[0009] Figure 4 These are schematic diagrams of semiconductor structures in some embodiments;

[0010] Figure 5 Schematic diagrams of semiconductor structures for some embodiments; and

[0011] Figure 6A and Figure 6B These are test results for semiconductor structures in some embodiments.

[0012] Symbol Explanation

[0013] 10, 20, 30, 40, 60: Transistor structure

[0014] 100:Substrate

[0015] 101: First Trap Zone

[0016] 101L, 102L, 121L, 502L, 521L: Lower surface

[0017] 101S, 101SS, 102S, 502S: Side surface

[0018] 102,502: Second trap region

[0019] 103,503: Third well region

[0020] 121,122,521,522: Isolation structure

[0021] 121S1, 121S2, 521S1, 521S2: Sidewall

[0022] 121-1, 521-1: Part One

[0023] 121-2, 521-2: Part Two

[0024] 121-3, 521-3: Part Three

[0025] 141: Drain region

[0026] 142,542: Source Region

[0027] 143,543: Doped region

[0028] 145,545: Gate structure

[0029] 160: Current path

[0030] G1, G2, G3, G4: Distance

[0031] H1, H2, H3, H4, H5, H6, H7, H8, H9: Depth Detailed Implementation

[0032] The accompanying drawings are simplified to clearly illustrate the embodiments, and the dimensions in the drawings are not drawn to scale with the actual product. In the following manufacturing methods, one or more additional operations may be present between the operations, and the order of the operations may vary. Therefore, the specification and drawings are for illustrative purposes only and are not intended to limit the scope of protection of the invention. The following description uses the same / similar symbols to denote the same / similar elements.

[0033] The ordinal numbers used to modify elements in the specification and claims, such as "first," "second," etc., do not imply or represent a specific position, arrangement, or manufacturing order in the structure; these ordinal numbers are merely used to clearly distinguish multiple elements with the same name. Spatial terms used in the specification and claims, such as "above," "over," "above," "higher than," "top," "below," "below," "below," "lower than," "bottom," etc., describe the relative spatial or positional relationship between one element and another in the drawings, and these spatial or positional relationships can be direct or indirect (with other elements disposed between the two elements), unless otherwise specified. Spatial terms may cover structures shown in other orientations, not limited to those shown in the drawings. Structures can be flipped or rotated at various angles, and the spatial terms used herein can be interpreted accordingly. The singular forms "a" and "the" used in the specification and claims are also intended to include the plural forms, unless the context clearly indicates otherwise. The word "and / or" as used in the specification and claims includes any and all combinations of one or more of the listed items. The term "adjacent" as used in the specification and appended claims means "adjacent and in contact".

[0034] Please refer to Figure 1 . Figure 1This is a schematic diagram illustrating a semiconductor structure according to some embodiments. The semiconductor structure includes a transistor structure 10. The transistor structure 10 may be a laterally diffused MOSFET. The transistor structure 10 includes a substrate 100, a first well region 101, a second well region 102, a third well region 103, an isolation structure 121, a drain region 141, a source region 142, and a gate structure 145. The substrate 100 may be formed of a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, germanium, diamond, gallium arsenide, silicon carbide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, or any combination thereof. The substrate 100 includes dopants, such as electron donors or electron acceptors. Depending on the type of dopants, the substrate 100 may have a first conductivity type or a second conductivity type different from the first conductivity type. For example, the first conductivity type is N-type, and the second conductivity type is P-type. A substrate 100 having a first conductivity type can be used for a P-type laterally diffused MOSFET. The substrate 100 having a second conductivity type can be used in an N-type laterally diffused MOSFET. The present invention is described below using a substrate 100 having a second conductivity type (P-type) and an N-type laterally diffused MOSFET as an example, but the present invention can also be applied to P-type laterally diffused MOSFETs.

[0035] A first well region 101 is located in the substrate 100. A dopant can be implanted into the substrate 100 to form the first well region 101. The first well region 101 has a first conductivity type. A second well region 102 is located in the substrate 100. A dopant can be implanted into the substrate 100 to form the second well region 102. The second well region 102 has a first conductivity type. A third well region 103 is located in the substrate 100. A dopant can be implanted into the substrate 100 to form the third well region 103. The third well region 103 has a second conductivity type. The second well region 102 is located between the first well region 101 and the third well region 103. The second well region 102 is adjacent to the third well region 103. Because the conductivity type of the second well region 102 is different from the conductivity type of the third well region 103, a PN junction (P-N junction) is formed at the contact interface between the second well region 102 and the third well region 103. Because the conductivity type of the first well region 101 is different from the conductivity type of the substrate 100, a PN junction is formed at the contact interface between the first well region 101 and the substrate. Because the conductivity type of the second well region 102 is different from that of the substrate 100, a PN junction is formed at the contact interface between the second well region 102 and the substrate. An isolation structure 121 is located in the substrate 100 and lies between the first well region 101 and the second well region 102. The isolation structure 121 separates the first well region 101 and the second well region 102 from each other. The isolation structure 121 is, for example, a shallow trench isolation (STI) structure. A portion of the first well region 101 extends below the isolation structure 121. A portion of the second well region 102 extends below the isolation structure 121.

[0036] Drain region 141 is located in first well region 101. Dopant can be implanted into first well region 101 to form drain region 141. Drain region 141 has a first conductivity type. The doping concentration of drain region 141 may be higher than the doping concentration of first well region 101 and second well region 102. Source region 142 is located in third well region 103. Dopant can be implanted into third well region 103 to form source region 142. Source region 142 has a first conductivity type. The doping concentration of source region 142 may be higher than the doping concentration of first well region 101 and second well region 102. Gate structure 145 is on the substrate and located between drain region 141 and source region 142. Gate structure 145 may include a gate dielectric film and a gate electrode film above the gate dielectric film. Gate electrode film may include a single layer or multiple layers. Gate structure 145 may partially overlap third well region 103 and isolation structure 121 in the longitudinal direction. The gate structure 145 may overlap or partially overlap the second well region 102 in the longitudinal direction. In some embodiments, the gate structure 145 is closer to the source region 142 than the drain region 141.

[0037] The transistor structure 10 may further include a doped region 143 and an isolation structure 122 within a third well region 103. The isolation structure 122 is situated between the doped region 143 and the source region 142. The isolation structure 122 separates the doped region 143 from the source region 142. The doped region 143 can be formed by implanting dopant into the third well region 103. The doped region 143 has a second conductivity type. The doping concentration of the doped region 143 may be higher than the doping concentration of the third well region 103. The third well region 103 may cover the lower surface of the isolation structure 122. The doped region 143 may be the base (body) region of a laterally diffused MOSFET. The isolation structure 122 is, for example, a shallow trench isolation structure.

[0038] The depth H1 of the first well region 101 in the longitudinal direction is greater than the depth H4 of the isolation structure 121 in the longitudinal direction. The depth H2 of the second well region 102 in the longitudinal direction is greater than the depth H4 of the isolation structure 121 in the longitudinal direction. The lower surface 121L of the isolation structure 121 is higher than the lower surface 101L of the first well region 101 and the lower surface 102L of the second well region 102. The depth H3 of the third well region 103 in the longitudinal direction is greater than the depth H5 of the isolation structure 122 in the longitudinal direction. The depths H1 of the first well region 101, H2 of the second well region 102, and H3 of the third well region 103 in the longitudinal direction may be the same or different from each other. The depths H4 of the isolation structure 121 and H5 of the isolation structure 122 in the longitudinal direction may be the same or different from each other. At least a portion of the lower surface 121L of the isolation structure 121 is not covered by the first well region 101 and the second well region 102 and can directly contact the substrate 100. exist Figure 1 In the embodiment shown, a portion of the lower surface 121L of the isolation structure 121 is covered by the first well region 101, another portion of the lower surface 121L of the isolation structure 121 is covered by the second well region 102, and yet another portion (or the remaining portion) of the lower surface 121L of the isolation structure 121 is not covered by the first well region 101 and the second well region 102.

[0039] The isolation structure 121 may partially overlap with the first well region 101 in the longitudinal direction. The isolation structure 121 may also partially overlap with the second well region 102 in the longitudinal direction. The isolation structure 121 may include a first portion 121-1, a second portion 121-2, and a third portion 121-3 located between the first portion 121-1 and the second portion 121-2. The first portion 121-1 overlaps with the first well region 101 in the longitudinal direction and directly contacts the first well region 101 and the drain region 141. The second portion 121-2 overlaps with the second well region 102 in the longitudinal direction and directly contacts the second well region 102. The third portion 121-3 does not overlap with either the first well region 101 or the second well region 102 in the longitudinal direction. The third portion 121-3 may directly contact the substrate 100.

[0040] The first well region 101 has a side surface 101S. The side surface 101S is located below the isolation structure 121. The second well region 102 has a side surface 102S. The side surface 102S is located below the isolation structure 121. The side surface 101S of the first well region 101 faces the side surface 102S of the second well region 102. The side surfaces 101S of the first well region 101 and 102S of the second well region 102 are separate. The substrate 100 can directly contact or cover the side surfaces 101S of the first well region 101 and 102S of the second well region 102.

[0041] The isolation structure 121 has a sidewall 121S1 and a sidewall 121S2 relative to the sidewall 121S1. The sidewall 121S1 of the isolation structure 121 is covered by a first well region 101. The sidewall 121S2 of the isolation structure 121 is covered by a second well region 102. The distance G1 between the sidewall 121S1 of the isolation structure 121 and the side surface 101S of the first well region 101 is greater than zero. The distance G2 between the sidewall 121S2 of the isolation structure 121 and the side surface 102S of the second well region 102 is greater than zero. Distances G1 and G2 are along the lateral direction. The lateral direction is perpendicular to the longitudinal direction. Distance G1 may be equal to distance G2 or may not be equal to distance G2.

[0042] When the transistor structure 10 is turned on, current can flow from the source region 142 through the third well region 103, the second well region 102, the substrate 100, and the first well region 101 to the drain region 141, such as... Figure 1 The current path 160 is shown. In some embodiments, when the transistor structure 10 is turned on, current can flow from the source region 142 through the third well region 103, the PN junction between the third well region 103 and the second well region 102, the second well region 102, the PN junction between the second well region 102 and the substrate 100 (e.g., side surface 102S), the substrate 100, the PN junction between the substrate 100 and the first well region 101 (e.g., side surface 101S), and the first well region 101 to the drain region 141.

[0043] Please refer to Figure 2 . Figure 2 This is a schematic diagram illustrating a semiconductor structure according to some embodiments. The semiconductor structure includes a transistor structure 20. The transistor structure 20 may be a laterally diffused MOSFET. The transistor structure 20 and... Figure 1The difference in the transistor structure 10 shown is that the lower surface 121L of the isolation structure 121 of the transistor structure 20 is not covered by the first well region 101, and the isolation structure 121 does not overlap with the first well region 101 in the longitudinal direction. In this embodiment, a portion of the lower surface 121L of the isolation structure 121 is covered by the second well region 102, and another portion of the lower surface 121L of the isolation structure 121 is not covered by the first well region 101 and the second well region 102 and directly contacts the substrate 102. The first portion 121-1 of the isolation structure 121 does not overlap with the first well region 101 in the longitudinal direction and directly contacts the substrate 100. The second portion 121-2 of the isolation structure 121 overlaps with the second well region 102 in the longitudinal direction and directly contacts the second well region 102. The third portion 121-3 of the isolation structure 121 does not overlap with the first well region 101 or the second well region 102 in the longitudinal direction. The third portion 121-3 can directly contact the substrate 100.

[0044] The lateral distance between the sidewall 121S1 of the isolation structure 121 and the side surface 101S of the first well region 101 is zero. The side surface 101S of the well region 101 is aligned with the sidewall 121S1 of the isolation structure 121 in the longitudinal direction. The distance G2 between the sidewall 121S2 of the isolation structure 121 and the side surface 102S of the second well region 102 is greater than zero.

[0045] When the transistor structure 20 is turned on, current can flow from the source region 142 through the third well region 103, the second well region 102, the substrate 100, and the first well region 101 to the drain region 141, such as... Figure 2 The current path 160 is shown. In some embodiments, when the transistor structure 20 is turned on, current can flow from the source region 142 through the third well region 103, the PN junction between the third well region 103 and the second well region 102, the second well region 102, the PN junction between the second well region 102 and the substrate 100 (e.g., side surface 102S), the substrate 100, the PN junction between the substrate 100 and the first well region 101 (e.g., side surface 101S), and the first well region 101 to the drain region 141.

[0046] Please refer to Figure 3 . Figure 3 This is a schematic diagram illustrating a semiconductor structure according to some embodiments. The semiconductor structure includes a transistor structure 30. The transistor structure 30 may be a laterally diffused MOSFET. The transistor structure 30 and... Figure 1The difference in the transistor structure 10 shown is that the lower surface 121L of the isolation structure 121 of the transistor structure 30 is not covered by the second well region 102, and the isolation structure 121 does not overlap with the second well region 102 in the longitudinal direction. In this embodiment, a portion of the lower surface 121L of the isolation structure 121 is covered by the first well region 101, and another portion of the lower surface 121L of the isolation structure 121 is not covered by the first well region 101 and the second well region 102 and directly contacts the substrate 102. The first portion 121-1 of the isolation structure 121 overlaps with the first well region 101 in the longitudinal direction and directly contacts the first well region 101. The second portion 121-2 of the isolation structure 121 does not overlap with the second well region 102 in the longitudinal direction and directly contacts the substrate 100. The third portion 121-3 of the isolation structure 121 does not overlap with the first well region 101 or the second well region 102 in the longitudinal direction. The third portion 121-3 can directly contact the substrate 100.

[0047] The distance G1 between the sidewall 121S1 of the isolation structure 121 and the side surface 101S of the first well region 101 is greater than zero. The distance in the lateral direction between the sidewall 121S2 of the isolation structure 121 and the side surface 102S of the second well region 102 is equal to zero. The side surface 102S of the second well region 102 is aligned with the sidewall 121S2 of the isolation structure 121 in the longitudinal direction.

[0048] When the transistor structure 30 is turned on, current can flow from the source region 142 through the third well region 103, the second well region 102, the substrate 100, and the first well region 101 to the drain region 141, such as... Figure 3 The current path 160 is shown. In some embodiments, when the transistor structure 30 is turned on, current can flow from the source region 142 through the third well region 103, the PN junction between the third well region 103 and the second well region 102, the second well region 102, the PN junction between the second well region 102 and the substrate 100 (e.g., side surface 102S), the substrate 100, the PN junction between the substrate 100 and the first well region 101 (e.g., side surface 101S), and the first well region 101 to the drain region 141.

[0049] Please refer to Figure 4 . Figure 4 This is a schematic diagram illustrating a semiconductor structure according to some embodiments. The semiconductor structure includes a transistor structure 40. The transistor structure 40 may be a laterally diffused MOSFET. The transistor structure 40 and... Figure 1The difference in the transistor structure 10 shown is that the lower surface 121L of the isolation structure 121 of the transistor structure 40 is not covered by the first well region 101 and the second well region 102, and the isolation structure 121 does not overlap with the first well region 101 and the second well region 102 in the longitudinal direction. In this embodiment, the lower surface 121L of the isolation structure 121 is completely not covered by the first well region 101 and the second well region 102 and directly contacts the substrate 102. The isolation structure 121 does not overlap with the first well region 101 and the second well region 102 in the longitudinal direction.

[0050] The lateral distance between the sidewall 121S1 of the isolation structure 121 and the side surface 101S of the first well region 101 is zero. The side surface 101S of the first well region 101 is aligned with the sidewall 121S1 of the isolation structure 121 in the longitudinal direction. The lateral distance between the sidewall 121S2 of the isolation structure 121 and the side surface 102S of the second well region 102 is zero. The side surface 102S of the second well region 102 is aligned with the sidewall 121S2 of the isolation structure 121 in the longitudinal direction.

[0051] When the transistor structure 40 is turned on, current can flow from the source region 142 through the third well region 103, the second well region 102, the substrate 100, and the first well region 101 to the drain region 141, such as... Figure 2 The current path 160 is shown. In some embodiments, when the transistor structure 40 is turned on, current can flow from the source region 142 through the third well region 103, the PN junction between the third well region 103 and the second well region 102, the second well region 102, the PN junction between the second well region 102 and the substrate 100 (e.g., side surface 102S), the substrate 100, the PN junction between the substrate 100 and the first well region 101 (e.g., side surface 101S), and the first well region 101 to the drain region 141.

[0052] Please refer to Figure 5 . Figure 5This is a schematic diagram illustrating a semiconductor structure according to some embodiments. The semiconductor structure includes a transistor structure 10 and a transistor structure 60. The transistor structure 60 is adjacent to the transistor structure 10. The transistor structure 60 includes a substrate 100, a first well region 101, a second well region 502, a third well region 503, an isolation structure 521, a drain region 141, a source region 542, a gate structure 545, a doped region 543, and an isolation structure 522. The transistor structure 60 and the transistor structure 10 may share the first well region 101, the drain region 141, and the substrate 100. The second well region 502 and the third well region 503 are in the substrate 100. The second well region 502 is adjacent to the third well region 503. The second well region 502 is located between the first well region 101 and the third well region 503. The second well region 502 can be formed by implanting a dopant into the substrate 100. The second well region 502 has a first conductivity type. The third well region 503 can be formed by implanting a dopant into the substrate 100. The third well region 503 has a second conductivity type. Since the conductivity type of the second well region 502 is different from that of the third well region 503, a PN junction is formed at the contact interface between the second well region 502 and the third well region 503. Since the conductivity type of the second well region 502 is different from that of the substrate 100, a PN junction is formed at the contact interface between the second well region 502 and the substrate. An isolation structure 521 is located in the substrate 100 and is situated between the first well region 101 and the second well region 502. The isolation structure 521 separates the first well region 101 and the second well region 502 from each other. Isolation structures 521 and 522 are, for example, shallow trench isolation structures.

[0053] Drain region 141 has a first conductivity type. The doping concentration of drain region 141 may be higher than the doping concentration of first well region 101 and second well region 502. Source region 542 is located in third well region 503. Dopant may be implanted into third well region 503 to form source region 542. Source region 542 has a first conductivity type. The doping concentration of source region 542 may be higher than the doping concentration of first well region 101 and second well region 502. Gate structure 545 is on the substrate and is located between drain region 141 and source region 542. Gate structure 545 may include a gate dielectric film and a gate electrode film above the gate dielectric film. The gate electrode film may include a single layer or multiple layers. Gate structure 545 may partially overlap third well region 503 and isolation structure 521 in the longitudinal direction. Gate structure 545 may overlap or partially overlap second well region 502 in the longitudinal direction. In some embodiments, the gate structure 545 is closer to the source region 542 than the drain region 141. An isolation structure 522 is situated between the doped region 543 and the source region 542. The isolation structure 522 separates the doped region 543 from the source region 542. The doped region 543 can be formed by implanting a dopant into the third well region 503. The doped region 543 has a second conductivity type. The doping concentration of the doped region 543 can be higher than the doping concentration of the third well region 503. The third well region 503 can cover the lower surface of the isolation structure 522. The doped region 543 can be the base region of a laterally diffused MOSFET.

[0054] The depth H1 of the first well region 101 in the longitudinal direction is greater than the depth H8 of the isolation structure 521 in the longitudinal direction. The depth H6 of the second well region 502 in the longitudinal direction is greater than the depth H8 of the isolation structure 521 in the longitudinal direction. The lower surface 521L of the isolation structure 521 is higher than the lower surface 101L of the first well region 101 and the lower surface 502L of the second well region 502. The depth H7 of the third well region 503 in the longitudinal direction is greater than the depth H9 of the isolation structure 522 in the longitudinal direction. The depths H1 of the first well region 101, H6 of the second well region 502, and H7 of the third well region 503 in the longitudinal direction may be the same or different from each other. The depths H8 of the isolation structure 521 and H9 of the isolation structure 522 in the longitudinal direction may be the same or different from each other.

[0055] At least a portion of the lower surface 521L of the isolation structure 521 is not covered by the first well region 101 and the second well region 502. In this embodiment, a portion of the lower surface 521L of the isolation structure 521 is covered by the first well region 101, another portion of the lower surface 521L of the isolation structure 521 is covered by the second well region 502, and yet another portion of the lower surface 521L of the isolation structure 521 can directly contact the substrate 100. The isolation structure 521 may include a first portion 521-1, a second portion 521-2, and a third portion 521-3 located between the first portion 521-1 and the second portion 521-2. The first portion 521-1 overlaps with the first well region 101 in the longitudinal direction and directly contacts the first well region 101 and the drain region 141. The second portion 521-2 overlaps with the second well region 502 in the longitudinal direction and directly contacts the second well region 502. The third portion 521-3 does not overlap with the first well region 101 or the second well region 502 in the longitudinal direction. Part 3, 521-3, can directly contact substrate 100.

[0056] The first well region 101 has a side surface 101SS. The side surface 101SS is located below the isolation structure 521. The second well region 502 has a side surface 502S. The side surface 502S is located below the isolation structure 521. The side surface 101SS of the first well region 101 faces the side surface 502S of the second well region 502. The side surface 101SS of the first well region 101 and the side surface 502S of the second well region 502 are separate. The substrate 100 can directly contact or cover the side surface 101SS of the first well region 101 and the side surface 502S of the second well region 502.

[0057] The isolation structure 521 has a sidewall 521S1 and a sidewall 521S2 relative to the sidewall 521S1. The sidewall 521S1 is covered by a first well region 101. The sidewall 521S2 is covered by a second well region 502. The distance G3 between the sidewall 521S1 of the isolation structure 521 and the side surface 101SS of the first well region 101 is greater than zero. The distance G4 between the sidewall 521S2 of the isolation structure 521 and the side surface 502S of the second well region 502 is greater than zero. Distances G3 and G4 are along the lateral direction. Distance G3 may be equal to or may not be equal to distance G4. When the transistor structure 60 is turned on, its current path may be similar to that of the transistor 10.

[0058] exist Figure 5In transistor structure 60, the relative positional relationship of the isolation structure 521, the first well region 101, and the second well region 502, as well as the form in which the lower surface 521L of the isolation structure 521 is covered by the first well region 101 and the second well region 502, are similar to those in transistor structure 10. However, this invention is not limited thereto, and the relative positional relationship of the isolation structure 521, the first well region 101, and the second well region 502, as well as the form in which the lower surface 521L of the isolation structure 521 is covered by the first well region 101 and the second well region 502, may also be similar to those in transistor structures 20, 30, or 40. Furthermore, Figure 5 The transistor structure 10 in the semiconductor structure can also be replaced by transistor structure 20, 30 or 40.

[0059] According to the above embodiments, the transistor structure in the semiconductor structure provided by the present invention has a first well region, a second well region, and an isolation structure between the first well region and the second well region. The side surface of the first well region and the side surface of the second well region facing this side surface are separated from each other, that is, at least a portion of the lower surface of the isolation structure is not covered by the well regions (including the first well region and the second well region).

[0060] Figure 6A and Figure 6B This illustrates test results of transistor structures in semiconductor structures according to some embodiments. Figure 6A The horizontal axis represents the length of the isolation structure between the first well region and the second well region in the lateral direction (or can be understood as the distance between sidewall 121S1 and sidewall 121S2 in the lateral direction). This length is the difference between the length of the isolation structure in the lateral direction of a standard transistor structure and that of the isolation structure in the lateral direction. Figure 6A The vertical axis represents the breakdown voltage of the transistor structure in the OFF-state, which is the difference between this breakdown voltage and that of the standard transistor structure. Figure 6B The horizontal axis represents the breakdown voltage of the transistor structure in the OFF-state, which is the difference between this breakdown voltage and that of the standard transistor structure. Figure 6B The vertical axis represents the percentage of the on-resistance relative to the on-resistance of a standard transistor structure. Figure 6A and Figure 6B In the diagram, "×" represents the transistor structure of the present invention, and "." represents the transistor structure of a comparative example. In the transistor structure of the comparative example, the isolation structure is located in a well region, and the lower surface of the isolation structure is completely covered by this well region. Figure 6A It is evident that, with the same length of the isolation structure, the transistor structure of the present invention exhibits a higher breakdown voltage; moreover, as the length of the isolation structure increases, the breakdown voltage of the transistor structure of the present invention increases significantly. Figure 6BIt is understood that although increasing the breakdown voltage leads to an increase in on-resistance, the transistor structure of the present invention can still maintain the on-resistance within an appropriate range, and the semiconductor structure still exhibits excellent electrical performance. Therefore, by ensuring that at least a portion of the lower surface of the isolation structure is not covered by the well region, the present invention can effectively increase the breakdown voltage, maintain a good balance between breakdown voltage and on-resistance, and improve the reliability and operational stability of the semiconductor structure. Furthermore, the transistor structure of the present invention is compatible with existing metal-oxide-semiconductor fabrication processes and does not require additional photomasks, resulting in low manufacturing costs and ease of fabrication.

[0061] In summary, although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A semiconductor structure comprising: substrate; A first well region is located in the substrate and has a first side surface; A second well region is located in the substrate and has a second side surface; In the substrate, the second well region is located between the first well region and the third well region; An isolation structure is located in the substrate and between the first well region and the second well region; The drain region is located within the first well region. The source region is located within this third well region; as well as Gate structure, on this substrate, The first side surface of the first well region faces the second side surface of the second well region, and the first side surface of the first well region and the second side surface of the second well region are separate.

2. The semiconductor structure of claim 1, wherein the first well region has a first conductivity type, the second well region has the first conductivity type, and the third well region has a second conductivity type, the second conductivity type being different from the first conductivity type.

3. The semiconductor structure of claim 1, wherein the isolation structure comprises a first portion and a second portion, the first portion overlapping the first well region in the longitudinal direction, and the second portion overlapping the second well region in the longitudinal direction.

4. The semiconductor structure of claim 1, wherein the isolation structure has a first sidewall and a second sidewall, and at least one of the distance between the first sidewall and the first side surface of the first well region and the distance between the second sidewall and the second side surface of the second well region is greater than zero.

5. The semiconductor structure of claim 4, wherein the first sidewall of the isolation structure is covered by the first well region, and the second sidewall of the isolation structure is covered by the second well region.

6. The semiconductor structure of claim 5, wherein current flows from the source region through the third well region, the second well region, the substrate, and the first well region to the drain region.

7. The semiconductor structure of claim 1, wherein the isolation structure has a first sidewall and a second sidewall, the first sidewall being zero relative to the second sidewall, the first sidewall being zero at a distance from the first side surface of the first well region, and the second sidewall being zero at a distance from the second side surface of the second well region.

8. The semiconductor structure of claim 7, wherein the first sidewall of the isolation structure is covered by the first well region, and the second sidewall of the isolation structure is covered by the second well region.

9. The semiconductor structure of claim 1, wherein the isolation structure has a first sidewall and a second sidewall, the first sidewall being aligned with the second sidewall in a longitudinal direction relative to the first sidewall of the isolation structure, and / or the second sidewall of the second well region being aligned with the second sidewall of the isolation structure in the longitudinal direction.

10. The semiconductor structure of claim 1, wherein at least a portion of the lower surface of the isolation structure is not covered by the first well region and the second well region.

11. The semiconductor structure of claim 1, wherein at least a portion of the lower surface of the isolation structure is in direct contact with the substrate.

12. The semiconductor structure of claim 1, wherein the isolation structure has a first sidewall and a second sidewall, the first sidewall being relative to the second sidewall, and the distance between the first sidewall and the first side surface of the first well region is equal to the distance between the second sidewall and the second side surface of the second well region.

13. The semiconductor structure of claim 1, wherein current flows from the source region through the third well region, the second well region, the substrate and the first well region to the drain region.

14. The semiconductor structure of claim 1, wherein the lower surface of the isolation structure is higher than the lower surface of the first well region and the lower surface of the second well region.

15. The semiconductor structure of claim 1, wherein the gate structure overlaps the second well region, and the gate structure partially overlaps the isolation structure and the third well region.

16. The semiconductor structure of claim 1, wherein the second well region is adjacent to the third well region.

17. The semiconductor structure of claim 1, further comprising a doped region in the third well region and another isolation structure, the other isolation structure separating the doped region from the source.

18. The semiconductor structure of claim 17, wherein the source region has a first conductivity type, the drain region has the first conductivity type, the doped region has a second conductivity type, and the first conductivity type is different from the second conductivity type.

19. The semiconductor structure of claim 18, wherein the substrate has the second conductivity type.

20. The semiconductor structure of claim 1, wherein the first side surface of the first well region and the second side surface of the second well region are covered by the substrate.

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