Semiconductor structure

Abstract

The invention provides a semiconductor structure, which comprises a substrate, a channel layer and a barrier layer which are stacked in sequence, and is characterized in that a P-type semiconductor layer located in a gate region is used for realizing an enhanced device; the crystalline layer, the SiN layer and the amorphous layer are sequentially arranged on the P-type semiconductor layer, the crystalline layer and the P-type semiconductor layer form a junction, block carrier injection and reduce leakage current, the crystalline layer can enhance polarization, induce increase of hole concentration of the P-type semiconductor layer and improve threshold voltage of the device, and when voltage is applied to a grid electrode, the device can be prevented from being damaged. Uniform electric field distribution can be formed in the gate region, and the possibility that the device is broken down is reduced. The amorphous layer can reduce electric leakage; the SiN layer is located between the crystalline layer and the amorphous layer, and the crystalline state stability of the crystalline layer and the amorphous layer can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure. BACKGROUND

[0002] Compared with the first and second generation semiconductor materials, the third generation semiconductor material, especially GaN (gallium nitride) based material, has the advantages of large band gap, high breakdown field strength, large electron mobility, strong radiation resistance, etc. GaN-based HEMT (high electron mobility transistor) devices have great development potential in high-frequency and high-power fields such as wireless communication base stations, radars, and automotive electronics.

[0003] Generally, GaN-based HEMT devices are depletion-mode field effect transistors. In radio frequency microwave applications, a negative turn-on voltage is required, which makes the circuit structure complex and the anti-misoperation protection function of the circuit is affected, thereby reducing the safety of the circuit. Therefore, it is necessary to develop an enhancement-mode GaN-based HEMT device. The traditional GaN-based HEMT device can use a P-type gate to realize the enhancement-mode, but there are still problems such as large gate leakage current. SUMMARY

[0004] Therefore, an embodiment of the present application provides a semiconductor structure to solve the technical problems of large gate leakage current and low breakdown voltage in the prior art.

[0005] According to one aspect of the present application, an embodiment of the present application provides a semiconductor structure, which comprises: a substrate, a channel layer and a barrier layer which are sequentially stacked, wherein the channel layer and the barrier layer comprise a gate region, and a source region and a drain region located on both sides of the gate region; on a side of the barrier layer away from the substrate, the gate region comprises: a P-type semiconductor layer, a crystalline layer, a SiN layer, an amorphous layer and a gate which are sequentially stacked; a source and a drain, wherein the source is located on the source region, and the drain is located on the drain region.

[0006] In one embodiment, the material of the crystalline layer comprises crystalline AlN; and / or, the material of the amorphous layer comprises amorphous AlN.

[0007] In one embodiment, the crystalline AlN is single-crystal AlN or polycrystal AlN.

[0008] In one embodiment, the crystalline layer, the SiN layer and the amorphous layer cover at least part of the sidewall of the P-type semiconductor layer.

[0009] In one embodiment, the crystalline layer, the SiN layer, and the amorphous layer are further located between the gate region and the source region, and also between the gate region and the drain region.

[0010] In one embodiment, the crystalline layer, the SiN layer, and the amorphous layer include vias, and the gate is in contact with the P-type semiconductor layer through the vias.

[0011] In one embodiment, the thickness of the P-type semiconductor layer is greater than the thickness of the crystalline layer.

[0012] In one embodiment, the thickness ratio of the P-type semiconductor layer to the crystalline layer is in the range of 2 to 20.

[0013] In one embodiment, the thickness of the crystalline layer is greater than the thickness of the SiN layer; and / or, the thickness of the amorphous layer is greater than the thickness of the SiN layer.

[0014] In one embodiment, the thickness ratio of the crystalline layer to the SiN layer is in the range of 2 to 10; and / or, the thickness ratio of the amorphous layer to the SiN layer is in the range of 2 to 10.

[0015] In one embodiment, the thickness of the crystalline layer is less than or equal to 80 nm.

[0016] In one embodiment, the bandgap of the amorphous layer is greater than the bandgap of the P-type semiconductor layer. An embodiment of this application provides a semiconductor structure comprising a substrate, a channel layer, and a barrier layer stacked sequentially. The channel layer and barrier layer form a heterojunction. When no voltage is applied to the semiconductor device, the P-type semiconductor layer can deplete the 2DEG at the channel, achieving an enhancement-mode device. A crystalline layer, a SiN layer, and an amorphous layer are sequentially disposed on the P-type semiconductor layer. The crystalline layer forms a junction with the P-type semiconductor layer, blocking carrier injection and reducing leakage current. Furthermore, the crystalline layer enhances polarization, inducing an increase in the hole concentration of the P-type semiconductor layer, raising the device's threshold voltage. When a voltage is applied to the gate, a uniform electric field distribution can be formed in the gate region, reducing the possibility of device breakdown. The amorphous layer reduces leakage current. The SiN layer, located between the crystalline and amorphous layers, improves the stability of their crystalline states. Attached Figure Description

[0017] Figure 1 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this application.

[0018] Figure 2 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0019] Figure 3The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0020] Figure 4 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0021] Figure 5 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0023] To address the issue of high gate leakage current, this application provides a semiconductor structure. The following describes... Figures 1 to 5 Further examples illustrate the semiconductor structures mentioned in this application.

[0024] Figure 1 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this application. Figure 1 As shown, the semiconductor structure includes: a substrate 10, a channel layer 20, and a barrier layer 30 stacked sequentially. The channel layer 20 and the barrier layer 30 include a gate region 40a, and a source region 40b and a drain region 40c located on both sides of the gate region 40a. On the side of the barrier layer 30 away from the substrate 10, the gate region 40a includes: a P-type semiconductor layer 51, a crystal layer 601, a SiN layer 602, an amorphous layer 603, and a gate 41 stacked sequentially; a source 42 and a drain 43, with the source 42 located on the source region 40b and the drain 43 located on the drain region 40c.

[0025] Specifically, such as Figure 1As shown, the channel layer 20 and the barrier layer 30 form a heterojunction, and a 2DEG channel is formed on the surface of the channel layer 20 near the barrier layer 30. When no voltage is applied to the semiconductor device, the P-type semiconductor layer 51 can deplete the 2DEG at the channel to realize an enhancement-mode device. Specifically, in the gate region 40a, a crystalline layer 601, a SiN layer 602, and an amorphous layer 603 are disposed on the side of the P-type semiconductor layer 51 away from the substrate 10. Firstly, the crystalline layer 601 can form a junction with the P-type semiconductor layer 51, blocking carrier injection and reducing leakage current. Secondly, the crystalline layer 601 can enhance polarization, inducing an increase in the hole concentration of the P-type semiconductor layer 51, thus increasing the device's threshold voltage. Furthermore, when a voltage is applied to the gate, it can form a uniform electric field distribution in the gate region, reducing the possibility of device breakdown. The amorphous layer 603 can reduce leakage current. To improve the stability of the crystallization state of the crystalline layer 601 and the amorphous layer 603, a SiN layer 602 is disposed between the crystalline layer 601 and the amorphous layer 603. The SiN layer 602 can also reduce leakage current. Therefore, in this semiconductor structure, three reinforcing layers—a crystalline layer, a SiN layer, and an amorphous layer—are disposed above the P-type semiconductor layer 51. By controlling the crystallization state of the amorphous layer and the crystalline layer, the gate leakage current can be reduced, and the device breakdown voltage can be increased.

[0026] Optionally, the material of the substrate 10 is selected from any one of single-crystal silicon, single-crystal germanium, sapphire, diamond, SiC and GaN.

[0027] Optionally, the semiconductor structure uses GaN-based semiconductor materials, for example, the channel layer 20 is made of GaN and the barrier layer 30 is made of AlGaN.

[0028] In one embodiment, the material of the crystalline layer 601 includes crystalline AlN; and / or, the material of the amorphous layer 603 includes amorphous AlN. Specifically, the crystalline layer 601 and the amorphous layer 603 use AlN materials with different crystalline states. The crystalline layer 601 uses crystalline AlN, which has a larger bandgap, further enhancing polarization, inducing an increase in the hole concentration of the P-type semiconductor layer, increasing the threshold voltage of the device, and forming a uniform electric field distribution in the gate region when a voltage is applied to the gate, reducing the possibility of device breakdown. The amorphous layer uses amorphous AlN, which has a larger bandgap, increasing the Schottky barrier height between the gate 41 and the P-type semiconductor layer 51, thereby increasing the breakdown voltage.

[0029] Optionally, the bandgap of the amorphous layer 603 is greater than the bandgap of the P-type semiconductor layer 51, which can increase the Schottky barrier height between the gate 41 and the P-type semiconductor layer 51, thereby increasing the breakdown voltage.

[0030] Optionally, when the material of the crystalline layer 603 is crystalline AlN, the crystalline AlN can be monocrystalline AlN or polycrystalline AlN. Among them, monocrystalline AlN has a more uniform crystal arrangement, thus forming a more uniform electric field distribution in the gate region, further reducing the possibility of device breakdown.

[0031] Optionally, a material with a larger bandgap is selected to fabricate the crystal layer 601. The bandgap of the crystal layer 601 is greater than the bandgap of the P-type semiconductor layer 51. The crystal layer 601 and the P-type semiconductor layer 51 form a junction, which can block carrier injection and reduce gate leakage current.

[0032] Optionally, the bandgap of the amorphous layer 603 is greater than the bandgap of the SiN layer 602, and the bandgap of the crystalline layer 601 is greater than the bandgap of the SiN layer 602, thereby reducing the gate forward current.

[0033] In one embodiment, Figure 2 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 2 As shown, the amorphous layer 601, the SiN layer 602, and the crystalline layer 603 at least cover a portion of the sidewalls of the p-type semiconductor layer 51. Specifically, in Figure 2 In the cross-section shown, the amorphous layer 601, the SiN layer 602, and the crystalline layer 603 cover the upper surface and part of the sidewalls of the P-type semiconductor layer 51, reducing leakage current and improving device reliability.

[0034] It should be noted that, as Figure 2 As shown, the semiconductor structure also includes a passivation layer 70, which is located between the gate region 40a and the source region 40b, between the gate region 40a and the drain region 40c, and between the crystal layer 601 and the barrier layer 30; optionally, the material of the passivation layer 70 is SiN or SiO2.

[0035] It should be noted that, as Figure 2 As shown, the amorphous layer 601, SiN layer 602, and crystal layer 603 are also located above the passivation layer 70. The amorphous layer 601, SiN layer 602, and crystal layer 603 between the gate region 40a and the source region 40b, and between the gate region 40a and the drain region 40c are not etched, thereby reducing etching damage and improving device reliability.

[0036] Specifically, a passivation layer 70 with an opening is formed on the barrier layer 30, and a P-type semiconductor layer 51 is formed by secondary epitaxy from the opening. Then, a crystalline layer 601, a SiN layer 602, and an amorphous layer 603 are deposited to cover the P-type semiconductor layer 51. Optionally, Figure 3 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 3As shown, the P-type semiconductor layer 51 is laterally epitaxial, covering part of the passivation layer 70. The laterally epitaxial P-type semiconductor layer 51 can alleviate the electric field strength near the gate region and improve the breakdown voltage of the device.

[0037] In one embodiment, Figure 4 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 4 As shown, the crystalline layer 601, SiN layer 602, and amorphous layer 603 are also located between the gate region 40a and the source region 40b, and also between the gate region 40a and the drain region 40c. Specifically, the crystalline layer 601, SiN layer 602, and amorphous layer 603 are deposited on the side of the barrier layer 30 and the P-type semiconductor layer 51 away from the substrate 10. Later, only the crystalline layer 601, SiN layer 602, and amorphous layer 603 of the source region 40b and the drain region 40c are etched, leaving positions for the formation of the source 42 and the drain 43, to avoid the deterioration of the device's power characteristics due to over-etching of the barrier layer 30.

[0038] It should be noted that the comparison Figure 2 and Figure 4 , Figure 2 A passivation layer 70 is added between the barrier layer 30 and the crystal layer 601.

[0039] In one embodiment, Figure 5 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 5 As shown, the crystalline layer 601, SiN layer 602, and amorphous layer 603 include vias 600, through which the gate 41 contacts the P-type semiconductor layer 51. Specifically, by controlling the area ratio of the via 600 to the gate region 40a, the contact area between the gate 41 and the P-type semiconductor layer 51 can be controlled, thereby controlling the range of the gate voltage. It can be understood that the smaller the area of ​​the via 600 relative to the gate region 40a, the larger the range of the gate voltage. Therefore, appropriately increasing the area of ​​the via 600 can narrow the range of the gate voltage, thereby reducing the risk of device breakdown and improving device reliability.

[0040] Optionally, the vias 600 are arranged periodically; in other words, each unit area of ​​gate region 40a has vias 600 of the same area, ensuring that the voltage per unit area of ​​the gate region remains consistent, further reducing the risk of device breakdown. Optionally, in the direction perpendicular to the substrate 10, the three-dimensional shape of the vias 600 is cubic, cylindrical, pyramidal, or frustum-shaped.

[0041] In one embodiment, the thickness of the P-type semiconductor layer 51 is greater than the thickness of the crystal layer 601. Specifically, reducing the thickness of the crystal layer 601 avoids affecting the gate control capability; appropriately increasing the thickness of the crystal layer 601 can induce an increase in the hole concentration of the P-type semiconductor layer, thereby improving the threshold voltage of the device.

[0042] Optionally, the thickness ratio of the P-type semiconductor layer 51 to the crystal layer 601 is in the range of 2 to 20, that is, the thickness of the P-type semiconductor layer 51 is 2 to 20 times the thickness of the crystal layer 601.

[0043] Optionally, the thickness of the crystalline layer 601 is less than or equal to 80 nm. Optionally, the thickness of the P-type semiconductor layer 51 is between 40 nm and 240 nm.

[0044] In one embodiment, the thickness of the crystalline layer 601 is greater than the thickness of the SiN layer 602; and / or, the thickness of the amorphous layer 603 is greater than the thickness of the SiN layer 602. Specifically, firstly, a thinner SiN layer 602 can stabilize the crystalline state of the crystalline layer 601 and the amorphous layer 603, and avoid a reduction in gate control capability due to excessive thickness of the amorphous layer 601, SiN layer 602, and crystalline layer 603, so the thickness of the SiN layer 602 can be appropriately reduced; secondly, appropriately increasing the thickness of the crystalline layer 601 and the amorphous layer 603 facilitates the control of forming different crystalline states.

[0045] Optionally, the thickness ratio of the crystalline layer 601 to the SiN layer 602 is in the range of 2 to 10, that is, the thickness of the crystalline layer 601 is 2 to 10 times the thickness of the SiN layer 602; and / or, the thickness ratio of the amorphous layer 603 to the SiN layer 602 is in the range of 2 to 10, that is, the thickness of the amorphous layer 603 is 2 to 10 times the thickness of the SiN layer 602.

[0046] Optionally, the thickness of the crystalline layer 601 is equal to the thickness of the amorphous layer 603.

[0047] This application provides a semiconductor structure comprising a substrate, a channel layer, and a barrier layer stacked sequentially. The channel layer and the barrier layer form a heterojunction. When no voltage is applied to the semiconductor device, the P-type semiconductor layer can deplete the 2DEG at the channel, realizing an enhancement-mode device. A crystalline layer, a SiN layer, and an amorphous layer are sequentially disposed on the P-type semiconductor layer. The crystalline layer forms a junction with the P-type semiconductor layer, blocking carrier injection and reducing leakage current. Furthermore, the crystalline layer can enhance polarization, inducing an increase in the hole concentration of the P-type semiconductor layer, increasing the threshold voltage of the device. When a voltage is applied to the gate, a uniform electric field distribution can be formed in the gate region, reducing the possibility of device breakdown. The amorphous layer can reduce leakage current. The SiN layer is located between the crystalline layer and the amorphous layer, which can improve the stability of their crystalline states.

[0048] It should be understood that the term "comprising" and its variations as used in this application are open-ended, meaning "including but not limited to". The term "one embodiment" means "at least one embodiment". Specific features, structures, materials, or characteristics described in this specification may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, a channel layer, and a barrier layer are stacked sequentially, wherein the channel layer and the barrier layer include a gate region, and a source region and a drain region located on both sides of the gate region; On the side of the barrier layer away from the substrate, the gate region includes: a P-type semiconductor layer, a crystalline layer, a SiN layer, an amorphous layer, and a gate layer stacked sequentially. A source and a drain, wherein the source is located in the source region and the drain is located in the drain region.

2. The semiconductor structure according to claim 1, characterized in that, The material of the crystalline layer 601 includes crystalline AlN; and / or, The material of the amorphous layer includes amorphous AlN.

3. The semiconductor structure according to claim 2, characterized in that, The crystalline AlN is either monocrystalline AlN or polycrystalline AlN.

4. The semiconductor structure according to claim 1, characterized in that, The crystalline layer, the SiN layer, and the amorphous layer at least cover a portion of the sidewalls of the P-type semiconductor layer.

5. The semiconductor structure according to claim 4, characterized in that, The crystalline layer, the SiN layer, and the amorphous layer are also located between the gate region and the source region, and also between the gate region and the drain region.

6. The semiconductor structure according to claim 1, characterized in that, The crystalline layer, the SiN layer, and the amorphous layer include vias, and the gate electrode contacts the P-type semiconductor layer through the vias.

7. The semiconductor structure according to claim 1, characterized in that, The thickness of the P-type semiconductor layer is greater than the thickness of the crystalline layer.

8. The semiconductor structure according to claim 7, characterized in that, The thickness ratio of the P-type semiconductor layer to the crystalline layer is in the range of 2 to 20.

9. The semiconductor structure according to claim 1, characterized in that, The thickness of the crystalline layer is greater than the thickness of the SiN layer; and / or, the thickness of the amorphous layer is greater than the thickness of the SiN layer.

10. The semiconductor structure according to claim 9, characterized in that, The thickness ratio of the crystalline layer to the SiN layer is in the range of 2 to 10; and / or, the thickness ratio of the amorphous layer to the SiN layer is in the range of 2 to 10.

11. The semiconductor structure according to claim 1, characterized in that, The thickness of the crystalline layer is less than or equal to 80 nm.

12. The semiconductor structure according to claim 1, characterized in that, The band gap of the amorphous layer is greater than the band gap of the P-type semiconductor layer.

Images