Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises a substrate, a channel layer and a barrier layer which are stacked in sequence, the channel layer and the barrier layer comprise a gate region, and a source region and a drain region which are located at the two sides of the gate region; the first P-type semiconductor layer is located in the gate region and located on the side, away from the substrate, of the barrier layer, and the first P-type semiconductor layer is used for achieving an enhanced device; and the semiconductor film layer covers the side wall of the first P-type semiconductor layer and the upper surface of one side far away from the substrate, so that defects and interface states, introduced by etching, on the top surface and the side wall of the P-type semiconductor are reduced, electrons are prevented from being captured in the defects or the interface states, current collapse is improved, and the reliability of the device is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] Compared with the first and second generation semiconductor materials, the third generation semiconductor material, especially GaN (gallium nitride) based material, has the advantages of large band gap, high breakdown field strength, large electron mobility, strong radiation resistance, etc. GaN based HEMT (high electron mobility transistor) devices have great development potential in high-frequency high-power fields such as wireless communication base stations, radars, and automotive electronics.

[0003] Generally, GaN based HEMT devices are depletion mode field effect transistors. In radio frequency microwave applications, a negative turn-on voltage is required, which makes the circuit structure complex and affects the anti-misoperation protection function of the circuit, thereby reducing the safety of the circuit. Therefore, it is necessary to develop an enhancement mode GaN based HEMT device. The traditional GaN based HEMT device can use a P-type gate to realize the enhancement mode, but there are still problems such as current collapse and large gate leakage current. SUMMARY

[0004] Therefore, an embodiment of the present application provides a semiconductor structure and a manufacturing method thereof to solve the technical problem of current collapse in the prior art.

[0005] According to one aspect of the present application, an embodiment of the present application provides a semiconductor structure. The semiconductor structure comprises a substrate, a channel layer and a barrier layer which are sequentially stacked, the channel layer and the barrier layer comprising a gate region, and a source region and a drain region located on both sides of the gate region; a first P-type semiconductor layer located in the gate region and on a side of the barrier layer away from the substrate; and a semiconductor film layer covering a side wall and an upper surface of the first P-type semiconductor layer away from the substrate.

[0006] According to another aspect of the present application, an embodiment of the present application provides a manufacturing method of a semiconductor structure. The manufacturing method comprises: sequentially epitaxially manufacturing a channel layer and a barrier layer on a substrate, the channel layer and the barrier layer comprising a gate region, and a source region and a drain region located on both sides of the gate region; epitaxially manufacturing a first P-type semiconductor layer on a side of the barrier layer away from the substrate and in the gate region; and epitaxially manufacturing a semiconductor film layer on the first P-type semiconductor layer, the semiconductor film layer covering a side wall and an upper surface of the first P-type semiconductor layer away from the substrate.

[0007] This application provides a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate, a channel layer, and a barrier layer stacked sequentially. The channel layer and barrier layer include a gate region and source and drain regions located on both sides of the gate region. A first P-type semiconductor layer is located in the gate region and on the side of the barrier layer away from the substrate. The first P-type semiconductor layer is used to realize an enhancement-mode device. A semiconductor film layer covers the sidewalls of the first P-type semiconductor layer and the upper surface away from the substrate. The semiconductor film layer reduces defects and interface states on the top surface and sidewalls of the P-type semiconductor introduced by etching, reduces the trapping of electrons in defects or interface states, improves current collapse, and thus improves device reliability. Attached Figure Description

[0008] Figure 1 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this application.

[0009] Figure 2 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0010] Figure 3 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0011] Figure 4 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0012] Figure 5 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0013] Figure 6 The diagram shown is a schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0014] Figures 7 to 10 The diagram shown is an intermediate structure diagram for fabricating a semiconductor structure according to an embodiment of this application;

[0015] Figure 11 and Figure 12 The diagram shown is an intermediate structure schematic diagram for fabricating another semiconductor structure according to an embodiment of this application;

[0016] Figure 13 The diagram shown is an intermediate structure diagram for fabricating another semiconductor structure according to an embodiment of this application. Detailed Implementation

[0017] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0018] In traditional GaN-based HEMT devices, the gate insulating layer is formed on the P-type gate through plasma chemical vapor deposition or through electrode processes. This non-in-situ formation process results in defects or interface states at the interface between the P-type gate and the gate insulating layer or the gate. Electrons are easily trapped in the defects or interface states, causing current collapse and reducing device reliability.

[0019] To address the aforementioned issues, this application provides a semiconductor structure comprising a substrate, a channel layer, and a barrier layer stacked sequentially, wherein the channel layer and the barrier layer include a gate region and source and drain regions located on either side of the gate region; a first P-type semiconductor layer located in the gate region and on the side of the barrier layer away from the substrate; and a semiconductor film layer covering the sidewalls of the first P-type semiconductor layer and the upper surface away from the substrate.

[0020] The following is combined with Figures 1 to 13 Further examples illustrate the semiconductor structures and fabrication methods mentioned in this application.

[0021] Figure 1 The diagram shown is a schematic representation of a semiconductor structure according to an embodiment of this application. Figure 1 As shown, a semiconductor structure includes a substrate 10, a channel layer 20, and a barrier layer 30 stacked sequentially. The channel layer 20 and the barrier layer 30 include a gate region 40a, and a source region 40b and a drain region 40c located on both sides of the gate region 40a. A first P-type semiconductor layer 51 is located in the gate region 40a and on the side of the barrier layer 30 away from the substrate 10. A semiconductor film layer 60 covers the sidewalls of the first P-type semiconductor layer 51 and the upper surface away from the substrate 10.

[0022] Specifically, such as Figure 1 As shown, the channel layer 20 and the barrier layer 30 constitute a heterojunction, and a 2DEG channel is formed on the surface of the channel layer 20 near the barrier layer 30. When no voltage is applied to the semiconductor device, the first P-type semiconductor layer 51 can deplete the 2DEG at the channel to realize an enhancement-mode device. The semiconductor film layer 60 covers the sidewalls of the first P-type semiconductor layer 51 and the upper surface away from the substrate 10. The semiconductor film layer 60 is formed in situ and completely covers the surface of the first P-type semiconductor layer 51, reducing defects and interface states on the top surface and sidewalls of the P-type semiconductor introduced by the etching process, reducing the trapping of electrons in defects or interface states, improving current collapse, and thus improving device reliability.

[0023] Optionally, Figure 2 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 2As shown, along the direction from the gate region 40a to the drain region 40c, the thickness of a portion of the first P-type semiconductor layer 51 gradually decreases between the gate region 40a and the drain region 40c. That is, a slope is formed on the side of the first P-type semiconductor layer 51 near the drain region 40c. Since the gate region 40a is prone to breakdown on the side near the drain region 40c, the first P-type semiconductor layer 51 at the slope can reduce the 2DEG density in the underlying channel and reduce the electric field strength of the gate region 40a on the side near the drain region 40c, thereby improving the breakdown voltage of the device. At this time, the semiconductor film layer 60 covers the vertical sidewalls, slope, and upper surface away from the substrate 10 of the first P-type semiconductor layer 51, reducing defects and interface states on the top surface, slope, and sidewalls of the P-type semiconductor introduced by the etching process, reducing the trapping of electrons in defects or interface states, improving current collapse, and thus improving device reliability.

[0024] In one embodiment, such as Figure 1 As shown, the semiconductor structure further includes: a gate 41 located in gate region 40a and on the side of semiconductor film layer 60 away from substrate 10; a source 42 located in source region 40b and on the side of channel layer 20 away from substrate 10; and a drain 43 located in drain region 40c and on the side of channel layer 20 away from substrate 10. Specifically, as Figure 1 As shown, source 42 and drain 43 are located above barrier layer 30, and source 42 and drain 43 form ohmic contacts with barrier layer 30 respectively; optionally, source 42 and drain 43 penetrate barrier layer 30 and form ohmic contacts with channel layer 20 (not shown).

[0025] It should be noted that, as Figure 2 As shown, the portion of the first P-type semiconductor layer with gradually decreasing thickness is located between the gate 41 and the drain 43, and is connected to the remaining portion of the first P-type semiconductor layer below the gate 41.

[0026] Optionally, the semiconductor structure further includes a nucleation layer and a buffer layer located between the substrate 10 and the channel layer 20. Figure 1 (Not shown), the nucleation layer provides nucleation sites for the subsequent fabrication of the channel layer 20, and the buffer layer is used to alleviate the lattice mismatch between the substrate 10 and the channel layer 20 to improve the crystal quality of the subsequent epitaxial structure.

[0027] In one embodiment, Figure 3 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 3As shown, the semiconductor film 60 covers the region between the source region 40b and the gate region 40a, and the region between the drain region 40c and the gate region 40a. Specifically, the semiconductor film 60 is epitaxially fabricated on the side of the barrier layer 30 and the first P-type semiconductor layer 51 away from the substrate 10. Later, only the semiconductor film 60 of the source region 40b and the drain region 40c is etched, leaving the positions for forming the source 42 and the drain 43. The semiconductor film 60 between the source region 40b and the gate region 40a, and between the drain region 40c and the gate region 40a, is retained to avoid the deterioration of the device's power characteristics due to over-etching of the barrier layer 30.

[0028] In one embodiment, the bandgap of the semiconductor film layer 60 is greater than the bandgap of the first P-type semiconductor layer 51. Specifically, by using a semiconductor film layer 60 with a larger bandgap to cover the surface of the first P-type semiconductor layer 51, the higher barrier height can increase the gate operating voltage. Secondly, when the device is in the on-state, the semiconductor film layer 60 covering the top surface increases the gate breakdown voltage of the semiconductor device, and when the device is in the off-state, it reduces the influence of the peak electric field on the sidewalls of the first P-type semiconductor layer 51. Therefore, this configuration improves the operating voltage of the device in the on-state and the withstand voltage in the off-state, while also improving the device reliability.

[0029] Optionally, the semiconductor film layer 60 contains Al element, and the Al element composition of the semiconductor film layer 60 is greater than or equal to 35%. Specifically, the material of the semiconductor film layer 60 is AlGaN, and the Al element composition is greater than or equal to 35%, while the material of the first P-type semiconductor layer 51 is GaN. In this case, the band gap of the semiconductor film layer 60 is greater than the band gap of the first P-type semiconductor layer 51. Alternatively, the Al element composition of the semiconductor film layer 60 is 1%, in which case the material of the semiconductor film layer 60 is AlN, and its band gap is greater than that of AlGaN, which can better improve the breakdown voltage of the device and improve the power characteristics of the device. It should be noted that the Al element composition refers to the proportion of Al element in the metal ions of the semiconductor film layer. For example, when the Al element composition is 35%, the material of the semiconductor film layer 60 is Al. 0.35 Ga 0.65 N.

[0030] In one embodiment, the semiconductor film 60 includes an N-type doped element. Specifically, the semiconductor film 60 covers the first P-type semiconductor layer 51. When the gate is forward biased, the PN junction formed by the N-type doped semiconductor film 60 and the P-type doped first P-type semiconductor layer 51 is reverse biased. This space charge region can bear part of the gate voltage, playing a buffering role, improving the breakdown voltage of the device, and improving the reliability of the device.

[0031] Optionally, the P-type doping concentration of the portion of the first P-type semiconductor layer 51 closest to the semiconductor film layer 60 is lower than the P-type doping concentration of the portion of the first P-type semiconductor layer 51 furthest from the semiconductor film layer 60. The different P-type doping concentrations in the first P-type semiconductor layer 51 form a high-low junction with a concentration difference at the junction. When the gate is forward biased, the high-low junction is reverse biased, which also plays a buffering role, improves the breakdown voltage of the device, and improves the reliability of the device.

[0032] Optionally, the semiconductor film 60 is not intentionally doped.

[0033] In one embodiment, the semiconductor film layer 60 covers the area between the source region 42 and the gate region 41, and also covers the area between the drain region 43 and the gate region 41. The N-type dopant concentration of the semiconductor film layer 60 located between the source region 42 and the gate region 41 is greater than that of the semiconductor film layer 60 located between the drain region 43 and the gate region 41. Specifically, increasing the N-type dopant concentration of the semiconductor film layer 60 between the source region 42 and the gate region 41 increases the electron concentration in the lower channel. Conversely, since the electric field strength is higher on the side of the gate near the drain, breakdown is more likely to occur. Reducing the N-type dopant concentration of the semiconductor film layer 60 between the drain region 43 and the gate region 41 appropriately reduces the electric field strength on the side of the gate near the drain, thus reducing the likelihood of breakdown.

[0034] In one embodiment, the thickness of the semiconductor film 60 in the direction perpendicular to the plane of the substrate 10 is 2 to 10 nm. Optionally, the thickness of the semiconductor film 60 is 3 to 5 nm. A thinner semiconductor film 60 can reduce defects or interface states and avoid affecting the gate control capability of the gate.

[0035] In one embodiment, Figure 4 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 4 As shown, the semiconductor structure also includes a second P-type semiconductor layer 52 located on the side of the barrier layer 30 away from the substrate 10, between the gate region 40a and the drain region 40c. Specifically, the second P-type semiconductor layer 52 provides a gentle electric field distribution on the drain side 43, which can reduce current collapse.

[0036] Optionally, Figure 5 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 5 As shown, the semiconductor film 60 also covers the sidewalls of the second P-type semiconductor layer 52 and the upper surface away from the substrate 10. The semiconductor film 60 is formed in situ and completely covers the surface of the second P-type semiconductor layer 52.

[0037] Optionally, in the direction perpendicular to the plane of the substrate 10, the thickness of the second P-type semiconductor layer 52 is less than the thickness of the first P-type semiconductor layer 51. The function of the second P-type semiconductor layer 52 is to reduce the electron concentration of the underlying channel, rather than to achieve a normally off state.

[0038] Optionally, the P-type doping concentration of the second P-type semiconductor layer 52 is lower than that of the first P-type semiconductor layer 51. The function of the second P-type semiconductor layer 52 is to reduce the electron concentration of the lower channel, rather than to achieve a normally off state.

[0039] Optionally, the second P-type semiconductor layer 52 and the first P-type semiconductor layer 51 are made of the same material and are formed simultaneously, simplifying the manufacturing process.

[0040] In one embodiment, Figure 6 The diagram shown is a schematic representation of another semiconductor structure provided in an embodiment of this application. Figure 6 As shown, the source region 40b and drain region 40c each include an N-type doped region 70, which extends into the channel layer 20. Specifically, for example, in the source region 40b, the thickness of the N-type doped region 70 in the direction perpendicular to the plane of the substrate 10 is greater than the thickness of the barrier layer 30. The N-type doped region 70 is located between the source 42 and the channel layer 20, and the N-type doped region 70 and the source 42 are in ohmic contact, reducing the ohmic contact resistance between the source 42 and the channel, thereby improving the electrical performance of the semiconductor structure. The N-type doped region in the drain region has the same effect, which will not be described in detail here.

[0041] Optionally, the N-type doped region 70 is heavily N-type doped, with a doping concentration greater than 1E18 / cm³. 3 .

[0042] Optionally, the N-type doped region 70 includes a superlattice structure, which can further reduce resistance and increase the 2DEG concentration at the channel through polarization effect, thereby increasing the mobility of 2DEG.

[0043] In one embodiment, this application provides a method for fabricating a semiconductor structure. Figures 7 to 10 The diagram shown is an intermediate structure diagram for fabricating a semiconductor structure according to an embodiment of this application. The fabrication method includes the following steps:

[0044] Step S1, as follows Figure 7 As shown, a channel layer 20 and a barrier layer 30 are sequentially epitaxially fabricated on a substrate 10. The channel layer 20 and the barrier layer 30 include a gate region 40a, a source region 40b, and a drain region 40c located on both sides of the gate region 40a.

[0045] Specifically, the substrate 10 can be sapphire, Si, SiC, diamond, or GaN.

[0046] Specifically, the channel layer 20 and the barrier layer 30 can be GaN-based semiconductor materials, with the channel layer 20 being GaN and the barrier layer 30 being AlGaN. The epitaxial processes of the channel layer 20 and the barrier layer 30 are performed by atomic layer deposition (ALD), chemical vapor deposition (CVD), molecular beam epitaxy (MBE), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), physical vapor deposition (PVD), metal-organic molecular beam epitaxy (MOMBE), metal-organic chemical vapor deposition (MOCVD), or combinations thereof.

[0047] Step S2, as follows Figure 9 As shown, a first P-type semiconductor layer 51 is epitaxially fabricated in the gate region 40a on the side of the barrier layer 30 away from the substrate 10. Specifically, as... Figure 8 As shown, a P-type semiconductor material layer 50 is fabricated over the entire surface of the barrier layer 30, and the entire layer is activated; optionally, the P-type semiconductor material layer 50 except for the gate region 40a is etched away to obtain the following: Figure 9 The first P-type semiconductor layer 51 is shown. Optionally, after fabricating the P-type semiconductor material layer 50 over the entire surface, only the P-type semiconductor material layer 50 of the gate region 40a (not shown) is activated, and then the unactivated P-type semiconductor material layer 50 is removed by etching.

[0048] Step S3, as follows Figure 10 As shown, a semiconductor film 60 is epitaxially fabricated on the first P-type semiconductor layer 51. The semiconductor film 60 covers the sidewalls of the first P-type semiconductor layer 51 and the upper surface away from the substrate 10. Specifically, the semiconductor film 60 is epitaxially fabricated on the first P-type semiconductor layer 51 to avoid defects or interface states on the surface of the first P-type semiconductor layer 51 caused by other non-in-situ processes, reduce the defect energy level or interface state between the first P-type semiconductor layer and the semiconductor film layer, reduce the trapping of electrons in defects or interface states, improve current collapse, and thus improve device reliability.

[0049] Optionally, Figure 11 and Figure 12 The diagram shown is an intermediate structure diagram for fabricating another semiconductor structure according to an embodiment of this application. Figure 11 and Figure 12 As shown, in step S3, a semiconductor film layer 60 is epitaxially fabricated on the first P-type semiconductor layer 51, including: as shown in the figure. Figure 11 As shown, on the side of the first P-type semiconductor layer 51 and barrier layer 30 away from the substrate 10, a full-surface epitaxial semiconductor film layer 60 is formed; as... Figure 12 As shown, the semiconductor film 60 of the source region 40b and the drain region 40c is then etched, so that the semiconductor film 60 covers the area between the source region 40b and the gate region 40a, and also covers the area between the drain region 40c and the gate region 40a. This approach can avoid the deterioration of the device's power characteristics due to over-etching of the barrier layer 30.

[0050] Optionally, such as Figure 11 As shown, the semiconductor film 60 is conformally fabricated on the side of the first P-type semiconductor layer 51 and the barrier layer 30 away from the substrate 10.

[0051] Optionally, Figure 13 The diagram shown is an intermediate structure diagram for fabricating another semiconductor structure according to an embodiment of this application. Figure 13 As shown, after epitaxially fabricating the semiconductor film 60, the process further includes: etching grooves 80 in the source region 40b and the drain region 40c, respectively, with the grooves 80 extending into the channel layer 20; and epitaxially fabricating an N-type doped region 70 in the grooves 80. Optionally, before etching, a mask layer with an opening is first fabricated, and then the semiconductor film 60, the barrier layer 30, and part of the channel layer 20 are etched within the opening.

[0052] Optionally, in Figure 10 In the embodiment shown, the semiconductor film layer 60 is etched first, then a mask layer with an opening is fabricated, and then the barrier layer 30 and part of the channel layer 20 (not shown) are etched within the opening.

[0053] This application provides a semiconductor structure and its fabrication method. The semiconductor structure includes a substrate, a channel layer, and a barrier layer stacked sequentially. The channel layer and barrier layer include a gate region and source and drain regions located on both sides of the gate region. A first P-type semiconductor layer is located in the gate region and on the side of the barrier layer away from the substrate. The first P-type semiconductor layer is used to realize an enhancement-mode device. A semiconductor film layer covers the sidewalls of the first P-type semiconductor layer and the upper surface away from the substrate. The semiconductor film layer reduces defects and interface states on the top surface and sidewalls of the P-type semiconductor introduced by etching, reduces the trapping of electrons in defects or interface states, improves current collapse, and thus improves device reliability.

[0054] It should be understood that the term "comprising" and its variations as used in this application are open-ended, meaning "including but not limited to". The term "one embodiment" means "at least one embodiment". Specific features, structures, materials, or characteristics described in this specification may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

Claims

1. A semiconductor structure, characterized in that, include: A substrate, a channel layer, and a barrier layer are stacked sequentially, wherein the channel layer and the barrier layer include a gate region, and a source region and a drain region located on both sides of the gate region; A first P-type semiconductor layer is located in the gate region and on the side of the barrier layer away from the substrate; A semiconductor film layer covering the sidewalls of the first P-type semiconductor layer and the upper surface away from the substrate.

2. The semiconductor structure according to claim 1, characterized in that, The semiconductor film layer covers the region between the source region and the gate region, and covers the region between the drain region and the gate region.

3. The semiconductor structure according to claim 1, characterized in that, The bandgap of the semiconductor film is greater than the bandgap of the first P-type semiconductor layer.

4. The semiconductor structure according to claim 3, characterized in that, The semiconductor film contains Al, and the Al content of the semiconductor film is greater than or equal to 35%.

5. The semiconductor structure according to claim 4, characterized in that, The semiconductor film is made of AlGaN or AlN.

6. The semiconductor structure according to claim 3, characterized in that, The semiconductor film layer includes N-type doped elements.

7. The semiconductor structure according to claim 6, characterized in that, The semiconductor film layer covers the area between the source region and the gate region, and also covers the area between the drain region and the gate region; The N-type dopant concentration of the semiconductor film layer located between the source region and the gate region is greater than the N-type dopant concentration of the semiconductor film layer located between the drain region and the gate region.

8. The semiconductor structure according to claim 1, characterized in that, The thickness of the semiconductor film is 2 to 10 nm in a direction perpendicular to the plane of the substrate.

9. The semiconductor structure according to claim 8, characterized in that, The thickness of the semiconductor film is 3 to 5 nm.

10. The semiconductor structure according to claim 1, characterized in that, Also includes: A second P-type semiconductor layer is located on the side of the barrier layer away from the substrate, and the second P-type semiconductor layer is located between the gate region and the drain region.

11. The semiconductor structure according to claim 1, characterized in that, The source region and the drain region each include an N-type doped region, which extends into the channel layer.

12. The semiconductor structure according to claim 1, characterized in that, Also includes: A gate is located in the gate region and on the side of the semiconductor film layer away from the substrate; The source electrode is located in the source region and on the side of the channel layer away from the substrate; and, The drain electrode is located in the drain region and on the side of the channel layer away from the substrate.

13. A method for fabricating a semiconductor structure, comprising: A channel layer and a barrier layer are sequentially epitaxially fabricated on a substrate. The channel layer and the barrier layer include a gate region, and a source region and a drain region located on both sides of the gate region. On the side of the barrier layer away from the substrate, a first P-type semiconductor layer is epitaxially formed in the gate region; A semiconductor film is epitaxially fabricated on the first P-type semiconductor layer, the semiconductor film covering the sidewalls of the first P-type semiconductor layer and the upper surface away from the substrate.

14. The manufacturing method according to claim 13, characterized in that, The step of epitaxially fabricating a semiconductor film layer on the first P-type semiconductor layer includes: On the side of the first P-type semiconductor layer and the barrier layer away from the substrate, the semiconductor film layer is epitaxially stretched across the entire surface, such that the semiconductor film layer covers the area between the source region and the gate region, and covers the area between the drain region and the gate region.

15. The manufacturing method according to claim 14, characterized in that, The semiconductor film is conformally fabricated on the side of the first P-type semiconductor layer and the barrier layer away from the substrate.

16. The manufacturing method according to claim 13, characterized in that, After epitaxially fabricating the semiconductor film layer, the process further includes: Grooves are etched into the source region and the drain region respectively, and the grooves extend into the channel layer; An N-type doped region is fabricated in the groove through secondary epitaxy.

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