Manufacturing method of semiconductor structure and semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure and the semiconductor structure, and the manufacturing method comprises the steps: providing a plurality of pseudo gate structures, and enabling the pseudo gate structures to be disposed on a substrate; a first nitride layer is formed on the top surface of the dummy gate structure, an oxide layer is formed on the first nitride layer, and the larger the width of the dummy gate structure is, the smaller the thickness of the oxide layer on the dummy gate structure is; forming a second nitride layer on the exposed surfaces of the oxide layer, the first nitride layer and the pseudo gate structure; forming a dielectric layer on the first nitride layer and the substrate; removing the dielectric layer, the second nitride layer and the oxide layer on the pseudo gate structure until the surfaces of the first nitride layer and the second nitride layer are flush; and removing the first nitride layer and a part of the second nitride layer to enable the second nitride layer to be flush with the surface of the pseudo gate structure. According to the manufacturing method of the semiconductor structure and the semiconductor structure provided by the invention, the surface smoothness of the manufactured semiconductor structure can be improved, so that the manufacturing yield is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure manufacturing method and a semiconductor structure. BACKGROUND

[0002] In the semiconductor manufacturing process, as the transistor size is continuously reduced, in order to ensure the gate control ability, it is necessary to maintain sufficient gate capacitance, so the gate oxide thickness is also continuously thinned. However, when the gate oxide thickness is too thin, the direct tunneling effect increases exponentially, and the device leakage current increases greatly, thereby causing the device to be unable to work in practice.

[0003] The introduction of high-k materials into the integrated circuit process can make the gate oxide thickness relatively large under the premise of continuously reducing the equivalent gate oxide thickness, thereby inhibiting the gate leakage current. However, when there are multiple semiconductor structures of different sizes and structures on the wafer, it is difficult to control the height of the metal gate and the surface flatness when introducing high-k gate dielectric materials into the forming process of the metal gate, which is prone to cause defects. SUMMARY

[0004] The purpose of the present application is to provide a semiconductor structure manufacturing method and a semiconductor structure, which can improve the surface flatness of semiconductor structure manufacturing and thereby improve the manufacturing yield.

[0005] To solve the above technical problems, the present application is realized by the following technical scheme: The present application provides a semiconductor structure manufacturing method, comprising: providing a plurality of pseudo gate structures, the pseudo gate structures being arranged on a substrate; forming a first nitride layer on the top surface of the pseudo gate structure, and forming an oxide layer on the first nitride layer, wherein the greater the width of the pseudo gate structure, the smaller the thickness of the oxide layer on the pseudo gate structure; forming a second nitride layer on the oxide layer, the first nitride layer and the exposed surface of the pseudo gate structure; forming a dielectric layer on the first nitride layer and the substrate; removing the dielectric layer, the second nitride layer and the oxide layer on the pseudo gate structure until the surfaces of the first nitride layer and the second nitride layer are flush; and removing the first nitride layer and part of the second nitride layer so that the surfaces of the second nitride layer and the pseudo gate structure are flush.

[0006] In an embodiment of the present application, when removing the second nitride layer and the oxide layer on the pseudo gate structure, the second nitride layer on the oxide layer is first removed by wet etching until the surface of the oxide layer is exposed.

[0007] In one embodiment of the present application, after exposing the surface of the oxide layer, the oxide layer, part of the second nitride layer and part of the dielectric layer are polished away with the first nitride layer as a stop layer.

[0008] In one embodiment of the present application, before removing the first nitride layer, a dielectric deposition layer is formed on the first nitride layer, on the second nitride layer and on the dielectric layer until the dielectric deposition layer between adjacent pseudo gate structures is higher than the surface of the first nitride layer.

[0009] In one embodiment of the present application, in the step of removing the first nitride layer and part of the second nitride layer, part of the dielectric deposition layer is polished away with the first nitride layer as a stop layer, and the first nitride layer, part of the second nitride layer and part of the dielectric deposition layer are removed with the surface of the pseudo gate structure as a stop layer, so that the surface of the second nitride layer, the dielectric deposition layer and the pseudo gate structure are flush in the obtained semiconductor structure.

[0010] In one embodiment of the present application, after forming the dielectric layer, the dielectric layer on top of the pseudo gate structure is removed, and part of the second nitride layer and part of the dielectric layer at the corner of the pseudo gate structure are removed.

[0011] In one embodiment of the present application, after removing the dielectric layer on the pseudo gate structure, before removing the second nitride layer on the pseudo gate structure, a dielectric deposition layer is formed on the dielectric layer and on the second nitride layer, wherein the surface of the dielectric deposition layer between adjacent pseudo gate structures is higher than the surface of the second nitride layer.

[0012] In one embodiment of the present application, after forming the dielectric deposition layer, part of the dielectric deposition layer and part of the second nitride layer on the pseudo gate structure are polished away until the surface of the oxide layer is exposed.

[0013] In one embodiment of the present application, after exposing the oxide layer, the oxide layer and part of the second nitride layer and part of the dielectric deposition layer are polished away with the first nitride layer as a stop layer, and the first nitride layer, part of the second nitride layer and part of the dielectric deposition layer are polished away with the surface of the pseudo gate structure as a stop layer, so that the semiconductor structure is obtained, in which the surface of the second nitride layer, the dielectric deposition layer and the pseudo gate structure are flush.

[0014] The present application provides a semiconductor structure based on the manufacturing method of a semiconductor structure as described above, comprising: a substrate; a plurality of dummy gate structures disposed on the substrate; a second nitride layer covering side portions of the dummy gate structures; and a dielectric deposition layer disposed on the substrate, and the dielectric layer filling between adjacent dummy gate structures, wherein top surfaces of the dummy gate structures, the second nitride layer and the dielectric deposition layer are flush.

[0015] As described above, the present application provides a manufacturing method of semiconductor structure and semiconductor structure, and the unexpected technical effects are as follows: the manufacturing method of forming high-K metal gate provided by the present application can overcome the load effect, form metal gate with high surface flatness, and at the same time, is beneficial to reduce the possibility of defects such as air bubbles in the metal gate forming process, thereby improving the effectiveness of the semiconductor structure and the forming yield of the semiconductor process.

[0016] Of course, implementing any product of the present application does not necessarily need to achieve all the advantages described above at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0018] Figure 1 The structure schematic diagram of the semiconductor stack structure in the present application.

[0019] Figure 2 The structure schematic diagram of forming the dielectric layer in the present application.

[0020] Figure 3 The structure schematic diagram of exposing the second nitride layer in the present application.

[0021] Figure 4 The structure schematic diagram of etching to remove part of the second nitride layer in an embodiment of the present application.

[0022] Figure 5 The structure schematic diagram of polishing to remove part of the second nitride layer and the oxide layer in an embodiment of the present application.

[0023] Figure 6 The structure schematic diagram of forming the first dielectric deposition layer in an embodiment of the present application.

[0024] Figure 7 The structure schematic diagram of polishing to remove part of the first dielectric deposition layer in an embodiment of the present application.

[0025] Figure 8A structure diagram of polishing the first nitride layer and obtaining a semiconductor structure in an embodiment of the present application.

[0026] Figure 9 A structure diagram of removing part of the second nitride layer and part of the dielectric layer in another embodiment of the present application.

[0027] Figure 10 A structure diagram of forming a second dielectric deposition layer in another embodiment of the present application.

[0028] Figure 11 A structure diagram of polishing part of the second nitride layer and part of the second dielectric deposition layer in another embodiment of the present application.

[0029] Figure 12 A structure diagram of polishing the oxidation layer, part of the second nitride layer and part of the second dielectric deposition layer in another embodiment of the present application.

[0030] Figure 13 A structure diagram of polishing the first nitride layer and obtaining a semiconductor structure in another embodiment of the present application.

[0031] In the figure: 100, substrate; 200, dummy gate structure; 300, first nitride layer; 400, oxidation layer; 500, second nitride layer; D1, first distance; D2, second distance; H1, first thickness; H2, second thickness; H3, third thickness; W1, first width; W2, second width; W3, third width; 600, dielectric layer; 601a, first dielectric film; 602a, first dielectric deposition layer; 601b, second dielectric film; 602b, second dielectric deposition layer. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0033] The manufacturing method of the semiconductor structure provided by the present application can be used to form a metal gate structure of high-K gate dielectric. For details, please refer to Figure 2As shown, the high-K material is a material with a dielectric constant higher than that of silicon dioxide (SiO2), which can replace the silicon dioxide material to form the gate dielectric layer 600 to improve the performance of the transistor and reduce the size. The high-K material has a higher dielectric constant, which can effectively reduce the gate leakage current and improve the working efficiency of the transistor. In the present application, the high-K material includes, but is not limited to, hafnium-based oxide, aluminum-based oxide, and zirconium-based oxide, etc. Among them, the hafnium-based oxide is, for example, hafnium dioxide (HfO2), hafnium silicate oxide compound (HfSiO), hafnium silicon oxynitride (HfSiON). Among them, the aluminum-based oxide is, for example, aluminum oxide (Al2O3). Among them, the zirconium-based oxide is, for example, zirconium oxide (ZrO2).

[0034] As shown in the figure, Figure 1 As shown in the figure, in the manufacturing method of the semiconductor structure provided by the present application, a dummy gate structure 200 is first provided. The dummy gate structure 200 is arranged on a substrate 100. The substrate 100 includes a substrate and a working area formed in the substrate. The substrate is, for example, a wafer silicon base material for forming a semiconductor structure. The substrate can include a base material and a silicon layer arranged above the base material, and the base material is, for example, a semiconductor substrate 100 material such as silicon (Si), silicon carbide (SiC), sapphire (Al2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO2), etc. The silicon layer is formed above the base material. Phosphorus ions or arsenic ions can be implanted in the silicon layer to form a doped region to form a functional doped region of the semiconductor structure, such as a source or drain region, thereby forming a working area. The present application does not limit the material and thickness of the substrate. In the present embodiment, the substrate can be an intrinsic semiconductor, or ions can be implanted in the substrate to form an N-type semiconductor or a P-type semiconductor. In the present embodiment, the dummy gate structure 200 includes a gate oxide layer, an isolation layer, and a polysilicon layer. The gate oxide layer is arranged on the substrate 100, and the gate oxide layer is a high-K material. The isolation layer is arranged on the gate oxide layer, and the isolation layer is, for example, titanium nitride (TiN). The polysilicon layer is arranged on the isolation layer.

[0035] It should be noted that there are various different sizes of dummy gate structures 200 on the wafer. For example, Figure 1 The dummy gate structure 200 with the first width W1, the second width W2, and the third width W3 is shown. In the present embodiment, the first width W1 is smaller than the second width W2, and the second width W2 is smaller than the third width W3. In addition, the spacing between different dummy gate structures 200 on the wafer is also different. In the dense pattern area, the spacing between adjacent dummy gate structures 200 is small. In the sparse pattern area, the spacing between adjacent dummy gate structures 200 is large. For example, Figure 1 The distribution diagram of the dummy gate structure 200 with the first spacing D1 and the second spacing D2 is shown, wherein the first spacing D1 is smaller than the second spacing D2.

[0036] As shown in the figure, Figure 1As shown, in the present application, a stack structure is formed on the dummy gate structure 200. First, a first nitride layer 300 is formed on the dummy gate structure 200, and the first nitride layer 300 covers the top surface of the dummy gate structure 200. Specifically, silicon nitride is deposited on the dummy gate structure 200 and the substrate 100 by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD), and then part of the deposited silicon nitride is etched and removed, and only the silicon nitride on the top surface of the dummy gate structure 200 is retained, thereby forming the first nitride layer 300. In this embodiment, the first nitride layer 300 formed on the plurality of dummy gate structures 200 has the same thickness. Then, an oxide layer 400 is formed on the first nitride layer 300. The oxide layer 400 can be formed by depositing silicon oxide by chemical vapor deposition or plasma enhanced chemical vapor deposition. In the step of forming the oxide layer 400, part of the oxide layer 400 is deposited on the surface of the substrate 100 and the surface of the dummy gate structure 200 during the deposition process. Therefore, after the deposition process, the deposited material outside the surface of the first nitride layer 300 can be removed by dry etching. In the present application, the thickness of the oxide layer 400 is inversely proportional to the width of the dummy gate structure 200. In this embodiment, the thickness of the oxide layer 400 above the dummy gate structure 200 with the first width W1 is a third thickness H3, the thickness of the oxide layer 400 above the dummy gate structure 200 with the second width W2 is a second thickness H2, and the thickness of the oxide layer 400 above the dummy gate structure 200 with the first width W1 is a first thickness H1. The first thickness H1 is less than the second thickness H2, and the second thickness H2 is less than the third thickness H3. Then, a second nitride layer 500 is formed on the exposed surface of the dummy gate structure 200, the exposed surface of the first nitride layer 300, and the exposed surface of the oxide layer 400. The second nitride layer 500 can be formed by depositing silicon nitride by chemical vapor deposition or plasma enhanced chemical vapor deposition. It should be noted that in the step of forming the second nitride layer 500, part of the deposited material is deposited on the substrate 100, and part of the deposited material on the substrate 100 is removed by dry etching after deposition.

[0037] See Figure 2 and Figure 3As shown, in this invention, after forming the second nitride layer 500, a dielectric layer 600 is then formed on the substrate 100 and the second nitride layer 500. The dielectric layer 600 located on the surface of the second nitride layer 500 is then removed, and the remaining dielectric layer 600 is defined as the first dielectric film 601a. ​​Specifically, silicon oxide is deposited on the substrate 100 and the surface of the second nitride layer 500 by chemical vapor deposition or plasma-enhanced chemical vapor deposition. Then, the dielectric layer 600 on the top surface of the second nitride layer 500 is removed by chemical mechanical polishing (CMP). In the step of removing the dielectric layer 600 on the top surface of the second nitride layer 500, a portion of the second nitride layer 500 can be removed, thereby ensuring that the top surface of the second nitride layer 500 above each dummy gate structure 200 is exposed.

[0038] Please see Figure 3 and Figure 4 As shown, in one embodiment of the present invention, after removing the dielectric layer 600 on the top surface of the second nitride layer 500, the entire second nitride layer 500 above the oxide layer 400 is etched away. In this embodiment, the entire second nitride layer 500 on the oxide layer 400 can be removed by wet etching. The etchant used in the wet etching can be a high-selectivity etchant, where the etching ratio of silicon nitride to silicon oxide is much higher than that of silicon oxide, thereby ensuring that the oxide layer 400 is not overly damaged when removing the second silicon nitride layer. In this step, the surface of the oxide layer 400 is exposed.

[0039] Please see Figure 4 and Figure 5In the embodiment of the present application, after the second nitride layer 500 is removed from the top surface of the oxide layer 400, the first nitride layer 300 is used as a stop layer, and the oxide layer 400, the second nitride layer 500 and the first dielectric film 601a are polished until the top surface of the first nitride layer 300 above the entire dummy gate structure 200 is exposed. After the polishing, the top surfaces of the first nitride layer 300, the second nitride layer 500 and the first dielectric film 601a are flush. In the polishing step, the oxide layer 400 with a large thickness is first contacted with the polishing surface, and then the oxide layer 400 with a small thickness is contacted with the polishing surface. For example, in the embodiment, the oxide layer 400 with the third thickness H3 is first contacted with the polishing surface, then the oxide layer 400 with the second thickness H2 is contacted with the polishing surface, and then the oxide layer 400 with the first thickness Hl is contacted with the polishing surface. In the polishing step, the polishing speed of the first dielectric film 601a is higher than that of the nitride layer. In the embodiment, after the etching step, because of the etching selectivity, the top surface of the first dielectric film 601a is higher than the surface of the second nitride layer 500, and the surface of the second nitride layer 500 is lower than or equal to the surface of the oxide layer 400. In addition, the top surface of the second nitride layer 500 is higher than the surface of the first nitride layer 300. In the polishing step, during the etching, the first dielectric film 601a and the oxide layer 400 are first contacted with the polishing surface and polished, and then the second nitride layer 500 is also contacted with the polishing surface and polished. Until the entire oxide layer 400 is removed, the first nitride layer 300 is exposed, and then the second nitride layer 500 is polished until the surface of the second nitride layer 500 is flush with the surface of the first nitride layer 300. After the polishing step is completed, the dielectric material covering the surface of the substrate 100 is not affected.

[0040] Please refer to Figures 5 to 7As shown in FIG. 6, in one embodiment of the present application, after the oxide layer 400 is removed, a first dielectric deposition layer 602a is formed on the first nitride layer 300, the first dielectric film 601a and the second nitride layer 500 until the first dielectric deposition layer 602a between the adjacent dummy gate structures 200 is higher than the surface of the first nitride layer 300. The silicon oxide can be deposited on the first nitride layer 300, the first dielectric film 601a and the second nitride layer 500 by chemical vapor deposition or plasma enhanced chemical vapor deposition. The first dielectric deposition layer 602a and the first dielectric film 601a are made of the same material and are connected to form an integral whole after the deposition. During the deposition, the dielectric material covers the first nitride layer 300 and the second nitride layer 500. Then, the first dielectric deposition layer 602a is polished to remove part of the first dielectric deposition layer 602a until the surface of the first dielectric deposition layer 602a, the second nitride layer 500 and the first nitride layer 300 are flush. During the polishing step, only the dielectric material is removed, so the polishing rate is balanced and the surface of the first dielectric deposition layer 602a, the second nitride layer 500 and the first nitride layer 300 can be flush.

[0041] As shown in FIG. 6, in one embodiment of the present application, after the oxide layer 400 is removed, a first dielectric deposition layer 602a is formed on the first nitride layer 300, the first dielectric film 601a and the second nitride layer 500 until the first dielectric deposition layer 602a between the adjacent dummy gate structures 200 is higher than the surface of the first nitride layer 300. The silicon oxide can be deposited on the first nitride layer 300, the first dielectric film 601a and the second nitride layer 500 by chemical vapor deposition or plasma enhanced chemical vapor deposition. The first dielectric deposition layer 602a and the first dielectric film 601a are made of the same material and are connected to form an integral whole after the deposition. During the deposition, the dielectric material covers the first nitride layer 300 and the second nitride layer 500. Then, the first dielectric deposition layer 602a is polished to remove part of the first dielectric deposition layer 602a until the surface of the first dielectric deposition layer 602a, the second nitride layer 500 and the first nitride layer 300 are flush. During the polishing step, only the dielectric material is removed, so the polishing rate is balanced and the surface of the first dielectric deposition layer 602a, the second nitride layer 500 and the first nitride layer 300 can be flush. Figure 7 Figure 8 As shown in FIG. 6, in one embodiment of the present application, after the oxide layer 400 is removed, a first dielectric deposition layer 602a is formed on the first nitride layer 300, the first dielectric film 601a and the second nitride layer 500 until the first dielectric deposition layer 602a between the adjacent dummy gate structures 200 is higher than the surface of the first nitride layer 300. The silicon oxide can be deposited on the first nitride layer 300, the first dielectric film 601a and the second nitride layer 500 by chemical vapor deposition or plasma enhanced chemical vapor deposition. The first dielectric deposition layer 602a and the first dielectric film 601a are made of the same material and are connected to form an integral whole after the deposition. During the deposition, the dielectric material covers the first nitride layer 300 and the second nitride layer 500. Then, the first dielectric deposition layer 602a is polished to remove part of the first dielectric deposition layer 602a until the surface of the first dielectric deposition layer 602a, the second nitride layer 500 and the first nitride layer 300 are flush. During the polishing step, only the dielectric material is removed, so the polishing rate is balanced and the surface of the first dielectric deposition layer 602a, the second nitride layer 500 and the first nitride layer 300 can be flush.

[0042] As shown in FIG. 6, in one embodiment of the present application, after the oxide layer 400 is removed, a first dielectric deposition layer 602a is formed on the first nitride layer 300, the first dielectric film 601a and the second nitride layer 500 until the first dielectric deposition layer 602a between the adjacent dummy gate structures 200 is higher than the surface of the first nitride layer 300. The silicon oxide can be deposited on the first nitride layer 300, the first dielectric film 601a and the second nitride layer 500 by chemical vapor deposition or plasma enhanced chemical vapor deposition. The first dielectric deposition layer 602a and the first dielectric film 601a are made of the same material and are connected to form an integral whole after the deposition. During the deposition, the dielectric material covers the first nitride layer 300 and the second nitride layer 500. Then, the first dielectric deposition layer 602a is polished to remove part of the first dielectric deposition layer 602a until the surface of the first dielectric deposition layer 602a, the second nitride layer 500 and the first nitride layer 300 are flush. During the polishing step, only the dielectric material is removed, so the polishing rate is balanced and the surface of the first dielectric deposition layer 602a, the second nitride layer 500 and the first nitride layer 300 can be flush. Figure 3 Figure 9 ​​As shown, in another embodiment of the present invention, after forming the dielectric layer 600, a portion of the dielectric layer 600 located on the second nitride layer 500 is etched away, and a portion of the second nitride layer 500 and a portion of the dielectric layer 600 located at the top corner of the dummy gate structure 200 are also removed, thereby increasing the deposition window size between adjacent dummy gate structures 200 and forming a second dielectric film 601b. In this embodiment, the etching of the portion of the dielectric layer 600 and the second nitride layer 500 can be done using dry etching, and different plasma gases can be used to first remove the dielectric layer 600 located on top of the dummy gate structure 200, and then remove a portion of the second nitride layer 500 and a portion of the dielectric layer 600 located at the top corner of the dummy gate structure 200, forming a chamfer structure at the corner of the dummy gate structure 200. During subsequent deposition of dielectric materials, the chamfer structure facilitates the formation of a dielectric deposition layer without internal bubbles or voids.

[0043] Please see Figures 9 to 11 As shown, in another embodiment of the present invention, after forming the chamfered structure, a second dielectric deposition layer 602b is then formed on the second dielectric film 601b and the second nitride layer 500. Using the second nitride layer 500 as a stop layer, a portion of the second dielectric deposition layer 602b is polished away. Then, using the oxide layer 400 as a stop layer, a portion of the second nitride layer 500 is polished away. In this embodiment, in the step of forming the second dielectric deposition layer 602b, silicon oxide is deposited by chemical vapor deposition until the deposition height of the silicon oxide material is greater than the maximum height of the dummy gate structure 200. After two polishing operations, due to the loading effect, the surfaces of the dummy gate structures 200 with different widths, and the dummy gate structures 200 located in the dense region and the gate region, are not flush. Furthermore, in the dense region, the larger the width of the dummy gate structure 200, the higher the surface height of the oxide layer 400 after polishing.

[0044] Please see Figures 11 to 13 As shown, in another embodiment of the present invention, the first nitride layer 300 is used as a stop layer, and the oxide layer 400, a portion of the second dielectric deposition layer 602b, and a portion of the second nitride layer 500 are removed by polishing. After polishing, the surfaces of the second nitride layer 500, the first nitride layer 300, and the second dielectric deposition layer 602b are flush. Next, the second nitride layer 500 is removed by polishing. After removing the second nitride layer 500, the surfaces of the dummy gate structure 200, the second nitride layer 500, and the second dielectric deposition layer 602b are flush, resulting in a semiconductor structure. Based on the semiconductor structure obtained in this embodiment, a high-k metal gate structure can be formed by subsequently etching away the polysilicon layer in the dummy gate structure 200, replacing the polysilicon layer, and depositing metal material.

[0045] The application provides a semiconductor structure manufacturing method and a semiconductor structure, and the manufacturing method comprises the following steps: providing a plurality of pseudo gate structures, and the pseudo gate structures are arranged on a substrate; forming a first nitride layer on top surfaces of the pseudo gate structures; forming an oxide layer on the first nitride layer; wherein the greater the width of the pseudo gate structure is, the smaller the thickness of the oxide layer on the pseudo gate structure is; forming a second nitride layer on the oxide layer, the first nitride layer and exposed surfaces of the pseudo gate structures; forming a dielectric layer on the first nitride layer and the substrate; sequentially removing the dielectric layer, the second nitride layer and the oxide layer on the pseudo gate structures until the surfaces of the first nitride layer and the second nitride layer are flush; and removing the first nitride layer and part of the second nitride layer so that the surfaces of the first nitride layer and the pseudo gate structures are flush. The application has the unexpected technical effect that the application provides a manufacturing method for forming a high-K metal gate, which can overcome the load effect, form a metal gate with high surface flatness, and at the same time, is beneficial to reducing the possibility of defects such as cavities and bubbles in the metal gate forming process, thereby improving the effectiveness of the semiconductor structure and the forming yield of the semiconductor process.

[0046] The above disclosed embodiments of the application are only used to help explain the application. The embodiments do not describe all the details, nor limit the application to the specific embodiments. Obviously, according to the content of the specification, many modifications and changes can be made. The specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the application, so that those skilled in the art can well understand and utilize the application. The application is limited by the claims and their entire scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: Multiple pseudo-gate structures are provided, and the pseudo-gate structures are disposed on a substrate; A first nitride layer is formed on the top surface of the pseudo-gate structure, and an oxide layer is formed on the first nitride layer, wherein the wider the pseudo-gate structure, the smaller the thickness of the oxide layer on the pseudo-gate structure; A second nitride layer is formed on the exposed surfaces of the oxide layer, the first nitride layer, and the pseudo-gate structure; A dielectric layer is formed on the first nitride layer and on the substrate; Remove the dielectric layer, the second nitride layer, and the oxide layer from the pseudo-gate structure until the surfaces of the first nitride layer and the second nitride layer are flush. as well as Remove the first nitrided layer and part of the second nitrided layer so that the surface of the second nitrided layer and the pseudo-gate structure are flush.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, When removing the second nitride layer and the oxide layer on the pseudo-gate structure, the second nitride layer located on the oxide layer is first removed by wet etching until the surface of the oxide layer is exposed.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, After exposing the surface of the oxide layer, the oxide layer, part of the second nitride layer, and part of the dielectric layer are removed by polishing, using the first nitride layer as the stop layer.

4. The method for manufacturing a semiconductor structure according to claim 3, characterized in that, Before removing the first nitride layer, a dielectric deposition layer is formed on the first nitride layer, the second nitride layer, and the dielectric layer until the dielectric deposition layer located between adjacent pseudo-gate structures is above the surface of the first nitride layer.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, In the step of removing the first nitride layer and a portion of the second nitride layer, the first nitride layer is used as a stop layer to polish and remove a portion of the dielectric deposition layer. The surface of the dummy gate structure is used as a stop layer to remove the first nitride layer, a portion of the second nitride layer, and a portion of the dielectric deposition layer. In the obtained semiconductor structure, the surfaces of the second nitride layer, the dielectric deposition layer, and the dummy gate structure are flush.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, After forming the dielectric layer, the dielectric layer located on top of the pseudo-gate structure is removed, and a portion of the second nitride layer and a portion of the dielectric layer located at the corners of the pseudo-gate structure are removed.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that, After removing the dielectric layer located on the pseudo-gate structure, and before removing the second nitride layer located on the pseudo-gate structure, a dielectric deposition layer is formed on the dielectric layer and the second nitride layer, wherein the surface of the dielectric deposition layer located between adjacent pseudo-gate structures is higher than the surface of the second nitride layer.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that, After the dielectric deposition layer is formed, a portion of the dielectric deposition layer and a portion of the second nitride layer located on the pseudo-gate structure are polished away until the surface of the oxide layer is exposed.

9. A method for manufacturing a semiconductor structure according to claim 8, characterized in that, After exposing the oxide layer, the oxide layer, a portion of the second nitride layer, and a portion of the dielectric deposition layer are polished away using the first nitride layer as a stop layer. Then, the first nitride layer, a portion of the second nitride layer, and a portion of the dielectric deposition layer are polished away using the surface of the dummy gate structure as a stop layer, to obtain the semiconductor structure. In the obtained semiconductor structure, the surfaces of the second nitride layer, the dielectric deposition layer, and the dummy gate structure are flush.

10. A semiconductor structure, based on a method for manufacturing a semiconductor structure according to any one of claims 1-9, characterized in that, include: substrate; Multiple pseudo-gate structures are disposed on the substrate; A second nitriding layer covers the side of the pseudo-gate structure; as well as A dielectric deposition layer is disposed on the substrate, and the dielectric layer fills the space between adjacent pseudo-gate structures, wherein the top surface of the pseudo-gate structure, the top surface of the second nitride layer, and the top surface of the dielectric deposition layer are flush.

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