Multi-layer stacked chip using Micro-LED photoelectric hybrid vertical interconnection and packaging method
By introducing a Micro-led optoelectronic hybrid interconnect structure between SoC chips, the problem of density limitation of traditional through-silicon vias is solved, achieving higher data transmission bandwidth and lower packaging difficulty, and improving signal integrity and chip reliability.
Patent Information
- Application Number
- CN202511322319.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-16
- Publication Date
- 2025-11-18
AI Technical Summary
The computing bandwidth between traditional logic computing chips and memory chips is limited by the density of through-silicon vias and microbumps, resulting in tight packaging space, high processing complexity, increased manufacturing difficulty and cost, and difficulty in guaranteeing signal integrity.
The multi-layer stacked chip structure with micro-led optoelectronic hybrid vertical interconnection is adopted. By introducing optoelectronic components between SoC chips to form optical signal transmission channels, the dependence on silicon via density is reduced, and signal transmission between chips is carried out by using optical emitting units and optical receiving units.
It increases the data transmission bandwidth between chips, reduces the complexity of the packaging process, enhances signal integrity, reduces electromagnetic interference, and improves the reliability and heat dissipation performance of the chips.
Smart Images
Figure CN120980941A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and in particular to a multilayer stacked chip and packaging method using Micro-led optoelectronic hybrid vertical interconnects. Background Technology
[0002] Traditionally, the computing bandwidth between logic chips and memory chips is highly dependent on the density of through-silicon vias (TSVs) and microbumps used for their interconnection. To achieve higher computing performance, logic chips typically integrate more transistors, but this often leads to a corresponding increase in chip size. Within a fixed package space, larger chips further compress the already limited vertical interconnect wiring resources, making the physical space available for arranging TSVs and microbumps even more scarce.
[0003] Therefore, to improve the data transmission bandwidth between chips in multi-layer vertical stacking architectures, the mainstream industry solution is to continuously increase the number and integration density of TSVs and microbumps. However, this approach faces significant challenges when dealing with multi-layer stacking (such as the 3D integration of HBM with advanced computing chips). The dramatic increase in the number of TSVs and microbumps makes the processing accuracy, alignment error, thermal stress management, and signal integrity control of the interconnect structure extremely complex, thus significantly increasing the manufacturing difficulty and cost of the packaging process. This not only places near-limit requirements on processes such as photolithography, etching, and bonding, but also poses a severe test to the heat dissipation efficiency and long-term reliability of the entire packaging structure. Summary of the Invention
[0004] This invention provides a multilayer stacked chip and packaging method using Micro-led optoelectronic hybrid vertical interconnect, the purpose of which is to increase the bandwidth of data transmission between chips while keeping the packaging space unchanged.
[0005] To achieve the above objectives, embodiments of the present invention provide a multilayer stacked chip using Micro-led optoelectronic hybrid vertical interconnects, comprising:
[0006] A substrate on which a SoC chip is electrically connected, the SoC chip comprising:
[0007] The first SoC chip is flip-chip mounted on the substrate and electrically connected to the substrate;
[0008] At least one second SoC chip, a plurality of second SoC chips are stacked vertically and electrically connected, and the bottommost second SoC chip is electrically connected to the first SoC chip;
[0009] The multilayer stacked chip also includes optoelectronic components, which include an optical emitting unit for emitting optical signals and an optical receiving unit for emitting optical signals. The optoelectronic components are respectively disposed between adjacent SoC chips and electrically connected to the SoC chips.
[0010] Preferably, the first SoC chip includes a first redistribution layer disposed on the back side of the first SoC chip, and the first SoC chip also has a first through-silicon via (TSV), which is electrically connected to the first redistribution layer.
[0011] Preferably, the substrate is further provided with a first solder ball, and the substrate and the first through-silicon via are electrically connected through the first solder ball.
[0012] Preferably, the second SoC chip located in the middle layer includes a second redistribution layer located on the front and back sides of the second SoC chip, and the second SoC chip also has a second through-silicon via (TSV) electrically connected to the second redistribution layer;
[0013] The second SoC chip located at the top layer includes a third redistribution layer disposed on the front side of the second SoC chip at the top layer, and the third redistribution layer is electrically connected to a second through-silicon via on the second SoC chip at the top layer.
[0014] Preferably, a second solder ball is provided between adjacent second SoC chips and between the second SoC chip and the first SoC chip. The second solder ball is used to electrically connect adjacent second SoC chips or to electrically connect the first SoC chip and the second SoC chip.
[0015] Preferably, a plurality of the optoelectronic components are arranged vertically between the first SoC chip and the second SoC chip or between adjacent second SoC chips, and the light transmission directions of adjacent optoelectronic components are opposite;
[0016] The optical emitting unit is Mciro-led, and the optical receiving unit is a PD.
[0017] This application also provides a packaging method for the aforementioned multilayer stacked chip using Micro-led optoelectronic hybrid vertical interconnects, comprising:
[0018] S10. Fabricate a first SoC chip and a second SoC chip with corresponding through-silicon vias and redistribution layers;
[0019] S20. The light emitting unit and the light receiving unit in the optoelectronic component are respectively bonded to the first SoC chip and the second SoC chip;
[0020] S30. Electroplating solder balls on copper pillars of redistribution layers or through-silicon vias, and achieving vertical stacking of SoC chips with substrates or SoC chips through thermo-press bonding.
[0021] Preferably, step S10 includes steps S11-S13.
[0022] Step S11 includes: etching a through hole on a silicon wafer, depositing an insulating layer in the through hole and on both sides of the silicon wafer, or depositing an insulating layer in the through hole and on one side of the silicon wafer, depositing a barrier layer and a seed layer in sequence on the insulating layer in the through hole, and then forming a copper pillar in the through hole by electroplating.
[0023] Step S12 includes: depositing a metal layer on at least one of the insulating layers on both sides of the silicon wafer, patterning the metal layer to form a redistribution layer, and marking the redistribution layer with punctuation marks for positioning optoelectronic components.
[0024] Step S13 includes: depositing a passivation layer on the redistribution layer, and making windows at the corresponding marked positions on the passivation layer to form a SoC chip.
[0025] Preferably, in this step S20, the light emitting unit and the light receiving unit are bonded to the markings on the redistribution layer using low-temperature solder;
[0026] On one surface of the same SoC, the light emitting unit and the light receiving unit are arranged in a matrix, and the light emitting unit and the light receiving unit are alternately set.
[0027] Preferably, the first or second solder ball is electroplated on the copper pillar of each through-silicon via, and the SoC chip is bonded layer by layer by hot pressing to form a vertical interconnect structure, and the light emitting unit and light receiving unit of a pair of optoelectronic components between adjacent SoC chips are located on the same straight line in the vertical direction.
[0028] The above-described solution of the present invention has the following beneficial effects:
[0029] In this application, by introducing optoelectronic components into the electrical interconnect architecture to form optical interconnects, the signal transmission paths between chips are significantly increased. This approach effectively reduces the dependence on through-silicon via (TSV) density, achieving higher transmission bandwidth while significantly reducing the complexity of the packaging process. Furthermore, the optoelectronic components between SoC chips construct independent optical signal transmission channels, possessing inherent immunity to electromagnetic interference, and exhibiting extremely low crosstalk between these optical channels. Compared to the increasingly severe crosstalk, signal attenuation, and ground bounce noise problems that arise with increasing frequency and density in traditional electrical interconnects, this optical interconnect solution maintains excellent signal integrity even at ultra-high data transmission rates.
[0030] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description
[0031] Figure 1 This is a cross-sectional view of the present invention (partially omitting the second SoC chip);
[0032] Figure 2 This is a schematic diagram showing the arrangement of optoelectronic components on the second SoC chip.
[0033] [Explanation of Labels in the Attached Image]
[0034] 10-Substrate,
[0035] 20 - First SoC chip, 21 - First redistribution layer, 22 - First through-silicon via, 23 - First solder ball
[0036] 30 - Second SoC chip, 32 - Second redistribution layer, 33 - Second through-silicon via, 34 - Third redistribution layer, 35 - Second solder ball,
[0037] 41-Optical transmitting unit, 42-Optical receiving unit. Detailed Implementation
[0038] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.
[0039] like Figures 1-2 As shown, an embodiment of the present invention provides a multilayer stacked chip with optoelectronic hybrid interconnect, comprising a substrate 10, a SoC chip, and optoelectronic components. The SoC chip is disposed above the substrate 10 and includes a first SoC chip 20 and at least one second SoC chip 30. The first SoC chip 20 is flip-chip mounted on the substrate 10 and electrically connected to it. When there is one second SoC chip 30, it is flip-chip mounted on the first SoC chip 20 and electrically connected to it. When there are two or more second SoC chips 30, they are stacked sequentially along the vertical direction, i.e., one second SoC chip 30 is flip-chip mounted on another and electrically connected. The bottommost second SoC chip 30 of the multiple vertically stacked second SoC chips 30 is flip-chip mounted on the first SoC chip 20 and electrically connected to it.
[0040] The aforementioned optoelectronic components include a light emitting unit 41 and a light receiving unit 42, wherein the light emitting unit 41 is used to emit light signals, and the light receiving unit 42 is used to receive the emitted light signals. The optoelectronic components are respectively disposed between adjacent SoC chips and electrically connected to the SoC chips.
[0041] It is understandable that adjacent SoC chips can be between two adjacent second SoC chips 30. For example, an optical emitting unit 41 is disposed on one side of one second SoC chip 30, and an optical receiving unit 42 is disposed on one side of the other second SoC chip 30. The two second SoC chips 30 are adjacent, and the sides of the two second SoC chips 30 with the optical emitting unit 41 and the optical receiving unit 42 facing each other, so that the optical receiving unit 42 can receive the optical signal emitted by the optical emitting unit 41. Adjacent SoC chips can also be a second SoC chip 30 and a first SoC chip 20. For example, an optical emitting unit 41 is disposed on one side of a second SoC chip 30, and an optical receiving unit 42 is disposed on one side of a first SoC chip 20. The second SoC chip 30 is flip-chip mounted on the first SoC chip 20, and the side of the second SoC chip 30 with the optical emitting unit 41 faces the side of the first SoC chip 20 with the optical receiving unit 42, so that the optical receiving unit 42 can receive the optical signal emitted by the optical emitting unit 41.
[0042] In this application, based on the traditional TSV multilayer stacking, the optical emitting unit 41 and the optical receiving unit 42 are laid flat on the surface of the multilayer stacked chip to form an inter-chip optical interconnect, which increases the number of signal transmission paths between chips and can effectively reduce the density of through silicon vias, thereby increasing the transmission bandwidth while reducing the packaging difficulty.
[0043] Furthermore, the first SoC chip 20 includes a first redistribution layer 21 (RDL), which is disposed on the back side of the first SoC chip 20, i.e., the side away from the substrate 10. A first through-silicon via (TSV) 22 is also formed on the first SoC chip 20, and the TSV 22 is electrically connected to the first redistribution layer 21. The aforementioned light emitting unit 41 and / or light receiving unit 42 are disposed on the first SoC chip 20 and electrically connected to the first redistribution layer 21.
[0044] A first solder ball 23 is also provided on the substrate 10, and the substrate 10 and the first push hole are electrically connected through the first solder ball 23.
[0045] Understandably, in the through-silicon via (TSV) process, copper pillars are typically deposited within the TSV. These copper pillars are electrically connected to the first redistribution layer 21 and the first solder ball 23, thereby enabling the light emitting unit 41 and / or the light receiving unit 42 located on the first SoC chip 20 to be electrically connected to the substrate 10.
[0046] For the second SoC chip 30, the second SoC chip 30 located in the intermediate layer includes a second redistribution layer 32, which is located on the front and back sides of the intermediate layer second SoC chip 30. The second SoC chip 30 has a second through silicon via 33, which is electrically connected to the second redistribution layer 32 located on the front and back sides of the second SoC chip 30.
[0047] The topmost second SoC chip 30 includes a third redistribution layer 34, which is located on the front side of the topmost second SoC chip 30. The topmost second SoC chip 30 also includes a second through-silicon via 33, which is electrically connected to the third redistribution layer 34.
[0048] Furthermore, second solder balls 35 are provided between adjacent second SoC chips 30 and between the second SoC chip 30 and the first SoC chip 20. The second solder balls 35 are used to electrically connect adjacent second SoC chips 30 or to electrically connect the first SoC chip 20 and the second SoC chip 30.
[0049] In this embodiment, the first SoC chip 20 and the second SoC chip 30 adjacent to the first SoC chip 20 are electrically connected via second solder balls 35. Specifically, since the second SoC chip 30 adjacent to the first SoC chip 20 has a second redistribution layer 32 on both its front and back surfaces, the first SoC chip 20 and the second SoC chip 30 adjacent to the first SoC chip 20 can be electrically connected to each other via the second solder balls 35 and the second redistribution layers 32 of the first SoC chip 20 and the second SoC chip 30. Similarly, two adjacent second SoC chips 30 can also be electrically connected in the vertical direction via the second solder balls 35. In this way, the first SoC chip 20, the multiple second SoC chips 30, and the substrate 10 are electrically connected in the vertical direction. The optoelectronic component is disposed between adjacent second SoC chips 30 or between the first SoC chip 20 and the second SoC chip 30 to achieve electrical connection with the substrate 10.
[0050] The aforementioned optoelectronic components are arranged vertically between the first SoC chip 20 and the second SoC chip 30, or vertically between adjacent second SoC chips 30, with the light transmission directions of adjacent optoelectronic components being opposite.
[0051] Specifically, the optoelectronic components are arranged in multiple groups. Each group of optoelectronic components includes a light emitting unit 41 and a corresponding light receiving unit 42. The light receiving unit 42 and the light emitting unit 41 are located on the same straight line in the vertical direction. When the optoelectronic components are arranged between the first SoC chip 20 and the second SoC chip 30, the light emitting unit 41 can be mounted on the first SoC chip 20, and the corresponding light receiving unit 42 can be mounted on the second SoC chip 30; or the light emitting unit 41 can be mounted on the second SoC chip 30, and the light receiving unit 42 can be mounted on the first SoC chip 20.
[0052] Similarly, when the optoelectronic components are arranged between adjacent second SoC chips 30, the light emitting unit 41 can be located on the upper second SoC chip 30, and the corresponding light receiving unit 42 can be located on the lower second SoC chip 30; or the light receiving unit 42 can be located on the upper second SoC chip 30, and the corresponding light emitting unit 41 can be located on the lower second SoC chip 30.
[0053] In this application, the light emitting unit 41 and the light receiving unit 42 located on the same SoC chip are arranged in a hybrid matrix, that is, the light emitting unit 41 and the light receiving unit 42 are arranged in a rectangular array, with one light emitting unit 41 surrounded by a light receiving unit 42, and one light receiving unit 42 surrounded by a light emitting unit 41.
[0054] By utilizing the alternating arrangement of optical signal transmission directions, the optoelectronic components can achieve parallel transmission through bidirectional independent optical channels, reducing the waiting time for bidirectional interaction and thus optimizing transmission latency. Simultaneously, the alternating arrangement of the optical emitting unit 41 and the optical receiving unit 42 between adjacent chip layers not only effectively reduces crosstalk between adjacent channels on the same side caused by light divergence, significantly improving signal transmission accuracy, but also disperses the heat generated by the optical emitting unit 41 to different chip layers, improving heat distribution and enhancing system heat dissipation performance.
[0055] Preferably, in this embodiment, the light emitting unit 41 is a Micro-led, and the light receiving unit 42 is a PD (photodetector).
[0056] Micro-led, as a preferred light emitting unit 41, has strong anti-interference capabilities and is unaffected by reflection interference and coherent noise, resulting in higher stability in complex packaging environments. Its high-temperature resistance makes this product more suitable for chip stacking scenarios at high temperatures. As a self-emissive device, Micro-led has no threshold limitation, maintains high efficiency even with low data volume, and has lower dynamic power consumption.
[0057] In this application, optical interconnection using optoelectronic components is employed on top of electrical interconnection to improve the signal transmission path between chips, reducing the density of through-silicon vias (TSVs). This increases transmission bandwidth while also reducing packaging complexity. Simultaneously, the optoelectronic components between SoC chips form independent optical channels for optical signal transmission. These optical signals are immune to electromagnetic interference, and crosstalk between different optical channels is extremely low. This contrasts sharply with the problems of crosstalk, attenuation, and ground bounce noise that rapidly worsen with increasing frequency and density in traditional electrical interconnection, ensuring signal quality at ultra-high data transmission rates.
[0058] Optical signal transmission inherently features low latency and low jitter, which can greatly reduce the timing uncertainty of data transmission between stacked chips. This is crucial for improving the performance of chips with stringent timing requirements, such as high-performance computers and artificial intelligence.
[0059] Because optoelectronic components are used for optical interconnection, it is not necessary to increase the transmission bandwidth of SoC chips by simply making more through-silicon vias. The density of through-silicon vias on each SoC chip is reduced. By reducing the number of through-silicon vias, this application can accommodate logic chips with stronger performance and larger area, while freeing up more packaging space for circuit layout.
[0060] The defect rate of through-silicon vias (TSVs) increases exponentially with increasing TSV density. This application significantly improves the yield of 3D chips by reducing the TSV density. Furthermore, reducing the TSV density effectively alleviates the thermal stress caused by the mismatch in the coefficients of thermal expansion between the copper pillars within the TSVs and the silicon wafer, thereby improving chip reliability.
[0061] Compared to traditional lasers, Micro-LEDs exhibit significant advantages in performance and integration: their miniaturization is remarkable (typical size 1-50μm), supporting ON-OFF modulation to achieve single-channel rates of several Gbps, and meeting Tbps-level aggregated bandwidth requirements through high-density array integration (100-1000 units per chip). In terms of energy efficiency, Micro-LEDs consume only a few hundred microwatts (1 / 100-1 / 1000 of laser power), and thanks to their structural and temperature insensitivity, their reliability and system compatibility are significantly improved, demonstrating great development potential.
[0062] This application also provides a packaging method for fabricating the aforementioned optoelectronic hybrid vertical interconnect multilayer stacked chip, which includes the following steps:
[0063] S10. Fabricate a first SoC chip 20 and a second SoC chip 30 with corresponding through-silicon vias and redistribution layers.
[0064] Taking the fabrication of the second SoC chip 30 as an example:
[0065] Through-holes are formed by etching on a silicon wafer. The location of these through-holes can be designed according to the structural characteristics of multilayer stacked chips. They are generally set at the edge of the silicon wafer. Insulating layers are deposited in the through-holes and on both sides of the silicon wafer. In this embodiment, the insulating layer is an oxide insulating layer, which is formed by chemical vapor deposition using silane or ethyl silicate.
[0066] A barrier layer and a seed layer are sequentially deposited on the insulating layer inside the through hole, and a copper pillar is formed inside the through hole by electroplating.
[0067] Metal layers are deposited on the insulating layers on both sides of the silicon wafer, ensuring that the metal layers are formed on the copper pillars and the insulating layers on both sides so that the metal layers can be electrically connected to the copper pillars. The metal layers are patterned to form a redistribution layer, which is the second redistribution layer 32. Markings are made on the redistribution layer to locate the optoelectronic components.
[0068] A passivation layer is deposited on the redistribution layer, and a window is made on the passivation layer. The window position corresponds to the mark position so that the mark is exposed, which facilitates the positioning and installation of optoelectronic components later.
[0069] The above describes the manufacturing process of the second SoC chip 30 in the middle layer. Unlike the manufacturing process of the middle second SoC chip 30, the first SoC chip 20 and the top second SoC chip 30 only need to deposit an insulating layer on one side of the silicon wafer during the manufacturing process, and then form a metal layer on the insulating layer.
[0070] S20. The light emitting unit 41 and the light receiving unit 42 in the optoelectronic component are respectively bonded to the first SoC chip 20 and the second SoC chip 30;
[0071] Plasma cleaning is performed on the light emitting unit 41, the light receiving unit 42, and the redistribution layer at the punctuation point. The light emitting unit 41 and the light receiving unit 42 are then bonded to the punctuation point of the redistribution layer using low-temperature solder.
[0072] It should be noted that in this embodiment, the light emitting unit 41 and the light receiving unit 42 are alternately arranged on the SoC chip along the length and width directions.
[0073] S30. Electroplating solder balls on copper pillars of the redistribution layer or through-silicon via, and achieving layer-by-layer stacking of the SoC chip with the substrate 10 or the SoC chip in the vertical direction through thermo-press bonding.
[0074] Specifically, first solder balls 23 are electroplated on the copper pillars of the first redistribution layer 21 or the first through-silicon via 22 of the first SoC chip 20, and vertical interconnection is achieved by thermo-press bonding of the first solder balls 23 with the pads on the substrate 10.
[0075] A second solder ball 35 is electroplated on the copper pillar of the second redistribution layer 32 or the second through-silicon via 33 of the second SoC chip 30, and vertical interconnection is achieved by thermo-press bonding of the second solder ball 35 with the first redistribution layer 21 of the first SoC chip 20 or the second redistribution layer 32 of the second SoC chip 30.
[0076] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A multilayer stacked chip using Micro-led optoelectronic hybrid vertical interconnect, characterized in that, include: A substrate (10) on which a SoC chip is electrically connected, the SoC chip comprising: The first SoC chip (20) is flip-chip mounted on the substrate (10) and electrically connected to the substrate (10); At least one second SoC chip (30), a plurality of second SoC chips (30) are stacked vertically and electrically connected, and the bottommost second SoC chip (30) is electrically connected to the first SoC chip (20); The multilayer stacked chip also includes optoelectronic components, which include an optical emitting unit (41) for emitting optical signals and an optical receiving unit (42) for emitting optical signals. The optoelectronic components are respectively disposed between adjacent SoC chips and electrically connected to the SoC chips.
2. The multilayer stacked chip using Micro-led optoelectronic hybrid vertical interconnect according to claim 1, characterized in that: The first SoC chip (20) includes a first redistribution layer (21) disposed on the back side of the first SoC chip (20), and the first SoC chip (20) also has a first through silicon via (22), which is electrically connected to the first redistribution layer (21).
3. The multilayer stacked chip using Micro-led optoelectronic hybrid vertical interconnect according to claim 2, characterized in that: The substrate (10) is further provided with a first solder ball (23), and the substrate (10) and the first through-silicon via (22) are electrically connected through the first solder ball (23).
4. The multilayer stacked chip using Micro-led optoelectronic hybrid vertical interconnect according to claim 3, characterized in that: The second SoC chip (30) located in the middle layer includes a second redistribution layer (32) located on the front and back sides of the second SoC chip (30), and the second SoC chip (30) also has a second through silicon via (33), which is electrically connected to the second redistribution layer (32); The second SoC chip (30) located at the top layer includes a third redistribution layer (34) disposed on the front side of the second SoC chip (30) at the top layer, and the third redistribution layer (34) is electrically connected to a second through-silicon via (33) on the second SoC chip (30) at the top layer.
5. The multilayer stacked chip using Micro-led optoelectronic hybrid vertical interconnect according to claim 4, characterized in that: A second solder ball (35) is provided between adjacent second SoC chips (30) and between the second SoC chip (30) and the first SoC chip (20). The second solder ball (35) is used to electrically connect adjacent second SoC chips (30) or to electrically connect the first SoC chip (20) and the second SoC chip (30).
6. The multilayer stacked chip using Micro-led optoelectronic hybrid vertical interconnect according to claim 5, characterized in that: A plurality of the aforementioned optoelectronic components are arranged vertically between the first SoC chip (20) and the second SoC chip (30) or between adjacent second SoC chips (30), and the light transmission directions of adjacent optoelectronic components are opposite; The optical emitting unit (41) is Mciro-led, and the optical receiving unit (42) is a PD.
7. A packaging method for a multilayer stacked chip using Micro-led optoelectronic hybrid vertical interconnect as described in claim 6, characterized in that, include: S10. Fabricate a first SoC chip (20) and a second SoC chip (30) with corresponding through-silicon vias and redistribution layers. S20. The light emitting unit (41) and the light receiving unit (42) in the optoelectronic component are respectively bonded to the first SoC chip (20) and the second SoC chip (30); S30. Electroplating solder balls on copper pillars of redistribution layers or through-silicon vias, and achieving vertical stacking of SoC chips with substrate (10) or SoC chips through thermo-press bonding.
8. The optoelectronic packaging method according to claim 7, characterized in that: Step S10 includes steps S11-S13. Step S11 includes: etching a through hole on a silicon wafer, depositing an insulating layer in the through hole and on both sides of the silicon wafer, or depositing an insulating layer in the through hole and on one side of the silicon wafer, depositing a barrier layer and a seed layer in sequence on the insulating layer in the through hole, and then forming a copper pillar in the through hole by electroplating. Step S12 includes: depositing a metal layer on at least one of the insulating layers on both sides of the silicon wafer, patterning the metal layer to form a redistribution layer, and marking the redistribution layer with punctuation marks for positioning optoelectronic components. Step S13 includes: depositing a passivation layer on the redistribution layer, and making windows at the corresponding marked positions on the passivation layer to form a SoC chip.
9. The packaging method according to claim 8, characterized in that: In this step S20, the light emitting unit (41) and the light receiving unit (42) are bonded to the markings of the redistribution layer using low-temperature solder; On one side of the same SoC, the light emitting unit (41) and the light receiving unit (42) are arranged in a matrix, and the light emitting unit (41) and the light receiving unit (42) are alternately set.
10. The packaging method according to claim 9, characterized in that: The first solder ball (23) or the second solder ball (35) is electroplated on the copper pillar of each through-silicon via, and the SoC chip is bonded layer by layer by hot pressing to form a vertical interconnect structure. The light emitting unit (41) and the light receiving unit (42) of a pair of optoelectronic components between adjacent SoC chips are located on the same straight line in the vertical direction.