Semiconductor structure, forming method, device and electronic device

Abstract

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a forming method, a device and an electronic device. The method comprises the following steps: providing an initial semiconductor structure; the initial semiconductor structure comprises a substrate and an epitaxial layer formed on the substrate; a first device region and a second device region are formed in the substrate, a first transistor is formed on the first device region, a second transistor is formed on the second device region, and the types of the first transistor and the second transistor are different; sequentially etching the epitaxial layer and the substrate corresponding to the junction of the first device region and the second device region, and forming an isolation groove in the substrate; filling an isolation material in the isolation groove to form a diffusion isolation structure; and forming a channel structure in the epitaxial layer corresponding to the first device region. According to the scheme, channel stress loss caused by etching of the channel structure is avoided, high compression stress of the channel structure is kept, the carrier mobility of the transistor is improved, and the device performance of the transistor is further improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure, a method of forming it, a device, and an electronic apparatus. Background Technology

[0002] With the development of semiconductor manufacturing processes, the size of transistors is gradually shrinking proportionally. As transistor size decreases, the current density in the device increases, making it crucial to improve carrier mobility to enhance transistor performance.

[0003] Since stress can alter the bandgap and carrier mobility of silicon, using stress to improve carrier mobility in transistors has become an increasingly common technique. In related technologies, germanium-silicon is typically used as the channel forming material to create the transistor channel, thereby introducing stress into the channel region to improve channel carrier mobility. However, due to the reduction in device size, to avoid leakage current between adjacent devices, diffusion isolation structures need to be fabricated between them during transistor manufacturing. However, the formation of these diffusion isolation structures requires etching away part of the channel structure, leading to channel stress loss, which reduces carrier mobility and degrades device performance. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a semiconductor structure, a method for forming it, a device, and an electronic apparatus.

[0005] In a first aspect, embodiments of this application disclose a method for forming a semiconductor structure, the method comprising:

[0006] An initial semiconductor structure is provided; the initial semiconductor structure includes a substrate and an epitaxial layer formed on the substrate; a first device region and a second device region are formed in the substrate, a first transistor is formed on the first device region, and a second transistor is formed on the second device region, the first transistor and the second transistor being of different types;

[0007] The epitaxial layer and substrate at the junction of the first device region and the second device region are etched sequentially to form an isolation groove in the substrate;

[0008] The isolation groove is filled with isolation material to form a diffusion isolation structure;

[0009] A channel structure is formed in the epitaxial layer corresponding to the first device region.

[0010] Secondly, embodiments of this application disclose a semiconductor structure, which is formed by the semiconductor structure formation method described above.

[0011] Thirdly, embodiments of this application disclose an electronic device, which includes the semiconductor structure described above.

[0012] Fourthly, embodiments of this application disclose an electronic device, which includes the electronic components described above.

[0013] The technical solution has the following technical effects:

[0014] The semiconductor structure, formation method, device, and electronic apparatus described in this application form a diffusion isolation structure by forming an isolation groove in a substrate and filling the isolation groove with an isolation material before forming a channel structure in the first device region. Since the diffusion isolation structure is formed before the channel structure is formed, it is not necessary to etch the channel structure to form the isolation groove after the channel structure is formed, thereby avoiding the channel stress loss caused by etching the channel structure, maintaining high compressive stress in the channel structure, improving the carrier mobility of the transistor, and thus improving the device performance of the transistor. Attached Figure Description

[0015] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure provided in an embodiment of this application;

[0017] Figures 2-7 This is a schematic diagram of a semiconductor structure formation process provided in an embodiment of this application.

[0018] The following is supplementary explanation of the attached figures:

[0019] 10-Substrate; 11-First device region; 12-Second device region; 20-Epipolar layer; 21-Channel structure; 30-Diffusion isolation structure; 40-Fin structure; 41-First fin structure; 42-Second fin structure; 43-Shallow trench isolation structure; 50-Gate structure; 51-Gate oxide layer. Detailed Implementation

[0020] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0021] It should be noted that the term "an embodiment" or "embodiment" in the specification of the embodiments of this application refers to a specific feature, structure, or characteristic that can be included in at least one implementation of this application. It should be understood that in the specification, claims, and accompanying drawings of the embodiments of this application, the terms "upper," "lower," "top," "bottom," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, in the description of this embodiment, unless otherwise stated, "a plurality of" means two or more. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, or product that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0022] To make the objectives, technical solutions, and advantages disclosed in the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of this application and are not intended to limit the embodiments of this application.

[0023] In related technologies, in the fabrication process of FinFETs based on Complementary Metal Oxide Semiconductor (CMOS) technology, the diffusion isolation between N-type Metal Oxide Semiconductor (PMOS) and P-type Metal Oxide Semiconductor (PMOS) is fabricated after the fin structure is formed. During the formation of the diffusion isolation between NMOS and PMOS, a portion of the channel structure is etched away. When the PMOS channel structure is formed using germanium-silicon material, etching away part of the channel structure causes stress release in the PMOS channel, reducing carrier mobility and thus degrading the performance of the PMOS device.

[0024] In view of this, embodiments of this application provide a semiconductor structure, a method for forming it, a device, and an electronic apparatus. Before forming a channel structure in a first device region, an isolation groove is formed in a substrate, and an isolation material is filled in the isolation groove to form a diffusion isolation structure. Since the diffusion isolation structure is formed before the channel structure is formed, it is not necessary to etch the channel structure to form the isolation groove after the channel structure is formed, thereby avoiding the channel stress loss caused by etching the channel structure, maintaining high compressive stress in the channel structure, improving the carrier mobility of the transistor, and thus improving the device performance of the transistor.

[0025] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for forming a semiconductor structure provided in an embodiment of this application, as shown below. Figure 1 As shown, the method includes:

[0026] S101: Provide an initial semiconductor structure; the initial semiconductor structure includes a substrate 10 and an epitaxial layer 20 formed on the substrate 10; a first device region 11 and a second device region 12 are formed in the substrate 10, the first device region 11 is used to form a first transistor, the second device region 12 is used to form a second transistor, and the first transistor and the second transistor are of different types.

[0027] In this embodiment, the initial semiconductor structure is obtained by processing an initial substrate. Specifically, an initial substrate is provided, and then a first device region 11 and a second device region 12 are formed in the initial substrate. An epitaxial layer 20 is formed on the initial substrate after the formation of the first device region 11 and the second device region 12 to obtain the initial semiconductor structure.

[0028] The initial substrate material can be suitable for process requirements or easy to integrate, such as silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, and indium gallium ionide. In some embodiments, the substrate 10 can be a thin film material substrate 10 on an insulator, such as a silicon on insulator substrate 10.

[0029] In this embodiment, the first device region 11 refers to the region on which a P-type metal-oxide-semiconductor (MOS) semiconductor is formed, i.e., the first device region 11 is a PMOS region. The second device region 12 refers to the region on which an N-type MOS semiconductor is formed, i.e., the second device region 12 is an NMOS region. The first device region 11 and the second device region 12 can be formed in the initial substrate by ion implantation. Specifically, the initial substrate can be a P-type substrate 10, such as a P-type silicon substrate 10. Optionally, by implanting N-type ions in a predetermined region on the initial substrate, an N-type region, i.e., the first device region 11, is formed in the initial substrate, while the region not implanted with N-type ions becomes the second device region 12.

[0030] In some embodiments, by performing two different ion implantations on different regions of the initial substrate, two hydrazine regions can be formed in the initial substrate, thereby obtaining the first device region 11 and the second device region 12. Specifically, Figure 2 This is a schematic diagram of the structure after forming a first device region 11 and a second device region 12 in an initial substrate, as provided in an embodiment of this application. Figure a is a top view, Figure b is a cross-sectional view along the X direction, and Figure c is a cross-sectional view along the Y direction. Figure 2 As shown, a first ion implantation mask is formed on the initial substrate, covering the surface of the initial substrate and exposing the initial substrate surface corresponding to the first device region 11. Then, the initial substrate is subjected to first ion implantation, transforming the implanted area into a first well region. The first ion is an N-type ion, including but not limited to ions formed by pentavalent elements such as phosphorus and arsenic. The first hydrazine region is an N-hydrazine region used to form a PMOS transistor. Next, the first ion implantation mask is removed, and a second ion implantation mask is formed on the initial substrate, covering the surface of the initial substrate and exposing the initial substrate surface corresponding to the second device region 12. Then, the initial substrate is subjected to second ion implantation, transforming the implanted area into a second well region. The first ion is a P-type ion, including but not limited to ions formed by trivalent elements such as boron and aluminum. The second hydrazine region is a P-hydrazine region used to form an NMOS transistor.

[0031] Figure 3 This is a schematic diagram of the structure after the epitaxial layer 20 on the substrate 10 provided in an embodiment of this application, wherein Figure a is a top view, Figure b is a cross-sectional view along the X direction, and Figure c is a cross-sectional view along the Y direction, as shown. Figure 3As shown, after forming the first device region 11 and the second device region 12 in the initial substrate, an epitaxial layer 20 is formed on the surface of the initial substrate by epitaxy. The epitaxial layer 20 is used to form the fin structure 40 in subsequent processing. Optionally, the material of the epitaxial layer 20 is silicon.

[0032] In this embodiment of the application, to avoid damage to the epitaxial layer 20 during subsequent processing, a protective layer of a predetermined thickness can be formed on the epitaxial layer 20 after its formation. Optionally, the protective layer is made of at least one of silicon oxide and silicon nitride. Optionally, the thickness of the protective layer is 50 angstroms to 200 angstroms, for example, 50 angstroms, 100 angstroms, 150 angstroms, 200 angstroms, etc.

[0033] S103: Sequentially etch the epitaxial layer 20 and the substrate 10 at the junction of the first device region 11 and the second device region 12 to form an isolation groove in the substrate 10.

[0034] In this embodiment, after obtaining the initial semiconductor structure, an isolation trench is formed in the substrate 10 by etching the initial semiconductor structure. Specifically, photoresist is coated on the protective layer, and the area above the junction of the first device region 11 and the second device region 12 is exposed. Pattern transfer is achieved through development, exposing the area above the junction of the first device region 11 and the second device region 12. Then, the protective layer and the epitaxial layer 20 above the junction of the first device region 11 and the second device region 12 are sequentially etched away. Next, the substrate is etched to form a trench of a predetermined depth in the substrate 10, which is the isolation trench. The isolation trench is formed at the junction of the first device region 11 and the second device region 12, i.e., one side of the isolation trench is the first device region 11, and the other side is the second device region 12. The depth of the isolation trench can be selected according to the thickness of the epitaxial layer 20 and the ion implantation depth of the first and second hydrazine regions. Simultaneously, the width of the isolation trench should not be too large or too small. The width of the isolation groove refers to the distance between the side of the isolation groove closest to the first device region 11 and the side of the isolation groove closest to the second device region 12. If the width of the isolation groove is too large, it will occupy too much space in the first device region 11 and the second device region 12, resulting in a smaller formation area for the first and second transistors, thereby increasing the manufacturing difficulty and affecting the device performance of the transistors. If the width of the isolation groove is too small, the diffusion isolation structure 30 formed in the isolation groove will be too thin, resulting in poor ion diffusion prevention by the diffusion isolation structure 30, which will cause leakage current between the first and second transistors.

[0035] S105: Fill the isolation groove with isolation material to form a diffusion isolation structure 30.

[0036] In this embodiment, the process of forming the diffusion isolation structure 30 in the isolation groove includes a high aspect ratio deposition process or an atomic layer deposition process. High aspect ratio deposition processes or atomic layer deposition processes have the characteristics of good gap filling performance and step coverage performance, which correspondingly improves the filling and coverage capability of the diffusion isolation structure 30, resulting in uniform thickness of the diffusion isolation structure 30.

[0037] In the embodiments of this application, Figure 4 This is a schematic diagram of the structure after the diffusion isolation structure 30 is formed in the initial semiconductor structure according to an embodiment of this application. Figure a is a top view, Figure b is a cross-sectional view along the X direction, and Figure c is a cross-sectional view along the Y direction. Figure 4 As shown, a diffusion isolation structure 30 is formed between the first device region 11 and the second device region 12 to prevent ions implanted in the first device region 11 from diffusing into the second device region 12, thereby avoiding any impact on the transistors formed on the second device region 12. Similarly, the diffusion isolation structure 30 also prevents ions implanted in the second device region 12 from diffusing into the first device region 11, thereby avoiding any impact on the transistors formed on the first device region 11, thus improving the performance of the semiconductor structure.

[0038] In this embodiment, the isolation material can be any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron nitride silicon, boron nitride silicon carbide, hafnium dioxide, and zirconium dioxide. In an optional embodiment, silicon nitride can be used as the isolation material. The stress of the silicon nitride material is adjustable. When forming the diffusion isolation structure 30, the silicon nitride can be adjusted to expand to apply compressive stress to the first device region 11, thereby improving the carrier mobility in the first transistor. In addition, using silicon nitride can also prevent the diffusion isolation layer from being etched away during the subsequent formation of the fin structure 40.

[0039] In some embodiments, after the diffusion isolation structure 30 is formed in the isolation groove, the diffusion isolation structure 30 can be ground to planarize its surface. During the grinding of the diffusion isolation structure 30, the protective layer can serve as a protection layer for the epitaxial layer 20 and a grinding stop layer. That is, grinding stops when the diffusion isolation structure 30 is flush with the protective layer.

[0040] In this embodiment, when the diffusion isolation structure 30 between the NMOS and PMOS is formed, the channel structure 21 in the PMOS has not yet been formed, so the stress in the PMOS channel will not be released, thereby avoiding the loss of stress in the PMOS channel.

[0041] S107: A channel structure 21 is formed in the epitaxial layer 20 corresponding to the first device region 11.

[0042] In this embodiment, after forming the diffusion isolation structure 30, a channel structure 21 can be formed in the epitaxial layer 20 corresponding to the first device region 11. Specifically, a channel groove is formed in the epitaxial layer 20 in the first device region 11 by etching a portion of the epitaxial layer 20. Figure 5 This is a schematic diagram of the structure after forming a channel structure 21 on an initial semiconductor structure, provided by an embodiment of this application. Figure a is a top view, Figure b is a cross-sectional view along the X direction, and Figure c is a cross-sectional view along the Y direction. Figure 5 As shown, a channel structure 21 is formed by filling the channel groove with channel material.

[0043] In this embodiment, an etching mask is formed on the initial semiconductor structure after the diffusion isolation structure 30 is formed. This etching mask exposes the region above the first device region 11. Then, the protective layer and epitaxial layer 20 above the exposed first device region 11 are etched sequentially to expose the surface of the substrate 10. The etching mask layer is then removed, and trench material is filled into the trench, thereby forming a channel structure 21 in the epitaxial layer 20 corresponding to the first device region 11. The channel material is germanium-silicon. In germanium-silicon, the mixing of silicon and germanium can result in higher electron and hole mobilities than pure silicon. The increased hole mobility, in particular, is crucial for improving the performance of PMOS transistors. This performance improvement becomes more significant as device size shrinks. Simultaneously, the high mobility of germanium-silicon allows for better drive current at shorter channel lengths, thereby reducing the impact of short-channel effects without sacrificing performance. Optionally, the germanium-silicon material can be one of phosphorus-doped silicon germanide, boron-doped silicon germanide, or arsenic-doped silicon germanide.

[0044] In some embodiments, after the channel structure 21 is formed in the channel groove, the channel structure 21 can be ground to flatten its surface. During the grinding of the channel structure 21, the protective layer can serve as a protection layer for the epitaxial layer 20 and a grinding stop layer. That is, grinding stops when the channel structure 21 is flush with the protective layer.

[0045] In this embodiment, the channel structure 21 of the PMOS is formed after the diffusion isolation structure 30 is formed. Therefore, after the channel structure 21 of the PMOS is formed, it will not be etched again, thereby avoiding the loss of stress in the PMOS channel. This allows the channel structure 21 of the PMOS to maintain high compressive stress, improve the carrier mobility of the PMOS channel, and thus improve the device performance of the PMOS.

[0046] In this embodiment of the application, after forming a channel structure 21 in the epitaxial layer 20 corresponding to the first device region 11, a first fin structure 41 corresponding to the first transistor and a second fin structure 42 corresponding to the second transistor can be further formed. Specifically, Figure 6 This is a schematic diagram of the structure after forming the fin structure 40 according to an embodiment of this application, wherein Figure a is a top view, Figure b is a cross-sectional view along the X direction, and Figure c is a cross-sectional view along the Y direction, as shown. Figure 6 As shown, after forming a channel structure 21 in the epitaxial layer 20 corresponding to the first device region 11, the first fin structure 41 corresponding to the first transistor is formed by etching the channel structure 21 on the first device region 11, and the second fin structure 42 corresponding to the second transistor is formed by etching the epitaxial layer 20 on the second device region 12.

[0047] The first fin structure 41 corresponding to the first transistor can be one or more. When there are multiple first fin structures 41 corresponding to the first transistor, adjacent first fin structures 41 can be isolated by shallow trenches, and the shallow trenches are filled with isolation material to form a shallow trench isolation structure 43. Similarly, the second fin structure 42 corresponding to the second transistor can be one or more. When there are multiple second fin structures 42 corresponding to the second transistor, adjacent second fin structures 42 can be isolated by shallow trenches, and the shallow trenches are filled with isolation material to form a shallow trench isolation structure 43. Optionally, the isolation material can be any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, silicon boron nitride, silicon boron carbide, hafnium dioxide, and zirconium dioxide. Specifically, the isolation material filled in the shallow trenches is different from the material forming the diffusion isolation structure 30 to prevent the diffusion isolation structure 30 from being etched away during the formation of the shallow trenches, thus avoiding damage to the diffusion isolation structure 30.

[0048] In this embodiment of the application, after forming the first fin structure 41 and the second fin structure 42, the gate structure 50 can be formed. Specifically, Figure 7 This is a schematic diagram of the structure after forming the gate structure 50 according to an embodiment of this application, wherein Figure a is a top view, Figure b is a cross-sectional view along the X direction, and Figure c is a cross-sectional view along the Y direction, as shown. Figure 7 As shown, after forming the first fin structure 41 corresponding to the first transistor and the second fin structure 42 corresponding to the second transistor, a gate oxide layer 51 is formed on the surface of the epitaxial layer 20, the surface of the diffusion isolation structure 30, and the first fin structure 41 and the second fin structure 42. Then, a first gate structure spanning the first fin structure 41, a second gate structure spanning the second fin structure 42, and a predetermined number of pseudo-gate structures are formed on the gate oxide layer 51.

[0049] The gate oxide layer 51 is located on the surface of the epitaxial layer 20, the surface of the diffusion isolation structure 30, and the structure itself, and covers the side and top surfaces of the first fin structure 41 and the second fin structure 42. Optionally, the gate oxide layer 51 can be made of silicon dioxide, hafnium dioxide, zirconium dioxide, aluminum oxide, etc. Optionally, the gate oxide layer 51 can be formed by thermal oxidation of silicon. After forming the gate oxide layer 51, a mask is formed on the gate oxide layer 51, and then the exposed gate oxide layer 51 is etched to expose the source and drain regions of the first fin structure 41 and the second fin structure 42. Then, a gate material is formed on the remaining gate oxide layer 51 to obtain the gate structure 50. Optionally, the gate material can be a high dielectric constant material, such as polysilicon, tungsten, nickel, platinum, etc.

[0050] In some embodiments, after forming the gate material on the gate oxide layer 51, sidewalls can also be formed on the sidewalls of the gate structure 50 to protect the gate structure 50. The sidewalls are used to protect the sidewalls of the gate structure 50. The sidewalls can be a single-layer structure or a stacked structure, and the material of the sidewalls can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. The sidewalls are formed by depositing sidewall material and etching the sidewall material using a maskless etching process, thereby removing the sidewall material on the top of the gate structure 50, the top and sidewalls of the first fin structure 41 and the second fin, and the diffusion isolation structure 30, while retaining the sidewall material located on the sidewalls of the gate structure 50 as sidewalls.

[0051] In this embodiment, the gate structure 50 includes a first gate structure corresponding to the first transistor, a second gate structure corresponding to the second transistor, and a dummy gate structure. Optionally, the first gate structure is located above the middle region of the first device region 11, and the second gate structure is located above the middle region of the second device region 12. The dummy gate structure includes a first dummy gate structure formed at the junction of the first device region 11 and the diffusion isolation structure 30, and a second dummy gate structure formed at the junction of the second device region 12 and the diffusion isolation structure 30. The first and second dummy gate structures are used to anchor the diffusion isolation structure 30, thereby preventing stress loss of germanium-silicon in the first device region 11.

[0052] This application also provides a semiconductor structure, which is formed by the semiconductor structure formation method described above.

[0053] The semiconductor structure described in this application embodiment is formed by the above-described semiconductor structure formation method. During the formation of the semiconductor structure, before forming the channel structure 21 in the first device region 11, an isolation trench is formed in the substrate 10, and an isolation material is filled in the isolation trench to form a diffusion isolation structure 30. Since the diffusion isolation structure 30 is formed before the channel structure 21 is formed, it is not necessary to etch the channel structure 21 again to form the isolation trench after the channel structure 21 is formed. This avoids channel stress loss caused by etching the channel structure 21, maintains high compressive stress in the channel structure 21, improves the carrier mobility of the transistor, and thus improves the device performance of the transistor.

[0054] This application also provides an electronic device comprising the semiconductor structure described above.

[0055] In this embodiment, the electronic device is a FinFET device formed using CMOS technology. Because this electronic device includes the aforementioned semiconductor structure, which is formed using the aforementioned semiconductor structure formation method, the resulting semiconductor structure exhibits high carrier mobility and improves the device performance of the transistor. Therefore, this electronic device also possesses similar advantages.

[0056] This application also provides an electronic device, which includes the electronic components described above.

[0057] The electronic device described in the embodiments of this application can be any electronic product or device such as a smartphone, desktop computer, tablet computer, laptop computer, digital assistant, augmented reality (AR) / virtual reality (VR) device, smart voice interaction device, smart home appliance, smart wearable device, vehicle terminal device, etc., or any intermediate product including the above-mentioned electronic devices.

[0058] The electronic device described in this application embodiment includes the aforementioned electronic components, and these components include the aforementioned semiconductor structure. Because the semiconductor structure is formed using the aforementioned semiconductor structure formation method, the resulting semiconductor structure exhibits high carrier mobility and improves the device performance of the transistor. Therefore, this electronic device also possesses similar advantages.

[0059] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0060] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0061] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0062] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: Provides the initial semiconductor structure; The initial semiconductor structure includes a substrate and an epitaxial layer formed on the substrate; A first device region and a second device region are formed in the substrate. A first transistor is formed on the first device region, and a second transistor is formed on the second device region. The first transistor and the second transistor are of different types. The epitaxial layer and the substrate at the junction of the first device region and the second device region are etched sequentially to form an isolation groove in the substrate; The isolation groove is filled with isolation material to form a diffusion isolation structure; A channel structure is formed in the epitaxial layer corresponding to the first device region.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The provision of the initial semiconductor structure includes: Provide initial substrate; The first device region and the second device region are formed in the initial substrate; An epitaxial layer is formed on the initial substrate after the formation of the first device region and the second device region to obtain the initial semiconductor structure.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The insulating material is one of silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, boron nitride, boron silicon nitride, boron silicon carbide, hafnium dioxide, and zirconium dioxide.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The step of forming a channel structure in the epitaxial layer corresponding to the first device region to obtain the target semiconductor structure includes: Etch a portion of the epitaxial layer on the first device region to form a trench in the epitaxial layer in the first device region; The groove of the channel is filled with channel material to form the channel structure.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, The channel material is germanium-silicon material.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, A protective layer is also formed on the epitaxial layer, the thickness of which is 50 to 200 angstroms.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, Before filling the isolation groove with isolation material to form a diffusion isolation structure, the method further includes: The diffusion isolation structure is ground until it is flush with the protective layer.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, After forming the channel structure in the epitaxial layer corresponding to the first device region, the method further includes: The channel structure on the first device region is etched to form the first fin structure corresponding to the first transistor, and the epitaxial layer on the second device region is etched to form the second fin structure corresponding to the second transistor.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, After etching the channel structure to form the fin structure corresponding to the first transistor, and etching the epitaxial layer on the second device region to form the fin structure corresponding to the second transistor, the method further includes: A gate oxide layer is formed, which covers the first fin structure and the second fin structure; A first gate structure spanning the first fin structure, a second gate structure spanning the second fin structure, and a predetermined number of dummy gate structures are formed on the gate oxide layer.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The pseudo-gate structure includes at least a pseudo-gate structure formed at the junction of the first device region and the diffusion isolation structure, and a pseudo-gate structure formed at the junction of the second device region and the diffusion isolation structure.

11. A semiconductor structure, characterized in that, The semiconductor structure is formed by the semiconductor structure forming method according to any one of claims 1 to 10.

12. An electronic device, characterized in that, The electronic device includes the semiconductor structure as described in claim 11.

13. An electronic device, characterized in that, The electronic device includes the electronic components as described in claim 12.

Images