Photonic surface topography in single photon avalanche diodes

Abstract

The invention relates to a photonic surface topography in a single photon avalanche diode. A photodetector includes a semiconductor layer having a top surface, a body having a first type of doping, and a first region having a second type of doping different from the first type. A first fraction of a surface area of the top surface of the semiconductor layer includes a surface topography. The semiconductor layer further includes a junction formed between the body and the first region, where the junction is configured to have a respective surface area that is a second fraction of the surface area of the top surface, where the second fraction is less than the first fraction.

Description

[0001] Copyright Notice

[0002] This patent document contains a portion of copyrighted material. As shown in the patent documents or records of the United States Patent and Trademark Office, the copyright holder does not object to any reproduction of this patent document or the patent disclosure, but will otherwise retain all copyright. Technical Field

[0003] This disclosure generally relates to methods, systems, and apparatus for improving the performance of silicon photomultiplier tubes and other photodetector arrays. Background Technology

[0004] Efficient light detection in semiconductor sensors relies on optimizing both photon transport to the device and photon absorption within the semiconductor. Photon transport is enhanced using an anti-reflective coating (ARC). Typically, ARC is formed by stacking dielectric layers with appropriate thickness and reflectivity. The stacking of dielectric layers presents several challenges, depending on the fabrication process, the wavelength to be transmitted, and the mechanical and environmental stability of the device passivation layer.

[0005] Another approach is to form broadband ARC through surface texturing. In this method, photon absorption can be optimized through detector design choices. For example, the absorption length of near-infrared light can be tens of micrometers, meaning that thicker layers or appropriate light trapping structures increase the optical path in the active region. Therefore, optimizing these two characteristics presents a challenge depending on the type of sensor.

[0006] In front-illuminated single-photon avalanche diodes (SPADs), both methods for forming ARC (augmented arc multiplication) are difficult to implement cost-effectively, especially for red / near-infrared light detection. In conventional SPAD designs, a planar surface is used to create a uniform electric field for avalanche multiplication. Surface texture can disrupt the field configuration or degrade the SPAD's optical performance.

[0007] Therefore, a photonic surface morphology for a front-illuminated single-photon avalanche diode is provided. Summary of the Invention

[0008] One embodiment of this disclosure provides a photodetector. The photodetector includes: a semiconductor layer having a top surface located on a first side, wherein the semiconductor layer is configured to allow light to enter via the first side. The semiconductor layer includes: a body having a first type of doping; and a first region having a second type of doping different from the first type. A first fraction of the surface area of ​​the top surface of the semiconductor layer includes a surface morphology. The semiconductor layer further includes a junction formed between the body and the first region, wherein the junction is configured to have a corresponding surface area that is a second fraction of the surface area of ​​the top surface, and wherein the second fraction is less than the first fraction. The photodetector further includes an electrode coupled to the first region.

[0009] Another embodiment of this disclosure provides an apparatus. The apparatus includes: a semiconductor layer having a first surface. The semiconductor layer includes: a body having a first type of doping; a first region having a second type of doping different from the first type; and wherein a first fraction of the surface area of ​​the first surface of the semiconductor layer includes a surface morphology. The semiconductor layer further includes a junction formed between the body and the first region, wherein the junction is configured to have a surface area that is a second fraction of the surface area of ​​the first surface, wherein the second fraction is less than the first fraction.

[0010] Another embodiment of this disclosure provides a photodetector array. The photodetector array includes a plurality of photodetectors arranged in a grid on a substrate, the plurality of photodetectors including a first photodetector. The first photodetector includes a semiconductor layer having a top surface located on a first side, wherein the semiconductor layer is configured to allow light to enter via the first side. The semiconductor layer includes a body having a first type of doping; a first region having a second type of doping different from the first type; and wherein a first fraction of the surface area of ​​the top surface of the semiconductor layer includes a surface morphology. The semiconductor layer further includes a junction formed between the body and the first region, wherein the junction is configured to have a corresponding surface area, the corresponding surface area being a second fraction of the surface area of ​​the top surface, wherein the second fraction is less than the first fraction. Attached Figure Description

[0011] A further understanding of the nature and advantages of particular embodiments can be achieved by referring to the remainder of the specification and the drawings, in which similar reference numerals are used to refer to similar components. In some examples, sublabels are associated with reference numerals to identify one of a plurality of similar components. When reference numerals are mentioned without detailing existing sublabels, they are intended to refer to all such plurality of similar components.

[0012] Figure 1 This is a partial schematic cross-sectional view of a SPAD array according to various embodiments;

[0013] Figure 2 This is a partial schematic top view of a SPAD array according to various embodiments;

[0014] Figure 3 This is a partial schematic cross-sectional view of an alternative configuration of a SPAD array according to various embodiments;

[0015] Figure 4 This is a partial schematic cross-sectional view of a SPAD array characterized by trenches according to various embodiments;

[0016] Figure 5 This is a partial schematic cross-sectional view of an alternative configuration of a SPAD array characterized by an insulating layer according to various embodiments;

[0017] Figure 6 The illustrations depict corresponding schematic cross-sectional views of several surface morphologies according to various embodiments;

[0018] Figure 7 Schematic perspective views illustrating the photonic surface topography characterized by apertures according to various embodiments;

[0019] Figure 8 The illustration shows a schematic perspective view of a photonic surface topography characterized by multi-layered holes and rods according to various embodiments.

[0020] Figure 9 The illustrations depict schematic perspective views of photonic surface morphology characterized by a lattice structure according to various embodiments. Detailed Implementation

[0021] Various embodiments describe a photonic surface morphology for a front-illuminated SPAD.

[0022] In some embodiments, a photodetector having a photonic surface morphology is provided. The photodetector includes a semiconductor layer having a top surface, a body having a first type of doping, and a first region having a second type of doping different from the first type. A first fraction of the surface area of ​​the top surface of the semiconductor layer includes the surface morphology. The semiconductor layer further includes a junction formed between the body and the first region, wherein the junction is configured to have a corresponding surface area that is a second fraction of the surface area of ​​the top surface, wherein the second fraction is less than the first fraction. An electrode is coupled to the first region.

[0023] In other embodiments, a device characterized by a photonic surface morphology is provided. The device includes a semiconductor layer having a first surface. The semiconductor layer includes a body having a first type of doping and a first region having a second type of doping different from the first type. A first fraction of the surface area of ​​the first surface of the semiconductor layer includes the surface morphology. The semiconductor layer further includes a junction formed between the body and the first region of the semiconductor layer. The junction is configured to have a surface area that is a second fraction of the surface area of ​​the first surface, wherein the second fraction is less than the first fraction.

[0024] In other embodiments, a photodetector array having a photonic surface morphology is provided. The photodetector array includes a plurality of photodetectors arranged in a grid on a substrate, the plurality of photodetectors including a first photodetector. The first photodetector includes a semiconductor layer having a top surface located on a first side, wherein the semiconductor layer is configured to allow light to enter via the first side. The semiconductor layer includes a body having a first type of doping and a first region having a second type of doping different from the first type. A first fraction of the surface area of ​​the top surface of the semiconductor layer includes the surface morphology. The semiconductor layer further includes a junction formed between the body and the first region of the semiconductor layer. The junction is configured to have a corresponding surface area, the corresponding surface area being a second fraction of the surface area of ​​the top surface, wherein the second fraction is less than the first fraction.

[0025] In the following description, numerous details are set forth for illustrative purposes to provide a thorough understanding of the described embodiments. However, those skilled in the art will understand that other embodiments may be practiced without some of these details. Several embodiments are described herein, and while various features pertain to different embodiments, it should be understood that a feature described with respect to one embodiment may also be incorporated into other embodiments. However, for the same reason, a single feature or features of any described embodiment should not be considered essential to every embodiment of the invention, as such features may be omitted in other embodiments of the invention.

[0026] When an element is referred to herein as "connected" or "coupled" to another element (including mechanical, electrical, or communicative connections or couplings), it should be understood that the element can be directly connected to the other element, or that there is an intermediary element between the elements. Conversely, when an element is referred to as "directly connected" or "directly coupled" to another element, it should be understood that there is no intermediary element in the "direct" connection between the elements. However, the presence of a direct connection does not preclude the possibility of other connections where intermediary elements may exist.

[0027] When an element is referred to herein as being "positioned" relative to another element in a certain manner (e.g., positioned on it, between it, below it, adjacent to it, or positioned in some other relative manner), it should be understood that the element may be positioned directly relative to the other element (e.g., directly on the other element), or that there may be an intervening element between the elements. In contrast, when an element is referred to as being "directly positioned" relative to another element, it should be understood that there is no intervening element in the "direct" instance. However, the presence of direct positioning does not preclude other instances in which intervening elements may be present.

[0028] Similarly, when an element is referred to herein as a “layer,” it should be understood that the layer may be a single layer or comprise multiple layers. For example, a conductive layer may comprise multiple different conductive materials or multiple layers of different conductive materials, and a dielectric layer may comprise multiple dielectric materials or multiple layers of dielectric materials. When a layer is described as coupled or connected to another layer, it should be understood that the coupled or connected layers may contain intermediary elements present between the coupled or connected layers. In contrast, when a layer is referred to as being “directly” connected or coupled to another layer, it should be understood that there are no intermediary elements between the layers. However, the presence of directly coupled or connected layers does not preclude the existence of other connections where intermediary elements may be present.

[0029] Furthermore, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for illustrative purposes only and are not limited to any fixed direction or orientation. Rather, they are used only to indicate the relative position and / or orientation between various parts of an object and / or component.

[0030] Furthermore, the methods and processes described herein may be presented in a particular order for ease of description. However, it should be understood that, unless the context otherwise requires, intermediate processes may occur before and / or after any part of the described process, and various other processes may be reordered, added, and / or omitted according to various embodiments.

[0031] Unless otherwise indicated, all numbers used herein to express quantity, size, etc., should be understood to be modified by the term “about” in all instances. In this application, unless specifically stated otherwise, the use of the singular includes the plural, and unless otherwise indicated, the use of the terms “and” and “or” means “and / or”. Furthermore, the use of the terms “including” and “having”, as well as other forms (e.g., “includes”, “included”, “has”, “have”, and “had”), should be considered non-exclusive. And, unless specifically stated otherwise, terms such as “element” or “component” cover both elements and components comprising one unit and elements and components comprising more than one unit.

[0032] As used herein, the phrase “at least one of” following a list of items (where each item is separated by the terms “and” or “or”) modifies the list as a whole, not each member of the list (i.e., each item). The phrase “at least one of” does not require the selection of at least one of every listed item; rather, the phrase has the meaning of including at least one of any of the items and / or at least one of any combination of items. By example, the phrases “at least one of A, B, and C” or “at least one of A, B, or C” each refer to only A, only B, or only C; and / or any combination of A, B, and C. This will be explicitly stated in examples where the selection of “at least one of each of A, B, and C” or alternatively “at least one of A, at least one of B, and at least one of C” is intended.

[0033] Conventional ARC has proven challenging to implement in SPAD designs. In a typical SPAD, a potential is applied to n... + and p - The region is designed to create a high electric field at the junction, enabling avalanche multiplication at potentials above the breakdown voltage. SPADs operate above the breakdown voltage, with the design goal of forming uniformly distributed avalanche regions. Typically, ion implantation is used to form n-layers on epitaxial p-layers on p+ substrates. + Region. When an anti-reflective (AR) texture is applied to the surface of a planar wafer, subsequent ion implantation is performed to form n + This process can affect n regions. + The shape of the region is altered, resulting in a non-uniform avalanche region. Alternatively, the region can be doped first, but this modification to the process has led to a reduction in the volume of the optically active region.

[0034] Therefore, a SPAD with a photonic surface morphology is provided. Specifically, a SPAD is provided in which point-like n +Region (and / or n) + The point-like pn junction between the region and the surrounding semiconductor body is combined with the surface nanomorphology on the front-facing (e.g., the illuminated side) planar wafer surface. By utilizing the point-like high-field region, the AR surface nanomorphology can be applied to the epitaxial layer surface while mitigating its effect on the avalanche region.

[0035] Figure 1 This is a partial schematic cross-sectional view of a SPAD array 100 according to various embodiments. The SPAD array 100 includes a substrate 105, a semiconductor layer 110, a dielectric layer 115, an electrode 135, an avalanche region 120, an n-doped region 125, and a surface texture 130. Figure 1 The schematic diagram illustrates the various elements of the SPAD array 100, and modifications to the various components and other arrangements of the SPAD array 100 are possible according to various embodiments.

[0036] In various embodiments, SPAD array 100 may be a photodetector array comprising a plurality of individual photodetector units (in this case, individual SPADs). SPAD array 100 may be interchangeably referred to as a silicon photomultiplier tube (SiPM). For illustrative purposes, the embodiments described below are described with reference to the structure of individual SPADs. However, as previously described, SPAD array 100 comprises a plurality of individual SPADs. In some instances, SPAD array 100 may comprise two or more individual SPADs. In other embodiments, SPAD array 100 may comprise tens, hundreds, thousands, millions, or more individual SPADs. For example, in some embodiments, SPAD array 100 may comprise at least 100,000 respective SPADs.

[0037] In various embodiments, substrate 105 may be a silicon substrate on which other structures of the SPAD array 110 are formed. Therefore, substrate 105 may be a semiconductor substrate, such as, but not limited to, bulk silicon. In some embodiments, substrate 105 may be a highly p-doped substrate formed by heavily doping a p-type dopant (e.g., boron). + Therefore, the substrate 105 serves as the "bulk" semiconductor of the SPAD array 100, on which (or within) other parts of the device are formed, such as the semiconductor layer 110, the dielectric layer 115, the n-doped region 125, and the electrode 135.

[0038] Semiconductor layer 110 may be disposed on substrate 105. In some embodiments, semiconductor layer 110 may be an epitaxial layer (e.g., a semiconductor material layer grown on substrate 105 via an epitaxial process). In various embodiments, semiconductor layer 110 may be in-situ doped during the epitaxial growth process. For example, in some embodiments, semiconductor layer 110 may be lightly p-doped (e.g., p-doped).- (Doped). In some instances, this may be referred to as first-type doping to distinguish it from different subsequent types of doping (e.g., second, third, etc.). It should be understood that in other embodiments, the doping of the body of semiconductor layer 110 may be referred to as doping of different numbered "types," such as second, third, or other numbered "types," and the doping type numbering order is only used to distinguish between different types of doping. Therefore, the body of semiconductor layer 110 may thus be considered lightly p-doped. As used herein, "body" may refer to the bulk / core of semiconductor layer 110 (or semiconductor layer) compared to the surface (e.g., top or bottom surface). Thus, body may refer to the bulk, internal region of semiconductor layer 110.

[0039] Therefore, in various embodiments, the semiconductor layer 110 may be formed of a semiconductor material such as silicon. In other embodiments, other materials may be used, including but not limited to germanium, III-V compound semiconductor materials (e.g., gallium arsenide (GaAs), indium phosphide (InP), etc.), or II-VI compound semiconductor materials (e.g., zinc oxide (ZnO), magnesium oxide (MgO), etc.).

[0040] In various instances, the semiconductor layer 110 may co-extend with the substrate 105. The optically active region 140 of the semiconductor layer 110 may be associated with a corresponding SPAD of the SPAD array 100, the corresponding SPAD having a corresponding electrode 135 coupled to a corresponding n-doped region 125 and having a corresponding avalanche region 120.

[0041] In various instances, the n-doped region 125 may be formed within the semiconductor layer. For example, in some embodiments, the n-doped region may be a region formed by in-situ doping using an n-type dopant (e.g., phosphorus). The n-doped region 125 may be heavily n-doped (e.g., n... + (Doping). In some instances, this may be referred to as a "second" type of doping, distinct from the first type previously described. Similarly, in some instances, the substrate (e.g., p-type) is doped. + The doping of the p-type can also be referred to as the "first" type of doping, but with a doping concentration that is different from that of the host (e.g., a lower dopant concentration).

[0042] In various embodiments, the n-doped region 125 can be formed in a dot-like size and shape. Therefore, the n-doped region 125 can be concentrated within a relatively small area of ​​the semiconductor layer 110. In various embodiments, the n-doped region 125 can be located at any depth within the semiconductor layer 110 (e.g., near the surface or deep within the semiconductor layer 110). In some instances, the n-doped region 125 (and the pillar 140) can be formed by first forming a cavity within the semiconductor layer 110 via a dry etching process, a wet etching process, or a combination of both. Doping can then be applied in situ (e.g., ion implantation or diffusion) to form the n-doped region 125.

[0043] In the embodiments described above and in other embodiments set forth below, boron and phosphorus are provided as non-limiting examples, and it should be understood that other dopants may be used in other embodiments. For example, suitable dopants may include, but are not limited to, pentavalent atoms (e.g., arsenic, phosphorus, antimony, bismuth, lithium, etc.) for n-type doping and trivalent atoms (e.g., indium, aluminum, gallium, boron, etc.) for p-type doping. Furthermore, as used herein, light doping and heavy doping may be relative to each other (e.g., a lightly doped region is doped with a relatively low dopant concentration compared to a heavily doped region). In some instances, lightly doped regions may be doped with dopant atoms in the range of parts per million (ppm) or lower. In contrast, heavily doped regions may be doped with dopant atoms in the range of parts per thousand (ppm) or higher.

[0044] In the embodiments described above and in other embodiments set forth below, boron and phosphorus are provided as non-limiting examples, and it should be understood that other dopants may be used in other embodiments. For example, suitable dopants may include, but are not limited to, pentavalent atoms (e.g., arsenic, phosphorus, antimony, bismuth, lithium, etc.) for n-type doping and trivalent atoms (e.g., indium, aluminum, gallium, boron, etc.) for p-type doping.

[0045] In various embodiments, the n-doped region 125 may be referred to as the "head," which is coupled to a first end of the pillar 140. The pillar 140 may in turn be coupled to the electrode 135 and / or a portion of the electrode 135. The n-doped region 125 may be formed to have a corresponding three-dimensional geometry. For example, in some embodiments, the n-doped region 125 may have a spherical geometry. In other embodiments, the n-doped region 125 may have different geometries, such as, but not limited to, elliptical, pyramidal, tetrahedral, other polyhedral, conical, or other shapes. In still other embodiments, the n-doped region 125 may be hemispherical or semi-elliptical. In the depicted embodiment, the n-doped region 125 is spherical.

[0046] Similarly, the pillar 140 may have different cross-sectional shapes. Therefore, the pillar 140 may be, but is not limited to, cylindrical (e.g., circular or elliptical cross-section) or rectangular (e.g., rectangular or square cross-section). In other instances, the pillar 140 may be conical, polyhedral, or otherwise have different shapes, and is not limited to any particular shape factor. In some instances, the n-doped region 125 and / or the pillar 140 may be at least partially surrounded by a dielectric material (e.g., an insulating layer) configured to electrically isolate at least a portion of the pillar 140 and / or a portion of the n-doped region 125 from direct contact with the semiconductor layer 110. In other embodiments, the dielectric material may surround the pillar 140 such that only the n-doped region 125 is in direct contact with the semiconductor layer 110. In various instances, the dielectric material may be formed, for example, from silicon oxide.

[0047] In various embodiments, the pillar 140 may be configured to electrically couple the n-doped region 125 to the electrode 135. Therefore, in some instances, the pillar 140 may be formed of a conductive material (e.g., copper or other suitable metal) or polycrystalline silicon.

[0048] Therefore, by employing the n-doped region 125 coupled to the electrode 135 via the pillar 140 as described above, a point-like high-field region (e.g., an avalanche region 120) can be formed at the pn junction between the n-doped region 125 and the lightly p-doped semiconductor layer 110. Thus, the avalanche region 120 can refer to the region surrounding the pn junction between the n-doped region 125 and the surrounding semiconductor layer 110 that is configured to undergo avalanche breakdown. In some instances, the n-doped region 125 can therefore be a point-like region embedded in the semiconductor layer 110, such that a corresponding point-like junction (and high-field region) is formed between the semiconductor layer 110 and the n-doped region 125.

[0049] In some instances, the n-doped region 125 can be directly disposed at the junction between the dielectric layer 115 and the semiconductor layer 110, such as... Figures 3 to 4 As depicted in the illustration. In various embodiments, the n-doped region 125 may be formed of a semiconductor material different from the material used in the semiconductor layer 110. For example, in some embodiments, the n-doped region 125 may be formed of polysilicon.

[0050] As used herein, "dot-like" may refer to the n-doped region 125 itself, or the pn junction formed between the n-doped region 125 and the semiconductor layer 110 (or other semiconductor layers), and / or the high-field region formed around the pn junction. In various embodiments, "dot-like" is used in contrast to conventional methods, in which the n-doped region is a planar shape extending across the entire surface or at least a large portion of the surface. Therefore, the junction may correspondingly be a "planar" shape, covering a large portion of the surface of the epitaxial layer and / or semiconductor layer. In contrast, the n-doped region 125 and the following description... Figures 2 to 5 The described n-doped regions can be localized (e.g., non-planar) and configured to form junctions with the surrounding epitaxial / semiconductor layers, wherein the area of ​​the junctions constitutes a smaller fraction of the surface area than that in a planar arrangement of n-doped regions. In some instances, this can be a very small fraction of the total surface area of ​​the epitaxial / semiconductor layers.

[0051] In some instances, surface texture 130 may be disposed on the top surface (alternatively, the "first surface") on a first side of semiconductor layer 110. Therefore, in various embodiments, surface topography may be formed by surface texture 130. Surface topography (e.g., surface texture 130) may cover a first fraction of the surface area of ​​the top surface of semiconductor layer 110. In other words, a first fraction of the surface area of ​​the top surface of semiconductor layer 110 may be characterized by surface topography (e.g., via surface texture 130). In some instances, regions of the top surface that are in contact with n-doped regions or alternatively disposed on a junction (e.g., a pn junction) formed between dotted n-doped regions 125 and semiconductor layer 110 may not have surface topography (e.g., surface texture 110). Therefore, a second fraction of the surface area of ​​the top surface of semiconductor layer 110 may not include surface topography. In some instances, the surface area of ​​the junction may be equal to a second fraction of the surface area of ​​the top surface of semiconductor layer 110.

[0052] For example, in some embodiments, the ratio of the surface area of ​​the junction (e.g., the surface area of ​​the top surface located above the junction (also called the "buffer" region)) to the surface area of ​​the surface topography (surface texture 130) may be a ratio of 1 to at least 10 (e.g., greater than 10). In other words, the first fraction of the surface area of ​​the top surface characterized by surface texture 130 may be at least 10 / 11. In some instances, the first fraction of the surface area of ​​the top surface characterized by surface texture 130 may be at least 7 / 10 (e.g., at least 70% of the top surface contains surface texture 130). In still other instances, at least 50% of the top surface contains surface texture 130.

[0053] A potential can be applied to n + (e.g., n-doped region 125) and p -Regions (e.g., semiconductor layer 110), which are in n-doped regions 125 (e.g., n-doped regions). + A high electric field is formed at the junction between the doped region 125 and the lightly p-doped region of the semiconductor layer 110, which enables avalanche multiplication within the avalanche region 120. Therefore, a uniformly distributed point-like (e.g., focal) (in this example, spherical) avalanche region 120 can be formed in the region surrounding the n-doped region 125 (e.g., around the "head" of the pillar 140).

[0054] Therefore, in various embodiments, a high-field region (e.g., an avalanche region 120) can be formed around the head (e.g., the n-doped region 125), thereby effectively forming a "shell" surrounding the n-doped region 125. A larger sensitive region can be further formed around the avalanche region 120, where photons absorbed in the sensitive region generate electron-hole pairs. When electrons reach the avalanche region 120, avalanche breakdown occurs, which multiplies the number of charge carriers flowing through the n-doped region (e.g., collected in the head). As used herein, the avalanche region 120 can be interchangeably referred to as the high-field region.

[0055] Therefore, as described above, electrode 135 may include conductive pads, traces, or other conductive structures through which an electrical bias can be applied to n-doped region 125 and / or a measurement voltage can be measured. Thus, as used herein, a pad may refer to a signal pad, input / output pad, attenuation pad, or other conductive structure within a circuit from which a signal can be applied and / or measured. In various instances, electrode 135 may be formed of a conductive material, such as a metal (e.g., tungsten (W), copper (Cu), or other suitable material), polycrystalline silicon, or a conductive oxide.

[0056] In various embodiments, the semiconductor layer 110 may be characterized by a surface texture 130 on the light-facing side (e.g., the front side facing the light source). Thus, the surface texture 130 may be disposed on the front side of the semiconductor layer 110 (e.g., the light-facing side or the side through which light can enter the semiconductor / epipolar layer) (alternatively referred to as the "top" side or "first" side). Although shown in cross-section (and therefore across only one axis), it should be understood that the topographic features of the surface texture 130 may extend along the top surface of the semiconductor layer 110 in all directions. Therefore, according to various embodiments, the surface texture 130 may cover at least a portion of the first side of the entire SPAD array 100, and thus at least a portion of the top side of each of the plurality of individual SPADs in the SPAD array 100. In some instances, the surface texture 130 covers (e.g., is present therein) at least half of the surface area of ​​the first side of the semiconductor layer 110. In some other embodiments, the surface texture 130 may cover the entire first side of the semiconductor layer 110, excluding the buffer zone surrounding the pillar 140, the electrode 135, and / or the n-doped region 125.

[0057] In various instances, surface texture 130 may have a photonic surface topography configured to provide broadband omnidirectional AR properties. In some embodiments, surface texture 130 may be a surface topography with photonic properties (e.g., a photonic surface topography) exhibiting further photonic characteristics, such as improved light absorption within semiconductor layer 110. Thus, as used herein, a photonic surface topography refers to a surface topography (e.g., the surface topography of surface texture 130) configured to interact with photons to produce the effects described above (e.g., AR, improved absorption, etc.). Thus, in some instances, surface texture 130 may be configured to have a surface topography configured to reduce reflections across a wide range of wavelengths (e.g., an AR surface topography). In some instances, surface texture 130 may be configured to confine light / photons once they enter semiconductor layer 110. In some instances, the surface topography may be a biomimetic nanostructure (e.g., a nanostructure mimicking structures found in nature, such as the eye of a moth). Therefore, in some instances, the surface morphology of surface texture 130 can be a parabolic nipple array, such as... Figure 6 As depicted in [the text]. In other instances, other surface morphologies may be used, such as porous silicon, where nanoscale pores (e.g., smaller than wavelength in size) with large hydrogenated surfaces can be formed on the first side of semiconductor layer 110. In still other instances, the surface morphology may be pyramidal, or have another polyhedral shape, or may be implemented as a grating. While various photonic surface morphologies have been described as surface texture 130, it should be understood that in other embodiments, the surface morphology may be formed as a photonic structure on the surface of a semiconductor layer (e.g., semiconductor layer 110). The following section discusses... Figures 6 to 9 Examples of surface morphology described in more detail. Therefore, surface morphology can generally refer to features of a surface or features formed on a surface (e.g., a semiconductor layer).

[0058] In various embodiments, dielectric layer 115 may be disposed on semiconductor layer 110 (including surface texture 130) and provides further electrical insulation for pillar 140 and / or n-doped region 125. Specifically, dielectric layer 115 may be disposed on a first side of semiconductor layer 110 (e.g., the side facing the illumination source / light source). In some instances, dielectric layer 115 may be disposed on semiconductor layer 110 after surface texture 130 is formed (e.g., deposited or otherwise formed thereon). Thus, dielectric layer 115 may be disposed on a first side of semiconductor layer 110 (e.g., the top surface). In some instances, dielectric layer 115 may be formed of silicon oxide (SiO).

[0059] Figure 2This is a partially schematic top view of a SPAD array 200 according to various embodiments. The SPAD array 200 includes a plurality of SPADs (interchangeably referred to as “cells”), including SPADs 220a to 220d, including first SPADs 220a to fourth SPADs 220d. The first SPAD 220a includes a first high-field region 205a, a corresponding AR surface texture 210a, and a corresponding buffer region 215a. The second SPAD 220b includes a second high-field region 205b, a corresponding AR surface texture 210b, and a corresponding buffer region 215b. The third SPAD 220c includes a third high-field region 205c, a corresponding AR surface texture 210c, and a corresponding buffer region 215c. Similarly, the fourth SPAD 220d includes a fourth high-field region 205d, a corresponding AR surface texture 210d, and a corresponding buffer region 215d. SPAD array 200 further includes conductive traces 225 coupled to each of the corresponding electrodes and to the high-field regions 215a to 215b of SPADs 220a to 220d. It should be noted that... Figure 2 The schematic diagram illustrates the various elements of the SPAD array 200, and modifications to the various components and other arrangements of the SPAD array 200 are possible according to various embodiments.

[0060] In some embodiments, each SPAD 220a to 220d may be surrounded by a groove (e.g., Figures 4 to 5 (As shown in the illustration). In some instances, the trenches may be filled with, for example, a dielectric material, metal, or other material. In some embodiments, the cells (e.g., SPADs 220a to 220b) may be arranged in a grid arrangement, such as a hexagonal grid. In other embodiments, other arrangements of the cells may be utilized, such as a rectangular grid.

[0061] In various instances, each of SPADs 220a to 220d may be coupled to a common feed line (e.g., conductive trace 225). In some instances, each SPAD 220a to 220d may be coupled to conductive trace 225 via a quench resistor. In some instances, each SPAD 220a to 220d may be coupled to conductive trace 225 via a respective conductive line (e.g., a metal wire, conductive trace, or other connection). In still other instances, each SPAD 220a to 220d may be individually fed by a respective feed line (e.g., not coupled to a common feed line, such as conductive trace 225).

[0062] As depicted, each of the high-field regions 215a to 215d (e.g., avalanche regions) of the SPAD array 200 is uniformly distributed and centered within each corresponding cell. Viewed from top, the high-field regions 215a to 215d may contain electrodes; in some instances, beneath the electrodes, pillars may extend through the dielectric layer and into the semiconductor layer of the corresponding SPADs 220a to 220d and into the corresponding n-doped regions (e.g., heads). The n-doped regions may be further disposed within the semiconductor layer and beneath the electrodes.

[0063] In other embodiments, the high-field regions 215a to 215d (and therefore the cells of the SPAD array 200) may have a variable density distribution according to a specific mapping. For example, in some embodiments, different regions of the SPAD array may have a higher (or lower) density of high-field regions per area (and correspondingly a higher cell count per area). Regions with higher density may exhibit relatively higher sensitivity, while lower-density regions exhibit relatively lower sensitivity. For example, in some embodiments, one or more of the SPADs 220a to 220d may have more struts and / or junctions than the other SPADs 220a to 220d of the SPAD array 200.

[0064] AR surface textures 210a to 210d are disposed on the top surface (e.g., the first side) of the semiconductor layer of each corresponding cell. In some instances, the AR surface textures 210a to 210d are present throughout the top surface of the corresponding semiconductor layer, except for a buffer region surrounding each corresponding high-field region 215a to 215d (or alternatively, surrounding the corresponding electrode, n-doped region, or a larger sensitive region surrounding the high-field region of each cell). This is because the high-field region is surrounded by a head (e.g., an n-doped region coupled to a conductive pillar, or...). Figures 3 to 5 The buffer region is highly localized (e.g., dotted) at the first end of the n-doped region depicted in the diagram, so the buffer region can be optional and / or small in size (e.g., close in size to the high-field region or sensitive region, and smaller than the region characterized by AR surface textures 210a to 210d).

[0065] Figure 3 This is a partial schematic cross-sectional view of an alternative configuration of a SPAD array 300 according to various embodiments. The SPAD array 300 includes a substrate 305, a semiconductor layer 310, a dielectric layer 315, electrodes 335, avalanche regions 320, n-doped regions 325, and surface texture 330. Figure 3 The schematic diagram illustrates the various elements of the SPAD array 300, and modifications to the various components and other arrangements of the SPAD array 300 are possible according to various embodiments.

[0066] Compared to the cells (e.g., individual SPADs) of the SPAD array 100, the n-doped region 325 is located at the interface between the top surface (e.g., the first side) of the semiconductor layer 310 and the dielectric layer 315. Furthermore, the n-doped region 325 is located at the interface between the semiconductor layer 310 and the surrounding optically active region 340 (e.g., p-type) of the semiconductor layer 310. - There is no dielectric channel between the doped regions. Therefore, the pn junction between the n-doped region 325 and the semiconductor layer 310, and the corresponding avalanche region 320, are moved closer to the top surface (e.g., the first side) of the semiconductor layer 310. Thus, the n-doped region 325 is located at the interface between the dielectric layer 315 and the semiconductor layer 310, which is consistent with the situation where... Figure 1 In the SPAD array 100, pillars 140 or channels (such as those inside the semiconductor layer 110) are placed within the SPAD array 100. Figure 5 The end of the image (as shown in the image) forms a contrast.

[0067] However, it should be understood that in other embodiments, the n-doped region 325 may include pillars extending into the semiconductor layer 310. For example, in some other embodiments, the n-doped region 325 may include pillars and "ends," as previously described. The ends of the n-doped region 325 may be located within the semiconductor layer 310. Thus, the n-doped region 325 may have a "T-shaped" structure, wherein the top of the "T" is disposed on the semiconductor layer 310 (e.g., on its top surface), and the pillars of the n-doped region 325 extend downward from the top of the "T" into the semiconductor layer 310 (e.g., on its top surface). Figure 5 (As depicted in the diagram), where the channel is formed to extend longitudinally downward into the semiconductor layer 310. In some instances, the pillars of the n-doped region 325 may be surrounded (e.g., electrically insulated) by a dielectric material (e.g., the dielectric material of the dielectric layer 315), such that only the ends of the n-doped regions (e.g., the first ends of the pillars on opposite sides of the top surface) are the only portions in direct contact with the semiconductor layer 310. In this arrangement, the pn junction is pushed lower into the semiconductor layer 310 (and the corresponding avalanche region 320), as in... Figure 1 In the arrangement of cells of the SPAD array 100.

[0068] Therefore, in various embodiments, the n-doped region 325 may itself be an electrode (e.g., a second electrode) disposed on the top surface of the semiconductor layer 310, which is coupled to the previously mentioned... Figure 1 The described electrode 335 (e.g., a first electrode) can be configured to bias the n-doped region 325. In some embodiments, the n-doped region 325 may extend at least partially into the semiconductor layer 310. The portion of the n-doped region 325 that extends into the semiconductor layer 310 and thus forms a pn junction in direct contact with the semiconductor layer 310 may be referred to as the “end” of the n-doped region 325. In some embodiments, the end of the n-doped region 325 may be referred to as the “first end”.

[0069] Therefore, in this arrangement, since the n-doped region 325 does not extend into the semiconductor layer 310, the avalanche region 320 is correspondingly shifted closer to the top surface. Thus, in some embodiments, the n-doped region 325 is a polysilicon structure disposed on the semiconductor layer 310, with its ends extending at least partially from the top surface into the semiconductor layer 310, in contrast to the n-doped region 125 formed within the semiconductor layer 110 in the SPAD array 100. Therefore, a pn junction is formed at and / or near the top surface (e.g., the first side) of the semiconductor layer 310.

[0070] Figure 4 This is a partial schematic cross-sectional view of a SPAD array 400 characterized by trenches according to various embodiments. Like SPAD array 300, SPAD array 400 includes a substrate 405, a semiconductor layer 410, a dielectric layer 415, an electrode 435, an avalanche region 420, an n-doped region 425, and a surface texture 430. However, SPAD array 400 is further characterized by trenches (e.g., trench 445). Figure 4 The schematic diagram illustrates the various elements of the SPAD array 400, and modifications to the various components and other arrangements of the SPAD array 400 are possible according to various embodiments.

[0071] As previously mentioned Figure 3 As described in SPAD array 300, an n-doped region 425 is disposed on the top surface of semiconductor layer 410. However, compared to SPAD array 300, SPAD array 400 includes one or more corresponding trenches, including trench 445. In various embodiments, corresponding cells (e.g., individual SPADs) may be separated by trench 445. Introducing deep trenches (e.g., trenches extending from dielectric layer 415 and at least partially into substrate 405) as cell separators reduces optical crosstalk between adjacent cells. This may generally be referred to as deep trench isolation (DTI). Thus, trench 445 may be a channel formed in semiconductor layer 410, configured to optically isolate corresponding SPAD cells from other SPAD cells.

[0072] For example, adding surface topography to surface texture 430 does not hinder the implementation of trenches (including trench 445) of various materials or different layouts. In some instances, the trenches may be filled with the same dielectric material as in dielectric layer 415 (e.g., SiO, etc.). In other instances, the trenches may be filled with other materials, such as metals (e.g., W, Cu, etc.).

[0073] Figure 5This is a partial schematic cross-sectional view of an alternative configuration of a SPAD array 500 characterized by an intermediate dielectric layer according to various embodiments. The SPAD array 500 includes a substrate 505, a semiconductor layer 510, a dielectric layer 515, electrodes 535, avalanche regions 520, n-doped regions 525, surface textures 530, and trenches 545. Compared to the cells of SPAD arrays 100, 300, and 400, the SPAD array 500 is further characterized by an insulating channel 550 and an insulating layer 555. Figure 5 The schematic diagram illustrates the various elements of the SPAD array 500, and modifications to the various components and other arrangements of the SPAD array 500 are possible according to various embodiments.

[0074] As previously mentioned Figure 3 As described, the n-doped region 525 of a cell in the SPAD array 500 may include pillars extending into the semiconductor layer 510. The n-doped region 525 may include a top 560, pillars 565, and ends 570, as previously described. The ends of the n-doped region 525 may be located within the semiconductor layer 510. Therefore, the n-doped region 525 may have a "T-shaped" structure, wherein the top 560 of the "T" is disposed on the semiconductor layer 510 (e.g., on its top surface), and the pillars 565 of the n-doped region 525 extend downward from the top 560 of the "T" into the semiconductor layer 510. Thus, in various embodiments, a channel extending longitudinally downward into the semiconductor layer 510 may be formed within the semiconductor layer 510.

[0075] In some instances, the pillars 565 of the n-doped region 525 may be surrounded by an insulating channel 550. The insulating channel 550 may be a dielectric material, such as the dielectric material of the dielectric layer 515 (e.g., SiO), which provides electrical insulation between the pillars 565 of the n-doped region 525 and the surrounding semiconductor layer 510. In this configuration, only the ends 570 of the n-doped region 525 (e.g., the first ends of the pillars 565 on opposite sides of the top surface) are in direct contact with the semiconductor layer 510. In this arrangement, the pn junction is pushed lower into the semiconductor layer 510 (and the corresponding avalanche region 520), as in... Figure 1 In the arrangement of cells of the SPAD array 100.

[0076] In various embodiments, the SPAD array 500 further includes an insulating layer 555. The insulating layer 555 may be disposed on a substrate 505 between the substrate 505 and the semiconductor layer 510. The insulating layer 555 may be formed of a dielectric material (e.g., the dielectric material used in dielectric layer 515, such as SiO). In various embodiments, the insulating layer 555 may be configured to reflect light back into the optically active region of the cell, thereby extending the photon path into the active region of the semiconductor layer 510 (e.g., a high-field region (e.g., avalanche region 520) or a larger sensitive region surrounding the high-field region). For example, in some embodiments, the insulating layer 555 may further include a metal layer within the dielectric material of the insulating layer 555. In some instances, the metal layer of the insulating layer 555 may extend in a coplanar direction with the dielectric material. In some embodiments, the metal layer may be a structure formed within the dielectric material, such as a coplanar, orthogonal, or angled wall located within the dielectric material.

[0077] In various embodiments, the semiconductor layer 510 used in the context of the SPAD array 500 may not be formed via an epitaxial process, unlike the previously described semiconductor layers 110, 310, 410. The semiconductor layer 510 may instead be lightly p-doped (e.g., p-doped). - The semiconductor layer 510 is a doped semiconductor layer disposed on an insulating layer formed via a silicon-on-insulator (SOI) process. Specifically, in some examples, the semiconductor layer 510 may be a semiconductor material (e.g., a silicon wafer) bonded to the insulating layer 555 via a wafer bonding process. In other examples, the insulating layer 555 and the “epitaxy” layer 510 may be formed using a separation process performed by ion implantation (e.g., SIMOX).

[0078] In some instances, the SPAD array 500 may optionally further include trenches 545 configured to separate adjacent (e.g., adjacent) SPAD cells. Specifically, in some instances, trenches 545 may extend between dielectric layer 515 and insulating layer 555. As previously described, trenches 545 may be implemented as portions of a DTI that optically and / or electrically insulate adjacent cells. In other instances, the SPAD array 500 may not feature trenches (e.g., trench 545).

[0079] exist Figures 1 to 5In each of the SPAD arrays 100 to 500, surface textures 130, 210, 330, 430, and 530 may be disposed on the top surface (e.g., the first side) of semiconductor layers 110, 310, 410, and / or semiconductor layer 510, without interfering with high-field regions (e.g., avalanche regions 120, 320, 420, and 520) or other portions of the corresponding n-doped regions 125, 325, 425, and 525, or other structures (e.g., trenches 445 and 545). Various AR morphologies can be utilized in the surface textures, as will be discussed below. Figure 6 describe.

[0080] Figure 6 The illustrations depict corresponding perspective views of several surface morphologies according to various embodiments. Specifically, surface textures (e.g., surface textures 130, 210, 330, 430, 530) may be disposed at semiconductor / dielectric interfaces (e.g., the interface between a respective dielectric layer and a semiconductor layer (including an epitaxial layer)) as previously described. Surface textures may be disposed on “free” surfaces (e.g., top surfaces) of the semiconductor and / or epitaxial layers, where the texture does not interfere with high-field regions (e.g., avalanche regions) or sensitive regions within or near the semiconductor / epitaxy layer.

[0081] In some instances, a biomimetic surface morphology 605 can be utilized. In this example, the surface morphology can mimic the structure of a moth's eye. Therefore, nanostructures with similar geometries can be formed on the top surface of the semiconductor / epitaxy layer. These nanostructures can provide broadband and omnidirectional anti-reflective properties exceeding those of a double-layer coating. In some instances, the biomimetic surface morphology 605 can have a parabolic shape and is referred to as a parabolic papillary array.

[0082] In some instances, a porous surface morphology 610 can be utilized. In this instance, nanoscale pores with large hydrogenation surfaces can be utilized. The pores can form multiple peaks with variable heights and variable distributions.

[0083] In other embodiments, a pyramidal surface topography 615 is provided, wherein a pyramidal structure is formed on the top surface of the semiconductor layer / epitaxial layer. In still other embodiments, a grating topography 620 is provided. Specifically, a pyramidal structure may be formed in which each face of the pyramid exhibits grating lines of variable width, height, and / or length. Each face itself may have a relative angle that is fixed and / or variable along the height of the pyramid (e.g., from the base to the end).

[0084] Figure 7The illustration depicts a schematic perspective view of a photonic surface topography 700 characterized by holes according to various embodiments. As depicted, in various embodiments, an array of holes can be formed within a semiconductor layer. In some instances, the hole array may be randomly distributed. In other instances, the hole array may be arranged according to a pattern, grid, or other design.

[0085] Figure 8 The illustrations depict schematic perspective views of photonic surface topologies characterized by multiple layers of holes and rods according to various embodiments. Like surface topology 700, surface topology 800 may be characterized by a semiconductor layer with holes. The layers with holes may alternate with rod layers disposed on the semiconductor layers with holes. The rod layers may separate the semiconductor layers with holes from the next (e.g., adjacent) semiconductor layer with holes. Therefore, the next semiconductor layer with holes may be disposed on the rod layer. In this way, the semiconductor layers with holes may alternate with the rod layers.

[0086] Figure 9 The illustration shows a schematic perspective view of a photonic surface topography 900 characterized by a lattice structure according to various embodiments. In various examples, the lattice structure can be formed on (or within) a semiconductor layer, as described above. In some examples, multiple elongated structures can be used to form the lattice structure. The elongated structure can be formed from a dielectric material, for example, via an epitaxial process. The elongated structure may include, but is not limited to, structures such as fins, pillars, trenches, or walls. The elongated structure can be formed on (or within) a semiconductor layer (e.g., semiconductor layers 110, 210, 310). In various examples, an array of elongated structures can be formed from multiple elongated structures. The array of elongated structures can extend co-existing in the longitudinal direction (e.g., parallel or nearly parallel within the limitations and tolerances of manufacturing technology). A next layer can be disposed on the array of elongated structures. The next layer may similarly include an array of elongated structures that are parallel to each other but offset at an angle from the elongated structures of the preceding (e.g., underlying) layer. For example, in some embodiments, any two adjacent elongated structures can be arranged orthogonally to each other (e.g., the longitudinal axes of the elongated layers are orthogonal or nearly orthogonal within the limitations and tolerances of manufacturing technology). In other instances, different offset angles can be used, such as, but not limited to, 30 degrees, 45 degrees, 60 degrees, etc.

[0087] By employing surface textures and utilizing photonic surface topography, the photoelectric detection efficiency of individual SPADs and SiPMs (e.g., SPAD arrays) can be improved over a wide wavelength range.

[0088] Furthermore, compared to typical planar pn junction methods, the point-like pn junctions and corresponding point-like high-field regions of SPADs allow surface textures to become features occupying a larger area of ​​the SPAD array. Introducing AR topography to the top surface (e.g., the first side or the front side facing the light source) can greatly improve the efficiency and sensitivity of photodetectors by improving light transmission and the randomness of the direction of light entering the semiconductor / epitaxy layer.

[0089] While some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that numerous modifications are possible. For example, although the various methods and processes described herein may be described with respect to specific structures and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any particular structure and / or functional architecture, but can instead be implemented in any hardware configuration suitable for them. Similarly, while a certain functionality may belong to one or more system components, unless the context otherwise requires, this functionality may be distributed among a variety of other system components according to several embodiments.

[0090] Furthermore, although the methods and processes described herein are presented in a particular order for ease of description, various processes may be reordered, added, and / or omitted according to various embodiments unless the context otherwise requires. Moreover, processes described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described with respect to a particular architecture and / or system may be organized in an alternative architecture and / or incorporated into other described systems. Therefore, although various embodiments are described as having or lacking certain features for ease of description and illustration of aspects of those embodiments, various components and / or features described herein with respect to particular embodiments may be replaced, added, and / or deleted in other described embodiments unless the context otherwise requires. Therefore, although several embodiments have been described above, it should be understood that the invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A photodetector, comprising: A semiconductor layer having a top surface located on a first side, wherein the semiconductor layer is configured to allow light to enter via the first side, the semiconductor layer comprising: The host body has type I doping; A first region having a second type of doping, different from the first type; and The first fraction of the surface area of ​​the top surface of the semiconductor layer includes the surface morphology; The semiconductor layer further includes a junction formed between the body and the first region. The knot is configured to have a corresponding surface area, the corresponding surface area being a second fraction of the surface area of ​​the top surface, wherein the second fraction is less than the first fraction; and Electrodes that are coupled to the first region.

2. The photodetector according to claim 1, further comprising: A substrate having a different concentration of the first type of doping than the host, wherein the semiconductor layer is disposed on the substrate.

3. The photodetector according to claim 2, wherein the semiconductor layer is an epitaxial layer formed on the substrate.

4. The photodetector according to claim 2, further comprising: An insulating layer disposed on the substrate, wherein the insulating layer is formed of a dielectric material, and wherein the semiconductor layer is disposed on the insulating layer.

5. The photodetector of claim 2, further comprising a dielectric layer disposed on the top surface of the semiconductor layer, and a trench formed in the semiconductor layer, wherein the trench has a depth extending from the top surface of the semiconductor layer into at least part of the substrate.

6. The photodetector according to claim 5, wherein the trench is filled with a dielectric material.

7. The photodetector of claim 1, wherein the first region includes a top portion disposed on the top surface of the semiconductor layer and in contact with the electrode, a post extending from the top portion into the body, and an end portion located at a first end of the post, wherein a junction is formed between the end portion and the body.

8. The photodetector of claim 7, further comprising an insulating channel formed around at least a portion of the pillar in the first region and between the first region and the body, wherein the insulating channel is configured to electrically insulate at least a portion of the first region from the semiconductor layer.

9. The photodetector according to claim 1, wherein the second type of doping is heavy n-type doping, and wherein the junction is a pn junction.

10. The photodetector according to claim 1, wherein the surface morphology is a parabolic papillary array.

11. An apparatus comprising: A semiconductor layer having a first surface, the semiconductor layer comprising: The host body has type I doping; A first region having a second type of doping, different from the first type; and The first fraction of the surface area of ​​the first surface of the semiconductor layer includes the surface morphology; The semiconductor layer further includes a junction formed between the body and the first region, wherein the junction is configured to have a surface area that is a second fraction of the surface area of ​​the first surface, wherein the second fraction is less than the first fraction.

12. The device according to claim 11, further comprising: A substrate having the first type of doping, wherein the semiconductor layer is disposed on the substrate.

13. The device according to claim 11, further comprising: An insulating layer disposed on the substrate, wherein the insulating layer is formed of a dielectric material, and wherein the semiconductor layer is disposed on the insulating layer.

14. The device of claim 11, further comprising a dielectric layer disposed on the first surface of the semiconductor layer, and a trench formed in the semiconductor layer, wherein the trench has a depth extending from the first surface of the semiconductor layer into at least part of the substrate.

15. The device of claim 11, wherein the first region includes a top portion disposed on the first surface of the semiconductor layer and in contact with an electrode, a pillar extending from the top portion into the body, and an end portion located at a first end of the pillar, wherein a junction is formed between the end portion and the body.

16. A photodetector array, comprising: Multiple photodetectors are arranged in a grid on a substrate, the multiple photodetectors including a first photodetector, the first photodetector comprising: A semiconductor layer having a top surface located on a first side, wherein the semiconductor layer is configured to allow light to enter via the first side, the semiconductor layer comprising: The host body has type I doping; A first region having a second type of doping, different from the first type; and The first fraction of the surface area of ​​the top surface of the semiconductor layer includes the surface morphology; The semiconductor layer further includes a junction formed between the body and the first region. The knot is configured to have a corresponding surface area, which is a second fraction of the surface area of ​​the top surface, wherein the second fraction is less than the first fraction.

17. The photodetector array of claim 16, wherein the surface morphology is a parabolic nipple array.

18. The photodetector array of claim 16, wherein the first photodetector further comprises: A substrate having a different concentration of the first type of doping than the host, wherein the semiconductor layer is disposed on the substrate; and An insulating layer disposed on the substrate, wherein the insulating layer is formed of a dielectric material, and wherein the semiconductor layer is disposed on the insulating layer.

19. The photodetector array of claim 16, further comprising a dielectric layer disposed on the top surface of the semiconductor layer, and a trench formed in the semiconductor layer and at least partially disposed between the first photodetector and adjacent photodetectors among the plurality of photodetectors, wherein the trench has a depth extending from the top surface of the semiconductor layer into at least partially within the substrate.

20. The photodetector array of claim 16, wherein the first region includes a top portion disposed on the top surface of the semiconductor layer and in contact with an electrode, a pillar extending from the top portion into the body, and an end portion located at a first end of the pillar, wherein a junction is formed between the end portion and the body.

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