Image sensor

Abstract

The present disclosure relates to an image sensor, and more particularly, to an image sensor having an enhancement structure. An image sensor according to some embodiments includes: a substrate; a plurality of unit regions; a plurality of isolation parts; and a doped region in the substrate. At least one of the plurality of cell regions includes a photoelectric conversion portion in the substrate. The plurality of isolation portions are disposed to correspond to boundaries of the plurality of cell regions. The plurality of isolation portions includes a first isolation portion and a second isolation portion having a height smaller than a height of the first isolation portion. The plurality of isolation portions includes a conductive layer. The doped region is electrically connected to a portion of the conductive layer in the second isolation.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0064614, filed on May 17, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The disclosure relates to an image sensor, and more particularly, to an image sensor having an enhanced structure. BACKGROUND

[0003] An image sensor is a semiconductor device that converts an optical image into an electrical signal. The image sensor can be classified into a charge-coupled device (CCD) type image sensor and a complementary metal-oxide semiconductor (CMOS) type image sensor (CIS) based on a silicon semiconductor.

[0004] Among them, the CMOS type image sensor can be driven by a simple method, and a signal processing circuit can be integrated on a single chip in the CMOS type image sensor. Accordingly, the CMOS type image sensor can be downsized and have low power consumption, and thus can be applied to products having a limited battery capacity. As the electronic industry advances, various researches are continuing to improve the performance of the CMOS type image sensor. SUMMARY

[0005] The disclosure attempts to provide an image sensor capable of enhancing performance and productivity.

[0006] An image sensor according to some embodiments includes a substrate, a plurality of unit regions, a plurality of isolation portions, and a doped region, in the substrate. At least one of the plurality of unit regions includes a photoelectric conversion portion in the substrate. The plurality of isolation portions are disposed to correspond to boundaries of the plurality of unit regions. The plurality of isolation portions include a first isolation portion and a second isolation portion, the second isolation portion having a height less than a height of the first isolation portion. The plurality of isolation portions include a conductive layer. The doped region is electrically connected to a portion of the conductive layer in the second isolation portion.

[0007] An image sensor according to some embodiments includes a substrate, a pixel array region including a plurality of pixel regions and a dummy array region including a plurality of dummy regions, a first isolation portion, a second isolation portion, and a doped region. The plurality of pixel regions respectively include a plurality of photoelectric conversion portions in the substrate. The first isolation portion is between the photoelectric conversion portions of the plurality of pixel regions in the pixel array region. The second isolation portion extends into the substrate to correspond at least at boundaries of the dummy regions of the plurality of dummy regions. The second isolation portion includes a conductive end through which a conductive layer is exposed. The doped region is in the substrate and is electrically connected to the conductive end of the second isolation portion.

[0008] An image sensor according to some embodiments includes a photoelectric conversion substrate and an additional wiring portion on a first surface of the photoelectric conversion substrate and including a pad configured to be electrically connected to an external element. The photoelectric conversion substrate includes a substrate, a plurality of cell regions, a plurality of isolation portions, a doped region, and a wiring portion. At least one of the plurality of cell regions includes a photoelectric conversion portion in the substrate. The plurality of isolation portions are provided corresponding to boundaries of the plurality of cell regions, and the plurality of isolation portions include a conductive layer. The doped region is in the substrate and electrically connected to a portion of the conductive layer of the plurality of isolation portions. The wiring portion is adjacent to the first substrate surface of the substrate and electrically connected to the additional wiring portion. The wiring portion includes a connection wiring electrically connected to the doped region.

[0009] According to some embodiments, the doped region electrically connected to the conductive layer in at least one of the plurality of isolation portions (e.g., the second isolation portion) in the substrate can be used to improve the dark current. For example, by applying a voltage (e.g., a negative voltage) to the isolation portion via the connection wiring electrically connected to the doped region, the dark current can be improved by hole accumulation.

[0010] The connection wiring can be included in the wiring portion adjacent to the first substrate surface of the substrate, so the path for applying a voltage to the isolation portion can be shortened, and the image sensor can be manufactured by an easy process. Thus, the performance of the image sensor can be enhanced by effectively applying a voltage to the isolation portion, and the productivity and yield of the image sensor can be enhanced by simplifying the manufacturing process and reducing process errors. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a block diagram schematically illustrating an example of an image sensor.

[0012] Figure 2 is a plan view schematically illustrating an image sensor according to some embodiments.

[0013] Figure 3 is a schematic cross-sectional view taken along line A-A' in Figure 2 .

[0014] Figure 4 is a rear plan view illustrating part B of Figure 2 .

[0015] Figure 5 is an enlarged view illustrating part C of Figure 3 .

[0016] Figure 6 is a rear plan view illustrating part D of Figure 2 .

[0017] Figures 7 to 16is a cross-sectional view schematically illustrating a manufacturing method of an image sensor according to some embodiments.

[0018] Figure 17 is a plan view schematically illustrating an image sensor according to some embodiments.

[0019] Figure 18 is a cross-sectional view schematically illustrating an image sensor according to some embodiments.

[0020] Figure 19 is a cross-sectional view schematically illustrating an image sensor according to some embodiments. DETAILED DESCRIPTION

[0021] Embodiments of the present disclosure are described below in greater detail with reference to the accompanying drawings, so that those skilled in the art to which the present disclosure pertains can easily practice the present disclosure. The present disclosure can be implemented in various different forms and is not limited to the embodiments provided herein.

[0022] In order to clearly describe the present disclosure, portions unrelated to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

[0023] In addition, since the sizes and thicknesses of portions, regions, members, units, layers, films, and the like shown in the drawings can be arbitrarily shown for better understanding and ease of explanation, the present disclosure is not limited to the shown sizes and thicknesses. In the drawings, the thicknesses of portions, regions, members, units, layers, films, and the like can be exaggerated or enlarged for ease of explanation and / or simple illustration.

[0024] It will be understood that when a component (such as a layer, film, region, or substrate) is referred to as being "on" another component, it can be directly on the other component or intervening components can also be present. In contrast, when a component is referred to as being "directly on" another component, there are no intervening components present. Furthermore, when a component is referred to as being "on" or "over" a reference component, the component can be positioned on or below the reference component, and need not be "on" or "over" the reference component in the opposite direction of gravity.

[0025] In addition, unless explicitly described to the contrary, the word "comprise" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of any stated components but not the exclusion of any other components.

[0026] In addition, throughout the specification, the phrase "on a plane," "in a plane," "on a plan view," or "in a plan view" can indicate a case where a portion is viewed from above or the top, and the phrase "on a cross-section" or "in a cross-sectional view" can indicate a case where a vertical cross-section is viewed from the side. Two elements can be "connected" by an electrical connection and / or a physical connection.

[0027] Hereinafter, an image sensor and a manufacturing method of an image sensor according to some embodiments will be described with reference to the accompanying drawings. Figures 1 to 16 The image sensor and the manufacturing method of the image sensor according to some embodiments are described in detail.

[0028] Figure 1 is a block diagram schematically illustrating an example of an image sensor 10.

[0029] Referring to Figure 1 , the image sensor 10 according to some embodiments can include a pixel array 10b and a logic circuit 20 that controls the pixel array 10b. The logic circuit 20 is a circuit configured to control the pixel array 10b, and can include, for example, a controller 22, a timing generator 24, a row driver 26a, a readout circuit 26b, a ramp signal generator 26c, and a data buffer 28. The image sensor 10 can further include an image signal processor 30. In some embodiments, the image signal processor 30 can be provided outside the image sensor 10.

[0030] The image sensor 10 can generate an image signal by converting light received from the outside into an electrical signal, and the image signal generated by the image sensor 10 can be provided to the image signal processor 30.

[0031] The image sensor 10 can be mounted on an electronic device having an image or light sensing function. For example, the image sensor 10 can be mounted on an electronic device such as a camera, a smartphone, a wearable device, an Internet of Things (IoT) device, a home appliance device, a tablet, a Personal Digital Assistant (PDA), a Portable Multimedia Player (PMP), a navigation, a drone, or an Advanced Driver Assistance System (ADAS). In some embodiments, the image sensor 10 can be mounted on a vehicle, furniture, a manufacturing facility, a door, or an electronic device provided as part of various measurement devices.

[0032] The pixel array 10b can include a plurality of pixel regions PX, and a plurality of row lines RL and a plurality of column lines CL electrically connected to the plurality of pixel regions PX, respectively.

[0033] In some embodiments, each pixel region PX can include at least one photoelectric conversion device. The photoelectric conversion device can detect incident light and convert the incident light into an electrical signal, i.e., a plurality of analog pixel signals, according to the amount of incident light. The photoelectric conversion device can be a photodiode or a pinned diode. In some embodiments, the photoelectric conversion device can be a Single Photon Avalanche Diode (SPAD) applied to a 3-dimensional (3D) sensor pixel. The level of the analog pixel signal output from the photoelectric conversion device can be proportional to the amount of light provided to each pixel region PX or the amount of charge output from the photoelectric conversion device.

[0034] A plurality of row lines RL can extend in one direction and be electrically connected to a plurality of pixel regions PX arranged in the one direction. For example, a control signal output from the row driver 26a to the row line RL can be sent to the gate of a transistor of the plurality of pixel regions PX connected to the row line RL. A column line CL can extend in an intersecting direction that is transverse to the one direction, intersects, or crosses the one direction, and can be connected to a plurality of pixel regions PX arranged in the intersecting direction or the crossing direction that is transverse to the one direction. A plurality of pixel signals output from the plurality of pixel regions PX can be sent to the readout circuit 26b through a plurality of column lines CL.

[0035] In some embodiments, the plurality of pixel regions PX can be grouped in the form of a plurality of columns and a plurality of rows to form one unit pixel group. That is, the plurality of pixel regions PX arranged in the extension direction of the row line RL and the plurality of pixel regions PX arranged in the extension direction of the column line CL can form one unit pixel group. For example, one unit pixel group includes a plurality of pixels arranged in the form of two columns and two rows, and one unit pixel group can output one analog pixel signal. However, embodiments are not limited thereto, and various modifications are possible.

[0036] In some embodiments, each pixel region PX can include a pixel circuit that processes charge generated by a photoelectric conversion device and outputs an electrical signal. The pixel circuit can include a transfer transistor, a reset transistor, a selection transistor, a drive transistor, and the like. Embodiments are not limited thereto, and the pixel circuit can have various structures.

[0037] The controller 22 can generally control the timing generator 24, the row driver 26a, the readout circuit 26b, the ramp signal generator 26c, and the data buffer 28 included in the image sensor 10. For example, the controller 22 can control the operation timing by using a control signal. In some embodiments, the controller 22 can receive a mode signal indicating an image mode from an application processor, and generally control the image sensor 10 based on the received mode signal.

[0038] The timing generator 24 can generate a signal used as a reference for the operation timing of the image sensor 10. The timing generator 24 can provide a control signal that controls the timing of the row driver 26a, the readout circuit 26b, and the ramp signal generator 26c.

[0039] The row driver 26a can generate a control signal for driving the pixel array 10b in response to a control signal of the timing generator 24, and can supply the control signal to a plurality of pixel regions PX of the pixel array 10b through a plurality of row lines RL. For example, the row driver 26a can generate a transfer signal that controls a transfer transistor, a reset control signal that controls a reset transistor, and a selection control signal that controls a selection transistor, and supply the transfer signal, the reset control signal, and the selection control signal to the pixel array 10b.

[0040] The readout circuit 26b can convert a pixel signal (or an electrical signal) output through a corresponding column line CL into a pixel value that represents an amount of light. The ramp signal generator 26c can generate a reference signal or a ramp signal, and transmit the reference signal or the ramp signal to the readout circuit 26b. For example, the readout circuit 26b can convert the pixel signal into the pixel value by comparing the ramp signal and the pixel signal. The pixel value can be image data having a plurality of bits.

[0041] The data buffer 28 can store the pixel value of the pixel region PX transmitted from the readout circuit 26b, and can output the stored pixel value in response to a signal from the controller 22.

[0042] The image signal processor 30 can perform image signal processing on an image signal received from the data buffer 28. For example, the image signal processor 30 can receive a plurality of image signals from the data buffer 28, and generate one image by combining the received image signals.

[0043] Embodiments are not limited to the above description, and the structure, type, etc. of the image sensor 10 can be variously modified.

[0044] Figure 2 is a plan view schematically showing the image sensor 10 according to some embodiments. For clear understanding, in Figure 2 , the pixel array region 12, the dummy array region 14, the pad region 16, the pixel region PX, the dummy pixel region DPX, the dummy region DA, the isolation portion 130, and the pad 210 of the image sensor 10 are mainly shown.

[0045] Referring to Figure 2 , the image sensor 10 according to some embodiments can include the pixel array region 12 and the dummy array region 14. In the pixel array region 12 and the dummy array region 14, a plurality of cell regions can be disposed. The cell region can include the pixel region PX, the dummy pixel region DPX, and / or the dummy region DA.

[0046] In a plan view, the pixel array region 12 can be provided in a central region of the image sensor 10, and the dummy array region 14 can be provided in an outer region of the pixel array region 12 to surround the pixel array region 12. At least a part of the dummy array region 14 can be an optical black region in which light is blocked by the optical black layer 190 (refer to Figure 3 ).

[0047] In the pixel array region 12, a plurality of pixel regions PX can be provided. The plurality of pixel regions PX can be provided to have a plurality of rows and a plurality of columns. For example, the plurality of pixel regions PX can be adjacent to each other in each of a first direction (Y-axis direction in the drawing) and a second direction (X-axis direction in the drawing) that is transverse to, intersects, or intersects with the first direction. The pixel region PX can include a photoelectric conversion section 120 (refer to Figure 3 ) and a pixel circuit 160 (refer to Figure 3 ).

[0048] In the dummy array region 14, at least a plurality of dummy regions DA can be provided, and a plurality of dummy pixel regions DPX can be further provided. The dummy pixel region DPX can include the photoelectric conversion section 120 and / or the pixel circuit 160 included in the pixel region PX, and can provide a reference charge amount in a state in which light is blocked. The dummy region DA can not include the photoelectric conversion section 120 and the pixel circuit 160, and can have a structure different from that of the pixel region PX and the dummy pixel region DPX. A first dummy array region 14a including the dummy pixel region DPX can be an optical black region provided with the optical black layer 190. A second dummy array region 14b including the dummy region DA can be an optical black region provided with the optical black layer 190 or a region not provided with the optical black layer 190.

[0049] In Figure 2 , as one example, it is shown that the first dummy array region 14a including the dummy pixel region DPX includes one row or one column for surrounding the pixel array region 12 in the outer region of the pixel array region 12, and the second dummy array region 14b including the dummy region DA includes two rows or two columns for surrounding the first dummy array region 14a in the outer region of the first dummy array region 14a. However, the embodiments are not limited to this. Thus, the arrangement, shape, and the like of the first dummy array region 14a and the second dummy array region 14b can be variously modified, and / or the arrangement, number, and the like of the dummy pixel region DPX and the dummy region DA can be variously modified.

[0050] In some embodiments, the isolation section 130 can include a first isolation section 140 and a second isolation section 150.

[0051] In the pad area 16, a pad 210 configured to be connected to an external element can be provided. The pad 210 can receive a voltage or a voltage signal supplied from an external circuit or the like, and transmit the received voltage or voltage signal to the image sensor 10 to operate the image sensor 10, and can transmit an electric signal generated in the pixel area PX and / or the dummy pixel area DPX to the external circuit or the like. In a plan view, the pad area 16 can be provided in an edge portion of the image sensor 10. Thereby, the pad 210 can be easily connected to the external circuit or the like.

[0052] In Figure 2 , as one example, it is shown that the pad area 16 or the pad 210 can be provided at both sides in the second direction (X-axis direction in the drawing). However, the embodiments are not limited thereto. Thus, the pad area 16 or the pad 210 can be provided at at least one of both sides in the first direction (Y-axis direction in the drawing), and / or can be provided at at least one of both sides in the second direction. The position, arrangement, etc. of the pad area 16 or the pad 210 can be variously modified.

[0053] In Figure 2 , as one example, it is shown that the isolation portion 130 is not provided in the pad area 16. However, the embodiments are not limited thereto. In some embodiments, in the pad area 16, the isolation portion 130 or a structure having the same or similar shape as that of the isolation portion 130 can be provided for electrical isolation.

[0054] With Figure 2 reference to Figures 3 to 6 , the pixel area PX, the dummy pixel area DPX, the dummy area DA, the isolation portion 130, and the pad 210 will be described in more detail.

[0055] Figure 3 is a schematic cross-sectional view taken along the line A-A' in Figure 2 .

[0056] With reference to Figure 2 and Figure 3 , the image sensor 10 according to some embodiments can include the photoelectric conversion substrate 100, and can further include an additional wiring portion 200 provided on the first surface 101 of the photoelectric conversion substrate 100 and including a pad 210 configured to be connected to the outside. The wiring portion 170 can be provided adjacent to the first surface 101 (lower surface in Figure 3 ) of the photoelectric conversion substrate 100, and the light-receiving portion including the color filter 182, the microlens 188, etc. can be provided adjacent to the second surface 102 (upper surface in Figure 3 ) of the photoelectric conversion substrate 100 opposite to the first surface 101. The photoelectric conversion substrate 100 can be referred to as a photoelectric conversion structure.

[0057] In some embodiments, the photoelectric conversion substrate 100 can include a substrate 110, a plurality of unit regions, a plurality of separation portions 130, and a doped region 130d. At least one of the unit regions can include a photoelectric conversion portion 120 in the substrate 110. The plurality of separation portions 130 can separate, divide, or define respective portions of the plurality of unit regions (e.g., the plurality of photoelectric conversion portions 120) in the substrate 110, or can be provided to correspond to boundaries of the plurality of unit regions. The separation portion 130 can include a conductive layer 134. The doped region 130d can be provided in the substrate 110. The doped region 130d can be electrically connected to a portion of the conductive layer 134 included in at least one of the plurality of separation portions 130. For example, the second doped region 150d (refer to Figure 5 ) can be electrically connected to the second conductive portion 154 (refer to Figure 5 ) included in the second separation portion 150. The plurality of unit regions can include a pixel region PX, a dummy pixel region DPX, and / or a dummy region DA. The separation portion 130 can be provided to separate, divide, or define respective portions of the pixel region PX, the dummy pixel region DPX, and / or the dummy region DA (e.g., the plurality of photoelectric conversion portions 120) in the substrate 110. The separation portion 130 can be provided to correspond to boundaries of the pixel region PX, the dummy pixel region DPX, and / or the dummy region DA in the substrate 110.

[0058] The pixel circuit 160 and the wiring portion 170 can be provided adjacent to a first substrate surface 111 (a lower surface in Figure 3 ) of the substrate 110, and a light-receiving portion including a color filter 182, a microlens 188, and the like can be provided on a second substrate surface 112 (an upper surface in Figure 3 ) of the substrate 110 opposite to the first substrate surface 111. The first substrate surface 111 of the substrate 110 can be an upper surface in a manufacturing process of the photoelectric conversion substrate 100, and the second substrate surface 112 of the substrate 110 can be a lower surface in the manufacturing process of the photoelectric conversion substrate 100.

[0059] In some embodiments, the substrate 110 can include or be formed of a semiconductor substrate including a semiconductor material. For example, the substrate 110 can include a bulk substrate including a semiconductor material, a substrate including a bulk substrate and an epitaxial layer on the bulk substrate, or a semiconductor-on-insulator. In this case, the semiconductor material included in the substrate 110 can include a first conductive type dopant having a first conductive type (e.g., a p-type or an n-type).

[0060] The semiconductor material included in the substrate 110 can include at least one of a Group IV semiconductor, a Group III-V compound semiconductor, and a Group II-VI compound semiconductor. For example, the semiconductor material included in the substrate 110 can include at least one of Si, Ge, SiGe, SiC, GaAs, InAs, GaP, InP, InSb, InGaAs, ZnTe, and CdS. For example, the bulk substrate can be a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate, and can include Si, Ge, or SiGe. In some embodiments, the semiconductor-on-insulator can be a silicon-on-insulator (SOI), a germanium-on-insulator (GOI), or a silicon-germanium-on-insulator (SGOI).

[0061] In some embodiments, the substrate 110 can include a pixel array region 12 in which a plurality of pixel regions PX is disposed, and a dummy array region 14 in which a plurality of dummy regions DA and / or a plurality of dummy pixel regions DPX is disposed.

[0062] In at least a portion of the pixel regions PX and the dummy pixel regions DPX of the substrate 110, a photoelectric conversion section 120 configured to convert light into an electrical signal can be disposed. In the dummy regions DA of the substrate 110, the photoelectric conversion section 120 can not be disposed.

[0063] The photoelectric conversion section 120 can include a second-conductivity-type well 120a, and can further include a first-conductivity-type well 120b. The second-conductivity-type well 120a can include a second-conductivity-type dopant having a second conductivity type (e.g., n-type or p-type) opposite to the substrate 110. The first-conductivity-type well 120b can include a first-conductivity-type dopant having a first conductivity type (e.g., p-type or n-type). The photoelectric conversion section 120 as a part of a photodiode can generate and accumulate an electric charge proportional to an amount of light provided to each pixel region PX or each dummy pixel region DPX. The second-conductivity-type well 120a can be formed by doping the second-conductivity-type dopant to the substrate 110, and the first-conductivity-type well 120b can be formed by doping the first-conductivity-type dopant to the substrate 110. In some embodiments, the first-conductivity-type well 120b can be omitted. In this case, the photodiode can include a pn junction between the second-conductivity-type well 120a and the substrate 110 having the first conductivity type.

[0064] The photoelectric conversion section 120 can correspond to at least the plurality of pixel regions PX, respectively, by the isolation section 130. The photoelectric conversion section 120 can correspond to at least a portion of the plurality of dummy pixel regions DPX by the isolation section 130.

[0065] In one embodiment, the device isolation portion 122 can be provided in a shallow trench (ST) to separate, divide, or define an active region in at least a portion of the pixel region PX or the dummy pixel region DPX. For example, the device isolation portion 122 can be a shallow trench isolation (STI). The device isolation portion 122 can include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the device isolation portion 122 can include a single layer or multiple layers. However, embodiments are not limited thereto. Thus, different modifications can be made to the material of the device isolation portion 122, or the device isolation portion 122 can be omitted. In the drawings, a boundary between the device isolation portion 122 and the isolation portion 130 is shown for clear understanding. However, in some embodiments, the boundary between the device isolation portion 122 and the isolation portion 130 can not be identified, and the device isolation portion 122 and the isolation portion 130 can form an integral structure at a portion adjacent to the first base surface 111 of the base 110.

[0066] The isolation portion 130 can pass through, penetrate, or extend into at least a portion of the base 110. The isolation portion 130 can be provided in a first trench 140t or a second trench 150t having a greater depth than the device isolation portion 122. In one example, the device isolation portion 122 can have a smaller height than a height of one of the plurality of isolation portions 130. For example, the first trench 140t or the second trench 150t can be a deep trench (DT). In some embodiments, the isolation portion 130 (e.g., the first isolation portion 140) can include a front deep trench isolation (FDTI) including a portion adjacent to the first base surface 111 of the base 110 and / or a back deep trench isolation (BDTI) including a portion adjacent to the second base surface 112 of the base 110. In Figure 3 In one example, it is shown that the isolation portion 130 (e.g., the first isolation portion 140) includes a front deep trench isolation, but embodiments are not limited thereto. In the specification, a depth can correspond to a height in a thickness direction (Z-axis direction in the drawings) or a vertical direction of the image sensor 10.

[0067] In a plan view, the isolation portion 130 can include a first portion extending in a first direction (Y-axis direction in the drawings) and a second portion extending in a second direction (X-axis direction in the drawings). For example, in a plan view, the isolation portion 130 can have a lattice shape corresponding to boundaries of the plurality of pixel regions PX, the dummy pixel region DPX, and / or the dummy region DA. Thus, in a plan view, a pair of the first portion and a pair of the second portion can be provided corresponding to a boundary of each of the pixel regions PX, a pair of the first portion and a pair of the second portion can be provided corresponding to a boundary of the dummy pixel region DPX, and a pair of the first portion and a pair of the second portion can be provided corresponding to a boundary of the dummy region DA.

[0068] In some embodiments, the isolation portion 130 can include a conductive layer 134. Dark current can be improved by the conductive layer 134 of the isolation portion 130. More specifically, the isolation portion 130 can include the sidewall insulating layer 132 and the conductive layer 134 disposed on the sidewall insulating layer 132, and can further include the cover portion 136.

[0069] The sidewall insulating layer 132 can include a first insulating portion 132a and a second insulating portion 132b disposed on both sides of the isolation portion 130 to be adjacent to the two cell regions while placing the isolation portion 130 between the first insulating portion 132a and the second insulating portion 132b.

[0070] The sidewall insulating layer 132 can include any one of various insulating materials. For example, the sidewall insulating layer 132 can include an oxide, a nitride, an oxynitride, etc. More specifically, the sidewall insulating layer 132 can include an insulating material including silicon (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). However, embodiments are not limited to the material of the sidewall insulating layer 132. The sidewall insulating layer 132 can include a single layer or multiple layers.

[0071] The conductive layer 134 can be disposed between the first insulating portion 132a and the second insulating portion 132b. The conductive layer 134 can include any one of various conductive materials. For example, the conductive layer 134 can include an undoped semiconductor material (e.g., undoped polycrystalline semiconductor material, as one example, undoped polysilicon), a doped semiconductor material including a dopant (e.g., doped polycrystalline semiconductor, as one example, doped polysilicon), etc. The dopant included in the conductive layer 134 can be a p-type dopant or an n-type dopant, for example, a p-type dopant. For example, the p-type dopant can include boron, aluminum, gallium, indium, etc.

[0072] In some embodiments, the conductive layer 134 can include a doped semiconductor layer and an undoped semiconductor layer. For example, the doped semiconductor layer can include p-type polysilicon, and the undoped semiconductor layer can include n-type polysilicon. However, embodiments are not limited thereto. In some embodiments, the dopant (e.g., p-type dopant) included in the doped semiconductor layer can be diffused to the undoped semiconductor layer, and at least a portion of the undoped semiconductor layer can be changed to the doped semiconductor layer. In some embodiments, the conductive layer 134 can include any one of various materials, and / or the conductive layer 134 can include a single layer or three or more layers.

[0073] The cover portion 136 can be provided on the conductive layer 134 between the first insulating portion 132a and the second insulating portion 132b to be adjacent to the first base surface 111. The cover portion 136 can include, for example, an oxide, a nitride, an oxynitride, a fluoride, or the like. More specifically, the cover portion 136 can include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, and hafnium oxide. However, the embodiment is not limited to the material of the cover portion 136. The cover portion 136 can include a single layer or a plurality of layers.

[0074] The doped region 130d can be provided at a portion of the base 110 adjacent to the isolation portion 130. The doped region 130d can be provided on at least the two sidewalls of the isolation portion 130, respectively. The doped region 130d can improve the dark current together with the conductive layer 134 of the isolation portion 130. In some embodiments, the doped region 130d can be electrically connected to a portion of the conductive layer 134 included in at least one of the plurality of isolation portions 130. For example, the doped region 130d can be electrically connected to the second conductive portion 154 included in the second isolation portion 150. The doped region 130d can have a first conductivity type (p-type or n-type) which is the same as the conductivity type of the base 110. For example, the doped region 130d can have a p-type. For example, the doped region 130d can include boron, aluminum, gallium, indium, or the like as a p-type dopant.

[0075] In Figure 3 , as one example, it is shown that the surface of the device isolation portion 122 adjacent to the first base surface 111 of the base 110 and the surface of the isolation portion 130 adjacent to the first base surface 111 of the base 110 are provided on the same plane as the first base surface 111 of the base 110. However, the embodiment is not limited thereto. The first base surface 111 of the base 110 can be provided on a different plane from the surface of the device isolation portion 122 and / or the surface of the isolation portion 130. The first base surface 111 of the base 110 can be at a different height from the surface of the device isolation portion 122 and / or the surface of the isolation portion 130 in the thickness direction of the image sensor 10.

[0076] The pixel circuit 160 can be provided to be adjacent to the first base surface 111 of the base 110. The pixel circuit 160 can be provided to be adjacent to the first base surface 111 of the base 110 and the surface of the device isolation portion 122 and / or the surface of the isolation portion 130. Figure 3 Referring to Figure 4 , an example of the pixel circuit 160 can be described in detail. Figure 4 is a rear surface view of Figure 2 part B. Figure 4 The pixel circuit 160 provided on the first base surface 111 of the base 110 is shown.

[0077] Referring to Figure 3 and Figure 4In some embodiments, the pixel circuit 160 can be disposed in the pixel region PX and / or the dummy pixel region DPX defined by the isolation portion 130 and / or the device isolation portion 122. For example, the pixel circuit 160 can include at least one transistor 162, a transfer transistor 164, and a dopant region 166. In Figure 4 In some embodiments, the pixel region PX is mainly illustrated. In some embodiments, Figure 4 The pixel circuit 160 illustrated in

[0078] The transfer transistor 164 can be electrically connected to the photoelectric conversion portion 120. The transfer transistor 164 can include a transfer gate structure 164a and a floating diffusion region 164b. The floating diffusion region 164b can have a second conductive type opposite to the first conductive type of the substrate 110, and the charge generated by the photoelectric conversion portion 120 can be accumulated in the floating diffusion region 164b. The floating diffusion region 164b can be adjacent to at least one side of the transfer gate structure 164a. The shape of the floating diffusion region 164b is not as limited as illustrated in Figure 4 and can be modified differently in some embodiments.

[0079] The transfer gate structure 164a can control the movement or non-movement of the charge generated in the photoelectric conversion portion 120 to the floating diffusion region 164b or non-movement according to the voltage applied. The transfer gate structure 164a can include a transfer gate electrode, a gate dielectric layer, and / or a gate spacer.

[0080] The transistor 162 can include at least one of a reset transistor, a selection transistor, and a drive transistor included in the pixel circuit. The transistor 162 can include a gate structure and a source region and a drain region at both sides of the gate structure. For example, the transistors 162 of a plurality of pixel regions PX adjacent to each other can be shared to form the pixel circuit 160. In some embodiments, Figure 4 The four pixel regions PX illustrated in

[0081] The dopant region 166 can be separated from the floating diffusion region 164b and the transistor 162. The dopant region 166 can be doped with a first conductive type dopant having the same conductive type as the substrate 110, and a ground voltage can be applied to the dopant region 166.

[0082] Referring again to Figure 2 and Figure 3The wiring portion 170 electrically connected to the pixel circuit 160 can be provided on the first base surface 111 of the base 110. That is, the wiring portion 170 can be provided adjacent to the first base surface 111 of the base 110 (the first base surface 111 is opposite to the second base surface 112 of the base 110 to which light is incident), and thus the wiring portion 170 can not be provided in a path of light incident to the image sensor 10. Thereby, light interference caused by the wiring portion 170 can be minimized.

[0083] The wiring portion 170 can include a plurality of wiring layers 174 and contact vias 176, an interlayer insulating layer 172 is disposed between the plurality of wiring layers 174, the contact vias 176 penetrate the interlayer insulating layer 172, penetrate through the interlayer insulating layer 172, or extend into the interlayer insulating layer 172 to connect the plurality of wiring layers 174 or to connect the pixel circuit 160 and the wiring layers 174. The wiring layers 174 and the contact vias 176 can be connected to form a desired circuit. The contact vias 176 can be formed in the same process as the wiring layers 174, or can be formed in a separate process from the wiring layers 174.

[0084] The interlayer insulating layer 172 can include an insulating material. For example, the interlayer insulating layer 172 can include silicon oxide, silicon nitride, silicon oxynitride, or a low dielectric constant material. The low dielectric constant material can be a material having a lower dielectric constant than that of silicon oxide.

[0085] The wiring layers 174 or the contact vias 176 can include at least one of a metal, a metal alloy, a metal nitride, a metal silicide, and a doped semiconductor material. The metal or the metal alloy can include at least one of tungsten, molybdenum, aluminum, copper, and cobalt, and the metal nitride can include at least one of tungsten nitride, molybdenum nitride, titanium nitride, and tantalum nitride. The wiring layers 174 or the contact vias 176 can further include a metal oxide or a metal oxynitride in which the above-described material is oxidized. The wiring layers 174 or the contact vias 176 can include a single layer or a plurality of layers.

[0086] However, embodiments are not limited thereto, and the interlayer insulating layer 172 can include any one of various insulating materials, and the wiring layers 174 or the contact vias 176 can include any one of various conductive materials.

[0087] In some embodiments, the wiring portion 170 provided on the first base surface 111 of the base 110 can further include a connection wiring 178. The connection wiring 178 can be connected to the doped region 130d (for example, the second doped region 150d (refer to Figure 5 )) provided in the dummy area DA. This will be described in more detail later.

[0088] In the pixel array region 12, a horizontal insulating layer 180, a color filter 182, a filter separator 184, a protective layer 186, and a microlens 188 can be disposed on the second base surface 112 of the base 110. In the dummy array region 14 of the base 110, a horizontal insulating layer 180, an optical black layer 190, a protective layer 186, a color filter layer 192, and an organic material layer 198 can be disposed on the second base surface 112 of the base 110.

[0089] More specifically, in the pixel array region 12 and the dummy array region 14, the horizontal insulating layer 180 can be disposed on the second base surface 112 of the base 110. The horizontal insulating layer 180 can be disposed to cover or be laminated with the second base surface 112 of the base 110 and the isolation portion 130. The horizontal insulating layer 180 can function as a kind of planarization layer configured to planarize the surface so that the color filter 182, the microlens 188, and the like disposed on the horizontal insulating layer 180 can be stably formed.

[0090] The horizontal insulating layer 180 can include any one of various insulating materials. For example, the horizontal insulating layer 180 can include an oxide, a nitride, an oxynitride, or a fluoride including at least one of hafnium, zirconium, aluminum, tantalum, titanium, yttrium, cerium, lanthanum, neodymium, praseodymium, ytterbium, and silicon. For example, the horizontal insulating layer 180 can function as an anti-reflection layer, but embodiments are not limited thereto.

[0091] In some embodiments, the horizontal insulating layer 180 can include a plurality of layers including different materials and having different thicknesses. For example, in the horizontal insulating layer 180, a first horizontal insulating layer adjacent to the second base surface 112 of the base 110 can be a fixed charge layer having a negative fixed charge. Thereby, a dark current can be improved by accumulation of holes at the periphery of the fixed charge layer. In some embodiments, the first horizontal insulating layer can include a metal oxide or a metal fluoride including at least one of hafnium, zirconium, aluminum, tantalum, titanium, and yttrium. For example, the horizontal insulating layer 180 or the anti-reflection layer can include a first horizontal insulating layer including hafnium oxide, a second horizontal insulating layer including silicon oxide or silicon nitride, and a third horizontal insulating layer including hafnium oxide. However, embodiments are not limited thereto, and the number, thickness, and the like of the layers included in the horizontal insulating layer 180 can be variously modified.

[0092] In the pixel array region 12, the filter separator 184 can be disposed on the horizontal insulating layer 180. In some embodiments, the filter separator 184 can surround at least a portion of the color filter 182. For example, the filter separator 184 can have the same or similar lattice structure as the isolation portion 130, but embodiments are not limited thereto. The filter separator 184 can be referred to as a fence pattern or a mesh pattern.

[0093] The filter separator 184 can prevent light incident obliquely into one color filter 182 in one pixel region PX from entering another color filter 182 in an adjacent pixel region PX. Accordingly, cross talk between the plurality of pixel regions PX can be prevented.

[0094] In some embodiments, the filter separator 184 can include a material having a refractive index smaller than that of the color filter 182 or silicon oxide, or include a material having a refractive index of about 1.0 to about 1.4. When the filter separator 184 includes the material having a small refractive index as described above, light incident on the filter separator 184 can be totally reflected and directed to the inside of the pixel region PX.

[0095] For example, the filter separator 184 can include polymethyl methacrylate (PMMA), silicone acrylate, cellulose acetate butyrate (CAB), silicon dioxide, or fluorosilicone acrylate (FSA). For example, the filter separator 184 can include a polymer material in which silicon dioxide particles are dispersed. However, embodiments are not limited thereto, and the filter separator 184 can include a material different from the materials described above.

[0096] In the pixel array region 12, the color filter 182 can be disposed on the horizontal insulating layer 180. The plurality of color filters 182 can include, for example, a green filter, a blue filter, and a red filter. In some embodiments, the plurality of color filters 182 can include a cyan filter, a magenta filter, a yellow filter, etc. In some embodiments, a pixel region PX in which all visible light is incident can be disposed. In some embodiments, the color filter 182 can further include an infrared filter for transmitting infrared light. The plurality of color filters 182 can be separated from each other by the filter separator 184.

[0097] In at least a portion of the dummy array region 14, an optical black layer 190 can be disposed on the horizontal insulating layer 180. The optical black layer 190 can cover or overlap the entire portion of the dummy array region 14, or cover or overlap a portion of the dummy array region 14. For example, the optical black layer 190 can cover or overlap the first dummy array region 14a in which a dummy pixel region DPX including at least the photoelectric conversion portion 120 and / or the pixel circuit 160 is disposed. The optical black layer 190 can not cover or overlap the second dummy array region 14b in which the dummy area DA is disposed.

[0098] The optical black layer 190 can include a metal material, and can include a single layer or multiple layers. The optical black layer 190 can correspond to a light blocking pattern or a light shielding pattern that blocks light incident on at least a portion of the dummy array area 14.

[0099] For example, the optical black layer 190 can include a metal layer including at least one of tungsten, aluminum, copper, titanium, and tantalum, or an alloy including at least one of tungsten, aluminum, copper, titanium, and tantalum. The optical black layer 190 can further include a diffusion barrier layer between the horizontal insulating layer 180 and the metal layer. The diffusion barrier layer can include a metal nitride layer including titanium nitride, tantalum nitride, tungsten nitride, or the like. However, embodiments are not limited thereto, and the optical black layer 190 can include any one of various materials or have any one of various stack structures.

[0100] In some embodiments, the optical black layer 190 (e.g., a metal layer included in the optical black layer 190) can not be electrically connected to another portion (e.g., the wiring part 170, the pad 210, or the conductive layer 134 included in the isolation part 130). Accordingly, the optical black layer 190 can include an insulating material capable of blocking light. In some embodiments, if light can be sufficiently blocked by the color filter layer 192 and / or other portions, the metal layer or the diffusion barrier layer of the optical black layer 190 can be omitted.

[0101] In some embodiments, in the pixel array area 12 and / or the dummy array area 14, a protective layer 186 can be disposed on the horizontal insulating layer 180, the filter separator 184, and / or the optical black layer 190. The protective layer 186 can be disposed between the horizontal insulating layer 180 and the color filter 182, between the filter separator 184 and the color filter 182, and / or between the optical black layer 190 and the color filter layer 192. For example, the protective layer 186 can extend on an upper surface of the horizontal insulating layer 180, on side surfaces and an upper surface of the filter separator 184, and / or on an upper surface of the optical black layer 190. For example, the protective layer 186 can include aluminum oxide, but embodiments are not limited thereto. The protective layer 186 can prevent damage to the horizontal insulating layer 180, the filter separator 184, and / or the optical black layer 190.

[0102] In the pixel array area 12, a microlens 188 can be disposed on the filter separator 184, the protective layer 186, and / or the color filter 182. The microlens 188 can include or be formed of a portion having a convex shape for converging or collecting light incident to the pixel area PX. The microlens 188 can include any or various resin materials, for example, a styrene-based resin, an acrylic-based resin, a styrene-acrylic copolymer resin, a siloxane-based resin, or the like. However, embodiments are not limited thereto, and the shape, material, or the like of the microlens 188 can be variously modified.

[0103] In Figure 3 In this case, a plurality of microlenses 188 are shown to correspond to a plurality of pixel regions PX, respectively. However, the embodiments are not limited to this, and one microlens 188 can correspond to a plurality of pixel regions PX. In some embodiments, an outer protective layer or the like can be further provided on an outer surface of the microlens 188.

[0104] In the dummy array region 14, a color filter layer 192 can be provided on the optical black layer 190. For example, in the dummy array region 14, the color filter layer 192 can be provided on a protective layer 186 provided on the optical black layer 190. For example, the color filter layer 192 can include a blue filter, but the embodiments are not limited to this.

[0105] In the dummy array region 14, an organic material layer 198 can be provided on the color filter layer 192. The organic material layer 198 can include a light-transmissive material (e.g., a light-transmissive resin), but the embodiments are not limited to this. In some embodiments, the organic material layer 198 can include the same material as that of the microlens 188.

[0106] In some embodiments, in a plan view, the relative positions between the pixel regions PX and the color filters 182 and / or the relative positions between the pixel regions PX and the microlenses 188 can be different from each other in a central portion of the pixel array region 12 and an edge portion of the pixel array region 12. That is, in a plan view, the area (e.g., planar area) of the color filter 182 superimposed with the pixel region PX and / or the area (e.g., planar area) of the microlens 188 superimposed with the pixel region PX can be smaller in the edge region of the pixel array region 12 than in the central region of the pixel array region 12. For example, the area (e.g., planar area) of the color filter 182 superimposed with the pixel region PX and / or the area (e.g., planar area) of the microlens 188 superimposed with the pixel region PX can decrease from the central region of the pixel array region 12 to the edge region of the pixel array region 12.

[0107] By adjusting the relative positions between the pixel regions PX and the color filters 182 and / or the relative positions between the pixel regions PX and the microlenses 188, the amount of light reaching the photoelectric conversion section 120 of the pixel region PX can be maximized. For example, the microlens 188, the color filter 182, and the photoelectric conversion section 120 of the pixel region PX can be disposed to be superimposed in the direction in which light passes. Since light is obliquely incident in the edge region of the pixel array region 12, the relative positions of the pixel region PX, the color filter 182, and / or the microlens 188 can be adjusted so that the obliquely incident light can reach the photoelectric conversion section 120 of the pixel region PX in a large amount.

[0108] In Figure 2In the present embodiment, as one example, it is shown that the dummy pixel region DPX in the dummy array region 14 includes a first dummy pixel region. The first dummy pixel region can include the photoelectric conversion section 120 and the pixel circuit 160. However, the embodiment is not limited thereto. The dummy pixel region DPX can also include a second dummy pixel region. The second dummy pixel region can include at least a portion of the pixel circuit 160, and can not include the photoelectric conversion section 120. The first dummy pixel region can provide a first reference charge amount when light is blocked. The first reference charge amount can be a relative reference when the amount of charge generated from the pixel region PX is calculated. The second dummy pixel region can provide a second reference charge amount when the photoelectric conversion section 120 is not included. The second reference charge amount can be used as information configured to remove process noise.

[0109] In some embodiments, the additional wiring section 200 can include the pad 210, and can also include a semiconductor substrate 220, a circuit element 230 (e.g., a transistor), a logic circuit portion, a power supply portion, a wiring 240, and the like. The pad 210 can be provided in the pad region 16. The wiring 240 of the additional wiring section 200 can include an interlayer insulating layer, a wiring layer, a contact via, and the like. The description of the interlayer insulating layer 172, the wiring layer 174, or the contact via 176 included in the wiring section 170 can be applied to the interlayer insulating layer, the wiring layer, or the contact via included in the wiring 240 of the additional wiring section 200. However, the embodiment is not limited thereto, and the members included in the additional wiring section 200 can be modified differently.

[0110] The pad 210 can be a portion configured to be electrically connected to an external circuit or the like. For example, the pad 210 can be connected to an external circuit or the like using wire bonding or the like, but the embodiment is not limited thereto. The pad 210 can be electrically connected to the wiring section 170 of the photoelectric conversion substrate 100. In one example, the pad 210 can be electrically connected to the wiring section 170 at a side of the first substrate surface 111. For example, the pad 210 can be electrically connected to the connection wiring 178 included in the wiring section 170. In the pad region 16, a recess 212 can be provided that extends into or penetrates a portion of the photoelectric conversion substrate 100 and a portion of the additional wiring section 200 to expose the pad 210.

[0111] In some embodiments, the pad 210 and the wiring section 170 can be provided adjacent to the first substrate surface 111 of the substrate 110, and thus, the image sensor 10 can have a relatively small parasitic capacitance compared to a comparative example in which the pad is provided on the second substrate surface of the substrate.

[0112] The additional wiring portion 200 can be electrically connected to the wiring portion 170 included in the photoelectric conversion substrate 100. The additional wiring portion 200 can be joined to the photoelectric conversion substrate 100 at the first surface 101 of the photoelectric conversion substrate 100. In one example, the additional wiring portion 200 can be located on the first surface 101 of the photoelectric conversion substrate 100 at a side of the first substrate surface 111 of the substrate 110. In some embodiments, the wiring portion 170 and the additional wiring portion 200 of the photoelectric conversion substrate 100 can be joined by a mixed joining including metal joining and insulating layer joining. In some embodiments, the wiring portion 170 and the additional wiring portion 200 of the photoelectric conversion substrate 100 can be joined by insulating layer joining, and then a connection member or the like configured to connect the wiring portion 170 and the additional wiring portion 200 can be formed. Other various modifications are possible.

[0113] When the photoelectric conversion substrate 100 and the additional wiring portion 200 are included as described above, congestion of wirings, circuit elements, and the like included in the wiring portion 170 of the photoelectric conversion substrate 100 and the additional wiring portion 200 can be reduced. As a result, an area (e.g., a planar area) of the pixel region PX of the image sensor 10 can be reduced, and thus the degree of integration and characteristics of the image sensor 10 can be enhanced.

[0114] In Figure 3 , as one example, it is shown that the image sensor 10 includes the photoelectric conversion substrate 100 and the additional wiring portion 200 including the pad 210. However, embodiments are not limited thereto. The wiring portion 170 included in the photoelectric conversion substrate 100 can include the pad 210. In this case, the pad 210 can be included in the wiring portion 170 provided on the first substrate surface 111 of the substrate 110, and thus the pad 210 can be adjacent to the first substrate surface 111 of the substrate 110. In some embodiments, the wiring portion 170 included in the photoelectric conversion substrate 100 can include the circuit element 230 (e.g., a transistor), a logic circuit portion, a power supply portion, a wiring 240, and the like included in the additional wiring portion 200. In this case, the image sensor 10 can be formed of the photoelectric conversion substrate 100 including the wiring portion 170, and the additional wiring portion 200 can be omitted.

[0115] With reference to Figure 2 and Figure 3 together, Figures 4 to 6 the isolation portion 130, the doped region 130d, and the connection wiring 178 connected to the doped region 130d will be described in detail.

[0116] Figure 5 is an enlarged view showing part C of Figure 3 . Figure 6 is a rear plan view showing part D of Figure 2 . Figure 6The connection wiring 178 is shown disposed on the first substrate surface 111 of the substrate 110.

[0117] Referring to Figures 2 to 6 In some embodiments, the isolation portion 130 can include a first isolation portion 140 and a second isolation portion 150 having a depth (or height) smaller than that of the first isolation portion 140. The depth of the first isolation portion 140 or the depth of the second isolation portion 150 can refer to a depth, e.g., a maximum depth, in a thickness direction of the image sensor 10 or a vertical direction perpendicular to the first surface 101 of the image sensor 10. The doped region 130d can include a first doped region 140d disposed at a periphery of the first isolation portion 140 and a second doped region 150d disposed at a periphery of the second isolation portion 150. The first doped region 140d and the second doped region 150d can have different shapes.

[0118] The first isolation portion 140 can be disposed at least in the pixel array region 12 to define the pixel region PX. For example, the first isolation portion 140 can be disposed at a boundary of the pixel region PX and / or a boundary of the dummy pixel region DPX in the pixel array region 12 and / or the dummy array region 14.

[0119] The second isolation portion 150 can be disposed at least at a portion of a boundary of the plurality of dummy regions DA. In Figure 2 In an embodiment, as an example, it is shown that the second isolation portion 150 is disposed to correspond to a portion of the boundary of the dummy region DA, and the first isolation portion 140 is disposed to correspond to another portion of the boundary of the dummy region DA. For example, at least a portion of the isolation portion 130 disposed to correspond to the boundary between two adjacent dummy regions DA can include the second isolation portion 150, and the isolation portion 130 disposed to correspond to the boundary between the dummy region DA and the dummy pixel region DPX can include the first isolation portion 140. In Figure 2 In an embodiment, as an example, it is shown that, in the isolation portion 130 disposed to correspond to the boundary between two adjacent dummy regions DA, a portion of the isolation portion 130 is formed by the second isolation portion 150, and another portion of the isolation portion 130 is formed by the first isolation portion 140.

[0120] The first isolation portion 140 can pass through, extend into, or penetrate at least a portion of the substrate 110. In some embodiments, in a thickness direction (Z-axis direction in the drawing) or a vertical direction of the image sensor 10, a first end 1401 of the first isolation portion 140 can be adjacent to the first substrate surface 111, and a second end 1402 of the first isolation portion 140 can be adjacent to the second substrate surface 112. For example, the first end 1401 of the first isolation portion 140 can pass through, extend into, or penetrate the first substrate surface 111, and the second end 1402 of the first isolation portion 140 can pass through, extend into, or penetrate the second substrate surface 112. However, embodiments are not limited thereto, and at least one of the first end 1401 and the second end 1402 of the first isolation portion 140 can be spaced apart from the first substrate surface 111 or the second substrate surface 112.

[0121] The first isolation portion 140 can include first sidewall insulating layers 142 and first conductive portions 144 disposed between the first sidewall insulating layers 142, and can further include a first cover portion 146. The first sidewall insulating layers 142 can include first insulating portions 142a and second insulating portions 142b. The first conductive portions 144 can be disposed between the first insulating portions 142a and the second insulating portions 142b of the first sidewall insulating layers 142. The first cover portion 146 can be disposed on the first conductive portions 144 between the first insulating portions 142a and the second insulating portions 142b of the first sidewall insulating layers 142, to be adjacent to the first substrate surface 111 of the substrate 110.

[0122] In a thickness direction (Z-axis direction in the drawing) or a vertical direction of the image sensor 10, at least a portion of the first insulating portions 142a and the second insulating portions 142b of the first sidewall insulating layers 142 and / or the first cover portion 146 can be adjacent to the first substrate surface 111 of the substrate 110. In the thickness direction (Z-axis direction in the drawing) or the vertical direction of the image sensor 10, at least a portion of the first insulating portions 142a and the second insulating portions 142b of the first sidewall insulating layers 142 and the first conductive portions 144 can be adjacent to the second substrate surface 112 of the substrate 110.

[0123] The first doped region 140d can include first doped portions 141d disposed on side surfaces of the first isolation portion 140. For example, the first doped region 140d or the first doped portions 141d can be disposed at both side surfaces of the first isolation portion 140. The first doped portions 141d can be formed by performing a process of doping a dopant to a portion adjacent to a surface of a first trench 140t formed to form the first isolation portion 140, after the first trench 140t is formed.

[0124] In a plan view, the first conductive portion 144 in one first isolation portion 140 can be connected (e.g., mechanically and / or electrically connected) to the first conductive portion 144 in another first isolation portion 140 and / or to the second conductive portion 154 of the second isolation portion 150 of the one first isolation portion 140.

[0125] In a cross section perpendicular to the extension direction of the first isolation portion 140 (XZ plane or YZ plane), the entire portion of the first conductive portion 144 can be spaced apart or electrically isolated from the substrate 110 or the first doped region 140d. For example, in a cross section perpendicular to the extension direction of the first isolation portion 140, both side surfaces of the first conductive portion 144 can be electrically isolated or electrically insulated by the first and second insulating portions 142a and 142b of the first sidewall insulating layer 142, the first end 1401 of the first conductive portion 144 can be electrically isolated or electrically insulated by the first cover portion 146, and the second end 1402 of the first conductive portion 144 can be electrically isolated or electrically insulated by the horizontal insulating layer 180. However, embodiments are not limited thereto, and at least a portion of the first conductive portion 144 can be electrically isolated or electrically insulated by other insulating layers or other insulating portions different from the first sidewall insulating layer 142, the first cover portion 146, and the horizontal insulating layer 180.

[0126] The second isolation portion 150 can pass through, extend into, or penetrate a portion of the substrate 110. In some embodiments, in a thickness direction (Z-axis direction in the drawing) or vertical direction of the image sensor 10, the first end 1501 of the second isolation portion 150 can be adjacent to the first substrate surface 111, and the second end 1502 of the second isolation portion 150 can be spaced apart from the second substrate surface 112. For example, the first end 1501 of the second isolation portion 150 can pass through or penetrate the first substrate surface 111, and the second end 1502 of the second isolation portion 150 can be disposed inside or extend into the substrate 110.

[0127] The second isolation portion 150 can include the second sidewall insulating layer 152 and the second conductive portion 154 disposed between the second sidewall insulating layer 152, and can further include the second cover portion 156. The second sidewall insulating layer 152 can include the first and second insulating portions 152a and 152b. The second conductive portion 154 can be disposed between the first and second insulating portions 152a and 152b of the second sidewall insulating layer 152. The second cover portion 156 can be disposed on the second conductive portion 154 between the first and second insulating portions 152a and 152b of the second sidewall insulating layer 152 to be adjacent to the first substrate surface 111 of the substrate 110.

[0128] In the thickness direction (Z-axis direction in the drawing) or vertical direction of the image sensor 10, at least a portion of the first insulating portion 152a and the second insulating portion 152b of the second sidewall insulating layer 152 and / or the second cover portion 156 can be adjacent to the first substrate surface 111 of the substrate 110. In the thickness direction (Z-axis direction in the drawing) or vertical direction of the image sensor 10, at least a portion of the first insulating portion 152a and the second insulating portion 152b of the second sidewall insulating layer 152 and the second conductive portion 154 can be spaced apart from the second substrate surface 112 of the substrate 110. For example, in the second end 1502, the first insulating portion 152a and the second insulating portion 152b of the second sidewall insulating layer 152 and the second conductive portion 154 can be disposed inside or extended into the substrate 110. The second end 1502 disposed inside or extended into the substrate 110 can be or can include a conductive end at which the conductive layer 134 (e.g., the second conductive portion 154) is exposed to allow electrical connection with another portion.

[0129] The second doped region 150d can include the first doped portion 151d and the second doped portion 152d, and can further include a bulk doped portion 154d.

[0130] The first doped portion 151d of the second doped region 150d can be disposed on the side surfaces of the second isolation portion 150 and on the second end 1502. For example, the first doped portion 151d of the second doped region 150d can be disposed to surround the entire portions of the two side surfaces of the second isolation portion 150 and the second end 1502. The first doped portion 151d of the second doped region 150d can be electrically connected to the second end 1502 of the second isolation portion 150. That is, the first doped portion 151d of the second doped region 150d can be electrically connected to the conductive end. In one example, the second conductive portion 154 of the second isolation portion 150 can be exposed to the second doped region 150d through the conductive end.

[0131] The second doped portion 152d can be formed by performing a process of doping a dopant to a portion adjacent to a surface of the second trench 150t after forming the second trench 150t configured to form the second isolation portion 150. The first doped portion 151d of the second doped region 150d and the first doped portion 141d of the first doped region 140d can be formed by the same doping process. However, embodiments are not limited thereto, and the first doped portion 151d of the second doped region 150d and the first doped portion 141d of the first doped region 140d can be formed by different processes.

[0132] The second doped portion 152d can be adjacent to the first base surface 111 of the substrate 110 and connected to the first doped portion 151d. The second doped portion 152d can be formed by performing a process of doping a dopant to the dummy area DA. The second doped portion 152d can be formed by a process separate from the process of forming the first doped portion 141d of the first doped region 140d and / or the first doped portion 151d of the second doped region 150d. The second doped portion 152d can be disposed in the dummy area DA adjacent to the second isolation portion 150, and can not be disposed in the pixel area PX and / or the dummy pixel area DPX.

[0133] For example, the doping concentration of the second doped portion 152d can be less than the doping concentration of the first doped portion 151d. The doping concentration can indicate an average doping concentration or a minimum doping concentration. By the relatively high doping concentration of the first doped portion 151d, the dark current can be effectively improved. However, embodiments are not limited thereto. In some embodiments, the doping concentration of the second doped portion 152d can be the same as or higher than the first doped portion 151d. Thereby, the resistance of the second doped portion 152d and the connection wiring 178 can be reduced.

[0134] The bulk doped portion 154d can have a doping concentration less than the doping concentration of the first doped portion 151d or the second doped portion 152d. The bulk doped portion 154d can be adjacent to the first base surface 111 of the substrate 110, and can be disposed in a portion deeper than the second doped portion 152d. The bulk doped portion 154d can be formed by the same process as forming the first conductivity type well 120b disposed in the pixel area PX and / or the dummy pixel area DPX and having the first conductivity type. However, embodiments are not limited thereto. The bulk doped portion 154d can be formed by a process different from the process of forming the first conductivity type well 120b disposed in the pixel area PX and / or the dummy pixel area DPX.

[0135] In some embodiments, in the dummy region DA, the pixel circuit 160 can not be provided adjacent to the first base surface 111 of the base 110. In the dummy region DA, the second doped region 150d (e.g., the second doped portion 152d) can be provided to have a relatively large area. For example, at a portion adjacent to the first base surface 111, in an entire portion of the dummy region DA, an area of a portion in which the second doped region 150d is provided can be larger than an area of another portion in which the second doped region 150d is not provided. At a portion adjacent to the first base surface 111, the second doped region 150d (e.g., the second doped portion 152d) provided in the dummy region DA can have an area larger than an area of the dopant region 166 provided in the pixel region PX and / or the dummy pixel region DPX and having the first conductivity type. Thus, an electrically connecting area between the second doped region 150d and the connection wiring 178 can be increased, and thus the second doped region 150d and the connection wiring 178 can be stably electrically connected to each other.

[0136] In Figure 6 As one example, it is shown that the device isolation portion 122 is provided at a portion where the first isolation portion 140 is provided, and the device isolation portion 122 is not provided at a portion where the second isolation portion 150 is provided. In other words, the device isolation portion 122 can be adjacent to the first isolation portion 140, and can be spaced apart from the second isolation portion 150. The first isolation portion 140 can pass through or penetrate a portion (e.g., a central portion) of the device isolation portion 122.

[0137] When the device isolation portion 122 is not provided at a portion where the second isolation portion 150 is provided as described above, the second isolation portion 150 having a smaller depth than a depth of the first isolation portion 140 can be formed by an easy process. This will be described in more detail later in a manufacturing method of the image sensor 10. However, embodiments are not limited thereto, and the device isolation portion 122 can be provided at a portion where the second isolation portion 150 is provided.

[0138] In a plan view, the second conductive portion 154 in one of the second isolation portions 150 can be connected (e.g., mechanically and / or electrically connected) to the first conductive portion 144 in the first isolation portion 140 and / or to the second conductive portion 154 in another of the second isolation portions 150 connected to the one of the second isolation portions 150.

[0139] The second conductive portion 154 disposed in the second isolation portion 150 can include a portion electrically connected to the base 110 (e.g., the second doped region 150d disposed at the periphery of the second isolation portion 150). In a cross-section (XZ plane or YZ plane) perpendicular to the extension direction of the second isolation portion 150, the second conductive portion 154 can be electrically connected to the second doped region 150d. For example, the second conductive portion 154 disposed inside or extending into the base 110 at the second end 1502 can be connected to the base 110 or the second doped region 150d. More specifically, the end of the second conductive portion 154 disposed at the second end 1502 can be connected (e.g., mechanically and / or electrically connected) to the first doped portion 151d. The second conductive portion 154 disposed at the second end 1502 can be directly connected to or in contact with the first doped portion 151d. For example, in a cross-section perpendicular to the extension direction of the second isolation portion 150, both side surfaces of the second conductive portion 154 can be electrically isolated or electrically insulated by the first and second insulating portions 152a and 152b of the second sidewall insulating layer 152, and the second conductive portion 154 can be electrically isolated or electrically insulated by the second cover portion 156 at the first end 1501.

[0140] However, embodiments are not limited thereto. In some embodiments, the second conductive portion 154 can be connected to the base 110 or the second doped region 150d at a position other than the second end 1502, or the second conductive portion 154 can be connected to a portion of the second doped region 150d other than the first doped portion 151d. In some embodiments, the second conductive portion 154 can be connected to the base 110 or the second doped region 150d through another member or portion. In some embodiments, at least a portion of the second conductive portion 154 can be electrically isolated or electrically insulated by other insulating layers or other insulating portions other than the second sidewall insulating layer 152 or the second cover portion 156.

[0141] In some embodiments, the entire portion of the first conductive portion 144 disposed in the first isolation portion 140 can be electrically insulated, and the first conductive portion 144 can not be directly connected to the first doped region 140d. However, the first conductive portion 144 disposed in the first isolation portion 140 can be electrically connected to the doped region 130d through the second conductive portion 154 disposed in the second isolation portion 150.

[0142] In Figure 5In the embodiment, as an example, it is shown that the depth of the second isolation portion 150 is greater than the thickness of the second doped portion 152d, and the depth of the second isolation portion 150 can be greater than the depth of the bulk doped portion 154d. The thickness of the second doped portion 152d can indicate a minimum thickness between the first base surface 111 and an inner surface of the second doped portion 152d adjacent to the second base surface 112, and the depth of the bulk doped portion 154d can indicate a minimum depth between the first base surface 111 and an inner surface of the bulk doped portion 154d adjacent to the second base surface 112. Thus, the second isolation portion 150 can be formed to have a stable depth. However, embodiments are not limited thereto. The depth of the second isolation portion 150 can be the same as or less than the thickness of the second doped portion 152d, and / or the depth of the second isolation portion 150 can be the same as or less than the depth of the bulk doped portion 154d.

[0143] In some embodiments, the wiring portion 170 disposed on the first base surface 111 of the base 110 can include a connection wiring 178 electrically connected to the doped region 130d (e.g., the second doped region 150d). That is, the connection wiring 178 connected to the doped region 130d (e.g., the second doped region 150d) can be disposed on the first base surface 111 of the base 110.

[0144] The connection wiring 178 can be a voltage application wiring (e.g., a negative voltage application wiring) that applies a voltage (e.g., a negative voltage) to the second conductive portion 154 disposed in the second isolation portion 150. The connection wiring 178 can include a connection wiring layer 178a and a connection contact via 178b that connects (e.g., directly connects) the connection wiring layer 178a and the second doped region 150d (e.g., the second doped portion 152d).

[0145] The connection wiring 178 can be a part of the wiring layer 174 included in the wiring portion 170 and the contact via 176 included in the wiring portion 170. The connection wiring layer 178a or the connection contact via 178b can include the same material as that of the wiring layer 174 or the contact via 176. The description of the material of the wiring layer 174 or the contact via 176 can be applied as it is to the material of the connection wiring layer 178a or the connection contact via 178b. For example, the material of the connection contact via 178b can have a higher conductivity than that of the material of the connection wiring layer 178a. Thus, the contact resistance of the second doped region 150d and the connection wiring 178 can be reduced by reducing the resistance of the connection contact via 178b. However, embodiments are not limited thereto, and the material of the connection contact via 178b can have the same conductivity as or a lower conductivity than that of the material of the connection wiring layer 178a.

[0146] Accordingly, like the wiring portion 170 or the pad 210, the connection wiring 178 electrically connected to the second doped region 150d in the dummy area DA can be disposed on the first base surface 111 of the base 110. Accordingly, a voltage can be applied to the conductive layer 134 disposed in the isolation portion 130 without the base through-hole that penetrates through the base 110, extends into the base 110, or penetrates the base 110. That is, the connection wiring 178 can apply a voltage to the first conductive portion 144 disposed in the first isolation portion 140 through the second doped region 150d and the second conductive portion 154 of the second isolation portion 150.

[0147] Referring to Figure 2 In some embodiments, the second isolation portion 150 can include a first extension portion 150a and a second extension portion 150b. The first extension portion 150a can extend in a first direction (Y-axis direction in the drawing), and the second extension portion 150b can extend in a second direction (X-axis direction in the drawing) transverse (e.g., perpendicular) to the first direction.

[0148] The first extension portion 150a of the second isolation portion 150 can extend in the first direction (Y-axis direction in the drawing) to correspond to the boundaries between the plurality of first dummy areas DA1 and the plurality of second dummy areas DA2. The plurality of first dummy areas DA1 can be adjacent to each other in the first direction, the plurality of second dummy areas DA2 can be adjacent to each other in the first direction, and the plurality of second dummy areas DA2 can be adjacent to the plurality of first dummy areas DA1, respectively, in the second direction (X-axis direction in the drawing). That is, the plurality of first portions disposed in the edge portion in the second direction to correspond to the boundaries between the first dummy areas DA1 and the second dummy areas DA2 can include the first extension portion 150a.

[0149] The second extension portion 150b of the second isolation portion 150 can extend in the second direction (X-axis direction in the drawing) to correspond to the boundaries between the plurality of third dummy areas DA3 and the plurality of fourth dummy areas DA4. The plurality of third dummy areas DA3 can be adjacent to each other in the second direction, the plurality of fourth dummy areas DA4 can be adjacent to each other in the second direction, and the plurality of fourth dummy areas DA4 can be adjacent to the plurality of third dummy areas DA3, respectively, in the first direction (Y-axis direction in the drawing). That is, the plurality of second portions disposed in the edge portion in the first direction to correspond to the boundaries between the third dummy areas DA3 and the fourth dummy areas DA4 can include the second extension portion 150b.

[0150] In Figure 2In the embodiment, as one example, it is shown that the first extension 150a extending in the first direction (Y-axis direction in the drawing) is provided at both sides in the second direction (X-axis direction in the drawing), respectively, the second extension 150b extending in the second direction is provided at both sides in the first direction, respectively, and the first extension 150a and the second extension 150b are connected to each other. Thus, the second isolation portion 150 can have a shape (for example, a rectangular shape) that surrounds the entire portion of the pixel array region 12, thereby uniformly applying a negative voltage to the pixel array region 12. However, the embodiment is not limited to this. Different modifications can be made to the position, shape, and the like of the second isolation portion 150.

[0151] In Figure 2 In the embodiment, as one example, it is shown that the first extension 150a extends longitudinally to correspond to the boundaries between the plurality of first dummy areas DA1 and the plurality of second dummy areas DA2, and to correspond to the entire portion of the edge of the pixel array region 12. In Figure 2 In the embodiment, as one example, it is shown that the second extension 150b extends transversely to correspond to the boundaries between the plurality of third dummy areas DA3 and the plurality of fourth dummy areas DA4, and to correspond to the entire portion of the edge of the pixel array region 12. In Figure 2 In the embodiment, as one example, it is shown that the first extension 150a provided at both sides of the pixel array region 12, respectively, has the same or symmetrical shape, and the second extension 150b provided at both sides of the pixel array region 12, respectively, has the same or symmetrical shape. However, the embodiment is not limited to this.

[0152] In some embodiments, the first extension 150a and / or the second extension 150b can be provided at a portion of the edge, the first extension 150a can be provided to correspond to the boundary between one first dummy area DA1 and one second dummy area DA2, or the second extension 150b can be provided to correspond to the boundary between one third dummy area DA3 and one fourth dummy area DA4. In some embodiments, a plurality of first extensions 150a and / or a plurality of second extensions 150b can be provided near one edge of the pixel array region 12. In some embodiments, the first extension 150a provided at both sides of the pixel array region 12, respectively, can be provided at different positions or can have different shapes, or the second extension 150b provided at both sides of the pixel array region 12, respectively, can be provided at different positions or can have different shapes.

[0153] In Figure 2In the example shown as an example, the interval between the two first isolation portions 140 is the same as the interval between the first isolation portion 140 and the second isolation portion 150. However, the embodiments are not limited thereto. In some embodiments, the interval between the two first isolation portions 140 can be larger than the interval between the first isolation portion 140 and the second isolation portion 150. By reducing the interval between the first isolation portion 140 and the second isolation portion 150, the area (e.g., planar area) of the second dummy array region 14b can be reduced. Thereby, the area (e.g., planar area) of the image sensor 10 can be reduced. In some embodiments, the interval between the two first isolation portions 140 can be smaller than the interval between the first isolation portion 140 and the second isolation portion 150. By increasing the interval between the first isolation portion 140 and the second isolation portion 150, the area (e.g., planar area) of the second dummy array region 14b can be sufficiently ensured. Thus, by sufficiently ensuring the area of the second doped portion 152d, the connection area with the connection wiring 178 can be increased to enhance the electrical connection characteristics.

[0154] According to some embodiments, the second doped region 150d in the substrate 110 electrically connected to the second conductive portion 154 in the second isolation portion 150 can be used to improve the dark current. For example, by applying a voltage (e.g., negative voltage) to the isolation portion 130 via the connection wiring 178 connected to the second doped region 150d, the dark current can be improved by hole accumulation.

[0155] The connection wiring 178 can be included in the wiring portion 170 disposed adjacent to the first substrate surface 111 of the substrate 110, and thus the path for applying a voltage to the isolation portion 130 can be shortened, and the image sensor 10 can be manufactured by a simple process. Thus, the performance of the image sensor 10 can be enhanced by effectively applying a voltage to the isolation portion 130, and the productivity and yield of the image sensor 10 can be enhanced by simplifying the manufacturing process and reducing process errors.

[0156] According to some embodiments, in a comparative example where the wiring portion is configured to be adjacent to a first substrate surface of the substrate and the negative voltage applying wiring, configured to apply a negative voltage to the isolation portion, is configured to be adjacent to a second substrate surface of the substrate, a process of forming the negative voltage applying wiring adjacent to the second substrate surface and a process of forming a substrate through-via are performed. The substrate through-via passes through the substrate, extends into the substrate, or penetrates the substrate for electrical connection between the negative voltage applying wiring adjacent to the second substrate surface and the wiring portion adjacent to the first substrate surface. Therefore, the manufacturing process is complex, and process errors may increase due to the generation of unwanted particles in the process of forming the substrate through-via. In addition, the path for applying the negative voltage is long, resulting in higher resistance, which may make it difficult to apply the negative voltage effectively. In another comparative example, including contact plugs that pass through a portion of the isolation portion, extend into a portion of the isolation portion, or penetrate a portion of the isolation portion, an additional process of forming a through-via that passes through or penetrates a portion of the isolation portion is performed. Therefore, the properties of the isolation portion may deteriorate, or the deviation or distribution of the manufacturing process may be large. As a result, reliability and productivity may be reduced.

[0157] Reference Figures 7 to 16 The manufacturing method of the image sensor 10 is described in detail.

[0158] Figures 7 to 16 This is a schematic cross-sectional view illustrating a method of manufacturing an image sensor 10 according to some embodiments. Figures 7 to 16 The portions corresponding to pixel array region 12 and dummy array region 14 are shown.

[0159] like Figure 7 As shown, a device isolation portion 122 may be formed on a first substrate surface 111 of a substrate 110, the substrate 110 including a first substrate surface 111 and a pre-existing surface 112p that are opposite to each other.

[0160] For example, a mask pattern 310 may be formed on a first substrate surface 111 of substrate 110. The mask pattern 310 may have an opening 312 that exposes a region corresponding to the device isolation portion 122. The mask pattern 310 may comprise any of a variety of insulating materials, such as silicon nitride. For the patterning process of forming the opening of the mask pattern 310, any of a variety of processes may be used, such as photolithography.

[0161] Shallow trenches 122t can be formed by etching a portion of the substrate 110 exposed through openings 312 of the mask pattern 310. Various etching processes, such as dry etching and wet etching, can be used for the etching process.

[0162] The device isolation portion 122 can be formed by filling an insulating material layer in the shallow trench 122t at a portion adjacent to the first base surface 111 of the base 110. In some embodiments, the device isolation portion 122 can be formed by forming an insulating material layer inside the shallow trench 122t and on the mask pattern 310 and then removing a portion of the insulating material layer disposed on the mask pattern 310. In some embodiments, the device isolation portion 122 can be formed by partially forming an insulating material layer for filling the shallow trench 122t.

[0163] In some embodiments, the device isolation portion 122 can be disposed to correspond to a portion where the first isolation portion 140 (refer to FIG. 2) will be disposed. The device isolation portion 122 can not be disposed in a portion where the second isolation portion 150 (refer to FIG. 2) will be disposed. Accordingly, the insulating material (e.g., silicon oxide) included in the device isolation portion 122 can be disposed at a portion where the first isolation portion 140 will be formed, and the insulating material (e.g., silicon nitride) included in the mask pattern 310 can be disposed at a portion where the second isolation portion 150 will be formed. Figure 13 Figure 13 Accordingly, the device isolation portion 122 and the mask layer 320 include the same insulating material (e.g., silicon oxide) in a portion where the device isolation portion 122 is disposed, and the mask pattern 310 and the mask layer 320 can include different materials in a portion where the device isolation portion 122 is not disposed. For example, the mask pattern 310 can include silicon nitride.

[0164] Subsequently, as shown in FIG. 3B, the mask layer 320 can be formed, and the first preliminary trench 140s and the second preliminary trench 150s can be formed. The second preliminary trench 150s can have a smaller depth than a depth of the first preliminary trench 140s. The first preliminary trench 140s can be formed to correspond to a portion where the first isolation portion 140 will be disposed, and the second preliminary trench 150s can be formed to correspond to a portion where the second isolation portion 150 will be disposed. Figure 8 For example, the mask layer 320 can be formed on the first base surface 111 of the base 110 (more specifically, on the mask pattern 310 and the device isolation portion 122 disposed on the first base surface 111). The mask layer 320 can be a kind of hard mask layer. The mask layer 320 can include any one of various insulating materials. The mask layer 320 can include an insulating material different from a material of the mask pattern 310 and the same as a material of the device isolation portion 122. For example, the mask layer 320 can include silicon oxide.

[0165] Accordingly, the device isolation portion 122 and the mask layer 320 include the same insulating material (e.g., silicon oxide) in a portion where the device isolation portion 122 is disposed, and the mask pattern 310 and the mask layer 320 can include different materials in a portion where the device isolation portion 122 is not disposed. For example, the mask pattern 310 can include silicon nitride.

[0166]

[0167] ​​Through an etching process, a first preparatory trench 140s can be formed in the portion where the device isolation portion 122 is provided, and a second preparatory trench 150s can be formed in the portion where the device isolation portion 122 is not provided. In the etching process, an etching material capable of etching both the device isolation portion 122 and the mask layer 320, but with difficulty etching the mask pattern 310, or with a relatively low etching rate for the mask pattern 310, can be used. Thus, in the portion where the device isolation portion 122 is provided, the first preparatory trench 140s can be formed, extending to the lower surface of the device isolation portion 122 inside the substrate 110 and having a relatively large depth. In the portion where the device isolation portion 122 is not provided, the second preparatory trench 150s can be formed, extending to the mask pattern 310 on the first substrate surface 111 of the substrate 110 and having a relatively small depth. By using the etching selectivity of the device isolation section 122, the mask pattern 310 and the mask layer 320, a first pre-trench 140s and a second pre-trench 150s with different depths can be formed by a simple process.

[0168] However, the embodiments are not limited to this, and the device isolation portion 122 may be disposed in the portion where the second isolation portion 150 will be formed. In this case, the first pre-grooved trench 140s and the second pre-grooved trench 150s with different depths may be formed by any of various methods, such as using an additional mask.

[0169] Subsequently, as Figure 9 As shown, a first trench 140t and a second trench 150t can be formed, and first doped portions 141d and 151d can be formed.

[0170] For example, this can be achieved by using the first pre-groove 140s (refer to...) Figure 8 ) and the second preparatory trench 150s (refer to) Figure 8 An etching process is performed to form a first trench 140t and a second trench 150t by penetrating, extending into, or piercing a portion of the substrate 110. In the etching process, an etching material capable of etching materials included in the substrate 110 can be used. Since the second trench 150t can have a depth smaller than the first trench 140t, a second trench 150t with a depth smaller than the first trench 140t can be formed. Thus, a first trench 140t and a second trench 150t with different depths can be formed by a simple process.

[0171] Each of the first and second trenches 140t and 150t can pass through, extend into, or penetrate a portion of the base 110, and can have an inner end spaced apart from the preliminary surface 112p of the base 110 and disposed inside or extended into the base 110.

[0172] The first and second doped portions 141d and 151d can be formed at the periphery of the first and second trenches 140t and 150t. More specifically, the first doped portion 141d of the first doped region 140d can be formed in a portion of the base 110 adjacent to the side and lower surfaces of the first trench 140t (refer to Figure 14 ), and the second doped portion 152d of the second doped region 150d can be formed in a portion of the base 110 adjacent to the side and lower surfaces of the second trench 150t (refer to Figure 14 ). The first doped portion 141d of the first doped region 140d and the first doped portion 151d of the second doped region 150d can be formed by the same doping process, and thus, the process can be simplified. However, embodiments are not limited thereto, and the first doped portion 141d of the first doped region 140d and the first doped portion 151d of the second doped region 150d can be formed by different processes.

[0173] For the doping process of forming the first doped portion 141d of the first doped region 140d and / or the first doped portion 151d of the second doped region 150d, any one of various doping processes, for example, a plasma doping process, can be used. The first doped portion 141d of the first doped region 140d and / or the first doped portion 151d of the second doped region 150d can have a first conductivity type.

[0174] Subsequently, as shown in Figures 10 to 13 , the isolation portion 130 can be formed. In some embodiments, in the process of forming the isolation portion 130, a portion of the sidewall insulating layer 132 adjacent to the lower surface of the isolation portion 130 inside the base 110 can be removed.

[0175] As shown in Figure 10 , the sidewall insulating layer 132 can be formed in each of the first and second trenches 140t and 150t, and the first layer 134a of the conductive layer 134 can be formed.

[0176] For example, the sidewall insulating layer 132 can be formed to have a substantially uniform thickness on the inner surface of each of the first trench 140t and the second trench 150t. In this case, the sidewall insulating layer 132 (e.g., the first sidewall insulating layer 142) disposed on the inner surface of the first trench 140t can be formed on the entire portion of the inner side surface and the inner end 140i of the second trench 140t, and the sidewall insulating layer 132 (e.g., the second sidewall insulating layer 152) disposed on the inner side surface and the entire portion of the inner end 150i of the second trench 150t can be formed on the inner surface of the second trench 150t. Alternatively, the sidewall insulating layer 132 can be completely disposed on the first substrate surface 111 of the substrate 110 (e.g., on the mask layer 320 disposed on the mask pattern 310).

[0177] The first layer 134a of the conductive layer 134 may be formed to have a uniform thickness on the sidewall insulating layer 132 on the inner surface of each of the first trench 140t and the second trench 150t. The first layer 134a of the conductive layer 134 may be completely formed on the sidewall insulating layer 132 on the inner surface of the first trench 140t, and the first layer 134a of the conductive layer 134 may be completely formed on the sidewall insulating layer 132 on the inner surface of the second trench 150t. Alternatively, the first layer 134a of the conductive layer 134 may be completely disposed on the first substrate surface 111 of the substrate 110 (e.g., on the sidewall insulating layer 132). The first layer 134a of the conductive layer 134 may comprise an undoped semiconductor material (e.g., a polycrystalline semiconductor material, such as polycrystalline silicon as an example), but the embodiments are not limited thereto.

[0178] Subsequently, as Figure 11 As shown, a portion of the sidewall insulating layer 132 disposed on the inner end 150i of the second trench 150t within the substrate 110 can be removed. In some embodiments, during the process of removing the portion of the sidewall insulating layer 132 disposed on the inner end 150i of the second trench 150t within the substrate 110, a portion of the sidewall insulating layer 132 disposed on the inner end 140i of the first trench 140t within the substrate 110 can also be removed. Furthermore, when a portion of the sidewall insulating layer 132 is removed, a portion of the first layer 134a of the conductive layer 134 "disposed on said portion of the sidewall insulating layer 132" can also be removed.

[0179] A portion of the sidewall insulating layer 132 can be removed by etching the sidewall insulating layer 132 and the first layer 134a of the conductive layer 134 together with the sum of the thickness of the sidewall insulating layer 132 and the thickness of the first layer 134a of the conductive layer 134. In the etching process, an etching material capable of removing the sidewall insulating layer 132 and the first layer 134a of the conductive layer 134 can be used. Therefore, the process can be simplified by performing an etching process on the entire portion. However, the embodiments are not limited thereto. In some embodiments, a patterning process or similar process capable of removing a portion of the sidewall insulating layer 132 and / or a portion of the first layer 134a of the conductive layer 134 can be used. In some embodiments, a portion of the sidewall insulating layer 132 can be removed without a process for forming the first layer 134a of the conductive layer 134.

[0180] In some embodiments, the first layer 134a of the conductive layer 134 can protect the sidewall insulating layer 132 by forming a first layer 134a of the conductive layer 134 and then performing an etching process to remove a portion of the sidewall insulating layer 132. However, the embodiments are not limited to this, and the manufacturing sequence of the etching process to remove a portion of the sidewall insulating layer 132 can be modified differently.

[0181] After an etching process that removes a portion of the sidewall insulating layer 132, a doping process can be performed to dope the first layer 134a of the conductive layer 134. Thus, the first layer 134a of the conductive layer 134 may include a doped semiconductor material (e.g., a p-type polycrystalline semiconductor material, such as p-type polycrystalline silicon as an example), but the embodiments are not limited thereto. In some embodiments, the fabrication sequence of the doping process for at least a portion of the conductive layer 134 may be modified differently.

[0182] Subsequently, as Figure 12 As shown, a second layer 134b of conductive layer 134 can be formed. For example, the second layer 134b of conductive layer 134 can be formed on the first layer 134a of conductive layer 134 on the inner surface of each of the first trench 140t and the second trench 150t. In the first trench 140t, the second layer 134b of conductive layer 134 can fill at least a portion of the interior space of the first trench 140t on the first layer 134a of conductive layer 134. In the second trench 150t, the second layer 134b of conductive layer 134 can fill at least a portion of the interior space of the second trench 150t on the first layer 134a of conductive layer 134. Alternatively, the second layer 134b of conductive layer 134 can be completely disposed on the first substrate surface 111 of substrate 110 (e.g., on the first layer 134a of conductive layer 134 disposed on the first substrate surface 111).

[0183] For example, the second layer 134b of the conductive layer 134 can include an undoped semiconductor material (e.g., an intrinsic polycrystalline semiconductor material, as one example, intrinsic polysilicon), although embodiments are not limited thereto. In some embodiments, a dopant included in the first layer 134a of the conductive layer 134 can be diffused to at least a portion of the second layer 134b of the conductive layer 134 in a process of forming the second layer 134b of the conductive layer 134 or a subsequent process, and thus at least a portion of the second layer 134b of the conductive layer 134 can include a doped semiconductor material.

[0184] Subsequently, as shown in FIG. 1C, the isolation portion 130 can be formed by forming the cover portion 136. Figure 13

[0185] For example, a portion of the conductive layer 134 can be etched by a back-etching process. In the back-etching process, an etching material capable of etching the conductive layer 134 can be used. The cover portion 136 can be formed inside each of the first trench 140t and the second trench 150t. The first cover portion 146 can be formed inside the first trench 140t, and the second cover portion 156 can be formed inside the second trench 150t.

[0186] The mask pattern 310 (refer to FIG. 1B) disposed on the first base surface 111, the mask layer 320 (refer to FIG. 1B), a portion of the sidewall insulating layer 132, and a portion of the conductive layer 134 can be removed. For example, for the removal process, a chemical mechanical polishing (CMP) process, an etching process, or the like can be used. Thereby, the isolation portion 130 can be formed. Figure 12 Figure 12

[0187] Subsequently, as shown in FIG. 1C, the isolation portion 130 can be formed by forming the cover portion 136. Figure 14 In this case, the photoelectric conversion portion 120 and the pixel circuit 160 can be formed in at least a portion of the dummy pixel region DPX and / or the pixel region PX. The photoelectric conversion portion 120 can include the second-conductivity-type well 120a, and further include the first-conductivity-type well 120b. The dopant region 166, the floating diffusion region 164b, or the like can be formed as the pixel circuit 160. The wiring portion 170 electrically connected to the pixel circuit 160 can be formed.

[0188] For example, the second-conductivity-type well 120a can be formed in at least a portion of the dummy pixel region DPX and / or the pixel region PX. The second-conductivity-type well 120a can not be formed in the dummy region DA.

[0189] ​​​In at least a portion of the dummy pixel region DPX and / or in the pixel region PX, a first conductivity type well 120b may be formed adjacent to the first substrate surface 111. In this case, a substrate doped portion 154d may be formed in the dummy region DA. The first conductivity type well 120b and the substrate doped portion 154d may be formed together by the same doping process, or they may be formed by different processes.

[0190] Dopant region 166, floating diffusion region 164b, etc., may be formed in at least a portion of the dummy pixel region DPX and / or pixel region PX. In this case, a second doped portion 152d may be formed in the dummy region DA. The dopant region 166 and the second doped portion 152d may be formed together using the same doping process, or the dopant region 166 and the second doped portion 152d may be formed using different processes.

[0191] Transistor 162, transmission transistor 164, etc., may be formed in at least a portion of the dummy pixel region DPX and / or in the pixel region PX. Any of various processes may be applied to the process of forming transistor 162, transmission transistor 164, etc.

[0192] A wiring portion 170 electrically connected to the pixel circuit 160 can be formed. The wiring portion 170 may include connection wiring 178 electrically connected to the second doped region 150d. Any of a variety of processes can be applied to the process of forming the wiring portion 170.

[0193] Subsequently, as Figure 15 As shown, the pre-prepared surface 112p of the substrate 110 (see reference) is removable from the substrate 110. Figure 14 A portion of the substrate 110 may be removed, for example, by performing grinding, polishing, lapping, etching, or other processes on the prepared surface 112p of the substrate 110, until the portion where the first isolation portion 140 is provided. For example, a portion of the substrate 110 may be removed such that the first isolation portion 140 passes through or penetrates the second substrate surface 112 of the substrate 110. In this case, the inner end 150i of the second isolation portion 150 may be spaced apart from the second substrate surface 112 of the substrate 110.

[0194] Subsequently, as Figure 16 As shown, an additional wiring portion 200 may be formed on the first substrate surface 111 of the substrate 110, and a light receiving portion including a color filter 182, a microlens 188, etc. may be formed on the second substrate surface 112 of the substrate 110. Furthermore, an exposure pad 210 (see reference) may be formed. Figure 3 The recessed portion 212 (refer to) Figure 3 ).

[0195] For the process of forming the additional wiring portion 200, the process of forming the light-receiving portion, or the process of forming the recessed portion 212, any one of various processes can be applied. The manufacturing order of the process of forming the additional wiring portion 200, the process of forming the light-receiving portion, or the process of forming the recessed portion 212 can be modified differently.

[0196] According to some embodiments, the image sensor 10 including the first isolation portion 140 and the second isolation portion 150 having different depths and including the first doped region 140d and the second doped region 150d having different shapes can be formed by a simple process. The connection wiring 178 configured to apply a voltage to the isolation portion 130 can be disposed adjacent to the first substrate surface 111 of the substrate 110, and thus, the process of forming the connection wiring 178, the process of connecting the connection wiring 178 and the pad 210 can be easily performed. Thereby, the productivity and yield of the image sensor 10 having enhanced performance can be enhanced.

[0197] Referring to Figure 17 and Figure 18 , the image sensor according to embodiments will be described in detail. To the extent that elements are not described in detail below, it is understood that such elements are similar, at least substantially, to corresponding elements already described elsewhere within this disclosure (and / or are identical). Portions not described above will be described in detail.

[0198] Figure 17 is a plan view schematically showing the image sensor 10 according to some embodiments. Figure 17 corresponding portions. Figure 2

[0199] Referring to Figure 17 , in some embodiments, the second isolation portion 150 can include a first extension portion 150a extending in a first direction (Y-axis direction in the drawing). The second isolation portion 150 can not include a second extension portion 150b extending in a second direction (X-axis direction in the drawing) transverse to or intersecting (e.g., perpendicular to) the first direction (refer to Figure 2 ). However, embodiments are not limited thereto, and the position, shape, etc. of the second isolation portion 150 can be modified differently. In some embodiments, the second isolation portion 150 can include the second extension portion 150b, and can not include the first extension portion 150a.

[0200] Referring to Figure 2 the description of the first extension portion 150a and / or the second extension portion 150b can be applied as is to the first extension portion 150a and / or the second extension portion 150b. Referring to Figure 2 ​Embodiments and / or modified embodiments of the first extension 150a and / or the second extension 150b described can be applied to the first extension 150a and / or the second extension 150b.

[0201] Figure 18 is a cross-sectional view schematically showing an image sensor 10c according to some embodiments. Figure 18 shows a corresponding portion. Figure 3 corresponding portion.

[0202] Referring to Figure 18 In the image sensor 10c according to some embodiments, the additional wiring portion 200 can include a first additional wiring portion 200a and a second additional wiring portion 200b provided on the first surface 101 of the photoelectric conversion substrate 100. Thereby, the image sensor 10c can have a multi-layer stacked structure including the photoelectric conversion substrate 100, the first additional wiring portion 200a, and the second additional wiring portion 200b.

[0203] In Figure 18 , as one example, it is shown that the pad 210 for connection to an external element is provided in the second additional wiring portion 200b, but the embodiments are not limited thereto. In some embodiments, the pad 210 for connection to the outside can be provided in the first additional wiring portion 200a. In this case, as with the connection wiring 178 electrically connected to the second conductive portion of the second isolation portion 150, the pad 210 can be provided on the first surface 101 of the photoelectric conversion substrate 100. In some embodiments, the pad 210 for connection to the outside can be provided in the wiring portion 170 included in the photoelectric conversion substrate 100. In this case, as with the connection wiring 178 electrically connected to the second conductive portion of the second isolation portion 150, the pad 210 can be provided adjacent to the first surface 101 of the photoelectric conversion substrate 100.

[0204] In Figure 18 , as one example, it is shown that the wiring portion 170 and the first additional wiring portion 200a are joined by mixed joining including metal joining and insulating layer joining, and the first additional wiring portion 200a includes a semiconductor substrate 220a, but the embodiments are not limited thereto. In some embodiments, the wiring portion 170 and the first additional wiring portion 200a are joined by insulating layer joining, and then, a connection member or the like configured to connect the wiring portion 170 and the first additional wiring portion 200a can be formed. The first additional wiring portion 200a and the second additional wiring portion 200b are joined by mixed joining including metal joining and insulating layer joining, but the embodiments are not limited thereto.

[0205] When the first additional wiring portion 200a and the second additional wiring portion 200b are further included as described above, congestion of wirings, circuit elements, and the like included in the wiring portion 170, the first additional wiring portion 200a, and the second additional wiring portion 200b can be effectively reduced. As a result, the area (e.g., planar area) of the pixel region PX of the image sensor 10c can be reduced, and thus the degree of integration and characteristics of the image sensor 10c can be enhanced.

[0206] For example, the wiring portion 170 can include wirings connected to the pixel circuit 160, the first additional wiring portion 200a can include circuit elements (e.g., transistors), wirings, and the like, and the second additional wiring portion 200b can include a logic circuit portion, a power supply portion, wirings, and the like. However, embodiments are not limited thereto. Different modifications can be made to the wirings, circuit elements, and the like included in the wiring portion 170, the first additional wiring portion 200a, and the second additional wiring portion 200b. In some embodiments, the image sensor 10c can further include additional wiring portions other than the first additional wiring portion 200a and the second additional wiring portion 200b.

[0207] Figure 19 is a cross-sectional view schematically showing an image sensor according to some embodiments. Figure 19 shows a corresponding portion and a connection contact 179. Figure 5 corresponding portion and a connection contact 179.

[0208] Referring to Figure 19 In some embodiments, the second isolation portion 150 can have the same or similar depth as the depth of the first isolation portion 140, and the second end 1502 of the second isolation portion 150 can be adjacent to the second base surface 112. That is, the second end 1502 of the second isolation portion 150, which is a conductive end at which the conductive layer 134 (e.g., the second conductive portion 154) is exposed to allow electrical connection with another portion, can be adjacent to the second base surface 112. The first doped portion 151d of the second doped region 150d can be disposed on a side surface of the second isolation portion 150.

[0209] The phrase "the first isolation portion 140 and the second isolation portion 150 have the same or similar depth" can indicate that the first isolation portion 140 and the second isolation portion 150 are manufactured by the same manufacturing process, and thus have a difference in depth within an error margin. The phrase "the first isolation portion 140 and the second isolation portion 150 have the same or similar depth" can indicate that the first isolation portion 140 and the second isolation portion 150 are manufactured by the same manufacturing process, and then the connection contact 179 is formed at a portion where the second isolation portion 150 is disposed. In this case, the first isolation portion 140 and the second isolation portion 150 can have substantially the same depth except for a portion where the connection contact 179 is disposed.

[0210] In some embodiments, the first isolation portion 140 and the second isolation portion 150 can be manufactured through the same manufacturing process. For example, the device isolation portion 122 can be provided at a portion where the first isolation portion 140 is provided, and the device isolation portion 122 is provided at a portion where the second isolation portion 150 is provided. The first isolation portion 140 can pass through, extend into, or penetrate a portion (e.g., a central portion) of the device isolation portion 122, and the second isolation portion 150 can pass through, extend into, or penetrate a portion (e.g., a central portion) of the device isolation portion 122. However, embodiments are not limited thereto.

[0211] In some embodiments, the connection contact 179 can be provided at a side of the second substrate surface 112 corresponding to a portion where the second isolation portion 150 is provided. In some embodiments, the connection contact 179 can be connected to the optical black layer 190. For example, the connection contact 179 can be formed of a portion of the optical black layer 190. Thereby, the optical black layer 190 including the connection contact 179 can be easily formed by forming an opening for the connection contact 179 at the horizontal insulating layer 180, and then forming the optical black layer 190. However, embodiments are not limited thereto. In some embodiments, the connection contact 179 can be formed separately from the optical black layer 190, or the optical black layer 190 can be omitted.

[0212] The optical black layer 190 and / or the connection contact 179 can include a metal material, and can include a single layer or multiple layers. For example, the optical black layer 190 and / or the connection contact 179 can include a metal layer including at least one of tungsten, aluminum, copper, titanium, and tantalum, or include an alloy including at least one of tungsten, aluminum, copper, titanium, and tantalum. The optical black layer 190 and / or the connection contact 179 can further include a diffusion barrier layer between the horizontal insulating layer 180 and the metal layer. The diffusion barrier layer can include a metal nitride layer including titanium nitride, tantalum nitride, tungsten nitride, or the like. However, embodiments are not limited thereto, and the optical black layer 190 and / or the connection contact 179 can include any one of various materials or have any one of various stack structures.

[0213] The first doped portion 151d of the second doped region 150d provided at a side surface of the second isolation portion 150 can be electrically connected to the conductive layer 134 (e.g., the second conductive portion 154) of the second isolation portion 150 through the connection contact 179 adjacent to (e.g., on) the second substrate surface 112.

[0214] In Figure 19As one example, it is shown that the second end 1502 of the second isolation portion 150 is disposed inside or extends into the base, rather than being in the same plane as the second base surface 112, but the embodiments are not limited thereto. The second end 1502 of the second isolation portion 150 can include a portion that is in the same plane as the second base surface 112.

[0215] According to some embodiments, the first isolation portion 140 and the second isolation portion 150 can be manufactured by the same manufacturing process, and the doped region 130d connected to the connection wiring 178 is connected to the conductive layer 134 of the isolation portion 130 through the connection contact 179. The connection wiring 178 can be included in a wiring portion disposed adjacent to the first base surface 111 of the base 110, so the path for applying a voltage to the isolation portion 130 can be shortened. In addition, the first isolation portion 140 and the second isolation portion 150 can be manufactured by the same manufacturing process, so the process can be simplified.

[0216] While some examples have been described in connection with what is presently considered to be some practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, and it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: Base; Multiple unit regions, wherein at least one of the multiple unit regions includes a photoelectric conversion unit in a substrate; Multiple isolation sections are configured to correspond to the boundaries of the multiple unit regions; and Doped regions, within the substrate, The plurality of isolation sections include a first isolation section and a second isolation section, wherein the second isolation section has a height smaller than that of the first isolation section. The plurality of isolation portions include a conductive layer, and The doped region is electrically connected to a portion of the conductive layer in the second isolation section.

2. The image sensor according to claim 1, wherein, The substrate has a first substrate surface and a second substrate surface that are opposite to each other, and The second isolation portion extends into the substrate, with a first end adjacent to the surface of the first substrate and a second end spaced apart from the second surface of the substrate.

3. The image sensor according to claim 2, wherein, The second end of the second isolation section includes a conductive end, through which the conductive layer is exposed, and The doped region is electrically connected to the conductive terminal of the second isolation section.

4. The image sensor according to claim 1, wherein, The doped regions include a first doped region on the first isolation portion and a second doped region on the second isolation portion, and The first doped region and the second doped region have different shapes.

5. The image sensor according to claim 4, wherein, The second isolation portion includes a conductive terminal that extends into the substrate, and the conductive layer is exposed to the second doped region through the conductive terminal. The first doped region includes a doped portion, which is located on the side surface of the first isolation portion, and The second doped region includes a first doped portion and a second doped portion. The first doped portion is on the side surface of the second isolation portion and on the conductive end and is electrically connected to the conductive end. The second doped portion is adjacent to the first substrate surface of the substrate and is connected to the first doped portion.

6. The image sensor according to claim 1, wherein, The substrate has a first substrate surface and a second substrate surface that are opposite to each other. The first isolation section extends into the substrate, and The first end of the first isolation portion is adjacent to the surface of the first substrate, and the second end of the first isolation portion is adjacent to the surface of the second substrate.

7. The image sensor according to claim 1, wherein, A portion of the conductive layer in the first isolation section is electrically connected to the doped region through a portion of the conductive layer in the second isolation section.

8. The image sensor according to claim 1, further comprising: The device isolation section has a height smaller than that of any one of the plurality of isolation sections. The device isolation section is adjacent to the first isolation section and spaced apart from the second isolation section.

9. The image sensor according to claim 1, wherein, The substrate includes a pixel array region and a dummy array region. The plurality of unit regions include a plurality of pixel regions in the pixel array region and a plurality of dummy regions in the dummy array region. The second isolation section is located at least at the boundary of one of the plurality of virtual regions.

10. The image sensor according to claim 9, wherein, In the plan view, the second isolation portion includes at least one of the first extension and the second extension. The first extension extends in a first direction between the dummy regions among the plurality of dummy regions. The second extension extends in a second direction that intersects the first direction, and the second extension is between the dummy regions in the plurality of dummy regions.

11. The image sensor according to claim 1, further comprising: Connecting wiring is provided on the first substrate surface of the substrate and electrically connected to the doped region; as well as The light receiving part is located on the second substrate surface of the substrate, which is opposite to the first substrate surface of the substrate.

12. The image sensor according to claim 11, wherein, The doped region includes a doped portion adjacent to the surface of the first substrate, and The connection wiring includes connection contact vias that are directly connected to the doped part.

13. The image sensor according to claim 11, further comprising: The wiring section is adjacent to the surface of the first substrate; as well as The pad is electrically connected to the wiring portion at the side edge of the first substrate surface and is configured to be electrically connected to external components. The connecting wiring is included in the wiring section.

14. The image sensor according to claim 11, further comprising: A photoelectric conversion substrate includes a substrate, a photoelectric conversion unit, the plurality of isolation units, a doped region, connecting wiring, and a light receiving unit; as well as An additional wiring section is located on the first surface of the photoelectric conversion substrate at the side of the first substrate surface of the substrate, and includes a pad electrically connected to the connecting wiring and configured to be electrically connected to an external component.

15. An image sensor, comprising: Base; The pixel array region includes multiple pixel regions, and the dummy array region includes multiple dummy regions, wherein each of the multiple pixel regions includes multiple photoelectric conversion units in the substrate; The first isolation section is located in the pixel array region and between the photoelectric conversion sections in the plurality of photoelectric conversion sections of the plurality of pixel regions; A second isolation portion extends into the substrate to correspond at least to the boundary of one of the plurality of dummy regions, and includes a conductive end through which the conductive layer is exposed; and The doped region is located in the substrate and is electrically connected to the conductive end of the second isolation portion.

16. The image sensor of claim 15, further comprising: The wiring section is adjacent to the first substrate surface of the substrate. The doped region includes a second doped region on the second isolation portion, and The second doped region includes a first doped portion and a second doped portion. The first doped portion is on the side surface and conductive end of the second isolation portion and is electrically connected to the conductive end. The second doped portion is adjacent to the first substrate surface of the substrate and is connected to the first doped portion.

17. The image sensor according to claim 16, wherein, The first doped portion is directly connected to the conductive terminal; or The first doped portion is electrically connected to a conductive end via a connecting contact on the second substrate surface of the substrate, and the second substrate surface is opposite to the first substrate surface.

18. The image sensor of claim 15, further comprising: Connecting wiring is provided on the first substrate surface of the substrate and electrically connected to the doped region; as well as The light receiving part is located on the second substrate surface of the substrate, which is opposite to the first substrate surface of the substrate.

19. An image sensor, comprising: Photoelectric conversion substrate; as well as Additional wiring is provided on the first surface of the photoelectric conversion substrate and includes pads configured for electrical connection to external components. The photoelectric conversion substrate includes: Base; Multiple unit regions, wherein at least one of the multiple unit regions includes a photoelectric conversion unit in a substrate; Multiple isolation sections are configured to correspond to the boundaries of the multiple unit regions, wherein the multiple isolation sections include conductive layers; A doped region, in the substrate, and a portion of a conductive layer electrically connected to the plurality of isolation portions; and The wiring section is adjacent to the first substrate surface of the substrate and is electrically connected to the additional wiring section. The wiring section includes connection wiring that is electrically connected to the doped region.

20. The image sensor according to claim 19, wherein, The conductive layer of the plurality of isolation sections is configured to receive negative voltage through connecting wiring and doped regions.

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