Miniature light emitting diode chip with high luminous efficiency and preparation method thereof
By employing a first current spreading layer and a second current spreading layer in the micro LED chip, and utilizing alternating stacks of Mg and C doped GaP layers, the problem of uneven current distribution caused by crystal defects in the micro LED chip is solved, thereby improving luminous efficiency.
Patent Information
- Application Number
- CN202510889941.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-30
- Publication Date
- 2025-11-18
AI Technical Summary
During the miniaturization process, micro LED chips are prone to crystal defects, which can lead to uneven current distribution and affect luminous efficiency.
The design employs a first current spreading layer and a second current spreading layer, utilizing alternating stacks of Mg and C-doped GaP layers to introduce compressive and tensile stresses for stress self-compensation, optimize crystal defects, and ensure uniform current distribution.
The luminous efficiency of the micro LED chip was improved, and the uniformity of current distribution was improved through stress self-compensation technology, thereby enhancing the luminous effect.
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Figure CN120981047A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure belongs to the technical field of semiconductor technology, and particularly relates to a micro light emitting diode chip with high light emitting efficiency and a preparation method thereof. BACKGROUND
[0002] A light emitting diode (LED) is a semiconductor diode that can convert electrical energy into optical energy.
[0003] In the related art, a light emitting diode chip is a main component of a light emitting diode, which mainly includes an N-type semiconductor layer, an active layer and a P-type semiconductor layer, electrons are injected from the N-type semiconductor layer to the active layer, and recombine with holes injected from the P-type semiconductor layer to emit light.
[0004] However, as the size of the light emitting diode chip is reduced, especially to the level of a micro light emitting diode (Micro-LED) chip, crystal defects are prone to occur, which leads to uneven current distribution and affects the light emitting efficiency of the light emitting diode. SUMMARY
[0005] The present disclosure provides a micro light emitting diode chip with high light emitting efficiency and a preparation method thereof, which can effectively optimize crystal defects, ensure uniform current distribution, and effectively improve the light emitting efficiency of the light emitting diode. The technical solution is as follows:
[0006] In one aspect, the present disclosure provides a micro light emitting diode chip, which comprises a first current spreading layer, a first semiconductor layer, an active layer, a second semiconductor layer and a second current spreading layer which are sequentially stacked.
[0007] The first semiconductor layer is of a first conductivity type, and the second semiconductor layer is of a second conductivity type different from the first conductivity type.
[0008] The first current spreading layer is an AlInP layer, and the second current spreading layer comprises a first sub-layer, a second sub-layer and a third sub-layer, the first sub-layer is a Mg-doped GaP layer, the second sub-layer is a Mg-doped GaP layer, and the third sub-layer is a C-doped GaP layer, and the second sub-layer and the third sub-layer are periodically and alternately stacked.
[0009] In one implementation manner of the present disclosure, the thickness of the first sub-layer is 3-4 pm, the thickness of the second sub-layer is 2-8 nm, the thickness of the third sub-layer is 3-9 nm, and the total thickness of the second sub-layer and the third sub-layer is 0.9-1.1 pm.
[0010] In another implementation manner of the present disclosure, the Mg doping concentration of the first sub-layer is 5e18-1e19 cm-3, the Mg doping concentration of the second sub-layer is 1e20-1e21 cm-3, and the C doping concentration of the third sub-layer is 1e20-1e21 cm-3.-3 The Mg doping concentration of the second sublayer is 5e18–5e19 cm⁻¹. -3 The C doping concentration of the third sublayer is 1e19 to 3e19 cm⁻¹ -3 .
[0011] In another implementation of this disclosure, the number of cycles for the second sub-layer and the third sub-layer is 30 to 100.
[0012] In another implementation of this disclosure, the micro LED chip further includes a blocking layer;
[0013] The barrier layer is Al. x In 1-x P layer, 0.5≤x≤1, the blocking layer is located between the active layer and the second current spreading layer.
[0014] In another implementation of this disclosure, the micro LED chip further includes a first ohmic contact layer and a second ohmic contact layer;
[0015] The first ohmic contact layer is (Al) x Ga 1-x ) 0.5 In 0.5 P layer, 0.3≤x≤1, the first ohmic contact layer is located on the side of the first current spreading layer that is opposite to the first semiconductor layer;
[0016] The second ohmic contact layer is a GaP layer, and the second ohmic contact layer is located on the side of the second current spreading layer that is opposite to the second semiconductor layer.
[0017] In another implementation of this disclosure, the micro LED chip further includes a substrate and a buffer layer;
[0018] The buffer layer is a GaAs layer, and the buffer layer is located between the substrate and the first current spreading layer.
[0019] On the other hand, embodiments of this disclosure provide a method for fabricating a miniature light-emitting diode chip, the method comprising:
[0020] Fabrication of the first current spreading layer;
[0021] A first semiconductor layer is fabricated on one side of the first current spreading layer, wherein the first semiconductor layer is of a first conductivity type;
[0022] An active layer is fabricated on one side of the first semiconductor layer;
[0023] A second semiconductor layer is prepared on one side of the active layer, the second semiconductor layer is of a second conductivity type, and the second conductivity type is different from the first conductivity type;
[0024] A first sub-layer is prepared on one side of the second semiconductor layer, the first sub-layer is a Mg-doped GaP layer;
[0025] Second sub-layers and third sub-layers are alternately prepared on one side of the first sub-layer, the second sub-layers are Mg-doped GaP layers, and the third sub-layers are C-doped GaP layers.
[0026] In an implementation form of the present disclosure, the first sub-layer prepared on one side of the second semiconductor layer comprises:
[0027] The growth temperature is set to 720-740℃, the growth thickness is set to 3-4μm, the growth rate is set to 3-4nm / s, and the Mg doping concentration is set to 5e18-1e19cm -3 , and the V / III ratio is set to 20-30.
[0028] In an implementation form of the present disclosure, the second sub-layers and the third sub-layers alternately prepared on one side of the first sub-layer comprise:
[0029] The growth period of the second sub-layers and the third sub-layers is set to 30-100;
[0030] In the process of growing the second sub-layers, the growth thickness is set to 2-8nm, and the Mg doping concentration is set to 5e18-5e19cm -3 ,
[0031] In the process of growing the third sub-layers, the growth thickness is set to 3-9nm, and the C doping concentration is set to 1e19-3e19cm -3 .
[0032] The technical scheme provided by the embodiments of the present disclosure has the beneficial effects that:
[0033] In the process of working of the micro light emitting diode chip, electrons are injected from one of the first semiconductor layer and the second semiconductor layer to the active layer, and recombine with holes injected from the other of the first semiconductor layer and the second semiconductor layer to emit light.
[0034] The first current expansion layer and the second current expansion layer are arranged on both sides of the first semiconductor layer and the second semiconductor layer, can play a role of current expansion, and improve the uniformity of current distribution. In addition, the second current expansion layer comprises a first sub-layer, and a second sub-layer and a third sub-layer which are periodically and alternately arranged on the first sub-layer. Since the second sub-layer is doped with Mg elements and the third sub-layer is doped with C elements, the larger ionic radius of Mg causes local expansion of the crystal lattice, introduces compressive stress, and the smaller atomic size of C causes contraction of the crystal lattice, introduces tensile stress. By alternately arranging the second sub-layer and the third sub-layer, the crystal lattice is expanded and contracted, compressive stress and tensile stress are introduced, stress self-compensation is realized, and then crystal defects are compensated, which is beneficial to uniform current distribution and effectively improves the light-emitting efficiency of the light-emitting diode. BRIEF DESCRIPTION OF DRAWINGS
[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.
[0036] Figure 1 is a structure schematic diagram of a micro light-emitting diode chip provided by the embodiments of the present disclosure;
[0037] Figure 2 is a structure schematic diagram of a second current expansion layer provided by the embodiments of the present disclosure;
[0038] Figure 3 is a flowchart of a preparation method of a micro light-emitting diode chip provided by the embodiments of the present disclosure;
[0039] Figure 4 is a flowchart of another preparation method of a micro light-emitting diode chip provided by the embodiments of the present disclosure.
[0040] The meanings of the symbols in the drawings are as follows:
[0041] 11, first current expansion layer; 12, second current expansion layer; 121, first sub-layer; 122, second sub-layer; 123, third sub-layer;
[0042] 21, first semiconductor layer; 22, second semiconductor layer;
[0043] 3, active layer;
[0044] 4, barrier layer;
[0045] 51, first ohmic contact layer; 52, second ohmic contact layer;
[0046] 6, substrate;
[0047] 7. a buffer layer;
[0048] 81. a first waveguide layer; 82. a second waveguide layer.
[0049] The specific embodiments of the present disclosure have been shown through the above drawings, and will be described in more detail hereinafter. These drawings and the written description are not intended to restrict the scope of the present disclosure concept in any way, but to illustrate the present disclosure concept to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION
[0050] In order to make the purposes, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be further described in detail below with reference to the drawings.
[0051] The present disclosure provides a micro light emitting diode chip, Figure 1 A structure diagram of the micro light emitting diode chip is shown in FIG. 1. Figure 1 In the present embodiment, the micro light emitting diode chip comprises a first current spreading layer 11, a first semiconductor layer 21, an active layer 3, a second semiconductor layer 22 and a second current spreading layer 12 which are sequentially stacked.
[0052] The first semiconductor layer 21 is of a first conduction type, the second semiconductor layer 22 is of a second conduction type, and the second conduction type is different from the first conduction type, and the first current spreading layer 11 is an AlInP layer.
[0053] Figure 2 A structure diagram of the second current spreading layer 12 is shown in FIG. 3. Figure 2 In the present embodiment, the second current spreading layer 12 comprises a first sub-layer 121, a second sub-layer 122 and a third sub-layer 123, the first sub-layer 121 is a Mg-doped GaP layer, the second sub-layer 122 is a Mg-doped GaP layer, and the third sub-layer 123 is a C-doped GaP layer, and the second sub-layer 122 and the third sub-layer 123 are periodically and alternately stacked.
[0054] In the working process of the micro light emitting diode chip, electrons are injected from one of the first semiconductor layer 21 and the second semiconductor layer 22 to the active layer 3, and recombine with holes injected from the other of the first semiconductor layer 21 and the second semiconductor layer 22 to emit light.
[0055] The first current expansion layer 11 and the second current expansion layer 12 are arranged on both sides of the first semiconductor layer 21 and the second semiconductor layer 22, and can play a role of current expansion, and improve the uniformity of current distribution. In addition, the second current expansion layer 12 includes the first sub-layer 121, and the second sub-layer 122 and the third sub-layer 123 which are periodically and alternately arranged on the first sub-layer 121. The second sub-layer 122 is doped with Mg element, and the third sub-layer 123 is doped with C element. The large ionic radius of Mg causes local lattice expansion, and introduces compressive stress. The atomic size of C is small, which causes lattice shrinkage and introduces tensile stress. By alternately arranging the second sub-layer 122 and the third sub-layer 123, the lattice expansion and shrinkage are introduced, and the compressive stress and tensile stress are introduced, so that stress self-compensation is realized, and the crystal defects are compensated, which is beneficial to the uniform distribution of current and effectively improves the light-emitting efficiency of the light-emitting diode.
[0056] In the embodiment, the first semiconductor layer 21 is an N-type AlInP layer, the active layer 3 is a multi-quantum well layer, and the second semiconductor layer 22 is a P-type AlInP layer.
[0057] In the above implementation, the first semiconductor layer 21 is an N-type layer, and the second semiconductor layer 22 is a P-type layer. Energy transition occurs between the first semiconductor layer 21 and the second semiconductor layer 22, so that light can be emitted at the active layer 3.
[0058] In addition, since the first semiconductor layer 21 is an N-type AlInP layer, and the second semiconductor layer 22 is a P-type AlInP layer, the micro light-emitting diode chip is a red light chip.
[0059] For example, the thickness of the first semiconductor layer 21 is 200-300 nm, and the carrier concentration is 1e18-2e18.
[0060] For example, the thickness of the second semiconductor layer 22 is 200-300 nm, and the carrier concentration is 7e17-9e17.
[0061] For example, the multi-quantum well layer includes periodically and alternately stacked quantum well layers and quantum barrier layers. The thickness of the quantum well layer is 3-4 nm, the thickness of the quantum barrier layer is 6-7 nm, and the number of stacking periods is 3-6.
[0062] In the embodiment, the first current expansion layer 11 is an N-type AlInP layer, and the second current expansion layer 12 is a P-type GaP layer.
[0063] For example, the thickness of the first sub-layer 121 is 3-4 μm, the thickness of the second sub-layer 122 is 2-8 nm, the thickness of the third sub-layer 123 is 3-9 nm, and the total thickness of the second sub-layer 122 and the third sub-layer 123 is 0.9-1.1 μm.
[0064] In the above implementation, the first sub-layer 121, the second sub-layer 122 and the third sub-layer 123 are designed to have the above thickness range, which can ensure the functionality of the three sub-layers and the preparation efficiency, and avoid the decrease of the preparation efficiency due to the excessive thickness.
[0065] In the embodiment, the thickness of the first sub-layer 121 is 3 μm, the thickness of the second sub-layer 122 is 5 nm, the thickness of the third sub-layer 123 is 5 nm, and the total thickness of the second sub-layer 122 and the third sub-layer 123 is 1 μm.
[0066] For example, the Mg doping concentration of the first sub-layer 121 is 5e18-1e19 cm-3, the Mg doping concentration of the second sub-layer 122 is 5e18-5e19 cm-3, and the C doping concentration of the third sub-layer 123 is 1e19-3e19 cm-3. -3 -3 -3 .
[0067] For the second sub-layer 122 and the third sub-layer 123, the doping element between adjacent layers changes from Mg to C or from C to Mg, forming a p-type doping concentration step.
[0068] For example, the number of periods of the second sub-layer 122 and the third sub-layer 123 is 30-100.
[0069] In the embodiment, the number of periods of the second sub-layer 122 and the third sub-layer 123 is 50, that is, one period of the second sub-layer 122 and the third sub-layer 123 is repeated for 50 periods.
[0070] Continuing to refer to Figure 1 In the embodiment, the micro light emitting diode chip further comprises a barrier layer 4, the barrier layer 4 is AlxGa1-xP layer, 0.5≤x≤1, and the barrier layer 4 is located between the active layer 3 and the second current spreading layer 12. x In 1-x P layer, 0.5≤x≤1, and the barrier layer 4 is located between the active layer 3 and the second current spreading layer 12.
[0071] In the above implementation, the barrier layer 4 is arranged between the active layer 3 and the second current spreading layer 12, which can block the escaped electrons, thereby effectively improving the light emitting efficiency of the micro light emitting diode chip.
[0072] Continuing to refer to Figure 1 In the embodiment, the micro light emitting diode chip further comprises a first waveguide layer 81 and a second waveguide layer 82, the first waveguide layer 81 is located between the first semiconductor layer 21 and the active layer 3, and the second waveguide layer 82 is located between the second semiconductor layer 22 and the active layer 3.
[0073] In the above implementation, the first waveguide layer 81 is an N-type waveguide layer, and the second waveguide layer 82 is a P-type waveguide layer. On one hand, the first waveguide layer 81 and the second waveguide layer 82 can play a role of optical confinement. On the other hand, the first waveguide layer 81 and the second waveguide layer 82 can also play a role of blocking diffusion of metal impurities or defects to the active layer 3, protecting the crystal quality of the quantum well, and maintaining high internal quantum efficiency.
[0074] For example, the thickness of the first waveguide layer 81 is 60-90 nm, and the thickness of the second waveguide layer 82 is 60-90 nm.
[0075] Continuing to refer to Figure 1 In this embodiment, the micro light emitting diode chip further includes a first ohmic contact layer 51 and a second ohmic contact layer 52.
[0076] The first ohmic contact layer 51 is an (Al x Ga 1-x ) 0.5 In 0.5 P layer, 0.3≤x≤1, and the first ohmic contact layer 51 is located on the side of the first current spreading layer 11 facing away from the first semiconductor layer 21.
[0077] The second ohmic contact layer 52 is a GaP layer, and the second ohmic contact layer 52 is located on the side of the second current spreading layer 12 facing away from the second semiconductor layer 22.
[0078] In the above implementation, the first ohmic contact layer 51 and the second ohmic contact layer 52 are both used to realize ohmic contact.
[0079] For example, the first ohmic contact layer 51 is an N-type ohmic contact layer, the thickness of the first ohmic contact layer 51 is 200-300 nm, and the carrier concentration is 4e18-6e18cm -3 The second ohmic contact layer 52 is a P-type ohmic contact layer, the thickness of the second ohmic contact layer 52 is 0.1-0.15 μm, and the carrier concentration is 7e19-1e20cm -3 .
[0080] Continuing to refer to Figure 1 In this embodiment, the micro light emitting diode chip further includes a substrate 6 and a buffer layer 7. The buffer layer 7 is a GaAs layer, and the buffer layer 7 is located between the substrate 6 and the first current spreading layer 11.
[0081] In the above implementation, the substrate 6 is a GaAs substrate, and through the substrate 6, a support basis can be provided for growth of other sub-layers. By providing the buffer layer 7, a good basis can be provided for preparation of other sub-layers, which is conducive to solving the problem of lattice mismatch.
[0082] For example, the buffer layer 7 is a GaAs layer, and the thickness of the buffer layer 7 is 200-300 nm.
[0083] In the above implementation, the thickness of the buffer layer 7 is designed to be in the above range, on the one hand, the crystal quality of the subsequent growth can be avoided to be reduced due to the too thin thickness, on the other hand, the light absorption of the buffer layer 7 can be avoided to be increased due to the too thick thickness, thereby the light emitting efficiency of the micro light emitting diode chip is reduced.
[0084] Figure 3 The preparation method of the micro light emitting diode chip provided in the embodiment of the present disclosure combines Figure 3 In the embodiment, the preparation method comprises:
[0085] Step 301: preparing a first current spreading layer 11.
[0086] Step 302: preparing a first semiconductor layer 21 on one side of the first current spreading layer 11, the first semiconductor layer 21 being of a first conductive type.
[0087] Step 303: preparing an active layer 3 on one side of the first semiconductor layer 21.
[0088] Step 304: preparing a second semiconductor layer 22 on one side of the active layer 3, the second semiconductor layer 22 being of a second conductive type, and the second conductive type being different from the first conductive type.
[0089] Step 305: preparing a first sub-layer 121 on one side of the second semiconductor layer 22, the first sub-layer 121 being a Mg-doped GaP layer.
[0090] Step 306: periodically and alternately preparing a second sub-layer 122 and a third sub-layer 123 on one side of the first sub-layer 121, the second sub-layer 122 being a Mg-doped GaP layer, and the third sub-layer 123 being a C-doped GaP layer.
[0091] The micro light emitting diode chip prepared by the above preparation method, in the working process, electrons are injected from one of the first semiconductor layer 21 and the second semiconductor layer 22 to the active layer 3, and combine with holes injected from the other of the first semiconductor layer 21 and the second semiconductor layer 22 to emit light.
[0092] The first current expansion layer 11 and the second current expansion layer 12 are arranged on both sides of the first semiconductor layer 21 and the second semiconductor layer 22, can play a role of current expansion, and improve the uniformity of current distribution. In addition, the second current expansion layer 12 includes the first sub-layer 121, and the second sub-layer 122 and the third sub-layer 123 which are periodically and alternately arranged on the first sub-layer 121. Since the second sub-layer 122 is doped with Mg elements, and the third sub-layer 123 is doped with C elements, the large ionic radius of Mg causes local expansion of the crystal lattice, introduces compressive stress, and the atomic size of C is small, which causes the crystal lattice to shrink and introduces tensile stress. By alternately arranging the second sub-layer 122 and the third sub-layer 123, the crystal lattice is expanded and shrunk, compressive stress and tensile stress are introduced, stress self-compensation is realized, and then the crystal defects are compensated, which is beneficial to uniform current distribution and effectively improves the light-emitting efficiency of the light-emitting diode.
[0093] Figure 4 Another preparation method of a micro light-emitting diode chip is provided in the embodiment of the present disclosure, which is combined with Figure 4 In the embodiment, the preparation method comprises the following steps.
[0094] Step 401: providing a substrate 6.
[0095] Illustratively, the substrate 6 is a GaAs substrate 6.
[0096] Step 402: preparing a buffer layer 7.
[0097] Illustratively, the buffer layer 7 is an N-type GaAs layer, the growth temperature is set to 675-695℃, the growth thickness is set to 200-300nm, the growth rate is set to 1-1.3nm / s, and the V / III ratio is set to 20-30.
[0098] Step 403: preparing a first ohmic contact layer 51.
[0099] Illustratively, the first ohmic contact layer 51 is an N-type (Al x Ga 1-x ) 0.5 In 0.5 P layer, 0.3≤x≤1, the growth temperature is set to 675-695℃, the growth thickness is set to 200-300nm, the growth rate is set to 0.3-0.4nm / s, and the V / III ratio is set to 20-30.
[0100] Step 404: preparing a first current expansion layer 11.
[0101] Exemplarily, the first current spreading layer 11 is an N-type AlInP layer, the growth temperature is set to 675-695℃, the growth thickness is set to 600-1000nm, the growth rate is set to 0.3-0.4nm / s, and the V / III ratio is set to 20-30.
[0102] Step 405: preparing the first semiconductor layer 21.
[0103] Exemplarily, the first semiconductor layer 21 is an N-type AlInP layer, the growth temperature is set to 685-705℃, the growth thickness is set to 200-300nm, the growth rate is set to 0.3-0.4nm / s, and the V / III ratio is set to 20-30.
[0104] Step 406: preparing the first waveguide layer 81.
[0105] Exemplarily, the first waveguide layer 81 is an N-type waveguide layer, the growth temperature is set to 685-705℃, the growth thickness is set to 60-90nm, the growth rate is set to 0.3-0.4nm / s, and the V / III ratio is set to 20-30.
[0106] Step 407: preparing the active layer 3.
[0107] Exemplarily, the active layer 3 is a multi-quantum well layer, alternately growing quantum well layers and quantum barrier layers in cycles. The growth temperature is set to 665-685℃, the growth rate is set to 0.3-0.4nm / s, the number of layer stacking cycles is 3-6, the growth thickness of the quantum well layer is set to 3-4nm, and the growth thickness of the quantum barrier layer is set to 6-7nm.
[0108] Step 408: preparing the second waveguide layer 82.
[0109] Exemplarily, the second waveguide layer 82 is a P-type waveguide layer, the growth temperature is set to 685-705℃, the growth thickness is set to 60-90nm, the growth rate is set to 0.3-0.4nm / s, and the V / III ratio is set to 20-30.
[0110] Step 409: preparing the barrier layer 4.
[0111] Exemplarily, the barrier layer 4 is an Al x In 1-x P layer, 0.5≤x≤1, the growth temperature is set to 685-705℃, the growth thickness is set to 10-20nm, the growth rate is set to 0.3-0.4nm / s, and the V / III ratio is set to 20-30.
[0112] Step 410: preparing the second semiconductor layer 22.
[0113] Exemplarily, the second semiconductor layer 22 is a P-type AlInP layer, the growth temperature is set to 685-705 °C, the growth thickness is set to 200-300 nm, the growth rate is set to 0.3-0.4 nm / s, and the V / III ratio is set to 20-30.
[0114] Step 411: preparing the second current spreading layer 12.
[0115] In this embodiment, step 411 comprises the following steps:
[0116] Step 4111: preparing a first sub-layer 121 on one side of the second semiconductor layer 22.
[0117] Exemplarily, the first sub-layer 121 is a Mg-doped GaP layer, the growth temperature is set to 720-740 °C, the growth thickness is set to 3-4 μm, the growth rate is set to 3-4 nm / s, the Mg doping concentration is set to 5e18-1e19 cm -3 , and the V / III ratio is set to 20-30.
[0118] Step 4112: periodically and alternately preparing a second sub-layer 122 and a third sub-layer 123 on one side of the first sub-layer 121.
[0119] Exemplarily, the second sub-layer 122 is a Mg-doped GaP layer, and the third sub-layer 123 is a C-doped GaP layer. The growth period of the second sub-layer 122 and the third sub-layer 123 is set to 30-100, the growth thickness is set to 2-8 nm, and the Mg doping concentration is set to 5e18-5e19 cm -3 during the growth of the second sub-layer 122, the growth thickness is set to 3-9 nm, and the C doping concentration is set to 1e19-3e19 cm -3 during the growth of the third sub-layer 123.
[0120] Step 412: preparing the second ohmic contact layer 52.
[0121] Exemplarily, the second ohmic contact layer 52 is a P-type GaP layer, the growth temperature is set to 650-670 °C, the growth thickness is set to 0.1-0.15 μm, the growth rate is set to 2-3 nm / s, and the V / III ratio is set to 20-30.
[0122] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first", "second", "third" and similar terms used herein do not denote any order, quantity, or importance, but are used to distinguish one element from another, and the terms "one", "another", "an" and "a" are defined as including one or more of the referenced elements. The terms "including" and "comprising" and similar terms are used herein to mean that the referenced elements are included or comprised, but not to the exclusion of other elements. The term "connected" or "coupled" and similar terms are used herein to mean either a direct connection or coupling between the connected or coupled elements, or an indirect connection or coupling between the connected or coupled elements through one or more additional elements. The terms "upper", "lower", "left", "right", and similar terms are used herein only to denote relative positions for ease of description, and can change accordingly when the absolute positions of the described objects are changed.
[0123] The above description is merely illustrative of the exemplary embodiments of this disclosure, and does not limit the scope of the disclosure. Any modification, equivalent replacement, improvement, and the like made within the spirit and principle of this disclosure shall be included in the scope of the disclosure.
Claims
1. A micro light emitting diode chip, characterized by, The micro light emitting diode chip comprises a first current spreading layer (11), a first semiconductor layer (21), an active layer (3), a second semiconductor layer (22) and a second current spreading layer (12) which are sequentially stacked; The first semiconductor layer (21) is of a first conductive type, and the second semiconductor layer (22) is of a second conductive type which is different from the first conductive type; The first current spreading layer (11) is an AlInP layer, and the second current spreading layer (12) comprises a first sub-layer (121), a second sub-layer (122) and a third sub-layer (123), the first sub-layer (121) is a Mg-doped GaP layer, the second sub-layer (122) is a Mg-doped GaP layer, and the third sub-layer (123) is a C-doped GaP layer, and the second sub-layer (122) and the third sub-layer (123) are periodically and alternately stacked.
2. The micro light emitting diode chip of claim 1, wherein, The thickness of the first sub-layer (121) is 3-4 μm, the thickness of the second sub-layer (122) is 2-8 nm, the thickness of the third sub-layer (123) is 3-9 nm, and the total thickness of the second sub-layer (122) and the third sub-layer (123) is 0.9-1.1 μm.
3. The micro light emitting diode chip of claim 1, wherein, The Mg doping concentration of the first sub-layer (121) is 5e18-1e19 cm -3 The Mg doping concentration of the second sub-layer (122) is 5e18-5e19 cm -3 The C doping concentration of the third sub-layer (123) is 1e19-3e19 cm -3 .
4. The micro light emitting diode chip of claim 1, wherein, The period number of the second sub-layer (122) and the third sub-layer (123) is 30-100.
5. The micro light emitting diode chip according to any one of claims 1 to 4, wherein, The micro light emitting diode chip further comprises a barrier layer (4); The barrier layer (4) is Al x In 1-x P layer, 0.5≤x≤1, the barrier layer (4) is located between the active layer (3) and the second current spreading layer (12).
6. The micro light emitting diode chip according to any one of claims 1 to 4, wherein The micro light emitting diode chip further comprises a first ohmic contact layer (51) and a second ohmic contact layer (52); The first ohmic contact layer (51) is (Al x Ga 1-x ) 0.5 In 0.5 P layer, 0.3≤x≤1, the first ohmic contact layer (51) is located on the side of the first current spreading layer (11) away from the first semiconductor layer (21); The second ohmic contact layer (52) is a GaP layer, and the second ohmic contact layer (52) is located on a side of the second current spreading layer (12) which is away from the second semiconductor layer (22).
7. The micro light emitting diode chip according to any one of claims 1 to 4, wherein, The micro light emitting diode chip further comprises a substrate (6) and a buffer layer (7); The buffer layer (7) is a GaAs layer, and the buffer layer (7) is located between the substrate (6) and the first current spreading layer (11).
8. A method of fabricating a micro light emitting diode chip, characterized by, The method comprises: Preparation of the first current spreading layer (11); Preparation of the first semiconductor layer (21) on a side of the first current spreading layer (11), the first semiconductor layer (21) being of a first conductive type; Preparation of the active layer (3) on a side of the first semiconductor layer (21); Preparation of the second semiconductor layer (22) on a side of the active layer (3), the second semiconductor layer (22) being of a second conductive type which is different from the first conductive type; Preparation of the first sub-layer (121) on a side of the second semiconductor layer (22), the first sub-layer (121) being a Mg-doped GaP layer; Periodic and alternate preparation of the second sub-layer (122) and the third sub-layer (123) on a side of the first sub-layer (121), the second sub-layer (122) being a Mg-doped GaP layer, and the third sub-layer (123) being a C-doped GaP layer.
9. The production method according to claim 8, characterized by, Preparation of the first sub-layer (121) on a side of the second semiconductor layer (22) comprises: The growth temperature is set to 720-740 °C, the growth thickness is set to 3-4 μm, the growth rate is set to 3-4 nm / s, and the Mg doping concentration is set to 5e18-1e19 cm -3 The V / III ratio is set to 20-30.
10. The preparation method according to claim 8, characterized in that, Periodic and alternate preparation of the second sub-layer (122) and the third sub-layer (123) on a side of the first sub-layer (121) comprises: The growth period of the second sub-layer (122) and the third sub-layer (123) is set to 30-100; In the process of growing the second sub-layer (122), the growth thickness is set to 2-8 nm, and the Mg doping concentration is set to 5e18-5e19 cm -3 , In the process of growing the third sub-layer (123), the growth thickness is set to 3-9 nm, and the C doping concentration is set to 1e19-3e19 cm -3 .