LED chip with large light-emitting area and manufacturing method

Abstract

The invention provides an LED chip with a large light-emitting area and a manufacturing method, and relates to the technical field of semiconductors. The chip sequentially comprises a transparent substrate, a bonding layer, a light window layer, a P-type limiting layer, an active layer, an N-type limiting layer and an N-type current expansion layer from bottom to top, an N-type electrode is arranged above the N-type current expansion layer, an N-type ohmic layer is arranged between the N-type electrode and the N-type current expansion layer, the light window layer comprises a light window upper side and a light window lower side, and the light window lower side is provided with a light window upper surface. A first step surface is formed between the light window upper side and the light window lower layer. A P-type electrode is arranged on the side face of the light window lower layer. And a second step surface is formed between the light window layer and the bonding layer. The P-type electrode comprises a main body part, the upper end of the main body part is provided with a first extension part extending to the first step surface, and the lower end of the main body part is provided with a second extension part extending to the second step surface. The chip can effectively improve the light-emitting area and the light-emitting brightness of LEDs with the same size level, thereby adapting to the requirements of terminal products.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to an LED chip with a large light-emitting area and its manufacturing method. Background Technology

[0002] Driven by market demand, Mini LED has rapidly moved towards large-scale commercialization and has shone brightly in fields such as TVs, monitors, laptops, tablets, automotive displays, and VR.

[0003] like Figure 14 As shown, traditional red Mini LEDs involve bonding a transparent material such as a sapphire substrate to a red epitaxial wafer via a SiO2 layer to replace the substrate. The epitaxial material is then etched down to the light window layer, and metal is deposited on the exposed step surface of the light window layer to form a P-type ohmic contact. This process loses brightness due to the etching away of part of the active layer. Furthermore, as the size of Mini LED chips continues to shrink, the light-emitting area also shrinks, significantly reducing the chip's brightness and making it unsuitable for the needs of end products. Summary of the Invention

[0004] To address the aforementioned issues, this application provides an LED chip with a large luminous area and a manufacturing method thereof, which can effectively improve the luminous area and brightness of LEDs of the same size, thereby better meeting the size and performance requirements of end products.

[0005] The technical solution adopted by this invention to solve its technical problem is: An LED chip with a large light-emitting area comprises, from bottom to top, a transparent substrate, a bonding layer, a light window layer, a P-type confinement layer, an active layer, an N-type confinement layer, and an N-type current spreading layer. An N-type electrode is disposed above the N-type current spreading layer, and an N-type ohmic layer is disposed between the N-type electrode and the N-type current spreading layer. The light window layer includes an upper light window and a lower light window layer, and a first step surface is formed between the upper light window and the lower light window layer. A P-type electrode is provided on the side of the lower layer of the optical window; A second step surface is formed between the optical window layer and the bonding layer; The P-type electrode includes a main body, the upper end of which is provided with a first extension extending to a first step surface, and the lower end of which is provided with a second extension extending to a second step surface.

[0006] Furthermore, a DBR passivation layer is deposited on the upper part, and P-type conductive holes and N-type conductive holes are respectively provided on the DBR passivation layer for avoiding the P-type electrode and the N-type electrode.

[0007] Furthermore, the DBR passivation layer is formed by overlapping TiO2 and SiO2 layers.

[0008] Furthermore, the sides of the upper layer of the optical window, the P-type confinement layer, the active layer, the N-type confinement layer, and the N-type current spreading layer are coplanar and together form a conical structure, and the sides of the lower layer of the optical window are also conical.

[0009] A method for fabricating an LED chip with a large light-emitting area includes the following steps: S1, a barrier layer, an N-type ohmic layer, an N-type confinement layer, an N-type current spreading layer, an active layer, a P-type confinement layer and an optical window layer are sequentially grown on a temporary substrate; S2, roughen the optical window layer of the epitaxial wafer to obtain the roughened surface of the optical window layer; S3, deposit a bonding layer on the roughened surface of the optical window layer, and polish the bonding layer to obtain a polished surface; S4. After cleaning and activating the polished surfaces of the transparent substrate and bonding layer, bonding is performed. S5, Remove the temporary substrate and barrier layer; S6, perform an etching on the epitaxial wafer, the etching extending into the optical window layer and forming a first step surface; S7, perform a second etching on the epitaxial wafer, the second etching extending to the bonding layer and forming a dicing channel; S8, an N-type electrode is fabricated on the N-type ohmic layer, and a P-type electrode is fabricated on the side of the layer below the optical window; S9, deposit a DBR passivation layer on the epitaxial wafer, and etch the DBR passivation layer to form P-conductive holes and N-conductive holes.

[0010] S10, thinning the epitaxial wafer and cutting it along the dicing path.

[0011] Furthermore, the roughening depth of the roughened surface of the optical window layer is 6000-10000 angstroms.

[0012] Furthermore, the thickness of the bonding layer is 2.5-3.5 μm, and the roughness of the polished surface after polishing is less than or equal to 2 nm.

[0013] Furthermore, the etching angle α for a single etching operation is 60°-80°.

[0014] Furthermore, the etching angle β of the secondary etching is 30°-50°.

[0015] Furthermore, the P-type electrode is Au / AuBe / Au, and the N-type electrode is AuGeNiPtAu.

[0016] The beneficial effects of this invention are: 1. The present application provides an LED chip with a large light-emitting area and a manufacturing method thereof. By increasing the sidewall area of ​​the light window layer and fabricating the P-type electrode on the sidewall and step surface formed by etching the light window layer, the etching area for the P-type electrode is eliminated. Without changing the size of the LED, the light-emitting area can be effectively increased, thereby improving the brightness of the chip.

[0017] 2. The LED chip with a large light-emitting area provided in this application embodiment can not only meet the size requirements of the end product, but also meet the brightness performance requirements of the end product.

[0018] 3. The LED chip with a large light-emitting area provided in this application embodiment can be further reduced in size while maintaining the same brightness. This not only better meets the requirements of highly integrated end products, but also reduces costs because more chips can be produced from a single wafer after the size reduction. Attached Figure Description

[0019] Figure 1 A schematic diagram of the structure of an LED chip with a large light-emitting area provided in an embodiment of this application; Figure 2 The process of fabricating an LED chip with a large light-emitting area provided in this application embodiment. Figure 1 ; Figure 3 The process of fabricating an LED chip with a large light-emitting area provided in this application embodiment. Figure 2 ; Figure 4 The process of fabricating an LED chip with a large light-emitting area provided in this application embodiment. Figure 3 ; Figure 5 The process of fabricating an LED chip with a large light-emitting area provided in this application embodiment. Figure 4 ; Figure 6 The process of fabricating an LED chip with a large light-emitting area provided in this application embodiment. Figure 5 ; Figure 7 The process of fabricating an LED chip with a large light-emitting area provided in this application embodiment. Figure 6 ; Figure 8 The process of fabricating an LED chip with a large light-emitting area provided in this application embodiment. Figure 7 ; Figure 9The process of fabricating an LED chip with a large light-emitting area provided in this application embodiment. Figure 8 ; Figure 10 The process of fabricating an LED chip with a large light-emitting area provided in this application embodiment. Figure 9 ; Figure 11 The process of fabricating an LED chip with a large light-emitting area provided in this application embodiment. Figure 10 ; Figure 12 The process of fabricating an LED chip with a large light-emitting area provided in this application embodiment. Figure 10 one; Figure 13 The process of fabricating an LED chip with a large light-emitting area provided in this application embodiment. Figure 10 two; Figure 14 This is a schematic diagram of the structure of a traditional red Mini LED chip.

[0020] In the figure: 11. Temporary substrate; 12. Barrier layer; 21. N-type ohmic layer; 22. N-type current spreading layer; 23. N-type confinement layer; 24. Active layer; 25. P-type confinement layer; 26. Optical window layer; 261. Upper optical window layer; 262. Lower optical window layer; 263. Roughened surface; 264. First step surface; 27. Bonding layer; 28. Transparent substrate; 31. P-type electrode; 32. N-type electrode; 4. DBR passivation layer; 41. P-conductive via; 42. N-conductive via; 5. Second step surface; 6. Cutter track. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings. The described embodiments are merely a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort should fall within the protection scope of this application.

[0022] like Figure 1 As shown, an LED chip with a large light-emitting area includes, from bottom to top, a transparent substrate 28, a bonding layer 27, a light window layer 26, a P-type confinement layer 25, an active layer 24, an N-type confinement layer 23, and an N-type current spreading layer 22.

[0023] An N-type electrode 32 is disposed above the N-type current extension layer 22, and an N-type ohmic layer 21 is disposed between the N-type electrode 32 and the N-type current extension layer 22. The size of the N-type ohmic layer 21 is the same as that of the N-type electrode 32, and the projections of the N-type ohmic layer 21 and the N-type electrode 32 in the horizontal plane coincide.

[0024] The optical window layer 26 comprises upper and lower layers. For ease of understanding of this specific embodiment, the portion located in the upper layer is defined as the upper side of the optical window, and the portion located in the lower layer is defined as the lower optical window layer 262. A first stepped surface 264 is formed between the upper side of the optical window and the lower optical window layer 262. A P-type electrode 31 is disposed on the side of the lower optical window layer 262.

[0025] Furthermore, a second stepped surface 5 is formed between the optical window layer 26 and the bonding layer 27. The P-type electrode 31 includes a main body portion, which is attached to the side of the lower optical window layer 262. The upper end of the main body portion is provided with a first extension portion extending horizontally inward (with the side closer to the upper side of the optical window as the inner side), and the lower side of the first extension portion is attached to the first stepped surface 264. The lower end of the main body portion is provided with a second extension portion extending horizontally outward (with the side closer to the lower side of the optical window as the inner side), and the lower side of the second extension portion is attached to the second stepped surface 5.

[0026] Furthermore, the sides of the upper optical window layer 261, the P-type confinement layer 25, the active layer 24, the N-type confinement layer 23, and the N-type current extension layer 22 are coplanar and together form a tapered structure with a smaller upper end and a larger lower end.

[0027] In one specific implementation, the sides of the upper optical window layer 261, the P-type confinement layer 25, the active layer 24, the N-type confinement layer 23, and the N-type current extension layer 22 together form a quadrangular pyramid structure.

[0028] Furthermore, the side of the lower layer 262 of the light window has a tapered structure with a smaller upper dimension and a larger lower dimension.

[0029] In one specific implementation, the side of the lower layer 262 of the light window in this embodiment has a square pyramid structure.

[0030] Furthermore, a DBR passivation layer 4 is deposited on the upper part of an LED chip with a large light-emitting area. The DBR passivation layer 4 is provided with P-type conductive holes 41 and N-type conductive holes 42 for avoiding the P-type electrode 31 and N-type electrode 32, respectively.

[0031] In one specific embodiment, the P-type conductive hole 41 is located directly above the P-type electrode 31, and the N-type conductive hole 42 is located directly above the N-type electrode 32.

[0032] In one specific embodiment, the temporary substrate 11 is made of GaAs material. The barrier layer 12 is made of GaInP material. The N-type ohmic layer 21 is made of GaAs material. The N-type current spreading layer 22 is made of AlGaInP material. The N-type confinement layer 23 is made of AlInP material. The P-type confinement layer 25 is made of AlInP material. The optical window layer 26 has a P-type structure and is made of GaP material. The bonding layer 27 is made of SiO2 material. The transparent substrate 28 is made of sapphire.

[0033] A method for fabricating an LED chip with a large light-emitting area includes the following steps: S1, using MOCVD technology, a barrier layer 12, an N-type ohmic layer 21, an N-type confinement layer 23, an N-type current spreading layer 22, an active layer 24, a P-type confinement layer 25, and an optical window layer 26 are sequentially grown on a temporary substrate 11, resulting in the following: Figure 2 The epitaxial wafer shown.

[0034] S2, the optical window layer 26 of the epitaxial wafer obtained in step S1 is roughened using a mixture of concentrated sulfuric acid, hydrofluoric acid, and iodic acid to obtain the following... Figure 3 The roughened surface 263 of the light window layer 26 shown.

[0035] Preferably, the roughening depth of the roughened surface 263 of the optical window layer 26 is 6000-10000 angstroms, and it is roughened 3 times, with each roughening time being 30 seconds.

[0036] S3, as Figure 4 As shown, a SiO2 layer is deposited on the roughened surface 263 of the optical window layer 26 as a bonding layer 27, and the bonding layer 27 is polished to obtain a smooth and clean polished surface.

[0037] Preferably, the bonding layer 27 has a thickness of 2.5-3.5 μm and is formed by PECVD or electron beam evaporation.

[0038] In one specific embodiment, the bonding layer 27 has a thickness of 2.5 μm and the roughness of the polished surface after polishing is less than or equal to 2 nm.

[0039] S4, as Figure 5 As shown, the polished surfaces of the transparent substrate 28 and the bonding layer 27 are cleaned and activated before bonding.

[0040] Preferably, the bonding temperature is 350-500℃ and the bonding pressure is 9-14KKG.

[0041] In one specific implementation, the bonding temperature in this embodiment is 400℃ and the bonding pressure is 13.5KKG.

[0042] S5, remove the temporary substrate 11 and the barrier layer 12 to complete the substrate replacement, resulting in the following: Figure 6 The epitaxial wafer shown.

[0043] In one specific embodiment, a mixed solution of ammonia, hydrogen peroxide, and water is used to remove the temporary substrate 11, with a volume ratio of 1:4:5. A mixed solution of hydrochloric acid and water is used to remove the barrier layer 12, with a volume ratio of 3:2.

[0044] S6, such as Figure 7 and Figure 8 As shown, a step surface pattern is formed on the epitaxial wafer obtained in step S5 by photolithography, and then an ICP etching process is used for a first etching. The first etching extends into the optical window layer 26 and forms the first step surface 264.

[0045] Preferably, the etching angle α for a single etching operation is 60°-80°.

[0046] In one specific implementation, the etching depth of a single etching step in this embodiment is 5.5 μm, and the etching angle α of a single etching step is 70°.

[0047] S7, such as Figure 9 and Figure 10 As shown, the epitaxial wafer obtained in step S6 is subjected to secondary etching through photolithography and ICP etching processes. The secondary etching extends to the bonding layer 27 and forms the dicing channel 6. Preferably, the etching angle β of the secondary etching is 30°-50°.

[0048] In one specific implementation, the etching angle β of the secondary etching in this embodiment is 40°.

[0049] S8, an N-type electrode 32 is fabricated on the N-type ohmic layer 21, and the N-type ohmic layer 21 is etched to make its shape the same as that of the N-type electrode 32. A P-type electrode 31 is fabricated on the side of the lower layer 262 of the optical window, resulting in... Figure 11 The epitaxial wafer shown.

[0050] In one specific embodiment, the P-type electrode 31 in this embodiment is Au / AuBe / Au, and the N-type electrode 32 is AuGeNiPtAu.

[0051] S9, such as Figure 12 and Figure 13 As shown, a DBR passivation layer 4 is deposited on the upper surface of the epitaxial wafer obtained in step S8, and the DBR passivation layer 4 above the P-type electrode 31 and N-type electrode 32 is etched by ICP, thereby forming P-conductive holes 41 and N-conductive holes 42.

[0052] In one specific implementation, the DBR passivation layer 4 described in this embodiment is formed by overlapping TiO2 layers and SiO2 layers, with an overlap period of 16. That is, the DBR passivation layer 4 includes 16 TiO2 layers and 16 SiO2 layers, which are arranged alternately.

[0053] S10, the epitaxial wafer obtained in step S9 is thinned and cut along the cutting path 6, and after sorting and testing, an LED chip with a large light-emitting area is obtained.

[0054] Other embodiments obtained by those skilled in the art based on the embodiments provided in this application by combining, splitting, or reorganizing the embodiments of this application do not exceed the protection scope of this application.

[0055] The above detailed embodiments have provided a detailed explanation of the purpose, technical solutions, and beneficial effects of the embodiments of this application. The above are merely specific embodiments of the embodiments of this application and are not intended to limit the protection scope of the embodiments of this application. That is, any modifications, equivalent substitutions, improvements, etc., made on the basis of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. An LED chip with a large light-emitting area, comprising, from bottom to top, a transparent substrate (28), a bonding layer (27), a light window layer (26), a P-type confinement layer (25), an active layer (24), an N-type confinement layer (23), and an N-type current spreading layer (22), wherein an N-type electrode (32) is disposed above the N-type current spreading layer (22), and an N-type ohmic layer (21) is disposed between the N-type electrode (32) and the N-type current spreading layer (22), characterized in that: The light window layer (26) includes an upper light window and a lower light window layer (262), and a first step surface (264) is formed between the upper light window and the lower light window layer (262). A P-type electrode (31) is provided on the side of the lower layer (262) of the optical window. A second step surface (5) is formed between the optical window layer (26) and the bonding layer (27); The P-type electrode (31) includes a main body, the upper end of which is provided with a first extension extending to a first step surface (264), and the lower end of which is provided with a second extension extending to a second step surface (5).

2. The LED chip with a large light-emitting area according to claim 1, characterized in that: A DBR passivation layer (4) is deposited on the upper part, and P conductive holes (41) and N conductive holes (42) are provided on the DBR passivation layer (4) for avoiding the P-type electrode (31) and N-type electrode (32), respectively.

3. The LED chip with a large light-emitting area according to claim 2, characterized in that: The DBR passivation layer (4) is formed by overlapping TiO2 and SiO2 layers.

4. The LED chip with a large light-emitting area according to claim 1, characterized in that: The sides of the upper optical window layer (261), the P-type confinement layer (25), the active layer (24), the N-type confinement layer (23), and the N-type current extension layer (22) are coplanar and together form a conical structure. The side of the lower optical window layer (262) is also conical.

5. A method for fabricating an LED chip with a large light-emitting area as described in any one of claims 2-4, characterized in that: Includes the following steps, S1, a barrier layer (12), an N-type ohmic layer (21), an N-type confinement layer (23), an N-type current spreading layer (22), an active layer (24), a P-type confinement layer (25), and an optical window layer (26) are sequentially grown on a temporary substrate (11). S2, roughen the optical window layer (26) of the epitaxial wafer to obtain the roughened surface (263) of the optical window layer (26). S3, deposit a bonding layer (27) on the roughened surface (263) of the optical window layer (26), and polish the bonding layer (27) to obtain a polished surface; S4, after cleaning and activating the polished surfaces of the transparent substrate (28) and the bonding layer (27), bonding is performed; S5, remove the temporary substrate (11) and the barrier layer (12). S6, the epitaxial wafer is etched once, the first etching extending into the optical window layer (26) and forming a first step surface (264). S7, perform secondary etching on the epitaxial wafer, the secondary etching extending to the bonding layer (27) and forming a dicing channel (6). S8, an N-type electrode (32) is fabricated on the N-type ohmic layer (21), and a P-type electrode (31) is fabricated on the side of the lower layer (262) of the optical window. S9, deposit a DBR passivation layer (4) on the epitaxial wafer and etch the DBR passivation layer (4) to form a P-conductive hole (41) and an N-conductive hole (42). S10, the epitaxial wafer is thinned and cut along the cutting path (6).

6. The method for fabricating an LED chip with a large light-emitting area according to claim 5, characterized in that: The roughening depth of the roughened surface (263) of the light window layer (26) is 6000-10000 angstroms.

7. The method for fabricating an LED chip with a large light-emitting area according to claim 5, characterized in that: The bonding layer (27) has a thickness of 2.5-3.5 μm, and the roughness of the polished surface after polishing is less than or equal to 2 nm.

8. The method for fabricating an LED chip with a large light-emitting area according to claim 5, characterized in that: The etching angle α for a single etching operation is 60°-80°.

9. The method for fabricating an LED chip with a large light-emitting area according to claim 5, characterized in that: The etching angle β for the secondary etching is 30°-50°.

10. The method for fabricating an LED chip with a large light-emitting area according to claim 5, characterized in that: The P-type electrode (31) is Au / AuBe / Au, and the N-type electrode (32) is AuGeNiPtAu.

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