Method for testing breakdown resistance of ultrathin gate oxide layer under ESD (Electro-Static Discharge) stress

Abstract

The invention discloses an ultra-thin gate oxide breakdown resistance test method under ESD stress, and the method comprises the steps: applying voltage to a gate electrode and a drain electrode of a to-be-tested semiconductor device, and carrying out the measurement to obtain a transfer characteristic curve of the to-be-tested device; applying an electrostatic pulse of which the amplitude increases progressively to the grid of the to-be-tested device, performing a TLP test, obtaining a grid stress voltage and a leakage current of the to-be-tested device under TLP stress, performing the TLP test circularly until the leakage current changes by more than three orders of magnitude, and regarding that a gate oxide layer of the to-be-tested device is broken down; and according to a channel carrier number fluctuation model and drain current noise, calculating the defect density of the gate oxide layer of the to-be-tested device after each round of TLP stress application, and utilizing the stress voltage and the defect density under each round of TLP stress to obtain a fitting curve of the stress voltage and the defect density for predicting the breakdown voltage of the gate oxide layer of the device of the same type. According to the method, the breakdown voltage of the gate oxide layer of the ESD to-be-protected device can be predicted in a large-scale and batch manner.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor and integrated circuit testing, and particularly relates to a method for testing the breakdown resistance of an ultra-thin gate oxide layer under ESD stress. BACKGROUND

[0002] Transistors are important components of integrated circuits. With the development of integrated circuit manufacturing processes, following Moore's Law, the feature size of devices has been scaled down to the nanometer level. The thickness of the gate oxide layer under advanced processes has been made to be several nanometers or even less than 1 nm, and the ultra-thin gate oxide layer makes the device extremely sensitive to ESD (electrostatic discharge) stress. Electrostatic discharge ESD refers to the phenomenon that when two objects with different charges approach each other, the insulating medium between them is broken down by the electric field to form a conductive channel, and the charge is transferred. Electrostatic discharge is considered to be the main cause of excessive electrical stress damage to various electronic components or integrated circuit systems. Because static electricity is manifested as a very high voltage and a large current of instantaneous accumulation, it can cause device breakdown and lead to device electrical and thermal failure. In integrated circuits, most of the input ports of CMOS current are inverter structures composed of PMOS and NMOS, and when an ESD pulse arrives, the gate oxide layer on the MOSFET is first impacted. Therefore, the ESD resistance of the gate oxide layer, i.e. the voltage resistance, greatly affects the performance of the transistor, and the breakdown voltage of the gate oxide layer of the device becomes an important indicator of ESD protection.

[0003] The existing test for the breakdown voltage of the gate oxide layer of a device is usually performed by a transmission line pulse (TLP) test method. The TLP test method can be used to study the relationship between voltage and current in the time domain of an integrated circuit device when an ESD event occurs, and its advantage lies in characterizing the transient characteristics of the device when an ESD event occurs. However, the existing TLP test method has the following disadvantages: the breakdown voltage of the gate oxide layer of the device can only be obtained when hard breakdown of the device occurs, and there is a lack of means to predict the breakdown resistance of the gate oxide layer; in large-scale batch testing, due to the process parameter fluctuations in the device manufacturing process, the breakdown voltages of similar devices may differ, and the existing TLP test method is low in efficiency. SUMMARY

[0004] The purpose of the present application is to provide a method for testing the breakdown resistance of an ultra-thin gate oxide layer under ESD stress, which can predict the breakdown voltage of the gate oxide layer of an ESD-protected device in large-scale batch testing.

[0005] In order to achieve the above-mentioned purpose, one aspect of the present application provides a method for testing the breakdown resistance of an ultra-thin gate oxide layer under ESD stress, comprising:

[0006] Step S1, using a semiconductor parameter analyzer to apply voltage to the gate and drain of the semiconductor device to be measured, and measuring the transfer characteristic curve of the device to be measured;

[0007] Step S2, using a TLP pulse generator to apply an electrostatic pulse to the gate of the device to be measured, and performing TLP test to obtain the gate stress voltage and leakage current of the device to be measured under TLP stress;

[0008] Step S3, after the TLP stress is applied, using the semiconductor parameter analyzer to measure the drain current noise under TLP stress, returning to step S2 to start the next round of TLP test, wherein the amplitude of the electrostatic pulse applied is increased in each round of TLP stress application, so as to obtain the change of the gate stress voltage and the leakage current of the device to be measured with the gradual increase of the pulse amplitude, and the TLP test is performed in a cycle until the leakage current changes by more than 3 orders of magnitude, which is regarded as the breakdown of the gate oxide layer of the device to be measured;

[0009] Step S4, according to the channel carrier number fluctuation model, calculating the defect density of the gate oxide layer of the device to be measured after each round of TLP stress application according to the measured drain current noise, using the stress voltage under each round of TLP stress and the defect density as a plotting point to obtain the fitting curve of the stress voltage and the defect density of the device to be measured, which is used for predicting the breakdown voltage of the gate oxide layer of the same type of device.

[0010] According to the ESD stress ultra-thin gate oxide layer breakdown resistance test method of the above aspect of the present application, the breakdown voltage of the gate oxide layer of the ESD protected device can be predicted in large scale and batch. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the present application, the following will briefly introduce the drawings used in the description of the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor:

[0012] Figure 1 The application scenario diagram of the ESD stress ultra-thin gate oxide layer breakdown resistance test method of one embodiment of the present application;

[0013] Figure 2 The flowchart of the ESD stress ultra-thin gate oxide layer breakdown resistance test method of one embodiment of the present application. DETAILED DESCRIPTION

[0014] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0015] The embodiments of the present invention provide a method for testing the breakdown resistance of an ultrathin gate oxide layer under ESD stress, which can utilize... Figure 1 The test setup shown was used to perform breakdown resistance tests on ultrathin gate oxide layers under ESD stress. Figure 1 The testing apparatus includes a semiconductor parameter analyzer 11, a TLP pulse generator 12, and a gating switch 13. The semiconductor device under test 10 has a source electrode S, a drain electrode D, a gate electrode G, and a substrate electrode B.

[0016] The semiconductor parameter analyzer 11 applies voltages to the gate (G) and drain (D) of the semiconductor device under test (DUT) 10 to measure and acquire the device's transfer characteristic curve (IV characteristic) and low-frequency noise (LFN characteristic). The defect density of the gate oxide layer is extracted from the acquired LFN characteristic, and then, combined with the stress-voltage data from the TLP pulse generator, a stress-voltage-defect density curve is plotted. The TLP pulse generator 12 applies an electrostatic pulse to the gate of the DUT 10 to perform TLP testing and acquire the current-voltage relationship of the device under TLP stress. The selector switch 13 switches the connection between the DUT 10 and the semiconductor parameter analyzer 11 or the TLP pulse generator 12. When testing the IV and LFN characteristics, the DUT is connected to the semiconductor parameter analyzer; when applying TLP stress, the DUT is connected to the TLP pulse generator.

[0017] like Figure 2 As shown, the test method for the breakdown resistance of an ultrathin gate oxide layer under ESD stress according to an embodiment of the present invention includes steps S1-S4.

[0018] Step S1, Initial Electrical Characteristic Parameter Measurement: Connect the semiconductor device under test to the semiconductor parameter analyzer by using a selector switch. Apply voltage to the gate and drain of the semiconductor device under test using the semiconductor parameter analyzer to measure and obtain the transfer characteristic curve of the device.

[0019] In this step, the semiconductor parameter analyzer provides a suitable voltage bias to the semiconductor device under test and measures the transfer characteristic curve of the device. Based on the transfer characteristic curve, the appropriate gate and drain voltage bias of the device can be determined for subsequent low-frequency noise testing.

[0020] Step S2, TLP electric stress application: a preset pulse parameter is applied to the gate of the semiconductor device to be measured to obtain the gate stress voltage and the leakage current of the semiconductor device to be measured under TLP stress. The gate voltage and current average value in the 70%-90% time period of the measurement period of each pulse amplitude can be taken as a drawing point of a TLP I-V curve, which is used for drawing the subsequent TLP I-V curve.

[0021] In this step, the TLP pulse generator applies a series of voltage pulse waves (electrostatic pulses) with increasing amplitude to the gate of the semiconductor device to be measured to obtain the current response curve of the semiconductor device to be measured as the pulse wave voltage gradually increases and the change of the gate leakage current of the device. The pulse wave can be generated by a high-voltage power supply, a fast switch and a transmission line, the amplitude of the pulse wave can be adjusted by changing the value of the constant voltage source, and the pulse width can be adjusted by replacing the length of the transmission line.

[0022] Step S3, low-frequency noise measurement after TLP stress: after each TLP stress application, the semiconductor parameter analyzer is switched to measure the drain current noise under the stress through the gating switch, and then the TLP pulse generator is switched back through the gating switch to return to step S2 to start the next round of TLP test. The data points obtained in each round are drawn into a complete TLP I-V curve and a leakage current curve, and the cycle is repeated until the leakage current changes by more than 3 orders of magnitude compared with the initial leakage current, which is regarded as the breakdown of the gate oxide layer of the device.

[0023] In this step, the TLP test applies a series of voltage pulse waves with increasing amplitude to obtain the gate stress voltage and the change of the gate leakage current of the semiconductor device to be measured as the pulse wave voltage gradually increases, specifically, to draw the TLP I-V curve and the leakage current curve, wherein the I-V curve can obtain the stress voltage value that the device can withstand, and the leakage current curve is used to judge when the device breaks down.

[0024] In the embodiment of the present application, the low-frequency noise is 1 / f noise, and the size of the 1 / f noise is expressed in the form of the power spectral density PSD (S id ) measured by the semiconductor parameter analyzer. By dividing the square of the drain current I d , the normalized low-frequency current noise intensity S id / I d 2 .

[0025] Step S4, defect density extraction and breakdown voltage prediction: according to the channel carrier number fluctuation model, the defect density N itThe voltage of the device under each round of TLP stress and the defect density are taken as a plot point to obtain a fitting curve of the stress voltage and the defect density of the semiconductor device under test, which is used to predict the breakdown voltage of the same type of device.

[0026] The test method for the breakdown resistance of the ultra-thin gate oxide layer under ESD stress in the embodiments of the present application is further described in detail below through a specific embodiment. In this embodiment, a batch of silicon-based N-type MOSFETs are selected as the semiconductor device under test.

[0027] In step S1, a suitable voltage is applied to the gate and drain of a silicon-based N-type MOSFET under test to obtain the initial transfer characteristic curve of the semiconductor device under test, for example, the relationship curve between the gate voltage and the drain current. The appropriate bias for the subsequent measurement of low-frequency noise can be selected according to the transfer characteristic curve. In order to facilitate the extraction of the defect density of the gate oxide layer of the device from the low-frequency noise characteristics of the device, the selected gate voltage bias test points cover the sub-threshold region and the saturation region of the device.

[0028] In step S2, an electrostatic pulse with an increasing amplitude is applied to the gate of the semiconductor device under test with preset pulse parameters, and the average value of the gate voltage and current in the 70%-90% time period of the measurement period at this pulse amplitude is taken as a plot point of a TLP I-V curve.

[0029] In step S3, after each round of TLP stress application, the semiconductor parameter analyzer is switched to measure the drain current noise under this stress through the gating switch. After the noise measurement is completed, the TLP pulse generator is switched back through the gating switch, and step S2 is returned to start the next round of TLP test. The data points obtained in each round are plotted into a complete TLP I-V curve and a leakage current curve, and the cycle is repeated until a change of more than 3 orders of magnitude in the leakage current is considered as the breakdown of the gate oxide layer of the device.

[0030] In step S4, according to the characteristics of the silicon-based N-type MOSFET, the defect density N it of the semiconductor device under test after each round of TLP stress application is extracted according to the channel carrier number fluctuation model.

[0031]

[0032] wherein N it is the defect density near the interface of the gate oxide layer, S vfb is the flat-band voltage noise, f is the frequency, W is the gate width of the device, L is the gate length of the device, and C oxis the capacitance of the gate oxide layer per unit area, q is the basic charge quantity, k is the Boltzmann constant, T is the temperature, and λ is the tunneling factor (the value in the gate oxide layer of SiO2 is about 0.1 nm).

[0033] The flat band voltage noise is calculated by the measured drain current noise, and the calculation formula of the flat band voltage noise is The drain current I d And the transconductance g m Can be obtained according to the initial transfer characteristic curve obtained in step S1.

[0034] In this embodiment, the stress voltage value (voltage obtained by TLP I-V curve) obtained by each round of TLP stress and the defect density are taken as a drawing point to obtain a fitting curve of the stress voltage and the defect density of the semiconductor device to be measured. Specifically, the fitting curve equation of the stress voltage and the defect density of the semiconductor device to be measured is:

[0035]

[0036] Wherein, V DUT is the voltage of the device under TLP stress, N it is the defect density near the gate oxide layer interface, and a, b and c are parameters to be fitted.

[0037] The fitting curve of the stress voltage and the defect density of the semiconductor device to be measured obtained above is for a single device, and the fitting curves of a batch of devices of the same type (same process parameters) are obtained in the same way. The average fitting curve of the stress voltage and the defect density of the device is obtained by averaging all the fitting curves of the batch of devices of the same type. The initial defect density N0 measured for the subsequent device of the same type is substituted into the averaged fitting curve to obtain the stress voltage V0, and the gate oxide breakdown voltage V BR0 of the device is predicted. BR Subtract V0.

[0038] In summary, the test method for the breakdown resistance of the ultra-thin gate oxide layer under ESD stress in the embodiment of the application provides a means for predicting the gate oxide breakdown voltage of the ESD-protected device, which can solve the problem of lack of predictability of the gate oxide breakdown voltage of the test device and provide a new perspective for ESD protection of the device.

[0039] The above only describes some exemplary embodiments of the application by way of illustration, and it is needless to say that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the application. Therefore, the above figures and description are illustrative in nature and should not be understood as limiting the scope of protection of the claims of the application.

Claims

1. A method for testing the breakdown resistance of an ultra-thin gate oxide under ESD stress, characterized in that The method comprises the following steps: S1, applying voltage to the gate and drain of the semiconductor device to be measured by using a semiconductor parameter analyzer to measure and obtain the transfer characteristic curve of the device to be measured; S2, applying an electrostatic pulse to the gate of the device to be measured by using a TLP pulse generator to perform TLP test and obtain the gate stress voltage and leakage current of the device to be measured under TLP stress; S3, after the TLP stress is applied, measuring the drain current noise under TLP stress by using a semiconductor parameter analyzer, returning to step S2 to start the next round of TLP test, wherein the amplitude of the applied electrostatic pulse is increased in each round of TLP stress application, so as to obtain the change of the gate stress voltage and leakage current of the device to be measured with the gradual increase of the pulse amplitude, and the TLP test is performed in a cycle until the leakage current changes by more than 3 orders of magnitude, which is regarded as the breakdown of the gate oxide layer of the device to be measured; S4, according to the channel carrier number fluctuation model, calculating the defect density of the gate oxide layer of the device to be measured after each round of TLP stress application according to the measured drain current noise, using the stress voltage and defect density under each round of TLP stress as a plotting point to obtain the fitting curve of the stress voltage and defect density of the device to be measured, which is used for predicting the breakdown voltage of the gate oxide layer of the same type of device.

2. The method of claim 1, wherein, The defect density of the gate oxide layer of the device to be measured is calculated as follows: where N it is the defect density near the gate oxide interface, S vfb is the flat band voltage noise, f is the frequency, W is the gate width of the device, L is the gate length of the device, C ox is the capacitance per unit area of the gate oxide, q is the elementary charge, k is the Boltzmann constant, T is the temperature, λ is the tunneling factor, and wherein, is the power spectral density of the drain current noise, I d is the drain current, g m is the transconductance.

3. The method according to claim 1 or 2, characterized in that, The fitting curve of the stress voltage and defect density of the device to be measured is as follows: wherein V DUT is the stress voltage of the device under test, and a, b, and c are parameters to be fitted.

4. The method according to claim 1 or 2, characterized in that, The method further comprises: The breakdown voltage of the gate oxide layer of the same type of device is predicted as follows: For a batch of devices of the same type, the fitting curves of the stress voltage and defect density of all devices are obtained, and the average fitting curve of the stress voltage and defect density of the devices of the same type is obtained by averaging all the fitting curves; The initial defect density measured for the same type of device is substituted into the average fitting curve to obtain the corresponding stress voltage as the initial stress voltage, and the breakdown voltage of the gate oxide layer of the same type of device is predicted as the stress voltage corresponding to the highest point of the average fitting curve minus the initial stress voltage.

5. The method according to claim 1 or 2, characterized in that, The connection between the device to be measured and the semiconductor parameter analyzer or the TLP pulse generator is switched by using a gating switch, so that the device to be measured is connected with the semiconductor parameter analyzer when measuring current, voltage and noise, and the device to be measured is connected with the TLP pulse generator when applying TLP stress.

6. The method of claim 1 or 2, wherein, The average value of the gate voltage and current in the period of 70%-90% of the measurement period of each round of TLP test is taken as a plotting point to draw the TLP current-voltage curve and the leakage current curve.

7. The method according to claim 1 or 2, characterized in that, The voltage bias of the gate and drain of the device to be measured is selected for the test of the drain current noise according to the transfer characteristic curve, wherein the selected gate voltage bias test points cover the sub-threshold region and the saturation region of the device.

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