Multi-core cascade EDT scanning test circuit and method
The multi-core cascaded EDT test architecture (SEDT) solves the problems of inconvenient wiring in multi-core chips and large circuit area overhead and fragmented test data in SSN architecture, and realizes an efficient and convenient testing process.
Patent Information
- Application Number
- CN202511481560.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-16
- Publication Date
- 2025-11-21
AI Technical Summary
Existing embedded deterministic testing (EDT) technologies are inconvenient for routing in multi-core chips and involve cumbersome testing operations. Furthermore, Mentor's Stream Scan Network (SSN) architecture suffers from problems such as large circuit area overhead, severe test data fragmentation, and cumbersome configuration operations.
A multi-core cascaded EDT test architecture (SEDT) was designed. By cascading multiple EDT compression interface modules and serial control modules, cross-core data transmission was achieved. The SEDT control signals were used to generate the enable and bypass operations of LFSR and MISR for each core, simplifying the test configuration process.
It enables convenient testing that is compatible with the timing of existing JTAG interfaces, reduces testing costs and time, lowers additional circuit area overhead, and improves testing efficiency.
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Figure CN120993173A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to integrated circuit testing technology, and in particular to the field of integrated circuit design-testability. Background Technology
[0002] Embedded Deterministic Test (EDT) uses LFSR pseudo-random sequence generation to decompress the input compressed data with a smaller bit width into a raw test vector with a larger bit width. At the same time, a mask is applied to the output test vector response to hide irrelevant bits in the test vector response, and then a signature is generated to generate a smaller bit width before output.
[0003] A single EDT unit's external scan channel behaves similarly to a normal scan chain; however, a chip often contains multiple EDTs enclosing the core under test (DUT). Multiple EDTs with the same scan channel width cannot be directly cascaded like a normal scan chain. This is because when multiple core EDTs are cascaded into a single scan channel, the compressed test vectors belonging to core A can only be decompressed by the LFSR when flowing into core A, and the test response is compressed and signed by the MISR when flowing out of core A. These compressed test vectors and responses cannot be processed by the LFSRs and MISRs of other cores when flowing through the scan channel. The key to the SEDT control circuit designed in this paper is to generate control signals that inform the LFSRs and MISRs of each core EDT when to enable data processing, when to bypass data and allow it to pass directly; and when to shift the scan chain of each core, and when to stop the shift.
[0004] Conventional testing methods involve adding routing units to the circuit to switch between different cores under test (DUTs), selecting one of multiple EDTs for testing each time. This routing-based EDT selection method is inconvenient for routing when the layout contains a large number of DUTs, and the testing procedures are cumbersome.
[0005] In 2020, Mentor released the Streaming Scan Network (SSN). This architecture strings together multiple EDT (Executable Test Deployment) compressed test units like pipes, aiming to efficiently and flexibly organize hierarchical testing of a large number of cores under test. Each EDT is coupled to an SSH (Streaming Hierarchical System) node. These SSHs are chained together to form a data pipeline. This decouples the bit width of the data pipeline from the bit width of each EDT, allowing numerous EDTs with varying bit widths to be organized using a single data pipeline with a fixed bit width. Each SSH node automatically calculates at what intervals and from which bits of the flowing data packets it should extract the test data fragments belonging to its node. Furthermore, the SSN network can be hierarchical; some SSH nodes do not connect to the EDTs of the cores under test but instead act as parent nodes for multiple SSH child nodes in the next layer. The parent nodes then distribute the test data packets they receive to their respective SSH child nodes, thus organizing a hierarchical test structure.
[0006] Examples of the shortcomings of SSN are as follows.
[0007] The format of the distributed data packets (i.e. which bits in the data packet correspond to which SSH) needs to be dynamically adjusted. In order to achieve flexible and real-time configuration, each SSH node needs to be equipped with components such as a division and remainder circuit, data packet distribution logic, a separate state machine, and an EDT control signal generation circuit. The circuit area of a single node is not lightweight.
[0008] In an SSN layered network, the terminals are individual cores under test; each core needs to be equipped with an SSH node; if there are many cores under test, the additional test circuit area overhead is significant.
[0009] If some cores under test are dynamically unloaded from the scanned network, the distribution and padding method of the test data packets transmitted across the entire network must be adjusted. Therefore, all SSH nodes must be reconfigured to match the new data packet distribution format. The configuration operation is cumbersome and prolongs the testing time.
[0010] In a hierarchical structure with nested SSH nodes, test data belonging to the same core is scattered into numerous fragmented data packets, resulting in severe fragmentation. The process of packaging test data and receiving and unpacking test responses is cumbersome and incompatible with ordinary test analysis programs.
[0011] This patented multi-core cascaded EDT test architecture can connect multiple EDT units of cores under test with the same input compressed data bit width and the scan chain within the core in series. Its features and beneficial effects are as follows.
[0012] The operation method is the same as that of a conventional IEEE 1149 scan chain with multiple cores under test (DUTs) without EDTs connected in series. From the perspective of the external test equipment, the entire system consisting of multiple cores connected in series with EDTs allows for direct input of compressed test data to each core at the scan channel inlet and direct acquisition of test response signatures to each core at the scan channel outlet. Therefore, it is timing compatible with existing JTAG interfaces, and the scan channel configuration and test data transmission are more intuitive and convenient.
[0013] Lightweight. Multiple EDTs with the same compression and signature data bit width can share a single SEDT control module; and the SEDT implementation is more streamlined, requiring only a small amount of combinational logic to generate control signals for each EDT, eliminating the need for packet transmission and reception logic, dividers, and state machines in the SSN node.
[0014] The operation of scanning channel configuration, dynamic mounting, and bypassing the core under test is intuitive and convenient. Unlike SSN, it does not require reconfiguring all nodes, does not take up extra test time, and saves test costs.
[0015] For chips with numerous cores under test, several SEDTs can be used to connect EDT units with the same compression and signature data bit width in these cores under test, directly encapsulating them into an external test interface as an independent test solution; alternatively, SEDTs can be integrated into the SSN architecture, connecting cores under test that are close in position on the layout and have the same compression and signature data bit width using SEDTs, sharing a single SSH node. This significantly reduces the number of nodes in the SSN test architecture and the total configuration time of all SSN nodes, thus lowering the test cost. Summary of the Invention
[0016] In a first aspect, the present invention provides a hardware architecture for a SEDT test circuit.
[0017] A configurable multi-core cascaded EDT scanning test architecture SEDT, characterized in that it includes:
[0018] ncore consists of n serially connected EDT compression interface modules, each EDT module wrapping a core under test;
[0019] A serial EDT control module is used to control the decompression, signature compression, bypass, and mask update operations of the above ncore EDT modules; the circuit structure includes a recording unit for storing the scan chain length of each core under test, a mask update flag register, a bypass flag register, a cross-core scan chain total length accumulation unit, a clock cycle counter, a controlled clock signal generation unit for the scan register, and an LFSR and MISR enable control signal generation unit.
[0020] The ncore EDT modules are connected in series to form a cross-core data transmission channel with a fixed bit width of wCH. The entry and exit points of the cross-core data channel are denoted as dat_in and dat_out. The circuit structure of each EDT module includes an LFSR decompression unit, a mask generation unit, and a MISR signature compression unit.
[0021] Each EDT compression interface module is numbered sequentially from 1. The ID number does not need to be fixed inside each core, but can be determined by the control signal brought out by SEDT and the physical connection order of each EDT core.
[0022] The test data fed into the test machine via dat_in includes, in sequence: compressed test vectors for ncore cores, ncore bitmask update flags indicating whether each core under test has updated its mask, and ncore bitbypass configuration flags indicating whether each core under test has been bypassed. While test data is fed into the cross-core data channel inlet dat_in, the test vector response signatures of each non-bypassed core are sent out one by one from the cross-core data channel outlet dat_out.
[0023] The aforementioned ncore EDT compression interface modules, specifically the ID-th such module, are characterized by having a circuit structure including:
[0024] Test data input / output ports ch_in and ch_out, bit width wCH;
[0025] If module ID=1, its ch_in is connected to the cross-core data channel inlet dat_in; otherwise, it is connected to the output ch_out of the (ID-1)th module. If module ID=ncore, its ch_out is connected to the cross-core data channel outlet dat_out; otherwise, it is connected to the input ch_in of the (ID+1)th module. This forms a cascaded data channel.
[0026] There are O equal-length scan chains, each with a length denoted as sc_len[ID], and its entry and exit points are denoted as sc_inlet and sc_outlet; the shift clock for the scan chain is clk_isr[ID].
[0027] An LFSR decompression unit is used to decompress the compressed test vector at the input wCH bit into wO bit test data plaintext and output it in the same clock cycle; the input of the LFSR unit is connected to ch_in; its enable terminal is en_lfsr[ID], which enables this unit when the level is high;
[0028] The MUX1 is a 2-to-1 data selector used to control the flow of test data. One of the two inputs of MUX1 is connected to the decompression data output of the LFSR unit mentioned above, and the other is connected to ch_in. The control terminal is en_lfsr[ID], which selects the output of the LFSR unit when it is high and selects ch_in when it is low. Its output terminal has a bit width wO and is connected to the entry sc_inlet of the wO scan chains mentioned above. Since the bit widths wO and wCH of the two input terminals are greater than wCH, the latter needs to be padded with zeros to wO bits when it is selected, that is, all the extra unused scan chains are filled with 0.
[0029] A mask generation unit outputs a wO-bit mask, with the enable pin set to en_mask. The mask is updated when an external circuit inputs a pulse. The output of the mask generation unit is bitwise ANDed with the output of the aforementioned wO scan chains to generate a wO-bit test vector response misr_in with the mask applied.
[0030] A MISR signature compression unit is used to compress a wO-bit test response into a wCH-bit signature; its input is misr_in, and its output is the signature of the test vector response; its enable is en_misr[ID].
[0031] The MUX2 is a 2-to-1 data selector used to control the flow of test data. One of the two inputs of MUX2 is connected to the signature output of the MISR unit mentioned above, and the other is connected to the output of the wO scan chains, sc_outlet. The control terminal is en_misr[ID]. When the level is high, the output of the MISR unit is selected. When the level is low, sc_outlet is selected and the unused fill-zero scan chains mentioned above are removed. Therefore, the effective bit width of both input terminals is wCH.
[0032] The MUX3 is a 2-to-1 data selector used to control the bypass of test data. MUX3 has two input terminals, one connected to the output terminal of the aforementioned MUX2 unit and the other connected to ch_in, both with a bit width of wCH. The control terminal is bypass[ID], which bypasses the ID-th core under test when it is high.
[0033] An output register Rout, with a bit width wCH, is used to buffer output data; its input is connected to the output of the aforementioned MUX3, and its output is the aforementioned ch_out.
[0034] During the shift_dr state of the TAP state machine as defined in IEEE 1149, the test data fed into the serial EDT control module by the test machine via dat_in includes the following:
[0035] The compressed test vectors of n cores are injected in the reverse order of the core ID numbers, that is, the compressed test vectors of the core with ID=ncore are injected first, and the test data of the core with ID=1 are injected last.
[0036] The ncore bitmask update flag is used to indicate whether each core under test should update its mask before the current test response is captured.
[0037] The ncore bit bypass configuration flag is used to indicate whether each core under test is bypassed in the next set of tests;
[0038] While test data is being fed into the cross-core data channel inlet dat_in, the test vector response signatures of each unbypassed core under test are sequentially output from the cross-core data channel outlet dat_out in reverse order of their ID numbers.
[0039] The mask and bypass configuration of this solution make full use of the time period when the compressed test data is transmitted on the scanning channel and the decompressed data stream is still moving within the ncore cores and has not yet been positioned. During this period, the mask and bypass configuration are transmitted on the scanning channel in parallel, without the need for additional configuration time, thus saving costs.
[0040] The aforementioned serial EDT control module is characterized in that its circuit structure includes:
[0041] The scan chain length recording unit stores the scan chain lengths of ncore cores under test, denoted as sc_len[1] to sc_len[ncore]. The chain length recording unit can be designed as a configuration register compatible with IEEE 1149, and the configuration value can be written by the JTAG interface. If the scan chain length of each core remains unchanged during the test, the scan chain length of each core under test can also be directly fixed into the SEDT circuit and become a constant.
[0042] The mask update flag register en_maskr and the mask update enable output en_mask, with a bit width of ncore, temporarily store the mask update flags of each core in the above test data; the latter is connected to the en_mask[ID] port of the EDT module of the core under test.
[0043] The bypass flag register bypassr and the bypass flag output bypass, with a bit width of ncore; the former temporarily stores the bypass configuration information of each core in the test data on the cross-core data channel; the latter is connected to the bypass[ID] port of the EDT module of the core under test;
[0044] The cross-core scan chain total length accumulation unit calculates the total length sc_tot of the entire cross-core scan chain in real time based on the bypass flag; it also accumulates the scan chain lengths of all test cores that were not bypassed.
[0045] ;
[0046] Remember cnt_tot=sc_tot+ID-1, cnt_shift_tot=sc_tot+ncore;
[0047] The clock cycle counter cnt_shift has a counting range from 0 to cnt_shift_tot. The increment ncore is due to the extension of the output register Rout of each EDT core by one clock cycle. The counter is reset to zero at the first rising edge of the clock after the TAP enters the shift_dr state and the shift_dr signal rises, and then begins counting the shift clock cycles. It increments by 1 at each subsequent rising edge of the shift clock until cnt_shift_tot. The counter then maintains this maximum value until it is reset to zero and restarts counting after the next rising edge of shift_dr.
[0048] The shift and capture clock signal output terminal of the scan register, clk_isr, has a bit width of ncore; its ID bit is connected to the clk_isr[ID] port of the EDT module of the core under test;
[0049] The LFSR enable control signal output terminal en_lfsr has a bit width of ncore; its ID bit is connected to the en_lfsr[ID] port of the EDT module of the core under test;
[0050] The MISR enable control signal output terminal en_misr has a bit width of ncore; its ID bit is connected to the en_misr[ID] port of the EDT module of the core under test.
[0051] The aforementioned serial EDT control module is characterized in that, for the ID-th core, if it is not bypassed, the control timing includes:
[0052] In the shift_dr state, during the period from cnt_shift count 0 to cnt_tot-1, clk_isr[ID] outputs a controlled clock signal with the same phase as the global clock signal, causing all scan registers on the scan chain to shift cycle by cycle; when cnt_shift counts to the cnt_tot cycle, all scan registers stop shifting, and clk_isr[ID] stops outputting the clock signal; in the capture_dr state, clk_isr[ID] also outputs a pulse of 1 cycle to drive the scan chain to capture the test response;
[0053] From the time the count starts from cnt_shift to cnt_tot-sc_len[ID] until the count reaches cnt_tot-1, en_lfsr[ID] is set to 1; during the remaining time period, en_lfsr[ID] is set to 0.
[0054] From the moment TAP exits the capture_dr state, it continues for sc_len[ID]-1 clock cycles, during which en_misr[ID] is set to 1; during the remaining time periods, en_misr[ID] is set to 0.
[0055] Secondly, this invention provides a testing method that matches the SEDT hardware architecture.
[0056] The SEDT-based testing method is characterized by including:
[0057] During the shift_dr state, the compressed test vector, mask update flag, and bypass flag of each core are sequentially input via dat_in;
[0058] Based on the current value of the cnt_shift counter, control the enable state of the LFSR and MISR units in each EDT module and the shift of the scan chain;
[0059] When the test vector and its response flow through the corresponding core under test, the LFSR and MISR units are enabled. The former decompresses the test vector, and the latter performs signature compression on the test response.
[0060] When the test vector and its response flow through a non-corresponding core under test, it first bypasses the core's LFSR and directly enters the core's scan chain, shifting periodically, and then bypasses the core's MISR unit, flowing out of the core from the output register Rout.
[0061] If a core is configured to bypass, its scan chain is skipped, and the test data flows directly to the next core after being tagged in the core's output register Rout.
[0062] An electronic device comprising the SEDT circuit architecture and testing method described above.
[0063] A computer-readable storage medium storing program instructions for implementing the above-described method. Attached Figure Description
[0064] Figure 1 This is a schematic diagram of the SSN+SEDT test architecture.
[0065] Figure 2 It is the overall circuit structure of SEDT.
[0066] Figure 3 It is the EDT circuit structure of each core under test.
[0067] Figure 4 This is a simulation timing diagram for SEDT tests and cases. Detailed Implementation
[0068] Case 1, SSN+SEDT Test Architecture
[0069] refer to Figure 1The data channel bandwidth of nodes SSH-1 to SSH-3 is wCH. The data port widths of these nodes can be different, as shown in the diagram as w1 to w3. An additional SSH link extends from node SSH-1, mounting cores under test (core1A, core1B, etc.), forming an SSN layered structure. The EDT data port widths (w1A, w1B, etc.) of cores core1A, core1B, etc., can be different. SSH-2 directly mounts core under test (core2). SSH-3 connects to SEDT, which organizes and connects multiple cores under test (core3A to core3N) with the same data port width (all w3).
[0070] Case 2: SEDT Test Example and Circuit Simulation
[0071] SEDT Overall Circuit Structure Reference Figure 2 Reference for the EDT circuit structure of each core under test Figure 3 .
[0072] In this example, there are four cores under test, core1 to core4, numbered 1 to 4 respectively. The compressed test vector input of core 1 (i.e., the core with ID=1, the same below) is the entry point of the entire cross-core data channel, dat_in, and the test response signature output of core 4 is the exit point of the entire cross-core data channel, dat_out. The scan chain lengths of cores 1 to 4 are 5, 7, 6, and 6 respectively. The circuit structures under test of cores 3 and 4 are the same, so the responses obtained after the same test vector input should be the same. The number of parallel scan chains wO for each core is 4; the data input / output port width wCH of each core's EDT is 2 bits; each core's LFSR decompresses the 2 bits of compressed data belonging to its own core into WO=4 bits, and sends them to the entry points sc_inlet of the 4 parallel scan chains of the above cores respectively.
[0073] To clearly display the data flow within each core, the compressed test vectors belonging to each core all begin with 2'b11 and end with 2'b01, with all zeros in between. This facilitates the identification and location of this data segment. For example, if the scan chain length of core 1 is 5, the compressed test vector sent will require 5 clock cycles to transmit, and will be transmitted sequentially as 2'b11_2'b00_2'b00_2'b00_2'b01; the compressed test vectors belonging to other cores follow the same pattern.
[0074] Simulation Timing Reference Figure 4 This is a timing diagram showing the control signals and data flow of each core's EDT and SEDT during the test data input period of cyc=1. From the completion of the previous round (cyc=0) test data input until the start of the next round (cyc=2) test data input, the response of the test vector in the cyc=1 round begins to be output.
[0075] Referring to this sequence diagram and its markings, the details are explained below.
[0076] P1: TAP enters the capture_dr state, and each core scan register QU (see the corresponding signals for each core in the figure) captures the response of the previous test vector when cyc=0.
[0077] R1.1~R1.4: After the capture_dr state, the en_misr control signal of each core is set to 1. The test responses of the wO=4 scan registers at the scan chain exit sc_outlet position are masked and sent to the misr input misr_in; the misr unit immediately outputs the wCH=2-bit compressed signature misr_out corresponding to these 4-bit test responses. In the subsequent shift_dr state, the scan registers begin to shift periodically, successively sending out the wO=4-bit signature data of the remaining rows in the scan chain.
[0078] R2.1~R2.4: Following R1.1~R1.4, on each rising edge of the clock in shift_dr state, the core test response is shifted out from the output ch_out.
[0079] R3.1~R3.4: Following R2.1~R2.4, the test response path of each core is connected downstream of each core until it flows out from the last core 4's dat_out and is received by the test machine. The timing of receiving the test response at the dat_out output is marked here. The number of clock cycles for the test response of core ID is equal to the length of the core's scan chain sc_len[ID]. The test response of core 4, which is closest to this output, flows out first, followed by cores 3, 2, and 1 in sequence. There is an extra cycle of blank space between the test response data segments of each core; this is due to the output register at the end of each core's EDT being extended by one clock cycle.
[0080] C1.4~C1.1 and M1, B1: After TAP enters the shift_dr state, the test data for the current cyc=1 round is fed in from the cross-core data channel entry dat_in, with wCH=2 bits input per clock cycle. In chronological order, the following are fed in sequentially: compressed test data C1.4 for core 4, C1.3 for core 3, C1.2 for core 2, C1.1 for core 1, the mask update flag M1 for each core, and the bypass flag B1 for each core. For ease of observation and location, C1.4~C1.1 all begin with 2'b11 and end with 2'b01. With a total of ncore=4 cores and a data channel bit width wCH=2, M1 and B1 each require [ncore / wCH]=2 clock cycles, where [a / b] is an integer division; if not divisible, it is rounded up. After the compressed test data is input, M1=4'b1101 is input in two cycles. The least significant and most significant bits correspond to the mask update flags for core 1 and core 4, respectively, and so on. A high level indicates that the currently input test vector requires a mask update; here, the masks for cores 1, 3, and 4 need to be updated. Subsequently, B1=4'b0011 is input in two cycles. The least significant and most significant bits correspond to the bypass flags for cores 1 and 4, respectively, and so on. A high level indicates that the next round of input test vectors does not include this core, and this core's scan chain needs to be bypassed in the next round of testing with cyc=2. Here, cores 1 and 2 need to be bypassed.
[0081] S1.1~S1.4: After TAP enters the shift_dr state, the counter cnt_shift starts counting. The scan register shift clock signal clk_isr[ID] of the ID core (ID=1~4) outputs a square wave during the period when the cnt_shift count value is between 0 and sc_tot+ID-1, lasting for a total of sc_tot+ID clock cycles.
[0082] S2.1~S2.4: Following S1.1~S1.4, the scan register QU of each core is shifted clockwise under the control of the clk_isr clock.
[0083] C2.1~C2.4: Following S2.1~S2.4, when the compressed test vector of the ID core with cyc=1 in this round arrives at the data input terminal ch_in of the core's EDT, the core's en_lfsr[ID] is set. As seen in the simulation diagram, within the sc_len[ID] clock cycles during which en_lfsr[ID] is high, the core's compressed test vector is fed into ch_in in batches; that is, the high-level phase of en_lfsr[ID] coincides precisely with a compressed test vector in ch_in that starts with 2'b11 and ends with 2'b01. The wCH=2-bit compressed data input in each clock cycle is immediately decompressed by the LFSR into wO=4-bit lfsr_out in the current cycle, and after passing through the MUX1 selector switch, arrives at the scan chain entry sc_inlet. Subsequently, it is shifted and fed into the core's scan chain cycle by cycle.
[0084] C3.1~C3.4: Following C2.1~C2.4, the test data filled in the QU of each core scan register is the data decompressed on lfsr_out during C2.1~C2.4. For example, lfsr_out of core 1 is divided into sc_len[1]=5 cycles, each time giving wO=4 bits of decompressed data (1001_1000_0100_0010_0000), which is being filled into the QU of the scan chain wO=4 at position C3.1 in the simulation diagram.
[0085] M2 and B2: Following M1 and B1, the bypass and mask configuration information sent at the cross-core data channel entry is temporarily stored in the en_maskr and bypass registers within the SEDT. Because en_maskr is 4'b1011, the masks for cores 1, 2, and 4 need to be updated when applying a mask to the current round of test vector responses. Because bypassr is 4'b0011, cores 1 and 2 need to be bypassed for the next round of test vectors with cyc=2.
[0086] B3.0: Following B2, the shift_dr state with cyc=1 ends in this round. At the falling edge of shift_dr, because cores 1 and 2 need to be bypassed, the total length of the cross-core scan chain sc_tot changes. The SEDT accumulation unit automatically calculates sc_tot after removing the bypassed cores and updates it. The upper limit of the cnt_shift counter, cnt_shift_tot=sc_tot+ncore-1, is also updated accordingly.
[0087] B3.1~B3.4: Following B2, the bypass flag input of the EDT module of cores 1 and 2 is set to 1, and the next round of cyc=2 stage is bypassed; the bypass flag input of cores 3 and 4 is 0, and the cyc=2 stage is not bypassed.
[0088] M3.1~M3.4, following M2, update the mask for cores 1, 3, and 4, while the mask for core 2 remains unchanged.
[0089] P2: Following M3.1~M3.4, the test vectors of each core are injected in the cyc=1 stage. The response is bitwise ANDed with the updated mask in the capture_dr state marked here. The value of the QU scan register of each core is updated to the response of the test vector after the mask is applied.
[0090] B4.1~B4.4: Following B3.1~B3.4, in the next round of cyc=2 phase, the EDT of cores 1 and 2 is disabled. The clk_isr of these cores' EDT modules has no square wave, the scan chain is not shifted, and the test vectors injected into the scan chain during the cyc=1 phase do not receive capture_dr capture responses. Only in a later test round, when the bypass flag of these two cores is configured to 0 and they are reattached to the scan chain, do they receive capture_dr capture responses, at which point these responses flow out along the cross-core data channel. Cores 3 and 4 are attached to the cross-core scan channel, and the test data of the cyc=2 round is injected into these cores. Simultaneously, the test vector response signatures of cores 3 and 4 from the cyc=1 round are shifted until they flow out from dat_out.
[0091] It should be noted that the above description is only one embodiment of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
Claims
1. A configurable multi-core cascaded EDT scanning test architecture SEDT, characterized in that, include: ncore consists of n serially connected EDT compression interface modules, each EDT module wrapping a core under test; A serial EDT control module is used to control the decompression, signature compression, bypass, and mask update operations of the above ncore EDT modules; the circuit structure includes a recording unit for storing the scan chain length of each core under test, a mask update flag register, a bypass flag register, a cross-core scan chain total length accumulation unit, a clock cycle counter, a controlled clock signal generation unit for the scan register, and an LFSR and MISR enable control signal generation unit. The ncore EDT modules are connected in series to form a cross-core data transmission channel with a fixed bit width of wCH. The entry and exit points of the cross-core data channel are denoted as dat_in and dat_out. The circuit structure of each EDT module includes an LFSR decompression unit, a mask generation unit, and a MISR signature compression unit. Each EDT compression interface module is numbered sequentially from 1. The ID number does not need to be fixed inside each core, but can be determined by the control signal brought out by SEDT and the physical connection order of each EDT core. The test data fed into the test machine via dat_in includes, in sequence: compressed test vectors for ncore cores, ncore bitmask update flags to indicate whether each core under test updates its mask, and ncore bitbypass configuration flags to indicate whether each core under test is bypassed. While test data is being fed into the cross-core data channel inlet dat_in, the test vector response signatures of each non-bypass core are flowing out one by one from the cross-core data channel outlet dat_out.
2. The n-core EDT compression interface module as described in claim 1, wherein the ID-th such module is characterized in that its circuit structure includes: Test data input / output ports ch_in and ch_out, bit width wCH; If module ID=1, its ch_in is connected to the cross-core data channel inlet dat_in; otherwise, it is connected to the output ch_out of the (ID-1)th module. If module ID=ncore, its ch_out is connected to the cross-core data channel outlet dat_out; otherwise, it is connected to the input ch_in of the (ID+1)th module. This forms a cascaded data channel. There are O equal-length scan chains, each with a length denoted as sc_len[ID], and its entry and exit points are denoted as sc_inlet and sc_outlet; the shift clock for the scan chain is clk_isr[ID]. An LFSR decompression unit is used to decompress the compressed test vector at the input wCH bit into wO bit test data plaintext and output it in the same clock cycle; the input of the LFSR unit is connected to ch_in; its enable terminal is en_lfsr[ID], which enables this unit when the level is high; The MUX1 is a 2-to-1 data selector used to control the flow of test data. One of the two inputs of MUX1 is connected to the decompression data output of the LFSR unit mentioned above, and the other is connected to ch_in. The control terminal is en_lfsr[ID], which selects the output of the LFSR unit when it is high and selects ch_in when it is low. Its output terminal has a bit width wO and is connected to the entry sc_inlet of the wO scan chains mentioned above. Since the bit widths wO and wCH of the two input terminals are greater than wCH, the latter needs to be padded with zeros to wO bits when it is selected, that is, all the extra unused scan chains are filled with 0. A mask generation unit outputs a wO-bit mask, with the enable pin set to en_mask. The mask is updated when an external circuit inputs a pulse. The output of the mask generation unit is bitwise ANDed with the output of the aforementioned wO scan chains to generate a wO-bit test vector response misr_in with the mask applied. A MISR signature compression unit is used to compress a wO-bit test response into a wCH-bit signature; its input is misr_in, and its output is the signature of the test vector response; its enable is en_misr[ID]. The MUX2 is a 2-to-1 data selector used to control the flow of test data. One of the two inputs of MUX2 is connected to the signature output of the MISR unit mentioned above, and the other is connected to the output of the wO scan chains, sc_outlet. The control terminal is en_misr[ID]. When the level is high, the output of the MISR unit is selected. When the level is low, sc_outlet is selected and the unused fill-zero scan chains mentioned above are removed. Therefore, the effective bit width of both input terminals is wCH. The MUX3 is a 2-to-1 data selector used to control the bypass of test data. MUX3 has two input terminals, one connected to the output terminal of the aforementioned MUX2 unit and the other connected to ch_in, both with a bit width of wCH. The control terminal is bypass[ID], which bypasses the ID-th core under test when it is high. An output register Rout, with a bit width wCH, is used to buffer output data; its input is connected to the output of the aforementioned MUX3, and its output is the aforementioned ch_out.
3. The serial EDT control module as described in claim 1, wherein during the shift_dr state of the TAP state machine as defined by IEEE 1149, the test data fed into it by the test machine via dat_in sequentially includes: The compressed test vectors of n cores are injected in the reverse order of the core ID numbers, that is, the compressed test vectors of the core with ID=ncore are injected first, and the test data of the core with ID=1 are injected last. The ncore bitmask update flag is used to indicate whether each core under test should update its mask before the current test response is captured. The ncore bit bypass configuration flag is used to indicate whether each core under test is bypassed in the next set of tests; While test data is being fed into the cross-core data channel inlet dat_in, the test vector response signatures of each unbypassed core under test are sequentially output from the cross-core data channel outlet dat_out in reverse order of their ID numbers. The mask and bypass configuration of this solution make full use of the time period when the compressed test data is transmitted on the scanning channel and the decompressed data stream is still moving within the ncore cores and has not yet been positioned. During this period, the mask and bypass configuration are transmitted on the scanning channel in parallel, without the need for additional configuration time, thus saving costs.
4. The serial EDT control module as described in claim 1, characterized in that, The circuit structure includes: The scan chain length recording unit stores the scan chain lengths of ncore cores under test, denoted as sc_len[1] to sc_len[ncore]. The chain length recording unit can be designed as a configuration register compatible with IEEE 1149, and the configuration value can be written by the JTAG interface. If the scan chain length of each core remains unchanged during the test, the scan chain length of each core under test can also be directly fixed into the SEDT circuit and become a constant. The mask update flag register en_maskr and the mask update enable output en_mask, with a bit width of ncore, temporarily store the mask update flags of each core in the above test data; the latter is connected to the en_mask[ID] port of the EDT module of the core under test. The bypass flag register bypassr and the bypass flag output bypass, with a bit width of ncore; the former temporarily stores the bypass configuration information of each core in the test data on the cross-core data channel; the latter is connected to the bypass[ID] port of the EDT module of the core under test; The cross-core scan chain total length accumulation unit calculates the total length sc_tot of the entire cross-core scan chain in real time based on the bypass flag; it also accumulates the scan chain lengths of all test cores that were not bypassed. ； Remember cnt_tot=sc_tot+ID-1, cnt_shift_tot=sc_tot+ncore; The clock cycle counter cnt_shift has a counting range from 0 to cnt_shift_tot. The increment ncore is due to the extension of the output register Rout of each EDT core by one clock cycle. The counter is reset to zero at the first rising edge of the clock after the TAP enters the shift_dr state and the shift_dr signal rises, and then begins counting the shift clock cycles. It increments by 1 at each subsequent rising edge of the shift clock until cnt_shift_tot. The counter then maintains this maximum value until it is reset to zero and restarts counting after the next rising edge of shift_dr. The shift and capture clock signal output terminal of the scan register, clk_isr, has a bit width of ncore; its ID bit is connected to the clk_isr[ID] port of the EDT module of the core under test; The LFSR enable control signal output terminal en_lfsr has a bit width of ncore; its ID bit is connected to the en_lfsr[ID] port of the EDT module of the core under test; The MISR enable control signal output terminal en_misr has a bit width of ncore; its ID bit is connected to the en_misr[ID] port of the EDT module of the core under test.
5. The serial EDT control module as described in claim 1, characterized in that, For the ID-th core, if it is not bypassed, the control timing includes: In the shift_dr state, during the period from cnt_shift count 0 to cnt_tot-1, clk_isr[ID] outputs a controlled clock signal with the same phase as the global clock signal, causing all scan registers on the scan chain to shift cycle by cycle; when cnt_shift counts to the cnt_tot cycle, all scan registers stop shifting, and clk_isr[ID] stops outputting the clock signal; in the capture_dr state, clk_isr[ID] also outputs a pulse of 1 cycle to drive the scan chain to capture the test response; From the time the count starts from cnt_shift to cnt_tot-sc_len[ID] until the count reaches cnt_tot-1, en_lfsr[ID] is set to 1; during the remaining time period, en_lfsr[ID] is set to 0. From the moment TAP exits the capture_dr state, it continues for sc_len[ID]-1 clock cycles, during which en_misr[ID] is set to 1; during the remaining time periods, en_misr[ID] is set to 0.
6. A testing method based on the SEDT architecture of claim 1, characterized in that, include: During the shift_dr state, the compressed test vector, mask update flag, and bypass flag of each core are sequentially input via dat_in; Based on the current value of the cnt_shift counter, control the enable state of the LFSR and MISR units in each EDT module and the shift of the scan chain; When the test vector and its response flow through the corresponding core under test, the LFSR and MISR units are enabled. The former decompresses the test vector, and the latter performs signature compression on the test response. When the test vector and its response flow through a non-corresponding core under test, it first bypasses the core's LFSR and directly enters the core's scan chain, shifting periodically, and then bypasses the core's MISR unit, flowing out of the core from the output register Rout. If a core is configured to bypass, its scan chain is skipped, and the test data flows directly to the next core after being tagged in the core's output register Rout.
7. An electronic device comprising the SEDT circuit architecture and test method as described in any one of claims 1 to 6.
8. A computer-readable storage medium storing program instructions for implementing the method of claim 6.