Rectangular plane phased-array antenna rapid phase matching resolving system and method based on FPGA

Abstract

The invention discloses a rectangular plane phased-array antenna rapid phase matching resolving system and method based on an FPGA, and relates to the technical field of phased-array antenna beam pointing control. According to the scheme, phase complementation operation in beam pointing control is converted into normalization processing of a numerical value 1, and a row and column step-by-step computing architecture is adopted; and the FPGA resource consumption is greatly reduced while the phase resolving precision is ensured. Input azimuth angle and pitch angle information is converted into corresponding trigonometric function values by combining a look-up table method with pre-stored trigonometric function values, phase difference information between adjacent array elements is obtained after the trigonometric function values are multiplied by corresponding frequency points and array element spacing information, a row / column phase matrix is generated through accumulation operation, combination operation is carried out, and the array element spacing information is obtained. And finally, phase matching calculation of more than 1024 array elements is completed at a microsecond level.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of phased array antenna beam pointing control, and particularly relates to an efficient phase matching solution based on FPGA, which is suitable for large-scale rectangular planar phased array antennas in high dynamic application scenarios such as low-orbit satellite communication and dynamic satellite communication. BACKGROUND

[0002] With the development of low-orbit satellite communication and 5G / 6G networks, terminals have put forward requirements for phased array antennas in terms of miniaturization, low cost and rapid beam switching (microsecond level). Traditional phase matching solutions based on digital signal processing (DSP) or software face problems such as large amount of calculation, high delay and large resource occupation in large-scale arrays (such as more than 1024 elements), and are difficult to meet the requirements of dynamic tracking satellites.

[0003] In the prior art, phase matching solution needs to calculate the phase difference of each element separately and perform a remainder operation, resulting in a large number of multipliers and storage units consumed in FPGA implementation. For example, the traditional scheme may need N multipliers (N is the number of elements), and the resource occupation of the trigonometric function table increases linearly with the array size. SUMMARY

[0004] In view of the above technical problems, the purpose of the present application is to provide an efficient phase matching solution based on FPGA, which significantly reduces hardware resource consumption while ensuring microsecond-level calculation speed, and is suitable for large-scale rectangular planar phased array antenna systems with low cost and low power consumption.

[0005] To achieve the above-mentioned purpose of the application, the technical scheme adopted by the present application is as follows: a fast phase matching solution device for a rectangular planar phased array antenna based on FPGA, comprising: an input module: receiving a beam pointing elevation angle and an azimuth angle ; a trigonometric function table module: adopting a symmetry compression storage strategy, only storing the sine and cosine values within , and extending to the full period through address mapping, for quickly obtaining the trigonometric function parameters required for phase calculation; a row-column decomposition calculation module: for decomposing a two-dimensional rectangular planar phased array into a one-dimensional linear array in the x-axis and y-axis directions, and calculating the phase difference between adjacent elements according to the elevation angle and azimuth angle of the beam pointing; (1) the phase difference between adjacent elements in the y-axis direction is: (2) wherein , is adjacent element spacing, is transmission signal carrier wavelength.

[0006] Phase accumulation module: used for accumulating adjacent phase difference obtained by row and column decomposition, generating row / column phase vector, and storing; accumulation operation is represented as multiplication operation on formula; phase difference between the mth element in row vector and 0 coordinate element is represented as: (3) Phase difference between the nth element in column vector and 0 coordinate element is represented as: (4) Element phase calculation module: according to row / column phase vector obtained by phase accumulation module, combination operation is carried out according to formula (5), and phase value of each element in array is obtained; (5) Modulo module: converting traditional modulo operation into normalized value modulo operation on value 1; in order to simplify calculation time and resource consumption of FPGA.

[0007] Traditional phase calculation formula is: (6) According to the essence of modulo operation, in the process of calculating phase and the module approximation, the formula is rewritten as: (7) Quantization output module: according to bit width of digital phase shifter, phase after modulo operation is quantized to generate element phase control code.

[0008] As a preferred mode of the application, the row and column decomposition calculation module further comprises parallel pipeline architecture, which respectively and independently processes phase difference accumulation operation in x-axis and y-axis directions, and stores intermediate results through double-port BRAM to support subsequent element phase synthesis.

[0009] As a preferred mode of the application, the modulo module specifically realizes the process, which converts absolute phase value in formula into normalized coefficient, and determines final phase value by calculating remainder of 1.

[0010] As a preferred mode of the application, the trigonometric function lookup table module adopts 16bit quantization precision, in which high bit is sign bit, and realizes parallel solution of multiple element phases through timing control.

[0011] The application further provides a solution method based on the above-mentioned fast phase matching solution device, comprising the following steps: Step one, the input triangle function lookup table module obtains the normalized triangle function value 、 Input the triangle function lookup table module to obtain the normalized triangle function value 、 And ; Step two, calculate the row and column direction normalization coefficients according to formula (10) and formula (11): (10) (11) Wherein 、 The spacing between each array element in the row and column direction, c is the speed of light, The carrier frequency is f; Step three, according to the results of steps one and two, calculate the phase difference between adjacent elements in the row / column direction through formula (12) and formula (13): (12) (13) Step four, according to the results of step three, and according to formula (14) and formula (15), generate the basic phase sequence through the row / column accumulator, and store it; (14) (15) Step five, according to the results of step four, and according to formula (16), the phase matching phase synthesis is carried out for each array element (m, n); (16) Step six, take 1 as the remainder of the synthesized phase to obtain the phase in 0~2pi; Step seven, according to the quantization accuracy of the phase shifter, the phase is quantized to obtain the phase shifter control code.

[0012] The application also provides a low-orbit satellite communication terminal antenna system, which comprises the FPGA-based rectangular planar phased array antenna fast phase matching solution device described above, and is configured to meet the technical requirements of beam pointing switching period ≤100ms and gain ≥25dBi.

[0013] Compared with the prior art, the technical scheme provided by the application has the following technical effects: 1、The phase matching solution system provided by the application supports completing single phase matching solution time ≤20us under the condition of clock frequency ≥100MHz, and adapts to rectangular planar phased array arrays with element number ≥1024.

[0014] 2、The application realizes hardware optimization of the phase matching solution system, utilizes the properties of triangle functions, and The three-valued function value of the phase calculation is mapped to Between them, 87.5% of storage resources are saved.

[0015] 3、The phase calculation is divided into table lookup, multiplication, accumulation, array element synthesis, remainder calculation, quantization and other stages, so that the throughput rate is improved.

[0016] 4、The application is particularly suitable for the fast beam pointing switching requirement of a low-orbit satellite communication terminal, and reduces the hardware cost while meeting the high real-time requirement. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 It is a FPGA-based rectangular planar phased array antenna phase distribution system block diagram in the embodiment.

[0018] Figure 2 It is a FPGA-based rectangular planar phased array antenna phase distribution method flowchart in the embodiment. DETAILED DESCRIPTION

[0019] In order to better understand the application, the following will be described in detail in conjunction with the drawings and specific embodiments.

[0020] As shown in Figure 1 , a FPGA-based rectangular planar phased array antenna phase distribution system block diagram, specifically comprising: Input module: receiving beam pointing elevation angle And azimuth angle ; Trigonometric function table lookup module: adopting a symmetric compression storage strategy, only storing The sine and cosine values in the range of 0-180°, and expanding to the full period through address mapping, used for quickly obtaining the three-valued function parameters required for phase calculation; Row and column decomposition calculation module: used for decomposing the two-dimensional rectangular planar phased array array into one-dimensional linear arrays in x-axis and y-axis directions, and calculating the phase difference between adjacent array elements according to the elevation angle and azimuth angle of the beam pointing; The phase difference between adjacent array elements in the x-axis direction is: (1) The phase difference between adjacent array elements in the y-axis direction is: (2) Wherein , is the distance between adjacent array elements, is the wavelength of the transmitted signal carrier.

[0021] Phase accumulation module: used for accumulating the adjacent phase difference obtained by row-column decomposition, generating row / column phase vector, and storing; the accumulation operation is represented as multiplication operation on formula; the phase difference between the mth element of row vector and 0 coordinate element is represented as: (3) The phase difference between the nth element of column vector and 0 coordinate element is represented as: (4) Array element phase calculation module: according to the row / column phase vector obtained by the phase accumulation module, the combination operation is carried out according to formula (5), and the phase value of each element in the array is obtained; (5) Modulo module: the traditional modulo operation is converted into the modulo operation of the normalized value of the value 1; in order to simplify the calculation time and resource consumption of FPGA.

[0022] The traditional calculation phase formula is: (6) According to the essence of modulo operation, the formula in the process of calculating phase is changed to: and the module for subsequent modulo operation is removed. Quantization output module: according to the bit width of digital phase shifter, the phase after modulo operation is quantized to generate array element phase control code.

[0023] As shown in Figure 2 , a rectangular plane phased array antenna phase distribution solution method based on FPGA flow chart, specifically comprising the following steps: Step one, input , to the trigonometric function lookup table module to obtain normalized trigonometric function values , and ; Step two, calculate the row-column direction normalization coefficient according to formula (10) and formula (11): (10) (11) Wherein , is the distance between each element in row-column direction, c is the speed of light, is the carrier frequency; Step three, according to the results of steps one and two, the phase difference between adjacent elements in the row / column direction is calculated by formula (12) and formula (13): (12) (13) Step four, according to the results of step three, the basic phase sequence is generated by the row / column accumulator according to formula (14) and formula (15), and is stored; (14) (15) Step five, according to the results of step four, the phase matching of each element (m, n) is synthesized according to formula (16); (16) Step six, the integrated phase is taken modulo 1 to obtain the phase in 0-2pi; Step seven, according to the quantization accuracy of the phase shifter, the phase is quantized to obtain the phase shifter control code.

[0024] The actual test data show that when the Xilinx Zynq-7045 chip is used, only 4 DSP multipliers and 70.5 BRAM resources are occupied, the resource amount is small, and the method can be transplanted to a low-end FPGA (such as an Artix series).

[0025] Speed: about 12 .

[0026] Extensibility: the array size can be expanded by adjusting the accumulator bit width, and the method can be extended to other polygonal arrays by discarding the calculated values of specific elements.

[0027] The above is only a preferred specific embodiment of the present application, but the protection scope of the present application is not limited thereto, any changes or replacements that can be easily thought of by those skilled in the art within the technical range disclosed by the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A fast phase matching solution system for a rectangular planar phased array antenna based on FPGA, characterized in that, include: Input module: Receive beam pointing elevation angle and azimuth ; Trigonometric function lookup table module: Employs a symmetric compression storage strategy, storing only... The range of sine and cosine values ​​is extended to the entire period through address mapping, which is used to quickly obtain the three solution function parameters required for phase calculation; The row and column decomposition calculation module is used to decompose a two-dimensional rectangular planar phased array into a one-dimensional linear array along the x-axis and y-axis, and calculate the phase difference between adjacent array elements based on the elevation and azimuth angles of the beam pointing. Phase accumulation module: used to accumulate the adjacent phase differences obtained from row and column decomposition, generate row / column phase vectors, and store them; Array element phase calculation module: Combines the row / column phase vectors obtained from the phase accumulation module to obtain the phase value of each array element in the array; The modulo module transforms the traditional modulo operation into a modulo operation on the normalized value of 1. Based on the nature of the remainder, in the process of calculating the phase... Modulus with subsequent modulo operations Go and rewrite the formula; Quantization output module: Based on the bit width of the digital phase shifter, the phase after the remainder is quantized to generate the array element phase control code.

2. The FPGA-based fast phase matching solution system for rectangular planar phased array antennas according to claim 1, characterized in that, In the row and column decomposition calculation module, the phase difference between adjacent array elements in the x-axis direction is: （1）； The phase difference between adjacent array elements along the y-axis is: （2）； in , The distance between adjacent array elements. The wavelength of the transmission signal carrier.

3. The FPGA-based fast phase matching solution system for rectangular planar phased array antennas according to claim 2, characterized in that, In the phase accumulation module, the accumulation operation is expressed as a multiplication operation in the formula; the phase difference between the m-th element and the 0-coordinate element in the row vector is expressed as: （3）； The phase difference between the nth element and the 0-coordinate element in the column vector is expressed as: （4）。 4. The FPGA-based fast phase matching solution system for rectangular planar phased array antennas according to claim 3, characterized in that, In the array element phase calculation module, a combination operation is performed according to formula (5): （5）。 5. The FPGA-based fast phase matching solution system for rectangular planar phased array antennas according to claim 4, characterized in that, In the remainder module, the traditional formula for calculating the phase is: （6）； The formula can be rewritten as follows: （7）。 6. The FPGA-based fast phase matching solution system for rectangular planar phased array antennas according to claim 2, characterized in that, The row and column decomposition calculation module also includes a parallel pipeline architecture, which independently processes the phase difference accumulation operation in the x-axis and y-axis directions, and stores intermediate results through a dual-port BRAM to support subsequent array element phase synthesis.

7. The FPGA-based fast phase matching solution system for rectangular planar phased array antennas according to claim 5, characterized in that, The specific implementation process of the remainder module includes: converting the absolute phase value in the formula into a normalized coefficient, and determining the final phase value by calculating the remainder of the logarithm 1.

8. The FPGA-based fast phase matching solution system for rectangular planar phased array antennas according to claim 1, characterized in that: The trigonometric function lookup table module uses 16-bit quantization precision, with the high-order bits being the sign bits, and implements parallel phase calculation of multiple array elements through timing control.

9. A solution method based on the rapid phasing calculation system according to any one of claims 1-8, characterized in that, Includes the following steps: Step 1: , Input the trigonometric function lookup table module to obtain normalized trigonometric function values , and ; Step 2: Calculate the row and column direction normalization coefficients according to formulas (10) and (11): （10）； （11）； in , The distance between array elements in the row and column directions is denoted by c, where c is the speed of light. For carrier frequency; Step 3: Based on the results of Steps 1 and 2, calculate the phase difference between adjacent array elements in the row / column direction using formulas (12) and (13): （12）； （13）； Step 4: Based on the results of Step 3, generate the basic phase sequence using the row / column accumulator according to formulas (14) and (15), and store it; （14）； （15）； Step 5: Based on the results of Step 4, perform phase coordination and synthesis on each array element (m,n) according to formula (16); （16）； Step 6: Take the remainder of the synthesized phase with respect to 1 to obtain the phase within the range of 0 to 2π; Step 7: Quantize the phase according to the quantization accuracy of the phase shifter to obtain the phase shifter control code.

10. A low-orbit satellite communication terminal antenna system, characterized in that: The system includes the FPGA-based fast phase matching calculation system for rectangular planar phased array antennas as described in any one of claims 1-8, and is configured to meet the technical requirements of beam pointing switching period ≤100ms and gain ≥25dBi.

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