FPGA-based rectangular planar phased array antenna fast phase matching solution system and method

Abstract

The application discloses a kind of fast phase matching solution systems and methods of rectangular plane phased array antenna based on FPGA, it is related to phased array antenna beam pointing control technical field, this scheme is by the phase remainder operation in beam pointing control conversion is normalized to log value 1 processing, and using row-column step-by-step calculation architecture, while guaranteeing the precision of phase solution, it is greatly reduced FPGA resource consumption.Utilize look-up table method to realize the azimuth and elevation angle information conversion corresponding trigonometric function value by pre-storing trigonometric function value, then it is multiplied after corresponding frequency point and array element spacing information, and the phase difference information between adjacent array elements is obtained, by accumulation operation, generate row / column phase matrix and then carry out combination operation, finally more than 1024 array elements are completed in microsecond level Phase matching solution.

Description

Technical Field

[0001] This invention relates to the field of phased array antenna beam pointing control technology, and in particular to an efficient phase matching solution based on FPGA, which is suitable for large-scale rectangular planar phased array antennas in high dynamic application scenarios such as low-orbit satellite communication and mobile communication. Background Technology

[0002] With the development of low-Earth orbit satellite communication and 5G / 6G networks, terminals are demanding miniaturization, low cost, and fast beam switching (microsecond level) from phased array antennas. Traditional phase matching calculation methods based on digital signal processing (DSP) or software face problems such as large computational load, high latency, and large resource consumption in large-scale arrays (such as those with more than 1024 elements), making it difficult to meet the requirements of dynamic satellite tracking.

[0003] In existing technologies, phase matching calculations require calculating the phase difference and performing modulo operations for each array element individually, resulting in a large number of multipliers and memory units being consumed during FPGA implementation. For example, traditional solutions may require N multipliers (N being the number of array elements), and the resource consumption for trigonometric function lookup tables increases linearly with the array size. Summary of the Invention

[0004] To address the aforementioned technical problems, the purpose of this invention is to provide an efficient phase matching solution system and algorithm based on FPGA, which significantly reduces hardware resource consumption while ensuring microsecond-level calculation speed, and is suitable for low-cost, low-power large-scale rectangular planar phased array antenna systems.

[0005] To achieve the above-mentioned objectives, the technical solution adopted by this invention is: a fast phase matching calculation device for a rectangular planar phased array antenna based on FPGA, comprising:

[0006] Input module: Receive beam pointing elevation angle and azimuth ;

[0007] Trigonometric function lookup table module: Employs a symmetric compression storage strategy, storing only... The sine and cosine values ​​within the range are obtained and extended to the entire cycle through address mapping, which is used to quickly obtain the trigonometric function parameters required for phase calculation;

[0008] The row and column decomposition calculation module is used to decompose a two-dimensional rectangular planar phased array into a one-dimensional linear array along the x-axis and y-axis, and calculate the phase difference between adjacent array elements based on the elevation and azimuth angles of the beam pointing.

[0009] The phase difference between adjacent array elements in the x-axis direction is:

[0010] (1)

[0011] The phase difference between adjacent array elements along the y-axis is:

[0012] (2)

[0013] in , The distance between adjacent array elements. The wavelength of the transmission signal carrier.

[0014] Phase accumulation module: Used to accumulate the adjacent phase differences obtained from row and column decomposition, generate row / column phase vectors, and store them; the accumulation operation is expressed as a multiplication operation in the formula; the phase difference between the m-th element and the 0-coordinate element in the row vector is expressed as:

[0015] (3)

[0016] The phase difference between the nth element and the 0-coordinate element in the column vector is expressed as:

[0017] (4)

[0018] Array element phase calculation module: Based on the row / column phase vectors obtained by the phase accumulation module, the phase value of each array element in the array is obtained by performing a combination operation according to formula (5);

[0019] (5)

[0020] Modulo module: Converts the traditional modulo operation into a modulo operation on the normalized value of 1, thereby simplifying the computation time and resource consumption of the FPGA.

[0021] The traditional formula for calculating phase is:

[0022] (6)

[0023] Based on the nature of the remainder, in the process of calculating the phase... Modulus with subsequent modulo operations Let's rewrite the formula as follows:

[0024] (7)

[0025] Quantization output module: Based on the bit width of the digital phase shifter, the phase after the remainder is quantized to generate the array element phase control code.

[0026] As a preferred embodiment of the present invention, the row and column decomposition calculation module further includes a parallel pipeline architecture, which independently processes the phase difference accumulation operation in the x-axis and y-axis directions, and stores intermediate results through a dual-port BRAM to support subsequent array element phase synthesis.

[0027] As a preferred embodiment of the present invention, the specific implementation process of the remainder module includes: converting the absolute phase value in the formula into a normalized coefficient, and determining the final phase value by calculating the remainder after dividing by 1.

[0028] As a preferred embodiment of the present invention, the trigonometric function lookup table module adopts 16-bit quantization precision, wherein the high-order bits are the sign bits, and multi-element phase parallel calculation is achieved through timing control.

[0029] The present invention also provides a solution method based on the above-mentioned rapid phase matching solution device, comprising the following steps:

[0030] Step 1: , Input the trigonometric function lookup table module to obtain normalized trigonometric function values , and ;

[0031] Step 2: Calculate the row and column direction normalization coefficients according to formulas (10) and (11):

[0032] (10)

[0033] (11)

[0034] in , The distance between array elements in the row and column directions is denoted by c, where c is the speed of light. For carrier frequency;

[0035] Step 3: Based on the results of Steps 1 and 2, calculate the phase difference between adjacent array elements in the row / column direction using formulas (12) and (13):

[0036] (12)

[0037] (13)

[0038] Step 4: Based on the results of Step 3, generate the basic phase sequence using the row / column accumulator according to formulas (14) and (15), and store it;

[0039] (14)

[0040] (15)

[0041] Step 5: Based on the results of Step 4, perform phase coordination and synthesis on each array element (m,n) according to formula (16);

[0042] (16)

[0043] Step 6: Take the remainder of the synthesized phase with respect to 1 to obtain the phase within the range of 0 to 2π;

[0044] Step 7: Quantize the phase according to the quantization accuracy of the phase shifter to obtain the phase shifter control code.

[0045] The present invention also provides a low-orbit satellite communication terminal antenna system, including the above-mentioned FPGA-based rectangular planar phased array antenna fast phase matching calculation device, and configured to meet the technical requirements of beam pointing switching period ≤100ms and gain ≥25dBi.

[0046] Compared with the prior art, the technical solution provided by the present invention has the following technical effects:

[0047] 1. The phase matching solution system provided by the present invention supports completing a single phase matching solution in a time of ≤20μs under a clock frequency ≥100MHz, and is compatible with rectangular planar phased arrays with a number of array elements ≥1024.

[0048] 2. This invention achieves hardware optimization of the phase coordination calculation system by utilizing the properties of trigonometric functions. The trigonometric function values ​​are mapped to In between, it saves 87.5% of storage resources.

[0049] 3. This invention decomposes phase calculation into stages such as table lookup, multiplication, accumulation, array element synthesis, remainder calculation, and quantization, thereby improving throughput.

[0050] 4. This invention is particularly suitable for the rapid beam pointing switching requirements of low-orbit satellite communication terminals, meeting high real-time requirements while reducing hardware costs. Attached Figure Description

[0051] Figure 1 This is a block diagram of a rectangular planar phased array antenna phase matching solution system based on FPGA in this embodiment.

[0052] Figure 2 This is a schematic diagram of a FPGA-based method for calculating the phase matching of a rectangular planar phased array antenna in this embodiment. Detailed Implementation

[0053] To better understand this invention, a detailed description will be provided below in conjunction with the accompanying drawings and specific embodiments.

[0054] like Figure 1 The diagram shows a block diagram of a rectangular planar phased array antenna phasing solution system based on FPGA, which specifically includes:

[0055] Input module: Receive beam pointing elevation angle and azimuth ;

[0056] Trigonometric function lookup table module: Employs a symmetric compression storage strategy, storing only... The range of sine and cosine values ​​is extended to the entire cycle through address mapping, which is used to quickly obtain the trigonometric function parameters required for phase calculation;

[0057] The row and column decomposition calculation module is used to decompose a two-dimensional rectangular planar phased array into a one-dimensional linear array along the x-axis and y-axis, and calculate the phase difference between adjacent array elements based on the elevation and azimuth angles of the beam pointing.

[0058] The phase difference between adjacent array elements in the x-axis direction is:

[0059] (1)

[0060] The phase difference between adjacent array elements along the y-axis is:

[0061] (2)

[0062] in , The distance between adjacent array elements. The wavelength of the transmission signal carrier.

[0063] Phase accumulation module: Used to accumulate the adjacent phase differences obtained from row and column decomposition, generate row / column phase vectors, and store them; the accumulation operation is expressed as a multiplication operation in the formula; the phase difference between the m-th element and the 0-coordinate element in the row vector is expressed as:

[0064] (3)

[0065] The phase difference between the nth element and the 0-coordinate element in the column vector is expressed as:

[0066] (4)

[0067] Array element phase calculation module: Based on the row / column phase vectors obtained by the phase accumulation module, the phase value of each array element in the array is obtained by performing a combination operation according to formula (5);

[0068] (5)

[0069] Modulo module: Converts the traditional modulo operation into a modulo operation on the normalized value of 1, thereby simplifying the computation time and resource consumption of the FPGA.

[0070] The traditional formula for calculating phase is:

[0071] (6)

[0072] Based on the nature of the remainder, in the process of calculating the phase... Modulus with subsequent modulo operations Let's rewrite the formula as follows:

[0073] (7)

[0074] Quantization output module: Based on the bit width of the digital phase shifter, the phase after the remainder is quantized to generate the array element phase control code.

[0075] like Figure 2 The diagram shows a flowchart of a FPGA-based method for calculating the phase alignment of a rectangular planar phased array antenna, which includes the following steps:

[0076] Step 1: , Input the trigonometric function lookup table module to obtain normalized trigonometric function values , and ;

[0077] Step 2: Calculate the row and column direction normalization coefficients according to formulas (10) and (11):

[0078] (10)

[0079] (11)

[0080] in , The distance between array elements in the row and column directions is denoted by c, where c is the speed of light. For carrier frequency;

[0081] Step 3: Based on the results of Steps 1 and 2, calculate the phase difference between adjacent array elements in the row / column direction using formulas (12) and (13):

[0082] (12)

[0083] (13)

[0084] Step 4: Based on the results of Step 3, generate the basic phase sequence using the row / column accumulator according to formulas (14) and (15), and store it;

[0085] (14)

[0086] (15)

[0087] Step 5: Based on the results of Step 4, perform phase coordination and synthesis on each array element (m,n) according to formula (16);

[0088] (16)

[0089] Step 6: Take the remainder of the synthesized phase with respect to 1 to obtain the phase within the range of 0 to 2π;

[0090] Step 7: Quantize the phase according to the quantization accuracy of the phase shifter to obtain the phase shifter control code.

[0091] Actual test data shows that when using the Xilinx Zynq-7045 chip, it only occupies 4 DSP multipliers and 70.5 BRAM resources, which is small and can be ported to low-end FPGAs (such as the Artix series).

[0092] Speed: Completing the phase calculation of 1024 array elements at a 100MHz clock frequency requires approximately 12 .

[0093] Scalability: The array size can be expanded by adjusting the accumulator bit width, and it can be expanded to other polygon arrays by discarding the calculated values ​​of specific array elements.

[0094] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A fast phase matching solution system for rectangular planar phased array antenna based on FPGA, characterized in that, Comprise: Input module: receive beam pointing elevation angle and azimuth angle ; Trigonometric function lookup table module: Employs a symmetric compression storage strategy, storing only... The range of sine and cosine values ​​is extended to the entire cycle through address mapping, which is used to quickly obtain the trigonometric function parameters required for phase calculation; Row-column decomposition calculation module: for decomposing a two-dimensional rectangular planar phased array into one-dimensional linear arrays in x-axis and y-axis directions, and calculating the phase difference between adjacent elements according to the elevation and azimuth of the beam pointing; Phase accumulation module: for accumulating the adjacent phase difference obtained by row-column decomposition to generate row / column phase vectors and store them; Element phase calculation module: combining the row / column phase vectors obtained by the phase accumulation module to obtain the phase value of each element in the array; Modulus module: converting the traditional modulus operation into a normalized value modulus operation on the value 1; According to the essence of the remainder, in the process of calculating the phase The module which is operated with the remainder in the following Approximately, rewrite the formula; Quantization output module: quantizing the phase after modulus operation according to the bit width of the digital phase shifter to generate element phase control code.

2. The FPGA-based fast phase alignment solution system for rectangular planar phased array antenna according to claim 1, characterized in that, In the row-column decomposition calculation module, the phase difference between adjacent elements in the x-axis direction is: （1）； The phase difference between adjacent elements in the y-axis direction is: （2）； wherein , is the adjacent element spacing, is the transmitted signal carrier wavelength.

3. The FPGA-based fast phase alignment solution system for rectangular planar phased array antenna according to claim 2, characterized in that, In the phase accumulation module, the accumulation operation is represented as multiplication operation in formula; the phase difference between the mth element in the row vector and the 0 coordinate element is represented as: （3）； The phase difference between the nth element in the column vector and the 0 coordinate element is represented as: （4）。 4. The FPGA-based fast phase alignment solution system for rectangular planar phased array antenna according to claim 3, characterized in that, In the element phase calculation module, the combination operation is performed according to formula (5): （5）。 5. The FPGA-based fast phase alignment solution system for rectangular planar phased array antenna according to claim 4, characterized in that, In the modulus module, the traditional phase calculation formula is: （6）； Rewrite the formula as: （7）。 6. The FPGA-based fast phase alignment solution system for rectangular planar phased array antenna according to claim 2, characterized in that, The row-column decomposition calculation module further comprises a parallel pipeline architecture, which independently processes the phase difference accumulation operation in the x-axis and y-axis directions, and stores the intermediate results through a double-port BRAM to support subsequent element phase synthesis.

7. The FPGA-based fast phase alignment solution system for rectangular planar phased array antenna according to claim 5, characterized in that, The specific implementation process of the modulus module includes: converting the absolute phase value in the formula into a normalized coefficient, and determining the final phase value by calculating the remainder of the logarithmic value 1.

8. The FPGA-based fast phase alignment solution system for rectangular planar phased array antenna according to claim 1, characterized in that: The trigonometric function lookup table module adopts 16-bit quantization precision, of which the high bits are sign bits, and realizes multi-element phase parallel solution through timing control.

9. A method for solving based on the fast phase-matching solver system according to any one of claims 1-8, characterized in that, Comprise the following steps: Step one, the input of the trigonometric function table module to obtain the normalized trigonometric function value , Input the trigonometric function table module to obtain the normalized trigonometric function value , and ; Step two, calculate the row-column direction normalization coefficients according to formula (10) and formula (11): （10）； （11）； wherein , is the distance between the elements in the row and column directions, c is the speed of light, is the carrier frequency; Step three, calculate the phase difference between adjacent elements in the row / column direction according to the results of steps one and two through formula (12) and formula (13): （12）； （13）； Step four, according to the results of step three, generate the basic phase sequence through the row / column accumulators according to formula (14) and formula (15), and store them; （14）； （15）； Step five, according to the results of step four, synthesize the phase of each element (m, n) according to formula (16); （16）； Step six, take the remainder of 1 for the synthesized phase to get the phase in 0-2π; Step seven, quantize the phase according to the quantization precision of the phase shifter to get the phase shifter control code.

10. A low earth orbit satellite communication terminal antenna system, characterized by: The rectangular planar phased array antenna fast phase matching solution system based on FPGA comprises any one of claims 1-8, and is configured to meet the technical requirements of beam pointing switching period ≤100ms and gain ≥25dBi.

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