High-efficiency pipeline double-DDR-group SAR imaging data storage and transposition system based on FPGA

Abstract

The invention discloses an efficient pipeline double-DDR-group SAR imaging data storage and transposition system based on an FPGA, and belongs to the technical field of radar imaging signal processing. An efficient DDR group state machine is configured in the system, each DDR has seven different states, two frames of radar data can be processed in total after running for one time, one DDR reads data, then the data is processed and transmitted to the other DDR for data writing, one DDR performs writing operation while reading the other DDR, and the data writing efficiency is greatly improved. High-speed pipeline multi-path parallel data processing is realized, so that time is saved to the greatest extent, and high real-time performance of the whole radar imaging system is ensured.

Description

Technical Field

[0001] This invention belongs to the field of radar imaging signal processing technology, specifically relating to a high-efficiency pipelined dual DDR group SAR imaging data storage and transposition system based on FPGA. Background Technology

[0002] Synthetic Aperture Radar (SAR), as a high-resolution imaging radar, boasts all-weather, all-day operation and the unique advantage of penetrating clouds and fog. It can acquire high-resolution radar images comparable to optical images under low visibility conditions and has been widely applied in military and civilian fields such as topographic mapping, resource surveys, and battlefield situational awareness. With the rapid development of hardware manufacturing technology, research on real-time SAR imaging systems continues to advance. However, the multi-dimensional transmission and storage of massive amounts of data involved in its imaging signal processing, particularly the data transposition efficiency between range and azimuth dimensions, directly restricts the imaging processing speed and has become a key challenge for current technological breakthroughs.

[0003] To accelerate the execution speed of SAR echo imaging algorithms, devices such as DSPs, GPUs, ASICs, and FPGAs can be considered. Among these, FPGAs, due to their advantages of flexible programming, high parallel processing, and low power consumption, can efficiently complete SAR imaging tasks. Currently, DDR SDRAM is increasingly used in SAR imaging signal processing due to its advantages of large storage capacity, high speed, low power consumption, and low cost. Therefore, using DDR SDRAM and FPGAs together to process SAR echo imaging algorithms has become a future trend.

[0004] Chinese patent application No. 2022102744580, entitled "FPGA Implementation Method of CS Algorithm in Real-Time Video SAR Imaging," discloses an FPGA implementation method for real-time SAR imaging based on DDR SDRAM. This method uses an ADC to collect radar echo data and alternately stores it into DDR3 SDRAMs 1 and 2 (ping-pong storage). The output data is processed and then stored into DDR3 SDRAM 3. Once DDR3 is full for one frame, the output data is again processed and alternately stored into DDR3 SDRAMs 1 and 2 (ping-pong storage). The disadvantage of this prior art method is the large number of DDR SDRAMs used, which significantly increases FPGA resource consumption, strains placement and routing resources, and easily causes timing violations. Furthermore, when processing one frame of radar echo data, one DDR SDRAM is idle at the same time, resulting in resource waste. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-efficiency pipelined dual DDR group SAR imaging data storage and transposition system based on FPGA.

[0006] The technical problem addressed by this invention is solved as follows:

[0007] A high-efficiency pipelined dual-DDR group SAR imaging data storage transposition system based on FPGA includes two DDRs, each with seven different states. After data is read from one DDR, it is processed by a subsequent data processing module and then sent to the other DDR for data writing. While one DDR is reading, the other DDR is writing. After one cycle, a total of two frames of radar echo data are processed, realizing high-speed pipelined multi-channel parallel processing of radar echo data.

[0008] Furthermore, for the first DDR, its state transition process is as follows:

[0009] 1) The first state is initialization, setting the initial values ​​of the first DDR parameters. When the input radar echo data is valid and the first DDR initialization is complete, it enters the second state. 2) The second state is sequential writing of radar echo data. Specifically, the output enable signal of the preceding radar echo data buffer module is first pulled low. When the first DDR is ready for a write operation, the first DDR write enable signal is pulled low, and the output enable signal of the preceding radar echo data buffer module and the first DDR write enable signal are pulled high. Radar echo data is written to the first DDR, and the write count is incremented. When a full frame of data is written, it enters the third state. 3) The third state is sequential reading. When radar echo data is output, if the first DDR is ready to perform a read operation and the FIFO of the subsequent module is not full, the first DDR read enable signal is pulled high, one data point is read, and the read count is incremented by one. When a full frame of data is read, the system enters the fourth state. 4) The fourth state is to transpose the range data to the azimuth data and write it to the data processed by the previous stage. Specifically, the output enable signal of the previous stage module is first pulled low. When the first DDR is ready to perform a write operation, the first DDR write enable signal is pulled low. When the second DDR is not in the second state, the output enable signal of the previous stage module and the first DDR write enable signal are pulled high, the data is written to the first DDR, and the write count is incremented. Increment by one, the write address changes in the order of 4-way parallel and transpose, and enters the fifth state after a full frame of data is written; 5) The fifth state is to read the transposed data of the fourth state as the imaging result data corresponding to the radar echo data of the current frame. When the first DDR is ready to perform a read operation, the first DDR read enable is pulled high, one data is read and the read count is incremented by one. The read address changes in the order of 4-way parallel and transpose, and enters the sixth state after a full frame of data is read; 6) The sixth state is to transpose the azimuth data to the range data and write the data after the previous stage processing. Specifically, first, the output enable signal of the previous stage module is pulled low, and when the first DDR is ready to perform a read operation, the first DDR read enable is pulled high, one data is read and the read count is incremented by one. After the DDR is ready to perform a write operation, the first DDR write enable signal is pulled low, the output enable signal of the preceding module and the first DDR write enable signal are pulled high, data is written to the first DDR and the write count is incremented by one. The write address changes in the order of 4-way parallel and transpose. When a frame of data is written, it enters the seventh state; 7) The seventh state is to read the data after the transpose of the sixth state. When the first DDR is ready to perform a read operation and the FIFO of the following module is not full, the first DDR read enable is pulled high, one piece of data is read and the read count is incremented by one. The read address changes in the order of 4-way parallel and transpose. When a frame of data is read, it enters the first state.

[0010] Furthermore, for the second DDR, its state transition process is as follows:

[0011] 1) The first state is initialization, setting the initial values ​​of the second DDR parameters. When the output data from the third state of the first DDR is valid and the second DDR initialization is complete, it enters the second state. 2) The second state involves transposing the azimuth data to the range data and writing the data processed by the previous stage. Specifically, the output enable signal of the previous stage module is pulled low. When the second DDR is ready to perform a write operation, the second DDR write enable signal is pulled low, and the output enable signal of the previous stage module and the second DDR write enable signal are pulled high. The data processed by the previous stage is written to the second DDR, and the write count is incremented. The write address changes according to the order of 4-way parallel processing and transposition. After a full frame of input data is obtained, the system enters the third state; 3) The third state is to read the transposed data from the second state. When the second DDR is ready to perform a read operation and the FIFO of the subsequent module is not full, the second DDR read enable is pulled high, a piece of data is read, and the read count is incremented by one. The read address changes in the order of 4-way parallel and transposed. After a full frame of read data is obtained, the system enters the fourth state; 4) The fourth state is to sequentially write the next frame of radar echo data. Specifically, the output enable signal of the front-end radar echo data buffer module is pulled low. When the DDR is ready to perform a write operation, the second DDR write enable signal is pulled low, and the output of the front-end radar echo data buffer module is pulled high. The enable signal and the second DDR write enable signal are used to write data to the second DDR and increment the write count. When a full frame of data is written, the system enters the fifth state. 5) The fifth state is to sequentially read radar echo data. When the second DDR is ready to perform a read operation and the FIFO of the subsequent module is not full, the second DDR read enable signal is pulled high, one data is read, and the read count is incremented. When a full frame of data is read, the system enters the sixth state. 6) The sixth state is to transpose the range data to the azimuth data and write the data after processing by the previous stage. Specifically, the output enable signal of the previous stage module is pulled low, and when the second DDR is ready to perform a write operation, the second DDR write enable signal is pulled low. When the first DDR is not in the sixth state, the output enable signal of the front-end module and the write enable signal of the second DDR are pulled high, data is written to the second DDR and the write count is incremented by one. The write address changes in the order of 4-way parallel and transpose. When the written data is full for one frame, it enters the seventh state; 7) The seventh state is to read the transposed data of the sixth state as the imaging result data corresponding to the radar echo data of the next frame. When the second DDR is ready to perform a read operation, the second DDR read enable is pulled high, one data is read and the read count is incremented by one. The read address changes in the order of 4-way parallel and transpose. When the read data is full for one frame, it enters the first state.

[0012] Furthermore, the post-module of the third state of the first DDR is the pre-module of the second state of the second DDR, the pre-module of the fourth state of the first DDR is the post-module of the third state of the second DDR, the pre-module of the sixth state of the first DDR is the post-module of the fifth state of the second DDR, and the post-module of the seventh state of the first DDR is the pre-module of the sixth state of the second DDR. All of them are the same data processing modules, capable of performing FFT, IFFT and complex multiplication operations on the input data and then outputting the data.

[0013] Furthermore, the write operation in the second state of the first DDR and the read operation in the seventh state of the second DDR are performed simultaneously, and the read operation in the fifth state of the first DDR and the write operation in the fourth state of the second DDR are performed simultaneously.

[0014] Furthermore, the system is applied to PCS imaging. Radar echo data first enters the serial-to-parallel conversion module, and the dual-DDR group SAR imaging data storage transposition system sequentially writes and reads out the radar echo data. The RAM data ping-pong conversion module outputs data for four-way parallel operations: complex multiplication, range FFT, complex multiplication, range IFFT, and complex multiplication. The four-way parallel data then enters the serial-to-parallel conversion module, where the dual-DDR group SAR imaging data storage transposition system performs range-to-azimuth transposition. The RAM data ping-pong conversion module outputs data for four-way parallel operations: complex multiplication, azimuth FFT, complex multiplication, azimuth IFFT, complex multiplication, azimuth FFT, and complex multiplication. The four-way parallel data then enters the serial-to-parallel conversion module, where the dual-DDR group SAR imaging data storage transposition system performs azimuth-to-range transposition. The RAM data ping-pong conversion module outputs data for four-way parallel range FFT, ultimately obtaining the imaging result.

[0015] The beneficial effects of this invention are:

[0016] The dual-DDR group SAR imaging data storage transposition system of the present invention uses two DDR SDRAMs to work together efficiently. The number of DDR SDRAMs used is small, which reduces the resources on the FPGA and makes timing violations less likely. The whole process is carried out in high-speed pipeline, which saves time to the greatest extent and ensures the high real-time performance of the entire radar system. Attached Figure Description

[0017] Figure 1 This is a block diagram illustrating the implementation of the system described in this invention;

[0018] Figure 2 This is a flowchart illustrating the specific process of the first DDR in the system described in this invention.

[0019] Figure 3 This is a detailed flowchart of the second DDR in the system described in this invention;

[0020] Figure 4 This provides input and output signals for the DDR control module in the system described in this invention.

[0021] Figure 5 This is a block diagram illustrating the application of the system described in this invention in the PCS imaging algorithm. Detailed Implementation

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] This embodiment provides a high-efficiency pipelined dual DDR group SAR imaging data storage and transposition system based on FPGA, such as... Figure 1 As shown, in the state machine of the high-efficiency DDR group designed in this system, each DDR has a total of seven different states. After running once, it can process a total of two frames of radar echo data. After a certain DDR reads data, it is processed and sent to another DDR for data writing. When one DDR is reading, another DDR is definitely performing a write operation. High-speed pipelined multi-path parallel data processing saves time to the greatest extent and ensures the high real-time performance of the entire radar system.

[0024] The specific process of the first DDR in the DDR group is as follows: Figure 2As shown: 1) The first state is initialization, where the parameters related to the first DDR are initialized. When the input radar echo data is valid and the first DDR is initialized, the second state is entered; 2) The second state is sequential writing of radar echo data. There are three steps in total for writing data. First, the output enable signal of the front-end radar echo data buffer module is pulled low. Second, when the first DDR is ready to perform a write operation, the first DDR write enable signal is pulled low. Third, the output enable signal of the front-end radar echo data buffer module and the first DDR write enable signal are pulled high, the radar echo data is written to the first DDR, and the write count is incremented by one. When a full frame of data is written, the third state is entered; 3) The third state is sequential reading of radar data. Echo data: When the first DDR is ready to perform a read operation and the FIFO of the subsequent module is not full, the first DDR read enable is pulled high, one data is read, and the read count is incremented by one. When a full frame of data is read, it enters the fourth state; 4) The fourth state is to transpose the range data to the azimuth data and write the data after processing by the previous stage. There are three steps in total for writing data. The first step is to pull the output enable signal of the previous stage module low. The second step is to pull the first DDR write enable signal low when the first DDR is ready to perform a write operation. The third step is to pull the output enable signal of the previous stage module high when both DDRs are in the write state, because the data output by the previous stage module will conflict when both DDRs are in the write state. Output enable signal and first DDR write enable signal, write data to the first DDR and increment the write count by one. The write address changes in the order of 4-way parallel and transpose. When the written data fills a frame, it enters the fifth state; 5) The fifth state is to read the transposed data of the fourth state as the imaging result data corresponding to the radar echo data of the current frame. When the first DDR is ready to perform a read operation, pull the first DDR read enable high, read one data and increment the read count by one. The read address changes in the order of 4-way parallel and transpose. When the read data fills a frame, it enters the sixth state; 6) The sixth state is to transpose the azimuth data to the range data and write the data after the previous stage processing. There are three steps in total for writing data. The first step is to... The first step is to pull the output enable signal of the front-end module low. The second step is to pull the first DDR write enable signal low when the first DDR is ready to perform a write operation. The third step is to pull the output enable signal of the front-end module and the first DDR write enable signal high, write data to the first DDR and increment the write count by one. The write address changes in the order of 4-way parallel and transpose. When a frame of data is written, the seventh state is entered. The seventh state is to read the transposed data of the sixth state. When the first DDR is ready to perform a read operation and the FIFO of the back-end module is not full, the first DDR read enable signal is pulled high, one piece of data is read and the read count is incremented by one. The read address changes in the order of 4-way parallel and transpose. When a frame of data is read, the first state is entered.

[0025] The specific process for the second DDR in the DDR group is as follows: Figure 3 As shown: 1) The first state is initialization, where the parameters related to the second DDR are initialized. When the output data from the third state of the first DDR is valid and the second DDR initialization is complete, the second state is entered; 2) The second state involves transposing the azimuth data to the range data and writing the data processed by the previous stage. The data writing process has three steps: First, the output enable signal of the previous stage module is pulled low; second, when the second DDR is ready to perform a write operation, the second DDR write enable signal is pulled low; third, the output enable signal of the previous stage module and the second DDR write enable signal are pulled high, the processed data is written to the second DDR, and the write count is incremented. The write address changes according to the order of 4-way parallel processing and transposition. When writing data... After a full frame is completed, the system enters the third state; 3) The third state reads the transposed data from the second state. When the second DDR is ready to perform a read operation and the FIFO of the subsequent module is not full, the second DDR read enable is pulled high, a data is read, and the read count is incremented by one. The read address changes in the order of 4-way parallel and transposed. After a full frame of data is read, the system enters the fourth state; 4) The fourth state sequentially writes the next frame of radar echo data. There are three steps in total for writing data. The first step is to pull the output enable signal of the front-end radar echo data buffer module low. The second step is to pull the second DDR write enable signal low when the DDR is ready to perform a write operation. The third step is to pull the output enable signal of the front-end radar echo data buffer module high and the second DDR write enable signal high. Enable signal, write data to the second DDR and increment the write count. When a full frame of data is written, enter the fifth state; 5) The fifth state is to sequentially read radar echo data. When the second DDR is ready to perform a read operation and the FIFO of the subsequent module is not full, pull the second DDR read enable high, read a data, and increment the read count. When a full frame of data is read, enter the sixth state; 6) The sixth state is to transpose the range data to the azimuth data and write the data after processing by the previous stage. There are three steps in total for writing data. The first step is to pull the output enable signal of the previous stage module low. The second step is to pull the second DDR write enable signal low when the second DDR is ready to perform a write operation. The third step is to pull the front-end module low when both DDRs are in the write state. The data output by the module may conflict. Therefore, when the first DDR is not in the sixth state (azimuth data transposed to range write state), the output enable signal of the front-end module and the write enable signal of the second DDR are pulled high. Data is written to the second DDR and the write count is incremented by one. The write address changes in the order of 4-way parallel and transposed. When the written data is full for one frame, it enters the seventh state. 7) The seventh state is to read the transposed data of the sixth state as the imaging result data corresponding to the radar echo data of the next frame. When the second DDR is ready to perform the read operation, the second DDR read enable is pulled high, one data is read and the read count is incremented by one. The read address changes in the order of 4-way parallel and transposed. When the read data is full for one frame, it enters the first state.

[0026] The first DDR third state's follow-up module is the second DDR second state's pre-stage module; the first DDR fourth state's pre-stage module is the second DDR third state's follow-up module; the first DDR sixth state's pre-stage module is the second DDR fifth state's follow-up module; and the first DDR seventh state's follow-up module is the second DDR sixth state's pre-stage module. All of these are the same data processing modules, capable of performing FFT, IFFT, and complex multiplication operations on the input data before outputting the results.

[0027] The write operation in the second state of the first DDR is performed simultaneously with the read operation in the seventh state of the second DDR, and the read operation in the fifth state of the first DDR is performed simultaneously with the write operation in the fourth state of the second DDR.

[0028] A schematic diagram of the DDR control module, abstracted from the dual-DDR group SAR imaging data storage transposition system, is shown below. Figure 4 As shown, clk is the clock signal, reset is the reset signal, fifo_empty is the FIFO empty signal of the front-end module, fifo_full is the FIFO full signal of the rear-end module, adc_data and adc_data_valid are the raw radar echo data and their valid signals, data2 and data2_valid are the processed output data and their valid signals, init_complete is the initialization completion signal of the two DDR MIG IP cores, app_rdy, app_wdf_rdy and app_rd_data_valid are the read / write command reception preparation completion signal, data reception preparation completion signal and read data valid signal of the DDR MIG IP core, respectively; fifo_en is the output enable signal of the data processing module, ddr1_state and ddt2_state are the status signals of the two DDRs, and app_en, app_wdf_wren, app_wdf_end, app_cmd, app_addr and app_wdf_data are the DDR MIG... IP core command write enable signal, data write enable signal, current clock is the last clock signal of the burst write process, read / write control command signal, user address input signal, user write data input signal.

[0029] The specific process of the PCS imaging algorithm in the system described in this embodiment is as follows: Figure 5As shown, in the dual-DDR group SAR imaging data storage transposition system, the downstream module of the third state of the first DDR is the upstream module of the second state of the second DDR, used to sequentially perform complex multiplication, range FFT, complex multiplication, range IFFT, and complex multiplication on the data; the upstream module of the fourth state of the first DDR is the downstream module of the third state of the second DDR, used to sequentially perform complex multiplication, azimuth FFT, complex multiplication, azimuth IFFT, complex multiplication, azimuth FFT, and complex multiplication on the data; the upstream module of the sixth state of the first DDR is the downstream module of the fifth state of the second DDR, used to sequentially perform complex multiplication, range FFT, complex multiplication, range IFFT, and complex multiplication on the data; the downstream module of the seventh state of the first DDR is the upstream module of the sixth state of the second DDR, used to sequentially perform complex multiplication, azimuth FFT, complex multiplication, azimuth IFFT, complex multiplication, azimuth FFT, and complex multiplication on the data.

[0030] Radar echo data first enters the serial-to-parallel conversion module. The dual-DDR group SAR imaging data storage transposition system sequentially writes and reads the radar echo data. The RAM data ping-pong conversion module outputs data for four parallel operations: complex multiplication, range FFT, complex multiplication, range IFFT, and complex multiplication. The four parallel data then enters the serial-to-parallel conversion module, where the dual-DDR group SAR imaging data storage transposition system transposes the data from the range direction to the azimuth direction. The RAM data ping-pong conversion module outputs data for four parallel operations: complex multiplication, azimuth FFT, complex multiplication, azimuth IFFT, complex multiplication, azimuth FFT, and complex multiplication. The four parallel data then enters the serial-to-parallel conversion module, where the dual-DDR group SAR imaging data storage transposition system transposes the data from the azimuth direction to the range direction. The RAM data ping-pong conversion module outputs data for four parallel range FFT operations, ultimately yielding the imaging result.

Claims

1. A high-efficiency pipelined dual DDR group SAR imaging data storage and transposition system based on FPGA, characterized in that, It includes two DDRs, each with seven different states. After reading data from one DDR, the data is processed by the subsequent data processing module and then sent to the other DDR for data writing. While one DDR is reading, the other DDR is definitely writing. After one cycle, a total of two frames of radar echo data are processed, realizing high-speed pipelined multi-channel parallel processing of radar echo data.

2. The high-efficiency pipelined dual DDR group SAR imaging data storage and transposition system based on FPGA according to claim 1, characterized in that, For the first DDR, the state transition process is as follows: 1) The first state is initialization, setting the initial values ​​of the first DDR parameters. When the input radar echo data is valid and the first DDR initialization is complete, it enters the second state. 2) The second state is sequential writing of radar echo data. Specifically, the output enable signal of the preceding radar echo data buffer module is first pulled low. When the first DDR is ready for a write operation, the first DDR write enable signal is pulled low, and the output enable signal of the preceding radar echo data buffer module and the first DDR write enable signal are pulled high. Radar echo data is written to the first DDR, and the write count is incremented. When a full frame of data is written, it enters the third state. 3) The third state is sequential reading. When radar echo data is output, if the first DDR is ready to perform a read operation and the FIFO of the subsequent module is not full, the first DDR read enable signal is pulled high, one data point is read, and the read count is incremented by one. When a full frame of data is read, the system enters the fourth state. 4) The fourth state is to transpose the range data to the azimuth data and write it to the data processed by the previous stage. Specifically, the output enable signal of the previous stage module is first pulled low. When the first DDR is ready to perform a write operation, the first DDR write enable signal is pulled low. When the second DDR is not in the second state, the output enable signal of the previous stage module and the first DDR write enable signal are pulled high, the data is written to the first DDR, and the write count is incremented. Increment by one, the write address changes in the order of 4-way parallel and transpose, and enters the fifth state after a full frame of data is written; 5) The fifth state is to read the transposed data of the fourth state as the imaging result data corresponding to the radar echo data of the current frame. When the first DDR is ready to perform a read operation, the first DDR read enable is pulled high, one data is read and the read count is incremented by one. The read address changes in the order of 4-way parallel and transpose, and enters the sixth state after a full frame of data is read; 6) The sixth state is to transpose the azimuth data to the range data and write the data after the previous stage processing. Specifically, first, the output enable signal of the previous stage module is pulled low, and when the first DDR is ready to perform a read operation, the first DDR read enable is pulled high, one data is read and the read count is incremented by one. After the DDR is ready to perform a write operation, the first DDR write enable signal is pulled low, the output enable signal of the preceding module and the first DDR write enable signal are pulled high, data is written to the first DDR and the write count is incremented by one. The write address changes in the order of 4-way parallel and transpose. When a frame of data is written, it enters the seventh state; 7) The seventh state is to read the data after the transpose of the sixth state. When the first DDR is ready to perform a read operation and the FIFO of the following module is not full, the first DDR read enable is pulled high, one piece of data is read and the read count is incremented by one. The read address changes in the order of 4-way parallel and transpose. When a frame of data is read, it enters the first state.

3. The high-efficiency pipelined dual DDR group SAR imaging data storage and transposition system based on FPGA according to claim 2, characterized in that, For the second DDR, the state transition process is as follows: 1) The first state is initialization, setting the initial values ​​of the second DDR parameters. When the output data from the third state of the first DDR is valid and the second DDR initialization is complete, it enters the second state. 2) The second state transposes the azimuth data to the range data and writes the data processed by the previous stage. Specifically, the output enable signal of the previous stage module is pulled low. When the second DDR is ready to perform a write operation, the second DDR write enable signal is pulled low, and the output enable signal of the previous stage module and the second DDR write enable signal are pulled high. The data processed by the previous stage is written to the second DDR, and the write count is incremented. The write address changes according to the order of 4-way parallel processing and transposition. When a full frame of data is written, it enters the third state. 3) The third state reads the first... After the data is transposed in the two states, when the second DDR is ready to perform a read operation and the FIFO of the subsequent module is not full, the second DDR read enable is pulled high, one data is read and the read count is incremented by one. The read address changes in the order of 4-way parallel and transposed. When the read data is full for one frame, it enters the fourth state; 4) The fourth state is to sequentially write the next frame of radar echo data. Specifically, the output enable signal of the front-end radar echo data buffer module is pulled low. When the DDR is ready to perform a write operation, the second DDR write enable signal is pulled low, and the output enable signal of the front-end radar echo data buffer module and the second DDR write enable signal are pulled high. Data is written to the second DDR and the write count is incremented by one. When the written data is full for one frame, it enters the fifth state; 5) The fifth state is sequentially reading radar echo data. When the second DDR is ready to perform a read operation and the FIFO of the subsequent module is not full, the second DDR read enable is pulled high, one data is read, and the read count is incremented by one. When a full frame of data is read, the sixth state is entered. 6) The sixth state is transposing the range data to the azimuth data and writing it into the data processed by the previous stage. Specifically, the output enable signal of the previous stage module is pulled low. When the second DDR is ready to perform a write operation, the second DDR write enable signal is pulled low. When the first DDR is not in the sixth state, the previous stage module is pulled high. The output enable signal and the second DDR write enable signal are used to write data to the second DDR and increment the write count. The write address changes in the order of 4-way parallel and transpose. When the written data is full for one frame, it enters the seventh state. 7) The seventh state is to read the transposed data of the sixth state as the imaging result data corresponding to the radar echo data of the next frame. When the second DDR is ready to perform a read operation, the second DDR read enable is pulled high, one data is read and the read count is incremented. The read address changes in the order of 4-way parallel and transpose. When the read data is full for one frame, it enters the first state.

4. The high-efficiency pipelined dual DDR group SAR imaging data storage and transposition system based on FPGA according to claim 3, characterized in that, The first DDR third state's follow-up module is the second DDR second state's pre-stage module; the first DDR fourth state's pre-stage module is the second DDR third state's follow-up module; the first DDR sixth state's pre-stage module is the second DDR fifth state's follow-up module; and the first DDR seventh state's follow-up module is the second DDR sixth state's pre-stage module. All of these are the same data processing modules, capable of performing FFT, IFFT, and complex multiplication operations on the input data before outputting the results.

5. The high-efficiency pipelined dual DDR group SAR imaging data storage and transposition system based on FPGA according to claim 4, characterized in that, The write operation in the second state of the first DDR is performed simultaneously with the read operation in the seventh state of the second DDR, and the read operation in the fifth state of the first DDR is performed simultaneously with the write operation in the fourth state of the second DDR.

6. The high-efficiency pipelined dual DDR group SAR imaging data storage and transposition system based on FPGA according to claim 5, characterized in that, The system is applied to PCS imaging. Radar echo data first enters the serial-to-parallel conversion module. The dual-DDR group SAR imaging data storage transposition system sequentially writes and reads out the radar echo data. The RAM data ping-pong conversion module outputs data for four parallel operations: complex multiplication, range FFT, complex multiplication, range IFFT, and complex multiplication. The four parallel data streams then enter the serial-to-parallel conversion module. The dual-DDR group SAR imaging data storage transposition system transposes the data from the range direction to the azimuth direction. The RAM data ping-pong conversion module outputs data for four parallel operations: complex multiplication, azimuth FFT, complex multiplication, azimuth IFFT, complex multiplication, azimuth FFT, and complex multiplication. The four parallel data streams then enter the serial-to-parallel conversion module. The dual-DDR group SAR imaging data storage transposition system transposes the data from the azimuth direction to the range direction. The RAM data ping-pong conversion module outputs data for four parallel range FFT operations, ultimately obtaining the imaging result.

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