A data writing method and device of a solid state disk and an electronic device

Abstract

The application provides a data writing method and device of a solid state disk and electronic equipment, wherein the method comprises the following steps: in a data moving process, if a current writing programming mode is a four-layer storage unit mode, then in the first programming, each group of logical addresses and physical addresses of effective data are stored in a pre-constructed temporary cache table, and the effective data is stored in a data cache area; each node of the temporary cache table stores a mapping relationship of a group of logical addresses and physical addresses; address information of the temporary cache table is managed through an insertion pointer, a deletion pointer and a data amount counting pointer; when the number of address information recorded by the insertion pointer reaches two programming lines, the second programming is entered, the recorded address information of the logical addresses and the physical addresses of the effective data is obtained from the temporary cache table, and the data corresponding to the address information in the data cache area is written into a target block; until all the effective data in a source block is moved to the target block, the source block is released.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive (SSD) technology, and in particular to a data writing method, apparatus, and electronic device for SSDs. Background Technology

[0002] Solid State Drives (SSDs) typically use Quad-Level Cell (QLC) flash memory. When writing data, the system first writes the data to Single-Level Cell (SLC) physical blocks, which offer higher speed and durability. As the SLC physical blocks are used up, the system moves the data from the SLC physical blocks to QLC physical blocks to complete the write operation. The advantage of this method is that the SLC physical blocks act as a cache, providing faster write speeds while reducing the number of write operations on the QLC physical blocks, thus extending the lifespan of the QLC flash memory. Furthermore, after the QLC physical blocks are exhausted, the system performs garbage collection, managing unused space in the flash memory and erasing invalid data to free up usable physical blocks for new data writing, ensuring a smooth process for new data input.

[0003] In related technologies, to ensure data is written completely to NAND flash memory, two programming processes (Coarse write and Fine write) are required during the writing of QLC physical blocks. Currently, during data migration, especially before reading valid data from the source block, it is necessary to first read the relevant table information (i.e., the correspondence between the logical address and physical address of the valid data in the solid-state drive) from the NAND flash memory. Then, the system reads the valid data into the data buffer based on this table information, and finally writes the valid data in the data buffer to the destination block through Coarse write or Fine write. Therefore, improving migration efficiency is particularly important during data migration. Summary of the Invention

[0004] This invention provides a data writing method, apparatus, and electronic device for solid-state drives (SSDs) to improve the efficiency of data transfer.

[0005] In a first aspect, embodiments of the present invention provide a data writing method for a solid-state drive (SSD), the SSD comprising multiple single-level storage unit physical blocks and multiple four-level storage unit physical blocks; the method comprising:

[0006] If the plurality of single-level storage unit physical blocks are consumed to the corresponding critical waterline, or if the plurality of four-level storage unit physical blocks are consumed to the corresponding critical waterline, then the garbage collection mechanism is triggered.

[0007] A source block is determined from the plurality of single-level storage cell physical blocks and the plurality of four-level storage cell physical blocks, and a destination block is determined from the plurality of four-level storage cell physical blocks, and valid data in the source block is moved to the destination block;

[0008] During the data migration process, if the current programming mode is a four-level storage unit mode, then during the first programming, the logical addresses and physical addresses of the valid data are stored in a pre-built temporary cache table, and the valid data is stored in the data cache area; the temporary cache table adopts a circular queue data structure, and each node of the temporary cache table stores a mapping relationship between a set of logical addresses and physical addresses;

[0009] The address information of the temporary cache table is managed by an insertion pointer, a deletion pointer, and a data volume count pointer; the insertion pointer is used to record the number of address information newly added to the temporary cache table during the first programming; the deletion pointer is used to record the number of address information of programmed data after the second programming is written to the temporary cache table; and the data volume count pointer is used to record the number of address information of currently cached valid data in the temporary cache table.

[0010] When the number of address information recorded by the insertion pointer reaches two levels of programming lines, the second programming is initiated. The logical address and physical address information of the recorded valid data are obtained from the temporary cache table, and the data corresponding to the address information in the data cache is written into the destination block.

[0011] The source block is released once all valid data in the source block has been moved to the destination block.

[0012] In one possible implementation, managing the address information of the temporary cache table through insertion pointers, deletion pointers, and data volume count pointers includes:

[0013] During the first programming, the insertion pointer and the data count pointer are incremented from zero until the address count of the two programming lines is reached. Then, the program transitions from the first programming to the second programming, and the insertion pointer is cleared.

[0014] During the second programming, the deletion pointer is incremented from zero until the data volume counter pointer is reduced from the number of addresses in two layers to the number of addresses in one layer. Then, the program switches to the first programming round and the deletion pointer is cleared. This process is repeated until the data transfer is complete.

[0015] In one possible implementation, before releasing the source block after all valid data in the source block has been moved to the destination block, the method further includes:

[0016] If the last data in the source block does not fill the current layer of the destination block, then determine the baseline number of data units required for the current layer.

[0017] Based on the baseline quantity, determine the amount of padding required to fill the remaining space of the target block; the padding amount includes first invalid data for filling the current layer, and second invalid data for preparing for the first programming of the next layer; the first invalid data undergoes two programming processes, including the first programming and the second programming, and the second invalid data undergoes the first programming once; the padding amount is (2*Dummy1+Dummy2); Dummy1 represents the first invalid data, and Dummy2 represents the second invalid data;

[0018] Based on the filling amount, specific data is filled into the data buffer and then flushed to the destination block.

[0019] In one possible implementation, determining the baseline number of data units required for the current layer includes:

[0020] The reference quantity is determined using the following formula:

[0021] AU_num=WL_AU*WL_Page*WL_Cnt*Die_Cnt*CH_cnt;

[0022] Wherein, AU_num represents the base number, WL_AU represents the number of minimum data units included in each programming unit, WL_Page represents the number of storage pages included in each programming unit, WL_Cnt represents the number of programming units included in each independent concurrent operation unit, Die_Cnt represents the number of independent concurrent operation units, and CH_cnt represents the number of storage channels.

[0023] In one possible implementation, after storing the logical and physical addresses of the valid data into a pre-built temporary cache table and storing the valid data into a data cache area during the first programming, the method further includes:

[0024] During the first programming process, the read status of each piece of data stored in the data buffer is detected;

[0025] If the read status of some data in the data buffer is an error status, then the logical address corresponding to the data in the error status is recorded;

[0026] Traverse the temporary cache table to find the index number corresponding to the logical address;

[0027] Move each node in the temporary cache table that records the logical address and physical address after the index number forward one by one, and move the node that records the logical address and physical address corresponding to the index number to the end of the temporary cache table as the last node, thus obtaining the adjusted temporary cache table.

[0028] In one possible implementation, after detecting the read status of each piece of data stored in the data buffer, the method further includes:

[0029] If the read status of all data in the data cache is the error status, then the logical address and physical address recorded for the data in the error status in the temporary cache table are deleted, and the insertion pointer and the data volume count pointer are pushed back to a preset number of positions, so as to reread the preset number of data from the source block to the data cache; the preset number is the amount of data that can be moved in this round based on the size of the data cache.

[0030] In one possible implementation, if a programming failure is detected during the transfer of valid data from the source block to the destination block, the method further includes:

[0031] Clear the temporary cache table;

[0032] The target block is marked as closed, and the target block is removed from the candidate pool;

[0033] Clean up the physical-to-logical mapping table of the memory corresponding to the target block; the physical-to-logical mapping table is used to store the logical addresses of all data in the memory and the corresponding physical addresses;

[0034] If the target block cannot be replaced, then the physical block to which it belongs is marked as a bad block;

[0035] Release the resources occupied by this round of waste recycling mechanism.

[0036] Secondly, embodiments of the present invention provide a data writing device for a solid-state drive (SSD), the SSD comprising multiple single-level storage unit physical blocks and multiple four-level storage unit physical blocks; the device includes:

[0037] The triggering unit is used to trigger the garbage collection mechanism if the plurality of single-level storage unit physical blocks are consumed to the corresponding critical waterline, or if the plurality of four-level storage unit physical blocks are consumed to the corresponding critical waterline.

[0038] A determining unit is used to determine a source block from the plurality of single-level storage unit physical blocks and the plurality of four-level storage unit physical blocks, and to determine a destination block from the plurality of four-level storage unit physical blocks, and to move the valid data in the source block to the destination block; a storing unit is used, during the data moving process, if the current writing programming mode is a four-level storage unit mode, to store each set of logical addresses and physical addresses of the valid data into a pre-built temporary cache table during the first programming, and to store the valid data into a data cache area; the temporary cache table adopts a circular queue data structure, and each node of the temporary cache table stores a set of logical address and physical address mapping relationships;

[0039] The management unit is used to manage the address information of the temporary cache table through an insertion pointer, a deletion pointer, and a data volume count pointer; the insertion pointer is used to record the number of address information newly added to the temporary cache table during the first programming; the deletion pointer is used to record the number of address information of programmed data after the second programming is written to the temporary cache table; and the data volume count pointer is used to record the number of address information of currently cached valid data in the temporary cache table.

[0040] The writing unit is used to enter the second programming when the number of address information recorded by the insertion pointer reaches two levels of programming lines, to obtain the logical address and physical address information of the recorded valid data from the temporary cache table, and to write the data corresponding to the address information in the data cache area into the destination block;

[0041] A release unit is configured to release the source block once all valid data in the source block has been moved to the destination block.

[0042] Thirdly, embodiments of the present invention provide an electronic device, including:

[0043] Memory, used to store computer programs;

[0044] When a processor executes a computer program stored in the memory, it implements the steps of the method described in any of the preceding descriptions.

[0045] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing a computer program for causing a computer to perform the steps of the method described in any of the preceding claims.

[0046] Fifthly, embodiments of the present invention provide a computer program product, the computer program product comprising: computer program code, which, when run on a computer, causes the computer to perform any of the methods described above.

[0047] The beneficial effects of the embodiments of the present invention are as follows:

[0048] This invention provides a data writing method, apparatus, and electronic device for a solid-state drive (SSD). If multiple single-level storage unit physical blocks in the SSD are consumed to their corresponding critical waterline, or if multiple four-level storage unit physical blocks in the SSD are consumed to their critical waterline, a garbage collection mechanism is triggered. Then, a source block is determined from the multiple single-level and multiple four-level storage unit physical blocks, and a destination block is determined from the multiple four-level storage unit physical blocks. Valid data from the source block is moved to the destination block. During the data movement process, if the current writing programming mode is four-level storage... In the cell mode, during the first programming iteration, the logical and physical addresses of the valid data are stored in a pre-built temporary cache table, and the valid data is stored in the data cache area. The temporary cache table adopts a circular queue data structure, and each node of the temporary cache table stores a mapping relationship between a set of logical and physical addresses. That is to say, during the data migration process, if the current programming mode is a four-level storage cell mode, during the first programming iteration, the temporary cache table built with a circular queue is used to cache the logical and physical addresses of the valid data read from the source block.

[0049] Then, the address information of the temporary cache table is managed through insertion pointers, deletion pointers, and data volume count pointers. The insertion pointer records the number of address information entries added to the temporary cache table during the first programming iteration; the deletion pointer records the number of address information entries for programmed data after the second programming iteration; and the data volume count pointer records the number of address information entries for currently cached valid data in the temporary cache table. When the number of address information entries recorded by the insertion pointer reaches two programming lines, the second programming iteration begins. The logical and physical address information of the recorded valid data is retrieved from the temporary cache table, and the data corresponding to the address information in the data buffer is written to the destination block. This process continues until all valid data in the source block is moved to the destination block, at which point the source block is released. In other words, during the second programming iteration, the logical and physical address information of the recorded valid data can be directly retrieved from the temporary cache table. This eliminates the need to repeatedly read data from the NAND flash memory during the second programming iteration; the logical and physical address information of the recorded valid data can be directly retrieved from the temporary cache table, and the data corresponding to the address information in the data buffer can then be written to the destination block. This reduces data read latency and improves data programming efficiency; at the same time, it reduces the number of NAND flash memory read operations, extending the lifespan of NAND flash memory; it also improves data migration speed and overall system responsiveness, optimizing the efficiency of data programming and access; especially during large-scale data migration, it significantly improves performance. Attached Figure Description

[0050] Figure 1 A flowchart illustrating a method for writing data to a solid-state drive according to an embodiment of the present invention;

[0051] Figure 2 This is a schematic diagram illustrating one possible partitioning of the storage page layout in a QLC physical block during a solid-state drive data writing method provided in an embodiment of the present invention.

[0052] Figure 3 for Figure 1 Flowchart of one method for step S104;

[0053] Figure 4 This is a schematic diagram of one of the processing mechanisms for the first programming and the second programming in a solid-state drive data writing method provided in an embodiment of the present invention;

[0054] Figure 5 This invention provides a flowchart of a solid-state drive data writing method with a garbage collection mechanism.

[0055] Figure 6 In order to be in Figure 1 Flowchart of one of the methods preceding step S106;

[0056] Figure 7 This is a schematic diagram of one possible structure of the data filling mechanism in a solid-state drive data writing method provided in an embodiment of the present invention;

[0057] Figure 8 In order to be in Figure 1 Flowchart of one of the methods following step S103;

[0058] Figure 9 This is a flowchart illustrating a fault detection mechanism in a solid-state drive data writing method provided by an embodiment of the present invention.

[0059] Figure 10 A flowchart illustrating one method of writing data to a solid-state drive according to an embodiment of the present invention;

[0060] Figure 11 This is a schematic diagram of one possible structure of a solid-state drive data writing device provided in an embodiment of the present invention;

[0061] Figure 12 This is a schematic diagram of one structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0062] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. Unless otherwise specified, the embodiments and features in the embodiments of this invention can be arbitrarily combined with each other. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than that shown here.

[0063] The terms "first" and "second" in the specification, claims, and accompanying drawings of this invention are used to distinguish different objects, not to describe a specific order. Furthermore, the term "comprising" and any variations thereof are intended to cover non-exclusive protection. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses. The term "multiple" in this invention can mean at least two, for example, two, three, or more, and the embodiments of this invention are not limited thereto.

[0064] The following description, in conjunction with the accompanying drawings, illustrates exemplary embodiments of the present invention, including various details to aid understanding. These are to be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope of the invention. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that in the embodiments of the present invention, references may be made to existing industry solutions such as software, components, and models. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solutions of the present invention, and do not imply that the inventors have used or necessarily used such solutions.

[0065] In the technical solution of this invention, the acquisition, transmission, storage, and use of data all comply with the requirements of relevant national laws and regulations.

[0066] Before introducing the solid-state drive data writing method provided in the embodiments of the present invention, the technical background of the embodiments of the present invention will be described in detail first for ease of understanding.

[0067] SSDs are one of the most common storage media. The two hardware components that significantly impact SSD read / write performance are the controller chip and the flash memory chips. Flash memory-based SSDs typically use flash memory chips as the data storage medium, and data storage and retrieval are achieved through electrical signals. Depending on the type of flash memory chip, the most common types in SSDs are SLC, Multi-Level Cell (MLC), Trinary-Level Cell (TLC), and QLC. A single SSD can contain one type of flash memory chip or multiple types. For example, a QLC SSD can also include SLC chips. In a QLC SSD, when writing data, the data is first written to the faster and more durable SLC physical blocks. As the SLC physical blocks are used up, when their storage space is exhausted, the system moves the data from the SLC physical blocks to the QLC physical blocks to complete the write operation.

[0068] In related technologies, to ensure data is written completely to NAND flash memory, two programming processes (Coarse write and Fine write) are required during the writing of QLC physical blocks. Currently, during data migration, especially before reading valid data from the source block, it is necessary to first read the relevant table information (i.e., the correspondence between the logical address and physical address of the valid data in the solid-state drive) from the NAND flash memory. Then, the system reads the valid data into the data buffer based on this table information, and finally writes the valid data in the data buffer to the destination block through Coarse write or Fine write. Therefore, improving migration efficiency is particularly important during data migration.

[0069] Therefore, the present invention provides a data writing method, apparatus and electronic device for solid-state drives (SSDs) to improve the efficiency of data transfer in SSDs.

[0070] like Figure 1 As shown, this embodiment of the invention provides a data writing method for a solid-state drive (SSD). The SSD includes multiple single-level storage unit (SLC) physical blocks and multiple four-level storage unit (QLC) physical blocks; wherein, the SLC physical block is an SLC physical block, and the QLC physical block is a QLC physical block. For example, a portion of the SSD's space is set as an SLC physical block resource pool, and the remaining space is set as a QLC physical block resource pool; the SLC physical block resource pool includes multiple SLC physical blocks, and the QLC physical block resource pool includes multiple QLC physical blocks; for example, the SLC physical blocks in the SLC physical block resource pool account for 15% of the total physical blocks of the SSD, and the QLC physical block resource pool accounts for 85% of the total physical blocks of the SSD. Whenever the host writes data to the SSD, it first writes to one of the SLC physical blocks in the SLC physical block resource pool. When that SLC physical block is full, another SLC physical block is reallocated, and data writing continues. Specifically, the writing method includes:

[0071] S101: If the plurality of single-level storage unit physical blocks are consumed to the corresponding critical waterline, or if the plurality of four-level storage unit physical blocks are consumed to the corresponding critical waterline, then the garbage collection mechanism is triggered.

[0072] In practice, each solid-state drive (SSD) comprises multiple SLC physical blocks and multiple QLC physical blocks, each with a corresponding critical waterline. When the number of available programmable blocks in multiple SLC physical blocks falls below their critical waterline (i.e., the SLC physical block resource pool is depleted to the critical waterline), or when the number of available programmable blocks in multiple QLC physical blocks falls below their critical waterline (i.e., the QLC physical block resource pool is depleted to the critical waterline), the corresponding storage system of the SSD will trigger a garbage collection mechanism. During the garbage collection process, a portion of the multiple SLC physical blocks or a portion of the multiple QLC physical blocks can be used as source blocks. The storage system then moves all valid data to the target QLC physical block and finally releases the source blocks.

[0073] S102: Determine a source block from the plurality of single-level storage cell physical blocks and the plurality of four-level storage cell physical blocks, and determine a destination block from the plurality of four-level storage cell physical blocks, and move the valid data in the source block to the destination block;

[0074] In practical implementation, the process of determining the source block can be as follows: Traverse all programmed physical blocks in the SLC physical block resource pool and the QLC physical block resource pool, and find the physical block with the most invalid data in each pool; then, based on the number of remaining available programmable blocks in the SLC and QLC physical block resource pools, further filter from the physical block with the most invalid data to determine the source block for this round of garbage collection. The number of remaining available programmable blocks in the SLC and QLC physical block resource pools determines the storage pressure of the storage system. For example, if the number of remaining available programmable blocks in the SLC physical block resource pool is small, the physical block with the most invalid data in the SLC physical block resource pool is preferentially selected as the source block to free up space in the SLC physical block pool. Similarly, if the number of remaining available programmable blocks in the QLC physical block resource pool is small, the physical block with the most invalid data in the QLC physical block resource pool is preferentially selected as the source block to free up space in the QLC physical block pool.

[0075] In addition, the process of determining the target block can be as follows: traverse the QLC physical block resource pool, find the physical block that is the youngest in programming (i.e. has the fewest wear times) and does not contain any valid data; and then use it as the target block.

[0076] In the specific implementation process, after determining the source block and the destination block, it is also necessary to filter out valid data from the source block. Specifically, all global tables (i.e., P2L tables) used to store the mapping relationship between logical addresses (LAA) and physical addresses (PAA) in the source block are read, and a global mapping table (GMT table) storing the physical addresses (PAA) of valid data is generated based on the logical addresses (LAA) of valid data in the P2L tables. That is, the LAAs of valid data in all P2L tables in the source block are traversed and converted into the corresponding PAAs through the mapping relationship to form a GMT table for recording PAAs. Then, the GMT table of valid data is marked in the valid bitmap. Subsequently, the physical addresses (PAA) of valid data can be found by scanning the marked GMT table in the valid bitmap, thereby locating the valid data. For example, the PAA of valid data in the GMT table is set to "1" at the corresponding position in the valid bitmap. In this way, scanning the valid bitmap can quickly locate the PAA (Personal Addresses) of all valid data, avoiding traversing the entire dataset, improving garbage collection efficiency, and preparing for subsequent data migration. The valid bitmap is a bitmap index structure where each bit corresponds to a physical address, and data validity can be quickly determined by the bit value (0 or 1). This enables rapid filtering of valid data.

[0077] S103: During the data migration process, if the current programming mode is a four-level storage unit mode, then during the first programming, the logical addresses and physical addresses of the valid data are stored in a pre-built temporary cache table, and the valid data is stored in the data cache area; the temporary cache table adopts a circular queue data structure, and each node of the temporary cache table stores a mapping relationship between a set of logical addresses and physical addresses;

[0078] It should be noted that during data migration, if the current programming mode is QLC mode, two programming operations—Coarse write and Fine write—are required to write the data into the NAND flash memory. In traditional processes, both programming writes require reading entries from the P2L table in the NAND flash memory, resulting in high read / write latency and low efficiency. In this embodiment of the invention, during the first programming (Coarse write), the logical and physical addresses of the valid data are stored in a pre-built temporary cache table, and the valid data is stored in the data cache area. The temporary cache table uses a circular queue data structure, and each node of the temporary cache table stores a mapping relationship between a set of logical and physical addresses.

[0079] S104: The address information of the temporary cache table is managed by an insertion pointer, a deletion pointer, and a data volume count pointer; the insertion pointer is used to record the number of address information newly added to the temporary cache table during the first programming; the deletion pointer is used to record the number of address information of programmed data after the second programming is written to the temporary cache table; and the data volume count pointer is used to record the number of address information of currently cached valid data in the temporary cache table.

[0080] In practice, the temporary cache table uses a circular queue and coordinates the address information (i.e., cached items) through an insertion pointer (InsertIdx), a deletion pointer (DeleteIdx), and a data volume count pointer (Num), thereby ensuring the sequential insertion and deletion of subsequent data. Specifically, the insertion pointer records the number of address information entries added to the temporary cache table during the first programming, the deletion pointer records the number of address information entries of data already programmed (i.e., written) after the second programming (Fine write), and the data volume count pointer records the number of address information entries of currently cached valid data in the temporary cache table. For example, at the start of data writing, the insertion pointer, deletion pointer, and data volume count pointer in the temporary cache table are all 0. Subsequently, during the data writing process, the insertion pointer records the number of data entries filled into the temporary cache table, the deletion pointer records the number of data entries that have been written after the second programming from the temporary cache table, and correspondingly, the data volume count pointer records the number of valid data entries cached from the temporary cache table. In this way, by inserting pointers, deleting pointers, and counting pointers, the address information in the temporary cache table can be dynamically recorded and updated.

[0081] S105: When the number of address information recorded by the insertion pointer reaches two levels of programming lines, the second programming is entered, the logical address and physical address address information of the recorded valid data are obtained from the temporary cache table, and the data corresponding to the address information in the data cache is written into the destination block;

[0082] In practice, when the number of address information recorded by the insertion pointer reaches two programming lines, the second programming phase begins. This involves retrieving the logical and physical addresses of the recorded valid data from the temporary cache table. Similarly, during this second programming phase, there's no need to repeatedly read data from the NAND flash memory; the logical and physical addresses of the recorded valid data can be directly retrieved from the temporary cache table. This allows the data corresponding to the address information in the data buffer to be directly written to the destination block. This reduces data read latency and improves the efficiency of data programming.

[0083] S106: Release the source block until all valid data in the source block has been moved to the destination block.

[0084] In practice, after the first and second programming operations are completed, the valid data can be programmed into the NAND flash memory. Then, the valid data in both the source and destination blocks can be updated. Subsequently, once all the valid data in the source block has been moved to the destination block, the source block can be released and added to the free list. This provides a favorable guarantee for subsequent data migration.

[0085] It's important to note that a single chip in a solid-state drive (SSD) can comprise multiple independent concurrent operation units (Dies). A die is the basic unit for executing flash memory commands. Only one read or write command can be executed simultaneously on a block within a die. Allowing more dies to work concurrently increases command parallelism, which in turn increases bandwidth for the SSD. Furthermore, a die can include multiple storage planes, a storage plane can include multiple storage blocks, a storage block can include multiple storage pages, and a storage page can include multiple storage cells. A storage page is the smallest unit of read / write operation in flash memory, and a storage block is the smallest unit of erase operation.

[0086] In practice, the storage structure of the solid-state drive (SSD) can be obtained to acquire its corresponding storage page layout information. Then, by combining this storage page layout information with the current programming progress, the storage page in which the current programming progress is located can be determined. For example, this determines the current programming progress's position within the storage page, the programming mode of that page, and so on.

[0087] In this embodiment of the invention, before writing data into a QLC physical block, the storage pages in the QLC physical block need to be laid out and divided, and then the corresponding programming mode is switched to program the data into the corresponding QLC physical block. For example... Figure 2 The diagram illustrates one possible partitioning of the storage page layout within a QLC physical block. During data migration, data needs to be written according to the storage page layout within the QLC physical block. Specifically, if the current writing programming mode is SLC or TLC, only one programming operation is required to write the data to the NAND flash memory (One Pass); if the current writing programming mode is QLC, two programming operations (Coarse Write and Fine Write) are required to write the data to the NAND flash memory (Two Pass). Of course, the specific partitioning method of the storage page layout within the QLC physical block can be set according to actual application needs, and is not limited here.

[0088] In embodiments of the present invention, such as Figure 3 As shown, step S104: managing the address information of the temporary cache table through insertion pointers, deletion pointers, and data volume count pointers, including:

[0089] S301: During the first programming, the insertion pointer and the data count pointer are incremented from zero until the address count of the two programming lines is reached, then the first programming is switched to the second programming, and the insertion pointer is cleared.

[0090] S302: During the second programming, the deletion pointer is incremented from zero until the data volume counter pointer is reduced from the number of addresses in two layers to the number of addresses in one layer. Then, the program switches to the first programming in the next round and the deletion pointer is cleared. This process is repeated until the data transfer is complete.

[0091] The following section, based on the writing principle of QLC NAND flash memory, combines... Figure 4 As shown, the processing mechanisms of the first programming (i.e., Coarse writing) and the second programming (i.e. Fine writing) in the embodiments of the present invention are explained in detail:

[0092] At the start of data writing, the insertion pointer, deletion pointer, and Num pointer in the temporary cache table are all 0. Subsequently, during the data writing process, the insertion pointer in the temporary cache table records the amount of data filled in the temporary cache table, and the deletion pointer records the amount of data that has been finely written from the temporary cache table.

[0093] During the Coarse write process, the storage system first retrieves valid data from the source block and records the LAA and PAA of this data in a temporary cache table. Then, the valid data is written from the data cache to the destination block until the temporary cache table records the data address information of the two programming lines. At the same time, the insertion pointer and Num pointer in the temporary cache table are counted from 0 to the amount of data in the two programming lines. Subsequently, the insertion pointer is cleared to zero, and the process transitions to the Fine write phase.

[0094] During a fine write, the system does not need to read valid data information from the NAND flash memory or filter valid data. Instead, it directly reads data from the source block into the data buffer based on the address information recorded in the temporary cache table, and then writes it to the destination block. This ensures data consistency and significantly improves the efficiency of data migration. Simultaneously, the storage system maintains a delete pointer, which counts from 0 up to the number of programming lines in the first layer. The Num pointer decreases sequentially based on the amount of data written until the number of remaining programming lines in the first layer is reached. Then, the delete pointer is reset to zero, and the process moves to the next coarse write. Throughout this process, coarse and fine writes cycle continuously until all valid data in the source block has been migrated. In practice, the insertion, deletion, and Num pointers in the temporary cache table can be used to determine whether a coarse or fine write is in progress.

[0095] In this embodiment of the invention, when writing data to QLC particles, it is necessary to ensure that all data is programmed twice (Two pass), that is, to complete the Coarse write and Fine write for all valid data in the source block before the source block can be released.

[0096] The following is combined Figure 5 The flowchart shown provides a detailed explanation of the entire process of the waste recycling mechanism in this embodiment of the invention.

[0097] S0: Start;

[0098] S1: Host data is written to the SLC physical block;

[0099] S2: Determine if the waterline for relocation has been reached;

[0100] If not, continue with step S1;

[0101] If yes, then proceed to step S3: retrieve the source block;

[0102] Specifically, iterate through all programmed physical blocks in the SLC and QLC physical block resource pools to find the physical block with the most invalid data. Based on the number of remaining physical blocks in the SLC and QLC physical block resource pools, select the corresponding physical block as the source block for this round of garbage collection.

[0103] S4: Request target block;

[0104] Specifically, iterate through the QLC physical block resource pool, find the youngest physical block that does not contain valid data, and use it as the target block.

[0105] S5: Filter valid data;

[0106] Specifically, the process involves reading all global tables (P2L tables) in the source block that store the mapping relationship between logical addresses (LAAs) and physical addresses (PAAs), and then converting the logical addresses of valid data in the P2L tables into a global mapping table (GMT table) that stores the physical addresses of the valid data. In other words, it iterates through all the LAAs of valid data in the P2L tables of the source block, converts them into their corresponding PAAs through the mapping relationship, and forms a GMT table for recording PAAs. Then, the GMT tables of valid data are marked in the valid bitmap. Subsequently, by scanning the marked GMT tables in the valid bitmap, the physical address (PAA) of the valid data can be found, thus locating the valid data.

[0107] S6: Data migration;

[0108] Specifically, determine whether the current programming mode being written is QLC mode;

[0109] If yes, then proceed to step A:

[0110] First, calculate the amount of data that can be moved in this round (denoted as ReadCnt) based on the size of the data buffer, and determine whether the data writing method in this round is Coarse write or Fine write;

[0111] Step B: Locate the physical addresses of the ReadCnt valid data entries by scanning the marked GMT table in the valid bit chart one by one;

[0112] Step C: Data reading and writing;

[0113] If the data writing method in this round is Coarse write, then ReadCnt data items are read from the source block into the data buffer based on the physical address. Subsequently, the physical and logical addresses of the ReadCnt data items are saved to a temporary cache table, and the insertion pointer of the temporary cache table is accumulated. Then, the ReadCnt data items in the data buffer are written to the destination block. Steps A to C are repeated until the insertion pointer in the temporary cache table reaches two levels of programming lines, at which point the Fine write stage can begin.

[0114] If the data writing method in this round is Fine write, then based on the physical and logical addresses recorded in the temporary cache table and the size of the data buffer, a maximum of ReadCnt data items are read into the data buffer each round. Subsequently, the number of pointers deleted and Num pointers in the temporary cache table is accumulated, and the number of inserted pointers and Num pointers is decremented. Step C is repeated until the Fine write reaches one programming line. Correspondingly, the number of inserted pointers in the temporary cache table reaches the amount of data for one programming line, at which point the process can switch to the next round of Coarse write.

[0115] Repeat steps A through C until all valid data in the source block has been moved.

[0116] S7: Data update;

[0117] Specifically, the data is programmed into the NAND flash memory only after the Coarse write and Fine write are completed, and then the amount of valid data in the source block and the destination block is updated.

[0118] S8: Erase source block;

[0119] Specifically, after all valid data in the source block has been moved to the destination block, the source block is added to the free list so that it can be used as the destination block for subsequent data moves. For example... Figure 6 As shown, in step S106: before releasing the source block after all the valid data in the source block has been moved to the destination block, the method further includes:

[0120] S601: If the last data of the source block does not fill the current layer of the destination block, then determine the baseline number of data units required for the current layer;

[0121] S602: Based on the baseline quantity, determine the amount of padding required to fill the remaining space of the target block; the amount of padding includes first invalid data for filling the current layer, and second invalid data for preparing for the first programming of the next layer; the first invalid data undergoes two programming operations, including the first programming and the second programming, and the second invalid data undergoes the first programming once; the amount of padding is (2*Dummy1+Dummy2); Dummy1 represents the first invalid data, and Dummy2 represents the second invalid data;

[0122] S603: Based on the filling amount, fill the data buffer with specific data and flush the specific data to the destination block.

[0123] In the specific implementation process, steps S601 to S603 are implemented as follows:

[0124] After moving data from the source block, if the last piece of data fails to fill the current layer of the destination block, a data padding mechanism is triggered until the current layer of the destination block containing the last piece of data is complete, thus ensuring data stability. Specifically, the baseline number of data units required for the current layer is determined; the baseline number of data units required for each programming line of a different SSD capacity varies. Then, based on the baseline number, the padding amount needed to fill the remaining space of the destination block is determined; this padding amount includes first invalid data used to fill the current layer, and second invalid data used to prepare for the first programming of the next layer; the first invalid data undergoes two programming processes (first and second programming), while the second invalid data undergoes one first programming process. Figure 7 The source block is shown as the destination block after it has been moved, where, Figure 7 The shaded area represents the portion that needs to be filled with invalid data (Dummy). Since the first invalid data (Dummy1) needs to be written twice—once with a Coarse write and once with a Fine write—this invalid data needs to be calculated twice. Because a Fine write can only be performed after two levels of Coarse writing, for the current garbage-collected source block, the second invalid data (Dummy2) only undergoes a Coarse write. However, its temporary cache table still records the InsertIdx pointer of the current Coarse write, waiting for the garbage collector to select the next source block before performing a Coarse write and writing it to another level of programming. Only when the InsertIdx pointer in its temporary cache table satisfies two levels of programming can a Fine write be performed again. Therefore, for the current invalid data filling process, the second invalid data only needs to be calculated once. In this way, after moving data from the source block, if the last piece of data fails to fill the current level of the destination block, the remaining space of the destination block is filled. The total amount of filling required to fill the remaining space of the destination block (denoted as Dummy Cnt) needs to satisfy the following formula:

[0125] Dummy Cnt=2*Dummy1+Dummy2;

[0126] Wherein, Dummy Cnt represents the total amount of fill required to complete the remaining space of the target block, Dummy1 represents the first invalid data, and Dummy2 represents the second invalid data.

[0127] Then, based on the determined fill amount, specific data is filled into the data buffer and flushed to the destination block.

[0128] Still combined Figure 7 The exemplary embodiment shown provides a detailed explanation of the specific implementation process of the data filling mechanism:

[0129] First, fill in the invalid data in the current layer. Specifically, when Coarse writes the last piece of data into the third programming unit in the last programming line, it does not meet the requirement of a programming line. In this case, to fill in the current layer, we need to calculate the amount of invalid data to fill the remaining three programming units, i.e., Dummy1.

[0130] It's important to note that for Coarse write operations, valid data must first be read into the data buffer. Then, the logical and physical addresses of the valid data are maintained in a temporary cache table, along with the InsertIdx and Num pointers in the temporary cache table. However, when maintaining invalid data in the garbage collection mechanism, it's only necessary to maintain the logical and physical addresses of the invalid data in the temporary cache table and mark it as invalid. Simultaneously, based on the amount of invalid data, the corresponding InsertIdx and Num pointers in the temporary cache table are updated. After maintaining the temporary cache table, a write request is issued. In this way, when handling invalid data, specific data is filled into the data buffer based on the calculated fill amount; subsequently, this specific data is flushed to the NAND flash memory, thus completing the programming line of the current layer.

[0131] Due to the data movement requirements of the garbage collection mechanism, two layers of coarse writes are necessary before fine writes can be performed. Therefore, in Figure 7 In the exemplary embodiment shown, a coarse write of invalid data for one programming line (including 6 programming units), namely Dummy2, is also required. Simultaneously, the logical and physical addresses of Dummy2 need to be stored in a temporary cache table, and these addresses are marked as invalid. Furthermore, the InsertIdx and Num pointers in the temporary cache table need to be maintained to reflect the number of programming lines in both layers. After the temporary cache table is maintained, a write request is issued. In this way, when processing invalid data, specific data is filled into the data buffer based on the calculated fill amount; subsequently, this specific data is flushed to the NAND flash memory, thus completing the coarse write of this programming line.

[0132] It should be noted that after the Coarse write operation completes two programming lines, it can switch to Fine write. During Fine write, ReadCnt valid data entries are first read into the data buffer based on the logical and physical addresses in the temporary cache table. ReadCnt represents the amount of data that can be moved in this round, determined by the size of the data buffer. If invalid logical and physical addresses exist in the temporary cache table, specific data needs to be filled into the corresponding positions in the data buffer to replace the invalid data. Then, the data in the data buffer can be flushed to the NAND flash memory until the first programming line (i.e., Dummy1) data writing is completed.

[0133] It should be noted that, in this embodiment of the invention, through the data filling mechanism, each valid data block must be programmed twice during the writing process of QLC particles (i.e., first a Coarse write, then a Fine write). This process must be completed before the source block is released, and the programming layer must also maintain alignment, thereby ensuring data integrity and reliability. In this way, it is ensured that all data will not be released prematurely before programming is completed, thus reducing the risk of data loss or corruption and optimizing the performance and stability of the storage system.

[0134] In this embodiment of the invention, step S601: If the last data of the source block does not fill the current layer of the destination block, then determine the baseline number of data units required for the current layer, including:

[0135] The reference quantity is determined using the following formula:

[0136] AU_num=WL_AU*WL_Page*WL_Cnt*Die_Cnt*CH_cnt;

[0137] Wherein, AU_num represents the base number, WL_AU represents the number of minimum data units included in each programming unit, WL_Page represents the number of storage pages included in each programming unit, WL_Cnt represents the number of programming units included in each independent concurrent operation unit, Die_Cnt represents the number of independent concurrent operation units, and CH_cnt represents the number of storage channels.

[0138] In this embodiment of the invention, during the data movement process in the garbage collection mechanism, when writing data to the destination block, it is necessary to first check the status of the data read from the source block into the data buffer. If the status is incorrect, it indicates that the current data read has failed, and the read failure handling mechanism is entered. Specifically, as follows... Figure 8As shown, in step S103: During the data transfer process, if the current programming mode is a four-level storage unit mode, then during the first programming, the logical addresses and physical addresses of the valid data are stored in a pre-built temporary cache table, and after the valid data is stored in the data cache area, the method further includes:

[0139] S801: During the first programming process, the read status of each piece of data stored in the data buffer is detected;

[0140] S802: If the read status of some data in the data buffer is an error status, then record the logical address corresponding to the data in the error status;

[0141] S803: Traverse the temporary cache table and find the index number corresponding to the logical address;

[0142] S804: Move each node of the record logical address and physical address in the temporary cache table from the index number forward one by one, and move the node of the record logical address and physical address corresponding to the index number to the end of the temporary cache table as the last node, to obtain the adjusted temporary cache table.

[0143] In the specific implementation process, combined with Figure 9 The flowchart shown below explains the specific implementation process of steps S801 to S804:

[0144] S91: Query read status; specifically, during the initial programming process, the read status of each piece of data stored in the data buffer is checked. For example, during a Coarse write, the system checks the read status of ReadCnt data items and counts the number of successfully read data items (denoted as WriteCnt). If a read failure occurs, the system records the corresponding logical address and iterates through the temporary cache table based on that logical address to find the index number (denoted as idx) corresponding to the logical address where the read failed. During a Fine write, there is no need to check the read status of ReadCnt data items; the data in the data buffer is directly flushed to the NAND flash memory. This ensures data consistency between Coarse and Fine writes, guaranteeing data integrity.

[0145] S92: Adjust the temporary cache table; specifically, for Coarse writes, move each record's logical and physical address nodes from index number idx onwards in the temporary cache table forward one by one, while the node containing the logical and physical addresses of the failed read data at the original index number idx is moved to the end of the temporary cache table as the last node. Simultaneously, mark the node with index number idx in the temporary cache table as invalid. This process is not executed for One Pass or Fine writes.

[0146] S93: Submit a write request; specifically, for a Coarse write, the write request is submitted based on WriteCnt. When there is read failure data but not all of it is failure data (i.e., some data in the data buffer is in an error state, and WriteCnt is not 0), the system will fill WriteCnt data to satisfy one write cycle (programming unit) required for the write request; then, it will be programmed and written into the NAND. When all data is read failure data (i.e., all data in the data buffer is in an error state, and WriteCnt is 0), the logical and physical addresses recorded for the read failure data in the temporary cache table are deleted, and the InsertIdx pointer and Num pointer are backed up by ReadCnt positions to reread ReadCnt data from the source block to the data buffer, avoiding the waste of space resources caused by continuing to fill specific data into the destination block due to unsuccessful reading of normal data; for a Fine write, the write request is submitted directly to the data in the data buffer.

[0147] In this embodiment of the invention, if a programming failure occurs while valid data from the source block is being transferred to the destination block during garbage collection or data migration, the following measures can be taken to ensure data integrity and system stability. For example, such as... Figure 10 As shown, if a programming failure is detected during the process of moving valid data from the source block to the destination block, the method further includes:

[0148] S1001: Clear the temporary cache table;

[0149] S1002: Mark the target block as closed and remove the target block from the candidate pool;

[0150] S1003: Clean up the physical-to-logical mapping table of the memory corresponding to the target block; the physical-to-logical mapping table is used to store the logical addresses of all data in the memory and the corresponding physical addresses;

[0151] S1004: If the target block cannot be replaced, mark its physical block as a bad block;

[0152] S1005: Release the resources used by this round of waste recycling mechanism.

[0153] In the specific implementation process, steps S1001 to S1005 are implemented as follows:

[0154] For example, the temporary cache table can be cleared; specifically, the physical address, logical address, insertion pointer, deletion pointer, and count pointer of the data stored in the currently used temporary cache table are all cleared. If there is padding data, the recorded padding data count (i.e., the aforementioned Total Dummy Cnt) is also cleared.

[0155] For example, one could wait for data synchronization to complete; specifically, if previous data has been written to the NAND flash memory, but its corresponding entry has not yet been synchronized, then the synchronization process for that entry must be completed. Once completed, the synchronization process for the currently programming-failed data entry is skipped to prevent abnormal data from being recorded in valid data entries.

[0156] For example, the physical-to-logical (P2L) mapping table on the data buffer can also be cleared. Specifically, when writing to a target block, the P2L mapping table of its corresponding Bank physical block needs to be loaded into the data buffer to update the logical address of the written data. Therefore, when a programming failure occurs, the P2L mapping table of the target block on the data buffer needs to be cleared to release the space occupied by the data buffer and avoid wasting space.

[0157] For example, the physical block candidate pool can also be removed; specifically, the target block where the programming failure occurred is removed from the physical block candidate pool to prevent write operations from continuing to be performed on the target block on the next write operation.

[0158] For example, the status of the target block can also be marked; specifically, the target block where programming failure occurs can be marked as "closed" and submitted to the garbage collection mechanism, which moves the data waiting to be written to it to other physical blocks, thereby improving the data stability of the system.

[0159] For example, this could also involve releasing resources from the current garbage collection process. Specifically, if a programming failure occurs during data migration in the current garbage collection mechanism, the current garbage collection process needs to be terminated, and the resources occupied by the current garbage collection process need to be released, such as data cache and write bandwidth. Simultaneously, the state of the source block in the current garbage collection process needs to be set to the closed state to stop data migration, awaiting subsequent data migration.

[0160] For example, a bad block replacement process could be added; specifically, after the subsequent garbage collection process has moved the valid data from the failed physical block, the physical block needs to be added to the bad block replacement process. If the physical block cannot be replaced by a bad block, then the entire super-large physical block needs to be marked as a bad block.

[0161] It should be noted that this embodiment of the invention also provides a fault detection and response mechanism. Specifically, automatic fault detection technology is integrated into the data migration process. During garbage collection, when the system detects an error while reading the source block, it triggers a garbage collection read failure mechanism, performing different processing operations based on the current write mode. Similarly, if a programming failure occurs while writing the destination block, the system activates the garbage collection programming failure mechanism, recording the fault and implementing remedial measures accordingly, such as marking the currently written data as invalid. In this way, these mechanisms not only ensure data consistency and integrity during data migration by promptly marking damaged or invalid data, but also ensure that the system can quickly recover from sudden failures through proactive exception handling mechanisms, avoiding data loss and enhancing data reliability.

[0162] Based on the same inventive concept, such as Figure 11 As shown, this embodiment of the invention provides a data writing device for a solid-state drive (SSD), the SSD including multiple single-level storage unit physical blocks and multiple four-level storage unit physical blocks; the device includes:

[0163] The triggering unit 10 is used to trigger the garbage collection mechanism if the plurality of single-level storage unit physical blocks are consumed to the corresponding critical waterline, or if the plurality of four-level storage unit physical blocks are consumed to the corresponding critical waterline.

[0164] The determining unit 20 is used to determine a source block from the plurality of single-level storage unit physical blocks and the plurality of four-level storage unit physical blocks, and to determine a destination block from the plurality of four-level storage unit physical blocks, and to move the valid data in the source block to the destination block;

[0165] Storage unit 30 is used to store the logical addresses and physical addresses of the valid data into a pre-built temporary cache table and store the valid data into the data cache area during the first programming if the current programming mode is a four-level storage unit mode during the data transfer process. The temporary cache table adopts a circular queue data structure, and each node of the temporary cache table stores a mapping relationship between a set of logical addresses and physical addresses.

[0166] The management unit 40 is used to manage the address information of the temporary cache table through an insertion pointer, a deletion pointer, and a data volume count pointer; the insertion pointer is used to record the number of address information newly added to the temporary cache table during the first programming; the deletion pointer is used to record the number of address information of programmed data after the second programming is written to the temporary cache table; and the data volume count pointer is used to record the number of address information of currently cached valid data in the temporary cache table.

[0167] The writing unit 50 is used to enter the second programming when the number of address information recorded by the insertion pointer reaches two levels of programming lines, to obtain the logical address and physical address information of the recorded valid data from the temporary cache table, and to write the data corresponding to the address information in the data cache area into the destination block;

[0168] Release unit 60 is used to release the source block until all the valid data in the source block has been moved to the destination block.

[0169] In this embodiment of the invention, the management unit 40 is used for:

[0170] During the first programming, the insertion pointer and the data count pointer are incremented from zero until the address count of the two programming lines is reached. Then, the program transitions from the first programming to the second programming, and the insertion pointer is cleared.

[0171] During the second programming, the deletion pointer is incremented from zero until the data volume counter pointer is reduced from the number of addresses in two layers to the number of addresses in one layer. Then, the program switches to the first programming round and the deletion pointer is cleared. This process is repeated until the data transfer is complete.

[0172] In this embodiment of the invention, before releasing the source block after all valid data in the source block has been moved to the destination block, the apparatus further includes a filling unit, the filling unit being used for:

[0173] If the last data in the source block does not fill the current layer of the destination block, then determine the baseline number of data units required for the current layer.

[0174] Based on the baseline quantity, determine the amount of padding required to fill the remaining space of the target block; the padding amount includes first invalid data for filling the current layer, and second invalid data for preparing for the first programming of the next layer; the first invalid data undergoes two programming processes, including the first programming and the second programming, and the second invalid data undergoes the first programming once; the padding amount is (2*Dummy1+Dummy2); Dummy1 represents the first invalid data, and Dummy2 represents the second invalid data;

[0175] Based on the filling amount, specific data is filled into the data buffer and then flushed to the destination block.

[0176] In this embodiment of the invention, the filling unit is used for:

[0177] The reference quantity is determined using the following formula:

[0178] AU_num=WL_AU*WL_Page*WL_Cnt*Die_Cnt*CH_cnt;

[0179] Wherein, AU_num represents the base number, WL_AU represents the number of minimum data units included in each programming unit, WL_Page represents the number of storage pages included in each programming unit, WL_Cnt represents the number of programming units included in each independent concurrent operation unit, Die_Cnt represents the number of independent concurrent operation units, and CH_cnt represents the number of storage channels.

[0180] In this embodiment of the invention, after storing the logical addresses and physical addresses of the valid data into a pre-built temporary cache table and storing the valid data into a data cache area during the first programming, the device further includes a first processing unit, the first processing unit being used for:

[0181] During the first programming process, the read status of each piece of data stored in the data buffer is detected;

[0182] If the read status of some data in the data buffer is an error status, then the logical address corresponding to the data in the error status is recorded;

[0183] Traverse the temporary cache table to find the index number corresponding to the logical address;

[0184] Move each node in the temporary cache table that records the logical address and physical address after the index number forward one by one, and move the node that records the logical address and physical address corresponding to the index number to the end of the temporary cache table as the last node, thus obtaining the adjusted temporary cache table.

[0185] In this embodiment of the invention, after detecting the read status of each piece of data stored in the data buffer, the first processing unit is further configured to:

[0186] If the read status of all data in the data cache is the error status, then the logical address and physical address recorded for the data in the error status in the temporary cache table are deleted, and the insertion pointer and the data volume count pointer are pushed back to a preset number of positions, so as to reread the preset number of data from the source block to the data cache; the preset number is the amount of data that can be moved in this round based on the size of the data cache.

[0187] In this embodiment of the invention, if a programming failure is detected during the process of transferring valid data from the source block to the destination block, the device further includes a second processing unit, the second processing unit being used to:

[0188] Clear the temporary cache table;

[0189] The target block is marked as closed, and the target block is removed from the candidate pool;

[0190] Clean up the physical-to-logical mapping table of the memory corresponding to the target block; the physical-to-logical mapping table is used to store the logical addresses of all data in the memory and the corresponding physical addresses;

[0191] If the target block cannot be replaced, then the physical block to which it belongs is marked as a bad block;

[0192] Release the resources occupied by this round of waste recycling mechanism.

[0193] Based on the same inventive concept, this invention also provides an electronic device that can achieve the aforementioned... Figure 11 For the functions of each module, please refer to [link / reference]. Figure 12 The electronic device includes:

[0194] Memory 100 is used to store computer programs;

[0195] When the processor 200 executes a computer program stored in the memory, it implements the steps of the solid-state drive data writing method as described in any of the preceding items.

[0196] In this embodiment of the invention, the specific connection medium between the processor 200 and the memory 100 is not limited. Figure 11 The example shown is the connection between processor 200 and memory 100 via bus 300. Bus 300 is... Figure 11 The connections between other components are indicated by thick lines and are for illustrative purposes only, not as limiting information. Bus 300 can be divided into address bus, data bus, control bus, etc., for ease of representation. Figure 11 The 300 is represented by a single thick line, but this does not mean that there is only one bus 300 or one type of bus 300. Alternatively, the processor 200 may also be called a controller; there is no restriction on the name.

[0197] In this embodiment of the invention, the memory 100 stores instructions that can be executed by the processor 200. When the processor 200 executes the computer program stored in the memory 100, it can execute the data writing method for the solid-state drive discussed above. The processor 200 can implement... Figure 10 The functions of each module are shown.

[0198] The processor 200 is the control center of the device. It can connect to various parts of the entire control device through various interfaces and lines. By running or executing computer programs stored in the memory 100 and calling data stored in the memory 100, it can monitor the various functions and data processing of the device as a whole.

[0199] In one possible design, processor 200 may include one or more processing units. Processor 200 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. In some embodiments, processor 200 and memory 100 may be implemented on the same chip; in some embodiments, they may also be implemented on separate chips.

[0200] Memory 100, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory 100 may include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic storage, magnetic disk, optical disk, etc. Alternatively, memory 100 may be any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited thereto. In embodiments of the present invention, memory 100 may also be a circuit or any other device capable of implementing storage functions for storing program instructions and / or data.

[0201] By designing and programming the processor, the code corresponding to the solid-state drive data writing method described in the foregoing embodiments can be embedded into the chip, enabling the chip to execute the steps of the solid-state drive data writing method discussed above during operation. How to design and program the processor is a technique well-known to those skilled in the art and will not be elaborated upon here.

[0202] Based on the same inventive concept, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, the computer program being used to cause a computer to execute the data writing method steps of the solid-state drive discussed above.

[0203] In some possible implementations, various aspects of the solid-state drive-based data writing method provided by the present invention can also be implemented in the form of a program product, which includes program code that, when the program product is run on a device, causes the control device to perform the steps in the solid-state drive data writing method according to various exemplary embodiments of the present invention described above.

[0204] This invention provides a data writing method, apparatus, and electronic device for a solid-state drive (SSD). If multiple single-level storage unit physical blocks in the SSD are consumed to their corresponding critical waterline, or if multiple four-level storage unit physical blocks in the SSD are consumed to their critical waterline, a garbage collection mechanism is triggered. Then, a source block is determined from the multiple single-level and multiple four-level storage unit physical blocks, and a destination block is determined from the multiple four-level storage unit physical blocks. Valid data from the source block is moved to the destination block. During the data movement process, if the current writing programming mode is four-level storage... In the cell mode, during the first programming iteration, the logical and physical addresses of the valid data are stored in a pre-built temporary cache table, and the valid data is stored in the data cache area. The temporary cache table adopts a circular queue data structure, and each node of the temporary cache table stores a mapping relationship between a set of logical and physical addresses. That is to say, during the data migration process, if the current programming mode is a four-level storage cell mode, during the first programming iteration, the temporary cache table built with a circular queue is used to cache the logical and physical addresses of the valid data read from the source block.

[0205] Then, the address information of the temporary cache table is managed through insertion pointers, deletion pointers, and data volume count pointers. The insertion pointer records the number of address information entries added to the temporary cache table during the first programming iteration; the deletion pointer records the number of address information entries for programmed data after the second programming iteration; and the data volume count pointer records the number of address information entries for currently cached valid data in the temporary cache table. When the number of address information entries recorded by the insertion pointer reaches two programming lines, the second programming iteration begins. The logical and physical address information of the recorded valid data is retrieved from the temporary cache table, and the data corresponding to the address information in the data buffer is written to the destination block. This process continues until all valid data in the source block is moved to the destination block, at which point the source block is released. In other words, during the second programming iteration, the logical and physical address information of the recorded valid data can be directly retrieved from the temporary cache table. This eliminates the need to repeatedly read data from the NAND flash memory during the second programming iteration; the logical and physical address information of the recorded valid data can be directly retrieved from the temporary cache table, and the data corresponding to the address information in the data buffer can then be written to the destination block. This reduces data read latency and improves data programming efficiency; at the same time, it reduces the number of NAND flash memory read operations, extending the lifespan of NAND flash memory; it also improves data migration speed and overall system responsiveness, optimizing the efficiency of data programming and access; especially during large-scale data migration, it significantly improves performance.

[0206] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0207] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0208] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0209] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0210] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for writing data to a solid-state drive, characterized in that, The solid-state drive includes multiple single-level storage unit physical blocks and multiple four-level storage unit physical blocks; the method includes: If the plurality of single-level storage unit physical blocks are consumed to the corresponding critical waterline, or if the plurality of four-level storage unit physical blocks are consumed to the corresponding critical waterline, then the garbage collection mechanism is triggered. A source block is determined from the plurality of single-level storage cell physical blocks and the plurality of four-level storage cell physical blocks, and a destination block is determined from the plurality of four-level storage cell physical blocks, and valid data in the source block is moved to the destination block; During the data migration process, if the current programming mode is a four-level storage unit mode, then during the first programming, the logical addresses and physical addresses of the valid data are stored in a pre-built temporary cache table, and the valid data is stored in the data cache area; the temporary cache table adopts a circular queue data structure, and each node of the temporary cache table stores a mapping relationship between a set of logical addresses and physical addresses; The address information of the temporary cache table is managed by an insertion pointer, a deletion pointer, and a data volume count pointer; the insertion pointer is used to record the number of address information newly added to the temporary cache table during the first programming; the deletion pointer is used to record the number of address information of programmed data after the second programming is written to the temporary cache table; and the data volume count pointer is used to record the number of address information of currently cached valid data in the temporary cache table. When the number of address information recorded by the insertion pointer reaches two levels of programming lines, the second programming is initiated. The logical address and physical address information of the recorded valid data are obtained from the temporary cache table, and the data corresponding to the address information in the data cache is written into the destination block. The source block is released once all valid data in the source block has been moved to the destination block. The method further includes, after storing the logical and physical addresses of the valid data into a pre-built temporary cache table and storing the valid data into a data cache area during the first programming, the method also includes: During the first programming process, the read status of each piece of data stored in the data buffer is detected; If the read status of some data in the data buffer is an error status, then the logical address corresponding to the data in the error status is recorded; Traverse the temporary cache table to find the index number corresponding to the logical address; Move each node in the temporary cache table that records the logical address and physical address after the index number forward one by one, and move the node that records the logical address and physical address corresponding to the index number to the end of the temporary cache table as the last node, thus obtaining the adjusted temporary cache table.

2. The method as described in claim 1, characterized in that, The method of managing the address information of the temporary cache table through insertion pointers, deletion pointers, and data volume count pointers includes: During the first programming, the insertion pointer and the data count pointer are incremented from zero until the address count of the two programming lines is reached. Then, the program transitions from the first programming to the second programming, and the insertion pointer is cleared. During the second programming, the deletion pointer is incremented from zero until the data volume counter pointer is reduced from the number of addresses in two layers to the number of addresses in one layer. Then, the program switches to the first programming round and the deletion pointer is cleared. This process is repeated until the data transfer is complete.

3. The method as described in claim 1 or 2, characterized in that, Before releasing the source block after all valid data in the source block has been moved to the destination block, the method further includes: If the last data entry of the source block does not fill the current layer of the destination block, then determine the baseline number of data units required for the current layer; Based on the baseline quantity, determine the amount of filler required to complete the remaining space of the target block; the filler includes first invalid data for completing the current layer, and second invalid data for preparing for the first programming of the next layer; the first invalid data undergoes two programming processes, including the first programming and the second programming, and the second invalid data undergoes one first programming process; the filler is (2 (Dummy1 + Dummy2); Dummy1 represents the first invalid data, and Dummy2 represents the second invalid data. Based on the filling amount, specific data is filled into the data buffer and then flushed to the destination block.

4. The method as described in claim 3, characterized in that, Determining the baseline number of data units required for the current layer includes: The reference quantity is determined using the following formula: AU_num=WL_AU WL_Page WL_Cnt The_Cnt CH_ctn; Wherein, AU_num represents the base number, WL_AU represents the number of minimum data units included in each programming unit, WL_Page represents the number of storage pages included in each programming unit, WL_Cnt represents the number of programming units included in each independent concurrent operation unit, Die_Cnt represents the number of independent concurrent operation units, and CH_cnt represents the number of storage channels.

5. The method as described in claim 1, characterized in that, After detecting the read status of each piece of data stored in the data buffer, the method further includes: If the read status of all data in the data cache is the error status, then the logical address and physical address recorded for the data in the error status in the temporary cache table are deleted, and the insertion pointer and the data volume count pointer are pushed back to a preset number of positions, so as to reread the preset number of data from the source block to the data cache; the preset number is the amount of data that can be moved in this round based on the size of the data cache.

6. The method as described in claim 1, characterized in that, If a programming failure is detected during the process of moving valid data from the source block to the destination block, the method further includes: Clear the temporary cache table; The target block is marked as closed, and the target block is removed from the candidate pool; Clean up the physical-to-logical mapping table of the memory corresponding to the target block; the physical-to-logical mapping table is used to store the logical addresses of all data in the memory and the corresponding physical addresses; If the target block cannot be replaced, then the physical block to which it belongs is marked as a bad block; Release the resources occupied by this round of waste recycling mechanism.

7. A data writing device for a solid-state drive, characterized in that, The solid-state drive includes multiple single-level storage unit physical blocks and multiple four-level storage unit physical blocks; the device includes: The triggering unit is used to trigger the garbage collection mechanism if the plurality of single-level storage unit physical blocks are consumed to the corresponding critical waterline, or if the plurality of four-level storage unit physical blocks are consumed to the corresponding critical waterline. A determining unit is used to determine a source block from the plurality of single-level storage unit physical blocks and the plurality of four-level storage unit physical blocks, and to determine a destination block from the plurality of four-level storage unit physical blocks, and to move the valid data in the source block to the destination block; a storing unit is used, during the data moving process, if the current writing programming mode is a four-level storage unit mode, to store each set of logical addresses and physical addresses of the valid data into a pre-built temporary cache table during the first programming, and to store the valid data into a data cache area; the temporary cache table adopts a circular queue data structure, and each node of the temporary cache table stores a set of logical address and physical address mapping relationships; The management unit is used to manage the address information of the temporary cache table through an insertion pointer, a deletion pointer, and a data volume count pointer; the insertion pointer is used to record the number of address information newly added to the temporary cache table during the first programming; the deletion pointer is used to record the number of address information of programmed data after the second programming is written to the temporary cache table; and the data volume count pointer is used to record the number of address information of currently cached valid data in the temporary cache table. The writing unit is used to enter the second programming when the number of address information recorded by the insertion pointer reaches two levels of programming lines, to obtain the logical address and physical address information of the recorded valid data from the temporary cache table, and to write the data corresponding to the address information in the data cache area into the destination block; A release unit is configured to release the source block once all valid data in the source block has been moved to the destination block. Wherein, during the first programming, after storing the logical addresses and physical addresses of the valid data into a pre-constructed temporary cache table and storing the valid data into a data cache area, the device further includes a first processing unit, the first processing unit being used for: During the first programming process, the read status of each piece of data stored in the data buffer is detected; If the read status of some data in the data buffer is an error status, then the logical address corresponding to the data in the error status is recorded; Traverse the temporary cache table to find the index number corresponding to the logical address; Move each node in the temporary cache table that records the logical address and physical address after the index number forward one by one, and move the node that records the logical address and physical address corresponding to the index number to the end of the temporary cache table as the last node, thus obtaining the adjusted temporary cache table.

8. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, when executing a computer program stored in the memory, implements the method steps as described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that causes a computer to perform the method steps as described in any one of claims 1-6.

10. A computer program product, characterized in that, The computer program product includes: computer program code, which, when run on a computer, causes the computer to perform the method described in any one of claims 1-6.

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