Storage system and storage method

Abstract

The embodiment of the invention relates to the field of storage device application, and discloses a storage system and a storage method, a field programmable gate array sends first data to a main controller through an IO interface, and / or receives second data sent by the main controller, and the main controller receives the first data through a data channel module, and / or receives the second data through a data channel module. Second data is sent to the field programmable gate array, and the data channel module communicates with the IO interface through a flash memory interface protocol; the main controller in the application can replace an SoC and an external storage device thereof in the existing scheme, and a storage function in the SoC does not need to be developed independently, so that the hardware design complexity and the overall cost of the system are reduced; compared with the prior art, the field programmable gate array adopts the common IO interface instead of the PCIe interface, and compared with a field programmable gate array supporting PCIe, the field programmable gate array adopting the common IO interface is lower in cost, so that the system hardware cost is reduced.

Description

Technical Field

[0001] This application relates to the field of storage device applications, and in particular to a storage system and storage method. Background Technology

[0002] A Field-Programmable Gate Array (FPGA) is a programmable integrated circuit chip that can be configured by users using a hardware description language to implement specific digital logic functions. FPGAs can acquire data, and in high-speed data storage scenarios, the data acquired by the FPGA needs to be transmitted to storage devices for storage.

[0003] Currently, systems for achieving high-speed data storage include the following: In the first type of storage system, the FPGA transmits data to the system-on-chip (SoC) via the Peripheral Component Interconnect Express (PCIe) interface, and then the SoC stores the data to an external storage device.

[0004] In the second type of storage system, the FPGA directly transmits data to the storage device via the PCIe interface.

[0005] In the third type of storage system, the FPGA transmits data to the PCIe switch chip via the PCIe interface, and the PCIe switch chip then stores the data in different storage devices.

[0006] In the process of developing this application, the inventors discovered at least the following problems in the prior art: In the first type of storage system, the SoC needs to be connected to an external storage device to realize data storage, which increases the hardware design complexity and cost of the system; In the above three types of storage systems, the FPGA realizes high-speed data transmission through the PCIe interface. The PCIe interface is a dedicated high-speed serial interface. Compared with FPGAs that support ordinary interfaces, FPGAs that support PCIe are more expensive, increasing the system hardware cost. Summary of the Invention

[0007] The embodiments of this application aim to provide a storage system and storage method to reduce the hardware design complexity and overall cost of the system.

[0008] The embodiments of this application provide the following technical solutions: In a first aspect, embodiments of this application provide a storage system including a field-programmable gate array (FPGA) and a main controller. The FPGA includes an I / O interface, and the main controller includes a data channel module. The data channel module and the I / O interface communicate via a flash memory interface protocol. The field-programmable gate array (FPGA) sends first data to the main controller via the I / O interface, and / or receives second data sent by the main controller. The main controller receives the first data through the data channel module and / or sends the second data to the field programmable gate array.

[0009] In a second aspect, embodiments of this application provide a storage method applied to a storage system of the first aspect. The storage system includes a field-programmable gate array (FPGA) and a main controller. The FPGA includes an I / O interface, and the main controller includes a data channel module. The data channel module and the I / O interface communicate via a flash memory interface protocol. The storage method includes: The first data is sent to the main controller via the I / O interface of the field-programmable gate array, and the first data is received via the data channel module of the main controller. And / or, based on the data channel module of the main controller, send the second data to the field programmable gate array, and receive the second data based on the IO interface of the field programmable gate array to store the second data in the field programmable gate array.

[0010] Thirdly, embodiments of this application also provide a non-volatile computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, cause the processor to perform the storage method as described in the second aspect.

[0011] Fourthly, embodiments of this application provide a computer program product, which includes instructions or a program that, when executed by a processor, causes the processor to execute the computer program of the storage method of the second aspect.

[0012] The beneficial effects of the embodiments of this application are as follows: Unlike the prior art, the embodiments of this application provide a storage system comprising a field-programmable gate array (FPGA) and a main controller. The FPGA includes an I / O interface, and the main controller includes a data channel module. The data channel module and the I / O interface communicate via a flash memory interface protocol. Specifically, the FPGA sends first data to the main controller via the I / O interface and / or receives and stores second data sent by the main controller; the main controller receives the first data via the data channel module and / or sends the second data to the FPGA.

[0013] The system uses a field-programmable gate array (FPGA) to send first data to the main controller via an I / O interface, and / or to receive and store second data sent by the main controller. The main controller receives the first data and / or sends the second data to the FPGA via a data channel module. The data channel module communicates with the I / O interface via a flash memory interface protocol. On the one hand, the main controller in this application can replace the SoC and its external storage device in existing solutions, eliminating the need to develop storage functions in the SoC separately, thereby reducing the hardware design complexity and overall cost of the system. On the other hand, the FPGA in this application uses a common I / O interface instead of a PCIe interface. Compared with FPGAs that support PCIe, FPGAs using a common I / O interface are cheaper, thereby reducing the system hardware cost. Attached Figure Description

[0014] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0015] Figure 1 This is a schematic diagram of the structure of the first storage system provided in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the second storage system provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of the third storage system provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of the fourth storage system provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of a data channel module provided in an embodiment of this application; Figure 6 This is a schematic diagram of a field-programmable gate array (FPGA) provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a high-speed channel module provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a high-speed interface module provided in an embodiment of this application; Figure 9 This is a detailed structural schematic diagram of a field-programmable gate array provided in an embodiment of this application; Figure 10 This is a flowchart illustrating an embodiment of adjusting input delay parameters provided in this application; Figure 11 This is a schematic diagram of a second window provided in an embodiment of this application; Figure 12 This is a flowchart illustrating an embodiment of adjusting output delay parameters provided in this application; Figure 13 This is a timing diagram of the control signals when a main controller reads the first data in a field-programmable gate array, according to an embodiment of this application. Figure 14 This is a timing diagram of the control signals when a main controller writes second data to a field-programmable gate array, provided in an embodiment of this application. Figure 15 This is a schematic diagram of a main controller reading first data according to an embodiment of this application; Figure 16 This is a schematic diagram illustrating how second data is written into a field-programmable gate array according to an embodiment of this application; Figure 17 This is a schematic diagram of the structure of the fifth storage system provided in the embodiments of this application; Figure 18 This is a timing diagram of the control signals when the main controller issues a second write command to the flash memory chip array, provided in an embodiment of this application; Figure 19 This is a timing diagram of the control signals when the main controller sends an address to the flash memory chip array, provided in an embodiment of this application. Figure 20 This is a timing diagram of control signals when writing first data to a flash memory chip array, provided in an embodiment of this application. Figure 21 This is a schematic diagram of writing first data into a flash memory chip array according to an embodiment of this application; Figure 22 This is a detailed structural diagram of the sixth storage system provided in the embodiments of this application; Figure 23 This is a detailed structural diagram of the seventh storage system provided in the embodiments of this application; Figure 24 This is a detailed structural diagram of the eighth storage system provided in the embodiments of this application; Figure 25 This is a detailed structural diagram of a main controller provided in an embodiment of this application; Figure 26 This is a flowchart illustrating a storage method provided in an embodiment of this application.

[0016] Explanation of icon numbers: Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] Furthermore, the technical features involved in the various embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0019] A Field-Programmable Gate Array (FPGA) is a programmable integrated circuit chip that can be configured by users using a hardware description language to implement specific digital logic functions. FPGAs can acquire data, and in high-speed data storage scenarios, the data acquired by the FPGA needs to be transmitted to storage devices for storage.

[0020] High-speed data storage scenarios refer to application scenarios that have high requirements for data transmission rate, latency, and storage efficiency during data acquisition, processing, and storage. These scenarios typically involve large-scale data generation, rapid data processing, and efficient storage operations to ensure that data is recorded and managed in a timely and complete manner.

[0021] Currently, systems for achieving high-speed data storage include the following: I. A storage system consisting of field-programmable gate arrays, system-on-chips (SoCs), and storage devices.

[0022] II. Storage system consisting of field-programmable gate arrays and storage devices.

[0023] 3. A storage system consisting of a field-programmable gate array, a PCIe switch, and at least one storage device.

[0024] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of the first storage system provided in the embodiments of this application; like Figure 1 As shown, the storage system 100 includes a field-programmable gate array (FPGA) 10, a system-on-a-chip (SoC) 20, and a storage device 30. The SoC 20 is communicatively connected to both the FPGA 10 and the storage device 30.

[0025] Specifically, both the field-programmable gate array 10 and the system-on-a-chip 20 have a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIe) interface, and the two communicate with each other through the PCIe interface. Among them, PCIe has the characteristics of high bandwidth and low latency, and high-speed data transmission can be achieved through the PCIe interface.

[0026] The field-programmable gate array 10 acquires data and transmits it to the system-on-a-chip 20 via the PCIe interface.

[0027] The system-on-a-chip 20 receives data transmitted by the field-programmable gate array 10 through the PCIe interface and stores the data to the storage device 30.

[0028] Storage device 30 receives and stores data transmitted by system-on-a-chip 20. This storage device includes, but is not limited to, flash memory devices. Flash memory devices, such as solid-state drives (SSDs), are storage devices that use semiconductor flash memory (NAND flash) as their medium.

[0029] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of the second storage system provided in the embodiments of this application; like Figure 2 As shown, the storage system 100 includes a field-programmable gate array (FPGA) 10 and a storage device 30. Both the FPGA 10 and the storage device 30 have PCIe interfaces, and they are connected for communication via the PCIe interfaces.

[0030] In the second type of storage system, after the field-programmable gate array 10 acquires data, it directly transmits the data to the storage device 30 via the PCIe interface.

[0031] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of the third storage system provided in the embodiments of this application; like Figure 3 As shown, the storage system 100 includes a field-programmable gate array 10, a PCIe switching chip 40, and at least one storage device 30. Figure 3 Taking two storage devices 30 as an example, the PCIe switching chip 40 is communicatively connected to the field-programmable gate array 10 and the storage device 30, respectively.

[0032] Specifically, both the field-programmable gate array 10 and the PCIe switching chip 40 have PCIe interfaces, and the two communicate with each other through the PCIe interface.

[0033] In the third type of storage system, after the field-programmable gate array 10 acquires data, it transmits the data to the PCIe switching chip 40 through the PCIe interface, and the PCIe switching chip 40 stores the data to different storage devices 30.

[0034] Among them, the PCIe switching chip 40 is a high-speed switching chip that extends and routes PCIe bus signals, and can efficiently allocate data streams and channels between the field programmable gate array 10 and multiple storage devices 30.

[0035] However, in the first type of storage system, the SoC needs to be connected to an external storage device to realize data storage, which increases the complexity and cost of the system's hardware design. Moreover, in all three types of storage systems, the FPGA realizes high-speed data transmission through the PCIe interface. The PCIe interface is a dedicated high-speed serial interface. Compared with FPGAs that support ordinary interfaces, FPGAs that support PCIe are more expensive, increasing the system hardware cost. Based on this, this application provides a storage system that achieves high-speed data storage through a field-programmable gate array (FPGA) and a main controller. On the one hand, the main controller in this application can replace the SoC and its external storage devices in existing solutions, eliminating the need to develop storage functions in the SoC separately, thereby reducing the hardware design complexity and overall cost of the system. On the other hand, the FPGA in this application uses a common I / O interface instead of a PCIe interface. Compared with FPGAs that support PCIe, FPGAs using a common I / O interface are cheaper, thereby reducing the system hardware cost.

[0036] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of the fourth storage system provided in the embodiments of this application; like Figure 4 As shown, the storage system 100 includes a field-programmable gate array (FPGA) 10 and a main controller 50. The FPGA 10 includes an I / O interface 101, and the main controller 50 includes a data channel module 51. The data channel module 51 and the I / O interface 101 communicate via a flash memory interface protocol.

[0037] The IO interface 101 uses flash memory interface pins as its physical carrier. The flash memory interface protocol is a communication protocol defined based on the flash memory interface pins. The flash memory interface protocol can be a custom communication protocol, including but not limited to the Open NAND Flash Interface (ONFI) protocol. The ONFI protocol is a standardized interface specification that supports high-bandwidth data transmission. The following uses the ONFI protocol as an example to illustrate the specific implementation of the storage system and storage method in this application.

[0038] The field-programmable gate array 10 sends first data to the main controller 50 through the I / O interface 101, and / or receives second data sent by the main controller 50. The first data is data sent by the field-programmable gate array 10 to the main controller 50, and the second data is data sent by the main controller 50 to the field-programmable gate array 10.

[0039] In some embodiments, the field-programmable gate array 10 acquires the first data before sending the first data to the main controller 50.

[0040] I / O interface 101 transmits first data and / or second data between the field-programmable gate array 10 and the main controller 50 according to a flash memory interface protocol (such as the ONFI protocol). When the flash memory interface protocol is the ONFI protocol, I / O interface 101 is an ONFI I / O interface.

[0041] The main controller 50 receives first data through the data channel module 51 and / or sends second data to the field-programmable gate array 10. In this embodiment, the main controller 50 includes, but is not limited to, the controller of a solid-state drive or other storage device using flash memory as the storage medium.

[0042] The data channel module 51 receives the first data sent by the IO interface 101 according to the flash interface protocol (such as the ONFI protocol), and / or sends the second data to the field programmable gate array 10.

[0043] Through communication between the data channel module 51 and the IO interface 101 based on a flash interface protocol (such as the ONFI protocol), the field-programmable gate array 10 and the main controller 50 in this application can achieve high-bandwidth, low-latency data interaction.

[0044] By employing a flash memory interface protocol (such as the ONFI protocol), the field-programmable gate array 10 sends first data to the main controller 50, the main controller 50 receives the first data, and / or the main controller 50 sends second data to the field-programmable gate array 10, the field-programmable gate array 10 receives and stores the second data. This application enables high-speed data storage through the field-programmable gate array and the main controller.

[0045] Compared to the first type of storage system where the SoC requires an external storage device, increasing the hardware design complexity and cost of the system, the main controller 50 in this application can replace the SoC and its external storage device in the solution, eliminating the need to develop storage functions in the SoC separately, thereby reducing the hardware design complexity and overall cost of the system.

[0046] The PCIe interface is a dedicated interface, while the interface used as ONFI IO on the field-programmable gate array 10 is a general-purpose IO interface. Compared with the field-programmable gate array 10 that supports PCIe, the field-programmable gate array 10 that uses a general-purpose IO interface is more flexible in selection and has a lower cost. Therefore, compared with the storage system that achieves high-speed data transmission through the PCIe interface, the storage system using the ONFI IO interface in this application has a lower hardware cost.

[0047] In this embodiment, there is at least one data channel module 51 and one IO interface 101, and the data channel module 51 and the IO interface 101 correspond one-to-one.

[0048] When the data channel module 51 is connected to the field programmable gate array 10, the main controller 50 controls the data channel module 51 to enter the data channel mode.

[0049] The data channel mode is the mode adopted by the data channel module 51 when it communicates with the field-programmable gate array 10. In the data channel mode, the data channel module 51 receives the first data sent through the IO interface 101 according to the flash memory interface protocol (such as the ONFI protocol), and / or sends the second data to the field-programmable gate array 10, thereby realizing high-speed data transmission between the main controller 50 and the field-programmable gate array 10.

[0050] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of a data channel module provided in an embodiment of this application; like Figure 5 As shown, the data channel module 51 includes a first signal driving module 511, a second signal driving module 512, and a data interface module 513.

[0051] The first signal driving module 511 is a driver module for the Read Enable (RE) signal. The second signal driving module 512 is a driver module for various control signals. The types of control signals can be set by those skilled in the art according to the flash memory interface protocol and the actual application scenario, and are not limited here. For example, when the flash memory interface protocol is the ONFI protocol, the control signals include the Chip Enable (CE) signal, the Address Latch Enable (ALE) signal, the Command Latch Enable (CLE) signal, and the Write Enable (WE) signal.

[0052] The first signal driving module 511 and the second signal driving module 512 execute corresponding operations according to the received control commands. The data interface module 513 serves as the data interface between the data channel module 51 and the main controller 50. The control commands are instructions that control the data channel module 51 to perform corresponding operations; these commands include read operation commands and write operation commands.

[0053] In some embodiments, the main controller includes firmware. The firmware outputs control commands based on the connection status of the data channel module 51 and the data received or sent by the main controller 50.

[0054] For example, when the data channel module 51 is connected to the field-programmable gate array 10 and the main controller 50 sends the second data, the control instruction is the write operation instruction corresponding to the data channel mode. That is, the control instruction instructs the data channel module 51 to perform a write operation according to the data channel mode. When the data channel module 51 is connected to the field-programmable gate array 10 and the main controller 50 receives the first data, the control instruction is the read operation instruction corresponding to the data channel mode. That is, the control instruction instructs the data channel module 51 to perform a read operation according to the data channel mode.

[0055] In data channel mode, the first signal driving module 511 outputs a clock signal to the field programmable gate array 10 according to the control command.

[0056] Specifically, in data channel mode, regardless of whether the control command is a read operation command or a write operation command, the first signal driving module 511 converts the RE signal into a clock signal and outputs the clock signal to the field programmable gate array 10.

[0057] The clock signal is a periodic square wave signal. The frequency and duty cycle of the clock signal output by the first signal driving module 511 can be set by those skilled in the art according to the actual application scenario, and are not limited here.

[0058] In data channel mode, the second signal driving module 512 sends the first write command or the first read command to the field programmable gate array 10 according to the control command and flash memory interface protocol.

[0059] Specifically, the first write instruction is a write instruction sent by the second signal driving module 512 to the field-programmable gate array 10, instructing the field-programmable gate array 10 to write the second data. The first read instruction is a read instruction sent by the second signal driving module 512 to the field-programmable gate array 10, instructing the field-programmable gate array 10 to read the first data and send the first data to the main controller 50.

[0060] The first write instruction and the first read instruction are characterized by different combinations of control signal levels and timing. The combinations of control signal levels and timing corresponding to the first write instruction and the first read instruction can be set by those skilled in the art according to the type of flash memory interface protocol and the actual application scenario, and are not limited here. For example, when the flash memory interface protocol is the ONFI protocol, the first write instruction and the first read instruction are characterized by combinations of the levels and timing of the CE signal, ALE signal, CLE signal, and WE signal.

[0061] Specifically, in data channel mode, if the control command is a read operation command, the second signal driving module 512 outputs a control signal of the corresponding level according to the flash memory interface protocol, thereby generating a first read command and sending the first read command to the field programmable gate array 10; in data channel mode, if the control command is a write operation command, the second signal driving module 512 outputs a control signal of the corresponding level according to the flash memory interface protocol, thereby generating a first write command and sending the first write command to the field programmable gate array 10.

[0062] In data channel mode, the data interface module 513 acquires first data or sends second data through data strobe signals and data signals.

[0063] Among them, the data signal (DQ signal) transmits data, and the data strobe (DQS) signal is a timing control signal that provides a synchronization reference during data transmission.

[0064] Specifically, in data channel mode, if the control command is a read operation command, the data interface module 513 receives the data strobe signal and data signal sent by the field programmable gate array 10 to obtain the first data; in data channel mode, if the control command is a write operation command, the data interface module 513 drives the data strobe signal and data signal to output the second data to the field programmable gate array 10.

[0065] In this embodiment, the field-programmable gate array includes a user logic module and at least one high-speed channel module, the high-speed channel module including an I / O interface.

[0066] Please see Figure 6 , Figure 6 This is a schematic diagram of a field-programmable gate array (FPGA) provided in an embodiment of this application; like Figure 6 As shown, the field-programmable gate array 10 includes a user logic module 11 and at least one high-speed channel module 12. The user logic module 11 is connected to the high-speed channel module 12, and the high-speed channel module 12 includes an I / O interface 101. Figure 6 Take two high-speed channel modules 12 as an example.

[0067] In this embodiment, each high-speed channel module 12 is connected to a data channel module 51, and the IO interface 101 is communicatively connected to the data interface module 513.

[0068] The high-speed channel module 12 receives the second data sent by the data channel module 51 based on the flash memory interface protocol and writes the second data into the user logic module 11; and / or, the high-speed channel module 12 reads the first data in the user logic module 11 and sends the first data to the data channel module 51 based on the flash memory interface protocol.

[0069] Specifically, when the field programmable gate array 10 receives and stores the second data sent by the main controller 50, the high-speed channel module 12 receives the second data sent by the data channel module 51 through the IO interface 101 according to the flash memory interface protocol, and writes the second data into the user logic module 11.

[0070] Alternatively, when the field-programmable gate array 10 sends the first data to the main controller 50, the high-speed channel module 12 reads the first data from the user logic module 11 and sends the first data to the data channel module 51 based on the flash memory interface protocol.

[0071] User logic module 11 stores the second data and / or generates the first data.

[0072] Specifically, when the field-programmable gate array 10 sends first data to the main controller 50, the user logic module 11 can act as a data generation source to generate the first data. Alternatively, when the field-programmable gate array 10 receives and stores second data sent by the main controller 50, the user logic module 11 can act as a data receiving source to store the second data.

[0073] In some embodiments, the first data may be data collected by the field-programmable gate array 10, and the first data is stored in the user logic module 11.

[0074] In the embodiments of this application, the user logic module 11 can be customized by those skilled in the art, and no restrictions are imposed here.

[0075] By using the high-speed channel module 12 and the IO interface 101 (i.e., the ONFI IO interface) to construct a high-speed data path between the field-programmable gate array 10 and the main controller 50, this application can transmit a large amount of high-speed data that the user needs to store to the main controller 50 via the high-speed channel module 12, and / or transmit the data in the main controller 50 to the field-programmable gate array 10 via the high-speed channel module 12, thereby realizing high-speed data transmission between the two.

[0076] Compared to the limited number of PCIe links supported by the existing field-programmable gate array 10, this application connects a data channel module 51 to each high-speed channel module 12. The high-speed channel module 12 includes an IO interface 101. The main controller 50 can be configured with multiple data channel modules 51, and the field-programmable gate array 10 can also be configured with multiple high-speed channel modules 12, thereby supporting a larger number of IO interfaces and enabling the use of multiple high-speed data paths to transmit data, thus improving data transmission bandwidth.

[0077] Moreover, compared to the PCIe interface, the IO interface 101 is a general-purpose interface, and the field-programmable gate array 10 supports a greater number of IO interfaces 101. Therefore, the selection of the field-programmable gate array 10 is more flexible and the cost is lower.

[0078] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a high-speed channel module provided in an embodiment of this application; In this embodiment of the application, during the transmission of the first data, the high-speed channel module 12 sends the first data to the main controller 50 by simulating the behavior of NAND flash memory.

[0079] like Figure 7 As shown, the high-speed channel module 12 includes a clock module 121, a command parsing module 122, a high-speed interface module 123, a first data interface 124, and a second data interface 125. The high-speed interface module 123 includes an I / O interface 101.

[0080] The clock module 121 connects the first signal driving module 511 and the high-speed interface module 123. The clock module 121 receives the clock signal sent by the first signal driving module 511 and sends the clock signal to the high-speed interface module 123.

[0081] Specifically, the clock module 121 receives the clock signal sent by the first signal drive module 511 in the main controller 50 and sends the clock signal to the high-speed interface module 123, thereby providing a clock source for the high-speed interface module 123.

[0082] Command parsing module 122 connects the second signal driving module 512 and the high-speed interface module 123. Command parsing module 122 receives and parses the first write command or the first read command sent by the second signal driving module 512, generates the corresponding operation command, and sends the operation command to the high-speed interface module 123.

[0083] The operation instructions are those sent by the command parsing module 122 to the high-speed interface module 123, and include write instructions or read instructions.

[0084] Specifically, when the field-programmable gate array 10 receives and stores the second data sent by the main controller 50, the command parsing module 122 receives the first write instruction sent by the second signal driving module 512 in the main controller 50, and parses the first write instruction to determine that the field-programmable gate array 10 needs to perform a data write operation, thereby generating a write instruction and sending the write instruction to the high-speed interface module 123 so that the high-speed interface module 123 performs the data write operation.

[0085] Alternatively, when the field-programmable gate array 10 sends the first data to the main controller 50, the command parsing module 122 receives the first read instruction sent by the second signal driving module 512 in the main controller 50, parses the first read instruction to determine that the field-programmable gate array 10 needs to perform a data read operation, thereby generating a read instruction and sending the read instruction to the high-speed interface module 123 so that the high-speed interface module 123 performs the data read operation.

[0086] The high-speed interface module 123 connects to the command parsing module 122, the data interface module 513, the clock module 121, the first data interface 124, and the second data interface 125. The high-speed interface module 123 receives and executes operation instructions to write the second data sent by the data interface module 513 into the user logic module 11, and / or read the first data and send the first data to the data channel module 51.

[0087] Specifically, when the field programmable gate array 10 receives and stores the second data sent by the main controller 50, the high-speed interface module 123 receives the write command sent by the command parsing module 122 and the second data sent by the data interface module 513, and performs the data writing operation according to the write command, and writes the second data into the user logic module 11 through the second data interface 125.

[0088] Alternatively, when the field programmable gate array 10 sends the first data to the main controller 50, the high-speed interface module 123 receives the read instruction sent by the command parsing module 122, performs the data read operation according to the read instruction, reads the first data in the user logic module 11 through the first data interface 124, and sends the first data to the data channel module 51.

[0089] The first data interface 124 connects the high-speed interface module 123 and the user logic module 11. The first data interface 124 transmits the first data output by the user logic module 11 to the high-speed interface module 123.

[0090] The first data interface 124 is the data writing interface between the high-speed interface module 123 and the user logic module 11. The first data interface 124 includes, but is not limited to, a First In First Out (FIFO) queue for sending data, namely tx_fifo.

[0091] Specifically, when the field programmable gate array 10 sends the first data to the main controller 50, the first data interface 124 transmits the first data output by the user logic module 11 to the high-speed interface module 123.

[0092] The second data interface 125 connects the high-speed interface module 123 and the user logic module 11. The second data interface 125 transmits the second data output from the high-speed interface module 123 to the user logic module 11.

[0093] The second data interface 125 is the data acquisition interface between the high-speed interface module 123 and the user logic module 11. The second data interface 125 includes, but is not limited to, a first-in-first-out queue for receiving data, i.e., rx_fifo.

[0094] Specifically, when the field programmable gate array 10 receives and stores the second data sent by the main controller 50, the second data interface 125 transmits the second data output by the high-speed interface module 123 to the user logic module 11.

[0095] Compared to the high development complexity of the PCIe interface in existing field-programmable gate arrays, this application uses tx_fifo to transmit the first data output by the user logic module 11 to the high-speed interface module 123, or uses rx_fifo to transmit the second data output by the high-speed interface module 123 to the user logic module 11, thereby realizing the interaction between the user logic module 11 and the high-speed interface module 123 within the field-programmable gate array 10. This interaction method is simpler than the PCIe interface and facilitates the development of user logic.

[0096] In some embodiments, the high-speed channel module 12 delays the transmission of second data to the user logic module 11, and / or delays the transmission of first data to the data channel module 51.

[0097] Specifically, when the field programmable gate array 10 receives and stores the second data sent by the main controller 50, the high-speed channel module 12, after receiving the second data sent by the main controller 50, transmits the second data to the user logic module 11 with a delay through the high-speed interface module 123.

[0098] Alternatively, when the field programmable gate array 10 sends the first data to the main controller 50, the high-speed channel module 12, after reading the first data in the user logic module 11, transmits the first data to the data channel module 51 with a delay through the high-speed interface module 123.

[0099] In this embodiment, the field-programmable gate array 10 further includes a control module, which communicates with the main controller 50 via a communication bus. The communication bus is a standardized interface or protocol for data transmission, and includes, but is not limited to, Inter-Integrated Circuit (I²C), Serial Peripheral Interface (SPI), and Universal Asynchronous Receiver / Transmitter (UART).

[0100] The control module connects the main controller 50 to the high-speed channel module 12. The control module controls the high-speed channel module 12 to delay the transmission of the first data and / or the second data.

[0101] Specifically, when the field programmable gate array 10 receives and stores the second data sent by the main controller 50, the control module controls the high-speed channel module 12 to delay the transmission of the first data.

[0102] Alternatively, when the field-programmable gate array 10 sends the first data to the main controller 50, the control module controls the high-speed channel module 12 to delay the transmission of the second data.

[0103] In some embodiments, the control module configures the parameters of the registers in the field-programmable gate array 10. The configurable parameters of the control module can be set by those skilled in the art according to the actual application scenario, and are not limited herein.

[0104] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a high-speed interface module provided in an embodiment of this application; like Figure 8 As shown, the high-speed interface module 123 includes an output delay link 1231, an input delay link 1232, a transmitting module 1233, a receiving module 1234, and an adjustment module 1235.

[0105] The output delay link 1231 includes the output delay link corresponding to the data strobe signal (DQS signal) (i.e., DQS output delay link 1201) and the output delay link corresponding to the data signal (DQ signal) (i.e., DQ output delay link 1202). The input delay link 1232 includes the input delay link corresponding to the data signal (i.e., DQ input delay link 1203) and the input delay link corresponding to the data strobe signal (i.e., DQS input delay link 1204).

[0106] IO interface 101 ( Figure 8 (Not shown) Connect the input delay link 1231 and the output delay link 1232 respectively.

[0107] Please see Figure 9 , Figure 9 This is a detailed structural schematic diagram of a field-programmable gate array provided in an embodiment of this application; Figure 9 Taking a field-programmable gate array 10 including a high-speed channel module 12 as an example.

[0108] Input delay link 1232 connects data interface module 513 and receiving module 1234. Input delay link 1232 transmits the second data sent by data interface module 513 to receiving module 1234 with a delay according to input delay parameters.

[0109] The input delay parameters are control parameters for configuring the input delay link 1232 to adjust the delay of the second data when it is transmitted to the receiving module 1234. The input delay parameters include the input delay parameters for the DQS signal and the DQ signal. The input delay parameter for the DQS signal controls the input delay time of the DQS signal to ensure the accuracy of the data sampling timing. The input delay parameter for the DQ signal controls the input delay time of the DQ signal to synchronize with the DQS signal and ensure the integrity of data transmission.

[0110] Specifically, when the field programmable gate array 10 receives and stores the second data sent by the main controller 50, the input delay link 1232 adjusts the input DQS signal and DQ signal according to the input delay parameters of the DQS signal and the DQ signal, thereby delaying the transmission of the second data to the receiving module 1234.

[0111] The DQ input delay link 1203 connects the data interface module 513 and the receiving module 1234. The DQ input delay link 1203 transmits the DQ signal corresponding to the second data to the receiving module 1234 with a delay according to the input delay parameter of the DQ signal.

[0112] DQS input delay link 1204 connects data interface module 513 and receiving module 1234. DQS input delay link 1204 transmits the DQS signal corresponding to the second data to receiving module 1234 with a delay according to the input delay parameter of the DQS signal.

[0113] The receiving module 1234 connects the input delay link 1232, the clock module 121, the command parsing module 122, the adjustment module 1235, and the second data interface 125. The receiving module 1234 receives the second data transmitted by the input delay link 1232 and transmits the second data to the second data interface 125.

[0114] Specifically, when the field programmable gate array 10 receives and stores the second data sent by the main controller 50, the receiving module 1234 receives the write instruction sent by the command parsing module 122 and performs a data write operation, that is, it receives the DQS signal and DQ signal transmitted by the input delay link 1232, obtains the second data by sampling the DQ signal through the DQ signal, and transmits the second data to the second data interface 125 so that the second data is stored in the user logic module 11 through the second data interface 125.

[0115] The transmitting module 1233 connects to the first data interface 124, the clock module 121, the command parsing module 122, the adjustment module 1235, and the output delay link 1202. The transmitting module 1233 acquires the first data transmitted by the first data interface 124 and sends the first data to the output delay link 1202.

[0116] Specifically, when the field programmable gate array 10 sends the first data to the main controller 50, the sending module 1233 receives the read instruction sent by the command parsing module 122 and performs the data reading operation, that is, reads the first data from the user logic module 11 through the first data interface 124 and sends the first data to the output delay link 1202 through the DQ signal, while generating the DQS signal.

[0117] The DQS signal is generated based on the presence or absence of data in the first data interface 124 (i.e., tx_fifo). For example, when there is no data in tx_fifo, the transmitting module 1233 stops generating a valid DQS signal, and the DQS output remains 0; when there is data in tx_fifo, the transmitting module 1233 converts the received parallel data into a serially output DQS signal according to the clock signal, and the DQS signal is aligned with the DQ signal on the rising and falling edges.

[0118] The output delay link 1202 connects the data interface module 513 and the transmitting module 1233. The output delay link 1202 transmits the first data to the data interface module 513 with a delay according to the output delay parameter.

[0119] The output delay parameters are control parameters configured for the output delay link 1202 to delay the output of the first data. These parameters include the output delay parameters for the DQS signal and the DQ signal. The DQS signal output delay parameter controls the output delay time of the DQS signal to ensure the accuracy of data transmission timing. The DQ signal output delay parameter controls the output delay time of the DQ signal to synchronize with the DQS signal and ensure the integrity of data transmission.

[0120] Specifically, when the field programmable gate array 10 sends the first data to the main controller 50, the output delay link 1202 adjusts the delay of the DQS signal and the DQ signal sent by the transmitting module 1233 according to the output delay parameters of the DQS signal and the DQ signal, thereby delaying the transmission of the first data to the receiving module 1234.

[0121] DQS output delay link 1201 connects data interface module 513 and transmitting module 1233. DQS output delay link 1201 delays the transmission of DQS signal sent by transmitting module 1233 to data interface module 513 according to the output delay parameter of DQS signal.

[0122] DQ output delay link 1202 connects data interface module 513 and transmitting module 1233. DQ output delay link 1202 transmits the DQ signal sent by transmitting module 1233 to data interface module 513 with a delay according to the output delay parameter of DQ signal.

[0123] The adjustment module 1235 is connected to the control module 126, the transmitting module 1233, and the receiving module 1234. The adjustment module 1235 adjusts the input delay parameters and / or the output delay parameters.

[0124] Specifically, when the field programmable gate array 10 sends the first data to the main controller 50, the adjustment module 1235 adjusts the output delay parameter of the output delay link 1202 under the control of the control module 126.

[0125] Alternatively, when the field programmable gate array 10 receives and stores the second data sent by the main controller 50, the adjustment module 1235 adjusts the input delay parameter of the input delay link 1232 under the control of the control module 126.

[0126] The following explains the process of adjusting the input delay parameter: The main controller 50 sends the first preset data to the field programmable gate array 10 through the data channel module 51.

[0127] The first preset data is the data sent by the main controller 50 to the field-programmable gate array 10 to adjust the input delay parameters. The first preset data can be set by those skilled in the art according to the actual application scenario and stored in advance in the main controller 50 and the field-programmable gate array 10, and there is no limitation here.

[0128] Specifically, after the adjustment module 1235 sets the parameter value of the input delay parameter to the first preset value, the main controller 50 sends the first preset data to the field programmable gate array 10.

[0129] The main controller 50 also sends updated first preset data to the field programmable gate array 10 via the data channel module 51.

[0130] The updated first preset data can be set by those skilled in the art according to the actual application scenario and stored in advance in the main controller 50 and the field programmable gate array 10, without any restrictions.

[0131] Specifically, when the number of times the input delay parameter is updated is less than the first preset number, after the adjustment module 123 updates the parameter value of the input delay parameter each time, the main controller 50 updates the first preset data and sends the updated first preset data to the field programmable gate array 10.

[0132] For example, after the adjustment module 123 updates the input delay parameter value, the field-programmable gate array 10 sends a request signal to the main controller 50. Upon receiving the request signal, the main controller 50 updates the first preset data and sends the updated first preset data to the field-programmable gate array 10. The request signal instructs the main controller 50 to send the updated first preset data to the field-programmable gate array 10.

[0133] The adjustment module 1235 sets the parameter value of the input delay parameter to a first preset value, reads the sampled data from the receiving module, and compares the sampled data with the first preset data stored in the adjustment module to obtain the determination result of the current input delay parameter; when the sampled data is the same as the first preset data, the determination result is determined to be a valid value; when the sampled data is different from the first preset data, the determination result is determined to be an invalid value.

[0134] The first preset value is the initial value of the input delay parameter set when adjusting the input delay parameter. This first preset value can be set by those skilled in the art according to the actual application scenario and is pre-stored in the field-programmable gate array 10; no restrictions are imposed here. The sampled data is the data received by the receiving module 1234, and the sampled data is transmitted to the receiving module via the input delay link based on the first preset value delay.

[0135] The current input delay parameter is judged as either valid or invalid. A valid value indicates that the current input delay parameter is valid, meaning that the currently set input delay parameter (such as the first preset value) enables the receiving module to correctly sample the expected test data (such as the first preset data). An invalid value indicates that the current input delay parameter is invalid, meaning that the currently set input delay parameter cannot enable the receiving module to correctly sample the expected test data.

[0136] Specifically, the adjustment module 1235 sets the input delay parameter value to a first preset value. After the main controller 50 sends the first preset data to the field programmable gate array 10, the input delay link 1232 delays the transmission of the first preset data to the receiving module 1234 according to the first preset value. The receiving module 1234 receives the data transmitted by the input delay link 1232 and uses this data as sampled data. The adjustment module 1235 reads the sampled data from the receiving module and compares it with the first preset data stored internally in the adjustment module. If the sampled data is the same as the first preset data, the current input delay parameter is determined to be a valid value; if the sampled data is different from the first preset data, the current input delay parameter is determined to be an invalid value, and then the determination result is recorded.

[0137] When the number of updates to the input delay parameter is less than the first preset number, the adjustment module 1235 updates the parameter value of the input delay parameter. After the main controller resends the updated first preset data to the field programmable gate array, the adjustment module 1235 reads the new sampled data from the receiving module and compares the new sampled data with the updated first preset data to obtain the determination result of the current input delay parameter.

[0138] The first preset number of times is the maximum number of times the input delay parameter can be updated when adjustment stops. The parameter value of each updated input delay parameter can be pre-stored in the field-programmable gate array 10 by those skilled in the art. The first preset number of times and the parameter value of each updated input delay parameter can be set by those skilled in the art according to the actual application scenario, and are not limited here. For example, the first preset number of times is 128. New sampled data is transmitted to the receiving module via the input delay link based on the updated input delay parameter delay.

[0139] Specifically, when the number of updates to the input delay parameter is less than a first preset number, the adjustment module 1235 updates the parameter value of the input delay parameter. After the main controller 50 sends the updated first preset data to the field programmable gate array 10, the input delay link 1232 transmits the updated first preset data to the receiving module 1234 with a delay according to the updated input delay parameter. The receiving module 1234 receives the data transmitted by the input delay link 1232 and uses this data as new sampled data. The adjustment module 1235 reads the new sampled data from the receiving module and compares the new sampled data with the updated first preset data to obtain the determination result of the current input delay parameter.

[0140] When the number of times the input delay parameter is updated equals the first preset number, the adjustment module 1235 stops updating the input delay parameter, determines the first target parameter, combines several first target parameters to obtain a first window, determines the median value of the first window, and sets the input delay parameter to the median value.

[0141] Wherein, the first target parameter is the input delay parameter for determining a valid value, the first window is a window obtained by combining several first target parameters, and the median value is the median of several first target parameters in the first window.

[0142] Specifically, the input delay parameter is not adjustable indefinitely. When the number of times the input delay parameter is updated equals the first preset number, the adjustment module 1235 stops updating the input delay parameter and takes the input delay parameter with a valid value as the first target parameter, thereby obtaining several first target parameters. The several first target parameters are combined to form a first window. The median of all the first target parameters in the first window is taken as the median value of the first window, and the input delay parameter is set to the median value. At this time, the input delay parameter adjustment is completed.

[0143] It is understandable that the input delay parameters include the input delay parameters of the DQS signal and the input delay parameters of the DQ signal. Each time the adjustment module 1235 updates, it simultaneously updates the input delay parameters of the DQS signal and the input delay parameters of the DQ signal. The input delay parameters of the DQS signal correspond to a first window, and the input delay parameters of the DQ signal correspond to a first window. The intermediate values ​​of these two first windows are the final input delay parameters of the DQS signal and the DQ signal, respectively.

[0144] Please see Figure 10 , Figure 10 This is a flowchart illustrating an embodiment of adjusting input delay parameters provided in this application; like Figure 10 As shown, the process for adjusting the input delay parameter includes: Step S1001: Adjust the module settings for input delay parameters; Specifically, the adjustment module 1235 sets the input delay parameters of the DQS signal and the DQ signal. For example, in the process of adjusting the input delay parameters, when the adjustment module 1235 sets the input delay parameters for the first time, it sets the input delay parameters of the DQS signal and the DQ signal to the corresponding first preset values; when the number of updates to the input delay parameters is less than the first preset number, the adjustment module 1235 resets the input delay parameters of the DQS signal and the DQ signal to update the input delay parameters.

[0145] Step S1002: The main controller sends the first preset data to the field programmable gate array; Specifically, the main controller 50 sends the first preset data to the field programmable gate array 10 through the data channel module 51. For example, after the adjustment module 1235 completes the initial setting of the input delay parameter, the main controller 50 sends the first preset data; after the adjustment module 123 updates the parameter value of the input delay parameter each time, the main controller 50 updates the first preset data and sends the updated first preset data to the field programmable gate array 10.

[0146] Step S1003: Adjust the module to acquire sampling data; Specifically, the field programmable gate array 10 receives the first preset data sent by the main controller 50 through the input delay link 1232. The input delay link 1232 delays the transmission of the first preset data to the receiving module 1234 according to the first preset value. The receiving module 1234 receives the data transmitted by the input delay link 1232 and uses the data as sampled data. The adjustment module 1235 reads the sampled data from the receiving module.

[0147] Step S1004: The adjustment module determines whether the sampled data is the same as the first preset data; Specifically, the adjustment module 1235 compares the sampled data with the first preset data stored inside the adjustment module to determine whether the sampled data is the same as the first preset data.

[0148] If the sampled data is the same as the first preset data, proceed to step S1005; if the sampled data is different from the first preset data, proceed to step S1006.

[0149] Step S1005: The adjustment module determines that the judgment result of the current input delay parameter is a valid value; Specifically, if the sampled data is the same as the first preset data, the adjustment module 1235 determines that the judgment result of the current input delay parameter is a valid value and records the judgment result.

[0150] Step S1006: The adjustment module determines that the current input delay parameter is invalid. Specifically, if the sampled data is different from the first preset data, the adjustment module 1235 determines that the current input delay parameter is invalid and records the determination result.

[0151] Step S1007: The adjustment module determines whether the number of times the input delay parameter is updated is equal to the first preset number; Specifically, if the number of times the input delay parameter is updated is less than the first preset number, then return to step S1001 and re-execute steps S1001-S1007; if the number of times the input delay parameter is updated is equal to the first preset number, then proceed to step S1008.

[0152] Step S1008: The adjustment module determines the first window and sets the input delay parameter to the middle value of the first window; Specifically, when the number of times the input delay parameter is updated equals the first preset number of times, the adjustment module 1235 stops updating the input delay parameter, determines the first target parameter, combines several first target parameters to obtain a first window, determines the intermediate value of the first window, and sets the input delay parameter to the intermediate value.

[0153] Step S1009: Input delay parameter adjustment completed.

[0154] The following explains the process of adjusting the output delay parameter: The adjustment module 1235 sets the output delay parameter value to a second preset value; it sends a trigger signal and second preset data to the sending module 1233 so that the sending module 1233 transmits the second preset data to the output delay link 1202, thereby causing the output delay link 1202 to transmit the second preset data to the main controller 50 with a delay based on the second preset value.

[0155] The second preset value is the initial value of the output delay parameter set when adjusting the output delay parameter. The second preset value can be set by those skilled in the art according to the actual application scenario and is pre-stored in the field-programmable gate array 10; no restrictions are imposed here. A trigger signal instructs the transmitting module 1233 to send the second preset data to the output delay link 1202.

[0156] The second preset data is the data sent from the field-programmable gate array 10 to the main controller 50 to adjust the output delay parameters. The second preset data can be set by those skilled in the art according to the actual application scenario and pre-stored in the main controller 50 and the field-programmable gate array 10, and there are no restrictions here.

[0157] The current output delay parameter is judged as either valid or invalid. A valid value indicates that the current output delay parameter is valid, meaning that the currently set output delay parameter (such as the second preset value) enables the main controller 50 to correctly receive the expected test data (such as the second preset data). An invalid value indicates that the current output delay parameter is invalid, meaning that the currently set output delay parameter (such as the second preset value) cannot enable the main controller 50 to correctly receive the expected test data.

[0158] Specifically, the adjustment module 1235 sets the parameter value of the output delay parameter to a second preset value and sends a trigger signal and second preset data to the sending module 1233, so that the sending module 1233 transmits the second preset data to the output delay link 1202, thereby causing the output delay link 1202 to transmit the second preset data to the main controller 50 with a delay based on the second preset value.

[0159] The main controller 50 receives the data transmitted by the output delay link 1202 and compares the data with the second preset data stored inside the main controller 50 to obtain the determination result of the current output delay parameter; when the data is the same as the second preset data, the determination result is determined to be a valid value; when the data is different from the second preset data, the determination result is determined to be an invalid value; and the determination result is sent to the field programmable gate array 10 through the data channel module 51.

[0160] Specifically, the main controller 50 receives data transmitted via the output delay link 1202 of the field-programmable gate array 10 and compares this data with second preset data stored internally by the main controller 50. If the data matches the second preset data, the current output delay parameter is determined to be a valid value; if the data differs from the second preset data, the current output delay parameter is determined to be an invalid value. The main controller 50 then sends the determination result to the field-programmable gate array 10 via the data channel module 51.

[0161] The adjustment module 1235 acquires and records the judgment result of the current output delay parameter sent by the main controller.

[0162] Specifically, after the main controller 50 sends the determination result of the current output delay parameter to the field programmable gate array 10, the adjustment module 1235 acquires and records the determination result.

[0163] When the number of times the output delay parameter is updated is less than the second preset number, the adjustment module 1235 updates the parameter value of the output delay parameter and the second preset data, and sends a trigger signal and the updated second preset data to the sending module 1233, so that the output delay link 1202 transmits the updated second preset data to the main controller 50 with a delay based on the updated output delay parameter; and obtains and records the judgment result of the current output delay parameter sent by the main controller 50.

[0164] The second preset number of times is the maximum number of times the output delay parameter can be updated when adjustment stops. The parameter value of each updated output delay parameter can be pre-stored in the field-programmable gate array 10 by those skilled in the art. The second preset number of times and the parameter value of each updated output delay parameter can be set by those skilled in the art according to the actual application scenario, and are not limited here. For example, the second preset number of times is 128.

[0165] Specifically, when the number of updates to the output delay parameter is less than the second preset number, the adjustment module 1235 updates the parameter value of the output delay parameter and the second preset data, and sends a trigger signal and the updated second preset data to the sending module 1233. After receiving the updated second preset data, the sending module 1233 sends the updated second preset data to the output delay link 1202, and the output delay link 1202 transmits the updated second preset data to the main controller 50 with a delay based on the updated output delay parameter. After the main controller 50 sends the determination result of the current output delay parameter to the field programmable gate array 10, the adjustment module 1235 acquires and records the determination result.

[0166] When the number of times the output delay parameter is updated equals the second preset number, the adjustment module 1235 stops updating the output delay parameter, determines the second target parameter, combines several second target parameters to obtain a second window, determines the median value of the second window, and sets the output delay parameter to the median value.

[0167] The second target parameter is the output delay parameter whose judgment result is valid. The second window is a window obtained by combining several second target parameters. The median value is the median of several output delay parameters in the second window.

[0168] Specifically, the output delay parameter is not adjusted indefinitely. When the number of times the output delay parameter is updated equals the second preset number, the adjustment module 1235 stops updating the output delay parameter and uses the output delay parameter with a valid value as the second target parameter, thereby obtaining several second target parameters. The several second target parameters are combined to obtain a second window. The median of all the second target parameters in the second window is used as the median value of the second window, and the output delay parameter is set to this median value. At this time, the output delay parameter adjustment is completed.

[0169] It is understood that the output delay parameters include the output delay parameters of the DQS signal and the output delay parameters of the DQ signal. Each time the adjustment module 1235 updates, it simultaneously updates the output delay parameters of the DQS signal and the output delay parameters of the DQ signal. The output delay parameters of the DQS signal correspond to a second window, and the output delay parameters of the DQ signal correspond to a second window. The intermediate values ​​of these two second windows are the final output delay parameters of the DQS signal and the DQ signal, respectively.

[0170] Please see Figure 11 , Figure 11 This is a schematic diagram of a second window provided in an embodiment of this application; like Figure 11 As shown, the second window is a window composed of several output delay parameters whose judgment results are valid.

[0171] Please see Figure 12 , Figure 12 This is a flowchart illustrating an embodiment of adjusting output delay parameters provided in this application; like Figure 12 As shown, the process for adjusting the output delay parameter includes: Step S1201: Adjust the module settings for output delay parameters; Specifically, the adjustment module 1235 sets the output delay parameters of the DQS signal and the DQ signal. For example, in the process of adjusting the output delay parameters, when the adjustment module 1235 sets the output delay parameters for the first time, it sets the output delay parameters of the DQS signal and the DQ signal to the corresponding second preset values; when the number of times the output delay parameters are updated is less than the second preset number, the adjustment module 1235 resets the output delay parameters of the DQS signal and the DQ signal to update the output delay parameters.

[0172] Step S1202: The adjustment module sends the second preset data to the main controller through the sending module and the output delay link; Specifically, the adjustment module 1235 sends a trigger signal and second preset data to the sending module 1233, so that the sending module 1233 transmits the second preset data to the output delay link 1202, thereby causing the output delay link 1202 to transmit the second preset data to the main controller 50 with a delay based on the second preset value.

[0173] When the number of times the output delay parameter is updated is less than the second preset number, the adjustment module 1235 updates the parameter value of the output delay parameter and the second preset data, and sends a trigger signal and the updated second preset data to the sending module 1233, so that the output delay link 1202 transmits the updated second preset data to the main controller 50 with a delay based on the updated output delay parameter.

[0174] Step S1203: The main controller receives data transmitted via the output delay link; Specifically, the main controller 50 receives the data transmitted by the output delay link 1202 and compares the data with the second preset data stored inside the main controller 50 to obtain the determination result of the current output delay parameter. The determination result is then sent to the field programmable gate array 10 through the data channel module 51.

[0175] Step S1204: The main controller determines whether the received data is the same as the second preset data; Specifically, the main controller 50 compares the received data with the second preset data stored inside the main controller 50 to obtain the determination result of the current output delay parameter.

[0176] Step S1205: The main controller determines that the current output delay parameter is a valid value; Specifically, if the data received by the main controller 50 is the same as the second preset data, then the determination result of the current output delay parameter is determined to be a valid value.

[0177] Step S1206: The main controller determines that the current output delay parameter is invalid. Specifically, if the data received by the main controller 50 is different from the second preset data, the determination result of the current output delay parameter is determined to be invalid.

[0178] Step S1207: The main controller sends the determination result of the current output delay parameter to the field programmable gate array; Specifically, the main controller 50 sends the determination result to the field programmable gate array 10 through the data channel module 51.

[0179] Step S1208: The adjustment module records the judgment result; Step S1209: The adjustment module determines whether the number of times the output delay parameter is updated is equal to the second preset number; Specifically, if the number of times the output delay parameter is updated is less than the second preset number, then return to step S1201 and re-execute steps S1201-S1209; if the number of times the output delay parameter is updated is equal to the second preset number, then proceed to step S1210.

[0180] Step S1210: The adjustment module determines the second window and sets the output delay parameter to the middle value of the second window; Specifically, when the number of times the output delay parameter is updated equals the second preset number, the adjustment module 1235 stops updating the output delay parameter, determines the second target parameter, combines several second target parameters to obtain a second window, determines the median value of the second window, and sets the output delay parameter to the median value.

[0181] Step S1211: Output delay parameter adjustment completed.

[0182] In some embodiments, the storage system 100 includes a memory that stores second data and / or first data received by the main controller 50.

[0183] Specifically, when the main controller 50 sends second data to the field-programmable gate array 10, the main controller 50 reads the second data from the memory and then sends the second data to the field-programmable gate array 10. Alternatively, when the field-programmable gate array 10 sends first data to the main controller 50, the main controller 50 stores the received first data in the memory.

[0184] The memory is located within the main controller 50, or the memory is communicatively connected to the main controller 50. The type of memory can be set by those skilled in the art according to the amount of data that the main controller needs to store in the actual application scenario, and is not limited here.

[0185] For example: When the amount of data that the main controller 50 needs to store is small, the memory is located inside the main controller 50. In this case, the memory includes, but is not limited to, Dynamic Random Access Memory (DRAM). When the amount of data that the main controller 50 needs to store is large, the memory is located outside the main controller 50, and the memory is communicatively connected to the main controller 50. In this case, the memory includes, but is not limited to, Double Data Rate Memory (DDR).

[0186] When the storage system 100 includes a memory, the second signal driving module 512 sends a pause transmission command to the field programmable gate array 10 when the amount of data stored in the memory is greater than or equal to a preset amount of data, so that the field programmable gate array 10 pauses the transmission of the first data or pauses the writing of the second data.

[0187] The preset data amount is the minimum amount of data stored in the memory when the second signal driving module 512 sends a pause transmission command to the field programmable gate array 10. The size of the preset data amount can be set by those skilled in the art according to the actual application scenario, and is not limited here.

[0188] The pause transmission command is sent by the second signal drive module 512 to the field-programmable gate array 10, instructing the field-programmable gate array 10 to pause the transmission of the first data or to pause the writing of the second data. The pause transmission command includes a first pause command and a second pause command. The first pause command is sent by the main controller 50 when it pauses reading the first data from the field-programmable gate array 10, and the second pause command is sent by the main controller 50 when it pauses writing the second data to the field-programmable gate array 10.

[0189] The pause transmission command is characterized by different combinations of control signal levels and timings. The levels and timings of the control signals corresponding to the pause transmission command can be set by those skilled in the art based on the type of flash memory interface protocol and the actual application scenario, and are not limited here. For example, when the flash memory interface protocol is the ONFI protocol, the CE and CLE signals corresponding to the first read command are both high, while the CE and CLE signals corresponding to the pause transmission command are both low.

[0190] Specifically, when the field-programmable gate array 10 sends the first data to the main controller 50, if the amount of data stored in the memory is greater than or equal to the preset amount of data, the second signal driving module 512 outputs a control signal of the corresponding level according to the flash memory interface protocol, thereby generating a first pause instruction and sending the first pause instruction to the field-programmable gate array 10 to make the field-programmable gate array 10 pause sending the first data.

[0191] In some embodiments, when the amount of data stored in the memory is less than a preset amount of data, the second signal driving module 512 sends a data continuation instruction to the field programmable gate array 10 so that the field programmable gate array 10 continues to send the first data or continues to write the second data.

[0192] The data continuation instruction is sent by the second signal driving module 512 to the field-programmable gate array 10, instructing the field-programmable gate array 10 to continue transmitting the first data or continue writing the second data. The data continuation instruction includes a first continuation instruction and a second continuation instruction. The first continuation instruction is sent by the main controller 50 when it continues to read the first data from the field-programmable gate array 10, and the second continuation instruction is sent by the main controller 50 when it continues to write the second data to the field-programmable gate array 10.

[0193] Data resume commands are characterized by different combinations of control signal levels and timings. The levels and timings of the control signals corresponding to the data resume commands can be set by those skilled in the art based on the type of flash memory interface protocol and the actual application scenario, and are not limited here. For example, when the flash memory interface protocol is ONFI, both the CE and CLE signals corresponding to the first read command are high, and both the CE and CLE signals corresponding to the data resume command are also high.

[0194] Specifically, if the amount of data stored in the memory is less than the preset amount of data, the second signal driving module 512 outputs a control signal of the corresponding level according to the flash memory interface protocol, thereby generating a first continuation instruction and sending the first continuation instruction to the field programmable gate array 10 so that the field programmable gate array 10 continues to send the first data.

[0195] When the main controller 50 sends the second data to the field-programmable gate array 10, if the amount of data stored in the memory is greater than or equal to the preset amount of data, the second signal driving module 512 outputs a control signal of the corresponding level according to the flash memory interface protocol, thereby generating a second pause instruction and sending the second pause instruction to the field-programmable gate array 10 to make the field-programmable gate array 10 pause writing the second data; if the amount of data stored in the memory is less than the preset amount of data, the second signal driving module 512 outputs a control signal of the corresponding level according to the flash memory interface protocol, thereby generating a second resume instruction and sending the second resume instruction to the field-programmable gate array 10 to make the field-programmable gate array 10 continue writing the second data.

[0196] Please see Figure 13 , Figure 13 This is a timing diagram of the control signals when a main controller reads the first data in a field-programmable gate array, according to an embodiment of this application. like Figure 13 As shown, when the main controller 50 reads the first data in the field programmable gate array 10, the second signal driving module 512 uses the level and timing combination of the RE signal, CE signal, CLE signal, and WE signal to represent the first read instruction, the first pause instruction, and the first resume instruction.

[0197] Please see Figure 14 , Figure 14 This is a timing diagram of the control signals when a main controller writes second data to a field-programmable gate array, provided in an embodiment of this application. like Figure 14 As shown, when the main controller 50 writes the second data to the field programmable gate array 10, the second signal driving module 512 uses the level and timing combination of the RE signal, CE signal, CLE signal, and WE signal to represent the first write instruction, the second pause instruction, and the second resume instruction.

[0198] In the case where the storage system 100 includes a memory, the command parsing module 122 receives and parses the pause transmission command to obtain the corresponding operation command, and sends the operation command to the high-speed interface module 123 so that the high-speed interface module 123 pauses the transmission of the first data or pauses the writing of the second data.

[0199] Specifically, when the field programmable gate array 10 sends the first data to the main controller 50, the command parsing module 122 receives and parses the first pause instruction sent by the second signal drive module 512 to obtain the corresponding operation instruction, and sends the operation instruction to the high-speed interface module 123 so that the high-speed interface module 123 pauses the transmission of the first data.

[0200] When the main controller 50 sends the second data to the field programmable gate array 10, the command parsing module 122 receives and parses the second pause instruction sent by the second signal drive module 512 to obtain the corresponding operation instruction, and sends the operation instruction to the high-speed interface module 123 so that the high-speed interface module 123 pauses writing the second data.

[0201] In some embodiments, the command parsing module 122 receives and parses the data continuation instruction to obtain the corresponding operation instruction, and sends the operation instruction to the high-speed interface module 123 so that the high-speed interface module 123 continues to send the first data or continues to write the second data.

[0202] Specifically, when the field programmable gate array 10 sends the first data to the main controller 50, the command parsing module 122 receives and parses the first continuation instruction sent by the second signal driving module 512 to obtain the corresponding operation instruction, and sends the operation instruction to the high-speed interface module 123 so that the high-speed interface module 123 continues to send the first data.

[0203] When the main controller 50 sends the second data to the field programmable gate array 10, the command parsing module 122 receives and parses the second continuation instruction sent by the second signal drive module 512 to obtain the corresponding operation instruction, and sends the operation instruction to the high-speed interface module 123 so that the high-speed interface module 123 continues to write the second data.

[0204] By sending pause transmission commands and / or data resume transmission commands to the field programmable gate array 10 through the second signal drive module 512, this application can solve the data flow control problem between the main controller 50 and the high-speed interface module 123, reduce the pressure on the data buffers at both ends, and thus reduce the occurrence of data loss.

[0205] Please see Figure 15 , Figure 15 This is a schematic diagram of a main controller reading first data according to an embodiment of this application; like Figure 15 As shown, the data channel module 51 operates in data channel mode. The first signal driving module 511 outputs a clock signal according to the control command, and the second signal driving module 512 outputs a first read command according to the control command. The clock module 121 receives the clock signal, and the command parsing module 122 parses the first read command and then starts the high-speed interface module 123 to read and transmit data. The second data is transmitted from the user logic module 11 through the first data interface 124 and the high-speed interface module 123 to the data interface module 513 in the data channel module 51. After the data interface module 513 collects the second data, it transmits the second data to the main controller 50. When there is no data in the first data interface 124, the high-speed interface module 123 stops data transmission.

[0206] When the amount of data stored in the memory is greater than or equal to a preset data amount, the data interface module 513 cannot receive data. The second signal driving module 512 sends a first pause command, and the command parsing module 122, after parsing the first pause command, stops the high-speed interface module 123 from transmitting data. When the amount of data stored in the memory is less than the preset data amount, the data interface module 513 can continue to receive data. The second signal driving module 512 sends a first transmission command, and the command parsing module 122, after parsing the first transmission command, restarts the high-speed interface module 123 to resume data transmission.

[0207] Please see Figure 16 , Figure 16 This is a schematic diagram illustrating how second data is written into a field-programmable gate array according to an embodiment of this application; like Figure 16As shown, the data channel module 51 operates in data channel mode. The first signal driving module 511 outputs a clock signal according to the control command, and the second signal driving module 512 outputs a first write command according to the control command. The clock module 121 receives the clock signal, and the command parsing module 122 parses the first write command and then starts the high-speed interface module 123 to receive data. The data interface module 513 obtains the second data from the main controller and sends the second data to the high-speed interface module 123. The high-speed interface module 123 transmits the second data to the user logic module 11 through the second data interface 125. When the data channel module 51 has no data to write, the high-speed interface module 123 stops receiving data.

[0208] In some embodiments, the fourth storage system 100 further includes at least one NAND flash memory array. The data channel module includes a first channel module or a second channel module, wherein the first channel module is a data channel module connected to a field-programmable gate array (FPGA), and the second channel module is a data channel module connected to the NAND flash memory array, with each NAND flash memory array connected to one second channel module.

[0209] Please see Figure 17 , Figure 17 This is a schematic diagram of the structure of the fifth storage system provided in the embodiments of this application; like Figure 17 As shown, the storage system 100 includes a field-programmable gate array (FPGA) 10, a main controller 50, and at least one flash memory array 60. The main controller 50 is connected to the FPGA 10 and the flash memory array 60. The FPGA 10 includes at least one I / O interface 101, and the main controller 50 includes at least one first channel module 501 and at least one second channel module 502. Figure 17 Take an IO interface 101, a first channel module 501, a flash memory array 60, and a second channel module 502 as an example.

[0210] Each I / O interface 101 is connected to a first channel module 501, and each flash memory chip array 60 is connected to a second channel module 502. The first channel module 501 communicates with the I / O interface 101 via the flash memory interface protocol.

[0211] The field-programmable gate array 10 sends first data to the main controller 50 through the IO interface 101, and / or receives and stores second data sent by the main controller 50. Figure 17 The functions of the field-programmable gate array 10 and the I / O interface 101 are as follows: Figure 4 The specific functions and structures of the field-programmable gate array 10 and the I / O interface 101 are the same, and will not be described again here.

[0212] The main controller 50 receives first data through the first channel module 501 and / or sends second data to the field programmable gate array 10.

[0213] The main controller 50 reads the second data stored in the flash memory array 60 through the second channel module 502, and sends the second data to the field programmable gate array 10 through the first channel module 501; and / or, the main controller 50 sends the first data to the flash memory array 60 through the second channel module 502, so that the flash memory array 60 stores the first data.

[0214] Specifically, when the main controller 50 sends the second data to the field programmable gate array 10, the main controller 50 reads the second data stored in the flash memory chip array 60 through the second channel module 502, and sends the second data to the field programmable gate array 10 through the first channel module 501, so that the field programmable gate array 10 stores the second data.

[0215] When the field programmable gate array 10 sends the first data to the main controller 50, the main controller 50 receives the first data through the first channel module 501 and sends the first data to the flash memory array 60 through the second channel module 502, so that the flash memory array 60 stores the first data.

[0216] The first channel module 501 receives first data sent through the I / O interface 101 according to a flash memory interface protocol (such as the ONFI protocol), and / or sends second data to the field-programmable gate array 10. The first channel module 501 is a data channel module 51 connected to the field-programmable gate array 10. Figure 17 The first channel module 501 and Figure 4 The specific function and structure of the data channel module 51 are the same, and will not be described again here.

[0217] The second channel module 502 reads the second data stored in the flash memory array 60, and / or sends the first data to the flash memory array 60 so that the flash memory array 60 stores the first data.

[0218] The flash memory array 60 stores the second data and / or the first data.

[0219] In some embodiments, when the data channel module 51 is communicatively connected to the flash memory chip array 60, the main controller 50 controls the data channel module 51 to enter the flash memory interface mode.

[0220] It is understandable that the data channel module 51 (which can be called the Flash channel) is also the control module for the NAND Flash. The data channel module 51 supports two operating modes (i.e., data channel mode and flash interface mode). When the data channel module 51 is connected to the field-programmable gate array 10, it enters data channel mode, and in this mode, it becomes the first channel module 501. When the data channel module 51 is connected to the flash memory chip array 60, it enters flash interface mode, and in this mode, it becomes the second channel module 502. The first channel module 501 and the second channel module 502 have the same structure. Figure 5 The structure of the data channel module 51 shown is illustrated.

[0221] The flash interface mode (i.e., ONFI IO mode) is the mode adopted by the data channel module 51 when communicating with the flash memory array 60. In flash interface mode, the second channel module 502 operates the flash memory array 60 according to the flash interface protocol (such as the ONFI protocol).

[0222] In flash memory interface mode, the first signal driving module 511 outputs a read enable signal to the flash memory chip array 60 according to the control instructions and flash memory interface protocol. The control instructions include read operation instructions or write operation instructions.

[0223] Specifically, in ONFI IO mode, the first signal driving module 511 outputs a RE signal conforming to a flash memory interface protocol (such as the ONFI protocol) according to a read operation instruction or a write operation instruction. The frequency, duty cycle, and level characteristics of the RE signal output by the first signal driving module 511 can be set by those skilled in the art according to the actual application scenario, and are not limited here.

[0224] In flash interface mode, the second signal driving module 512 sends a second write command or a second read command to the flash memory chip array according to the control command and flash interface protocol.

[0225] Specifically, the second write instruction is a write instruction sent by the second signal driving module 512 to the flash memory array 60, instructing the flash memory array 60 to write the first data. The second read instruction is a read instruction sent by the second signal driving module 512 to the flash memory array 60 to read the second data stored in the flash memory array 60.

[0226] The second write instruction and the second read instruction are characterized by different combinations of control signal levels and timing. The combinations of control signal levels and timing corresponding to the second write instruction and the second read instruction can be set by those skilled in the art according to the type of flash memory interface protocol and the actual application scenario, and are not limited here. For example, when the flash memory interface protocol is the ONFI protocol, the second write instruction and the second read instruction are characterized by combinations of the levels and timing of the CE signal, ALE signal, CLE signal, and WE signal.

[0227] Specifically, in ONFI IO mode, if the control command is a read operation command, the second signal driving module 512 outputs a control signal conforming to the flash memory interface protocol (such as the ONFI protocol) to generate a second read command and send the second read command to the flash memory chip array 60; in ONFI IO mode, if the control command is a write operation command, the second signal driving module 512 outputs a control signal conforming to the flash memory interface protocol (such as the ONFI protocol) to generate a second write command and send the second write command to the flash memory chip array 60.

[0228] In flash interface mode, the data interface module 513 obtains the second data stored in the flash memory array 60 through the data strobe signal and the data signal, so that the main controller sends the second data to the field programmable gate array 10; and / or sends the first data to the flash memory array 60, so that the flash memory array 60 stores the first data.

[0229] Specifically, in ONFI IO mode, if the control command is a read operation command, the data interface module 513 receives the data strobe signal and data signal sent by the flash memory array 60 to obtain the second data, thereby enabling the main controller 50 to send the second data to the field programmable gate array 10 through the first channel module 501. In ONFI IO mode, if the control command is a write operation command, the data interface module 513 drives the data strobe signal and data signal to output the first data to the flash memory array 60, thereby enabling the flash memory array 60 to store the first data.

[0230] Please see Figure 18 , Figure 18 This is a timing diagram of the control signals when the main controller issues a second write command to the flash memory chip array, provided in an embodiment of this application; like Figure 18As shown, CE represents the chip select signal, CLE represents the command latch enable signal, ALE represents the address latch enable signal, and WE represents the write enable signal. RE_t represents the read enable transition signal, indicating the start of the read operation. RE_c represents the read enable complete signal, indicating the completion of the read operation. DQS_t represents the "true" terminal of the data strobe signal, which is the positive signal in the differential signal pair. DQS_c represents the "complement" terminal of the data strobe signal, which is the negative signal in the differential signal pair. DQ[7:0] represents the 8-bit data signal on the data bus. Figure 18 Command bytes are transmitted via the data bus DQ[7:0].

[0231] Please see Figure 19 , Figure 19 This is a timing diagram of the control signals when the main controller sends an address to the flash memory chip array, provided in an embodiment of this application. like Figure 19 As shown, the address bytes are transmitted via the data bus DQ[7:0].

[0232] Please see Figure 20 , Figure 20 This is a timing diagram of control signals when writing first data to a flash memory chip array, provided in an embodiment of this application. Wherein, CE_n represents the chip select signal, which is active when low; WE_n represents the write enable signal, which is active when low.

[0233] In some embodiments, the fifth storage system 100 includes a memory that stores second data and / or first data received by the main controller. The memory is located within the main controller 50, or the memory is communicatively connected to the main controller 50.

[0234] For example, when the amount of data that the main controller 50 needs to store is small, the memory is located inside the main controller 50. In this case, the memory includes, but is not limited to, DRAM. When the amount of data that the main controller 50 needs to store is large, the memory is located outside the main controller 50, and a communication connection is established between the memory and the main controller 50. In this case, the memory includes, but is not limited to, DDR.

[0235] In the case where the fifth storage system 100 includes a memory, when the amount of data stored in the memory is greater than or equal to a preset data amount, the second signal driving module 512 sends a pause transmission command to the field-programmable gate array 10, causing the field-programmable gate array 10 to pause transmitting the first data or pause writing the second data. When the amount of data stored in the memory is less than the preset data amount, the second signal driving module 512 sends a data resume transmission command to the field-programmable gate array 10, causing the field-programmable gate array 10 to continue transmitting the first data or continue writing the second data.

[0236] In the case where the fifth storage system 100 includes a memory, the command parsing module 122 receives and parses a pause transmission command to obtain a corresponding operation command, and sends the operation command to the high-speed interface module 123 to cause the high-speed interface module 123 to pause the transmission of first data or pause the writing of second data. And / or, the command parsing module 122 receives and parses a data resume transmission command to obtain a corresponding operation command, and sends the operation command to the high-speed interface module 123 to cause the high-speed interface module 123 to continue transmitting the first data or continue writing the second data.

[0237] In the case where the fifth storage system 100 includes a memory, the main controller 50 caches the read second data into the memory and sends the second data in the memory to the field programmable gate array 10 through the first channel module 501; and / or, the main controller 50 receives the first data through the first channel module 501, caches the first data into the memory, and writes the first data in the memory into the flash memory array 60 through the second channel module 502.

[0238] Specifically, when the main controller 50 sends the second data to the field programmable gate array 10, the main controller 50 reads the second data stored in the flash memory chip array 60 through the second channel module 502, caches the read second data in the memory, and then sends the second data in the memory to the field programmable gate array 10 through the first channel module 501.

[0239] When the field programmable gate array 10 sends the first data to the main controller 50, the main controller 50 receives the first data through the first channel module 501, stores the first data in the memory, and then sends the first data in the memory to the flash memory array 60 through the second channel module 502.

[0240] When the memory is located outside the main controller 50, the main controller 50 also includes a data management module and a memory control module.

[0241] The data management module connects the first channel module 501 to the memory control module. The data management module controls the transmission of first data and / or second data between the main controller 50 and the flash memory array 60. Specifically, when the field-programmable gate array 10 sends first data to the main controller 50, the data management module acquires the first data received by the first channel module 501 and sends it to the memory control module, which then transmits the first data to the flash memory array 60 via the memory.

[0242] When the main controller 50 sends the second data to the field programmable gate array 10, the data management module obtains the second data read from the flash memory chip array 60 by the second channel module 502 through the memory control module, and sends the second data to the first channel module 501.

[0243] The memory control module connects the data management module, the memory, and the second channel module 502, and manages the memory. Specifically, when the field-programmable gate array 10 sends first data to the main controller 50, the memory control module receives the first data sent by the data management module, caches the first data in the memory, then retrieves the cached first data from the memory, and sends the first data to the second channel module 502, thereby the second channel module 502 writes the first data into the flash memory array 60.

[0244] When the main controller 50 sends the second data to the field programmable gate array 10, the memory control module obtains the second data read from the flash memory chip array 60 by the second channel module 502, caches the second data in the memory, then obtains the cached second data in the memory and sends the second data to the data management module.

[0245] Please see Figure 21 , Figure 21 This is a schematic diagram of writing first data into a flash memory chip array according to an embodiment of this application; Figure 21 Taking the case where the memory is located outside the main controller 50 as an example.

[0246] like Figure 21 As shown, the first data stored in the user logic module 11 is written to the main controller 50 through the high-speed channel module 12. The first data is cached in the memory 70 through the first channel module 501, the data management module 52, and the memory control module 53. The memory control module 53 retrieves the cached first data from the memory 70 and writes the first data to the flash memory array 60 through the second channel module 502.

[0247] In some embodiments, the fifth storage system 100 further includes a host, which includes a PCIe interface.

[0248] Please see Figure 22 , Figure 22 This is a detailed structural diagram of the sixth storage system provided in the embodiments of this application; like Figure 22 As shown, the storage system 100 includes a field-programmable gate array (FPGA) 10, a main controller 50, a host 80, and at least one flash memory array 60. The main controller 50 is connected to the FPGA 10, the flash memory array 60, and the host 80. The FPGA 10 includes at least one I / O interface 101, and the main controller 50 includes at least one first channel module 501 and at least one second channel module 502. Figure 22 Take an IO interface 101, a first channel module 501, a flash memory array 60, and a second channel module 502 as an example.

[0249] Each I / O interface 101 is connected to a first channel module 501, and each flash memory chip array 60 is connected to a second channel module 502. The first channel module 501 communicates with the I / O interface 101 via the flash memory interface protocol.

[0250] The field-programmable gate array 10 sends first data to the main controller 50 through the IO interface 101, and / or receives and stores second data sent by the main controller 50. Figure 22 The functions of the field-programmable gate array 10 and the I / O interface 101 are as follows: Figure 17 The specific functions and structures of the field-programmable gate array 10 and the I / O interface 101 are the same, and will not be described again here.

[0251] The main controller 50 receives first data through the first channel module 501 and sends the first data to the flash memory array 60 through the second channel module 502. And / or, the main controller 50 reads second data stored in the flash memory array 60 through the second channel module 502 and sends the second data to the field programmable gate array 10 through the first channel module 501.

[0252] The main controller 50 also includes a PCIe interface. After writing the first data sent by the field-programmable gate array 10 into the flash memory array 60, the main controller 50 reads the first data stored in the flash memory array 60 through the second channel module 502 and sends the first data to the host 80 through the PCIe interface. And / or, the main controller 50 reads the first data stored in the field-programmable gate array 10 through the first channel module 501 and sends the first data to the host 80 through the PCIe interface.

[0253] After the host 80 sends the second data stored in the host 80 to the main controller 50 through the PCIe interface, the main controller 50 receives the second data sent by the host 80 through the PCIe interface; the main controller 50 writes the second data into the field programmable gate array 10 through the first channel module 501, or writes the second data into the flash memory chip array 60 through the second channel module 502.

[0254] Figure 22 The first channel module 501 and the second channel module 502 in Figure 17 The first channel module 501 and the second channel module 502 have the same function and structure, and will not be described again here.

[0255] The flash memory array 60 stores the second data and / or the first data.

[0256] The host 80 obtains the first data stored in the flash memory array 60 or the field programmable gate array 10 through the PCIe interface; and / or, the host 80 sends the second data stored in the host 80 to the main controller 50 through the PCIe interface, so that the main controller 50 writes the second data into the field programmable gate array 10 or the flash memory array 60.

[0257] Specifically, when host 80 obtains the first data stored in flash memory array 60 via PCIe interface: After the main controller 50 writes the first data sent by the field-programmable gate array 10 into the flash memory array 60, the host 80 sends a first command to the main controller 50 via the PCIe interface. Upon receiving the first command, the main controller 50 reads the first data stored in the flash memory array 60 through the second channel module 502 and sends the first data to the host 80 via the PCIe interface. The host 80 receives the first data via the PCIe interface, thereby acquiring the first data stored in the flash memory array 60. The first command is an instruction for the main controller 50 to send the first data stored in the flash memory array 60 to the host 80.

[0258] When host 80 obtains the first data stored in field-programmable gate array 10 via PCIe interface: The host 80 sends a second command to the main controller 50 via the PCIe interface. Upon receiving the second command, the main controller 50 reads the first data stored in the field-programmable gate array 10 through the first channel module 501 and sends the first data to the host 80 via the PCIe interface. The host 80 receives the first data via the PCIe interface, thereby acquiring the first data stored in the field-programmable gate array 10. The second command instructs the main controller 50 to read the first data stored in the field-programmable gate array 10 and send it to the host 80.

[0259] When host 80 sends the second data stored in host 80 to main controller 50 via PCIe interface: The host 80 sends the second data stored in the host 80 to the main controller 50 through the PCIe interface; the main controller 50 receives the second data sent by the host 80 through the PCIe interface; the main controller 50 writes the second data into the field programmable gate array 10 through the first channel module 501, or writes the second data into the flash memory array 60 through the second channel module 502.

[0260] In some embodiments, the fourth storage system further includes at least one flash memory device, and the main controller 50 further includes a PCIe interface.

[0261] Please see Figure 23 , Figure 23 This is a detailed structural diagram of the seventh storage system provided in the embodiments of this application; like Figure 23 As shown, the storage system 100 includes a field-programmable gate array (FPGA) 10, a main controller 50, and at least one flash memory device 90. The main controller 50 is connected to the FPGA 10 and the flash memory device 90. The FPGA 10 includes at least one I / O interface 101, and the main controller 50 includes at least one data channel module 51. Figure 23 Take an IO interface 101, a data channel module 51, and a flash memory device 90 as an example.

[0262] Each IO interface 101 is connected to a data channel module 51, and the data channel module 51 communicates with the IO interface 101 through the flash interface protocol.

[0263] The field-programmable gate array 10 sends first data to the main controller 50 through the IO interface 101, and / or receives and stores second data sent by the main controller 50.

[0264] The main controller 50 receives first data through the data channel module 51 and / or sends second data to the field programmable gate array 10.

[0265] The main controller 50 reads the second data stored in the flash memory device through the PCIe interface and sends the second data to the field programmable gate array 10 through the data channel module 51; and / or, the main controller 50 sends the first data to the flash memory device 90 through the PCIe interface so that the flash memory device 90 stores the first data.

[0266] Specifically, when the main controller 50 sends the second data to the field programmable gate array 10, the main controller 50 reads the second data stored in the flash memory device through the PCIe interface and sends the second data to the field programmable gate array 10 through the data channel module 51.

[0267] When the field programmable gate array 10 sends the first data to the main controller 50, the main controller 50 receives the first data sent by the field programmable gate array 10 through the data channel module 51, and sends the first data to the flash memory device 90 through the PCIe interface, so that the flash memory device 90 stores the first data received by the main controller 50.

[0268] The flash memory device 90 stores the second data and / or the first data received by the main controller 50.

[0269] Figure 23 The specific functions of the field-programmable gate array 10, I / O interface 101, and data channel module 51 are as follows: Figure 4 The specific functions and structures of the field-programmable gate array 10, IO interface 101, and data channel module 51 are the same, and will not be described again here.

[0270] In some embodiments, the seventh storage system 100 further includes at least one flash memory array. The data channel module includes a first channel module or a second channel module, wherein the first channel module is a data channel module connected to a field-programmable gate array (FPGA), and the second channel module is a data channel module connected to a flash memory array, with each flash memory array connected to one second channel module.

[0271] Please see Figure 24 , Figure 24 This is a detailed structural diagram of the eighth storage system provided in the embodiments of this application; like Figure 24 As shown, the storage system 100 includes a field-programmable gate array (FPGA) 10, a main controller 50, at least one flash memory chip array 60, and at least one flash memory device 90. The main controller 50 is connected to the FPGA 10, the flash memory chip array 60, and the flash memory device 90. The FPGA 10 includes at least one I / O interface 101, and the main controller 50 includes at least one first channel module 501 and at least one second channel module 502. Figure 22 Take an IO interface 101, a first channel module 501, a flash memory array 60, a second channel module 502, and a flash memory device 90 as an example.

[0272] Each I / O interface 101 is connected to a first channel module 501, and each flash memory chip array 60 is connected to a second channel module 502. The first channel module 501 communicates with the I / O interface 101 via the flash memory interface protocol.

[0273] The field-programmable gate array 10 sends first data to the main controller 50 through the IO interface 101, and / or receives and stores second data sent by the main controller 50. Figure 24 The functions of the field-programmable gate array 10 and the I / O interface 101 are as follows: Figure 17 The field-programmable gate array 10 and the IO interface 101 in the above have the same function, and will not be described again here.

[0274] The main controller 50 receives first data through the first channel module 501 and / or sends second data to the field programmable gate array 10.

[0275] Flash memory array 60 stores second data and / or first data received by the main controller. Flash memory device 90 stores second data and / or first data received by the main controller 50.

[0276] The flash memory device 90 and the flash memory array 60 can store different data or the same data. When the flash memory device 90 and the flash memory array 60 store the same data, the data stored in the flash memory device 90 can serve as a backup of the data stored in the flash memory array 60.

[0277] The main controller 50 reads the second data stored in the flash memory array 60 or the flash memory device 90 and sends the second data to the field programmable gate array; and / or, the main controller 50 writes the first data into the flash memory array 60 and / or the flash memory device 90.

[0278] Specifically, when the main controller 50 sends the second data to the field programmable gate array 10, the main controller 50 reads the second data stored in the flash memory chip array 60 through the second channel module 502 and sends the second data to the field programmable gate array; or, the main controller 50 reads the second data stored in the flash memory device 90 through the PCIe interface and sends the second data to the field programmable gate array.

[0279] When the Field Programmable Gate Array (FPGA) 10 sends first data to the FPGA 10, the main controller 50 receives the first data sent by the FPGA 10 through the data channel module 51, and sends the first data to the flash memory device 90 through the PCIe interface, so that the flash memory device 90 stores the first data received by the main controller 50. Alternatively, after receiving the first data, the main controller 50 sends the first data to the flash memory array 60 through the second channel module 502, so that the flash memory array 60 stores the first data received by the main controller 50. Alternatively, after receiving the first data, the main controller 50 divides the first data into two parts for storage, sends part of the first data to the flash memory array 60 through the second channel module 502, and sends the other part of the first data to the flash memory device 90 through the PCIe interface, so that the flash memory array 60 and the flash memory device 90 each store a part of the first data. Alternatively, after receiving the first data, the main controller 50 sends the first data to the flash memory array 60 through the second channel module 502, and then sends the first data to the flash memory device 90 through the PCIe interface. The flash memory array 60 and the flash memory device 90 store the first data simultaneously, thereby achieving data backup.

[0280] pass Figure 17 , Figure 22 , Figure 23 , Figure 24 All with Figure 4 The storage system 100 in this application adopts different structures, and this application can provide a variety of storage solutions to adapt to different user scenarios: Figure 4 The storage system 100 in the middle has a simple structure and can achieve high-speed data storage; Figure 17 The storage system 100 in the middle has a simple structure and can achieve high-speed data storage and provide a large bandwidth; Figure 22 The storage system 100 in the middle can not only realize high-speed data storage, but also support direct access to data by the host; Figure 23 The storage system 100 has a simple structure, supports high-speed data storage, can provide high bandwidth and large capacity storage, and is compatible with flash memory devices on the market. Figure 24 The storage system 100 supports high-speed data storage and can provide large-capacity storage, offering different storage options for different types of data.

[0281] Please see Figure 25 , Figure 25 This is a detailed structural diagram of a main controller provided in an embodiment of this application; Figure 25 Taking the memory located outside the main controller 50 as an example, the main controller 50 includes a memory control module 53.

[0282] like Figure 25As shown, the main controller 50 includes at least one data channel module 51, a data management module 52, a memory control module 53, and a PCIe interface 54. This main controller 50 is adaptable to... Figure 4 , Figure 17 , Figure 22 , Figure 23 , Figure 24 Any one of the storage systems 100.

[0283] The data channel module 51 supports two operating modes. When the data channel module 51 is connected to the field-programmable gate array 10, the data channel module 51 enters the data channel mode, which is the first channel module 501. When the data channel module 51 is connected to the flash memory chip array 60, the data channel module 51 enters the flash memory interface mode, which is the second channel module 502.

[0284] The data management module 52 can manage the transmission of first data and / or second data between the data channel module 51 and the memory control module 53, and can also manage the transmission of first data and / or second data between the data channel module 51 and the PCIe interface 54. The memory control module 53 stores the first data and / or second data in the memory. The PCIe interface 54 can be connected to the host 80 or to a flash memory device 90.

[0285] In this embodiment, a storage system is provided, comprising a field-programmable gate array (FPGA) and a main controller. The FPGA includes an I / O interface, and the main controller includes a data channel module. The data channel module and the I / O interface communicate via a flash memory interface protocol. The FPGA sends first data to the main controller via the I / O interface and / or receives and stores second data sent by the main controller. The main controller receives the first data via the data channel module and / or sends the second data to the FPGA.

[0286] The system uses a field-programmable gate array (FPGA) to send first data to the main controller via an I / O interface, and / or to receive and store second data sent by the main controller. The main controller receives the first data and / or sends the second data to the FPGA via a data channel module. The data channel module communicates with the I / O interface via a flash memory interface protocol. On the one hand, the main controller in this application can replace the SoC and its external storage device in existing solutions, eliminating the need to develop storage functions in the SoC separately, thereby reducing the hardware design complexity and overall cost of the system. On the other hand, the FPGA in this application uses a common I / O interface instead of a PCIe interface. Compared with FPGAs that support PCIe, FPGAs using a common I / O interface are cheaper, thereby reducing the system hardware cost. Please see Figure 26 , Figure 26 This is a flowchart illustrating a storage method provided in an embodiment of this application; In this embodiment, the storage method is applied to the storage system 100 in the above embodiment. The storage system 100 includes a field-programmable gate array 10 and a main controller 50. The field-programmable gate array 10 includes an I / O interface 101, and the main controller 50 includes a data channel module 51. The data channel module 51 and the I / O interface 101 communicate via a flash memory interface protocol.

[0287] like Figure 26 As shown, the storage method includes: Step S261: Send the first data to the main controller based on the IO interface of the field programmable gate array, and receive the first data based on the data channel module of the main controller; Specifically, when the main controller 50 reads and stores the first data in the field programmable gate array 10, the field programmable gate array 10 sends the first data to the main controller 50 through the IO interface 101, and the main controller 50 receives the first data through the data channel module 51, thereby realizing high-speed data storage.

[0288] Step S262: The second data is sent to the field programmable gate array (FPGA) based on the data channel module of the main controller, and the second data is received based on the IO interface of the FPGA to store the second data in the FPGA.

[0289] Specifically, when the main controller 50 writes the second data to the field programmable gate array 10, the main controller 50 sends the second data to the field programmable gate array 10 through the data channel module 51, and the field programmable gate array 10 receives the second data through the IO interface 101, thereby realizing high-speed data storage.

[0290] For details on the specific structure of the main controller 50 and the field-programmable gate array 10, as well as the data interaction process of each module, please refer to the relevant content of the fourth type of storage system 100 above, which will not be repeated here.

[0291] By interacting with the main controller's data channel module through the I / O interface based on the field-programmable gate array (FPGA), this application eliminates the need to use the SoC and its external storage devices in existing solutions, and also eliminates the need to develop storage functions in the SoC separately. Moreover, compared with FPGAs that support PCIe, the FPGA using a common I / O interface in this application is less expensive, thereby reducing the hardware design complexity and hardware cost of the system. In some embodiments, the fourth storage system 100 further includes at least one flash memory array connected to the host controller. In this case, the storage system 100 employs... Figure 17The structure of the fifth type of storage system in China.

[0292] The method further includes: reading second data stored in the flash memory array based on the main controller and sending the second data to the field programmable gate array; and / or sending first data to the flash memory array based on the main controller, so that the flash memory array stores the first data.

[0293] Specifically, when the main controller 50 reads and stores the first data in the field programmable gate array 10, the field programmable gate array 10 sends the first data to the main controller 50 through the IO interface 101. The main controller 50 receives the first data through the data channel module 51 and sends the first data to the flash memory array 60 so that the flash memory array 60 stores the first data.

[0294] When the main controller 50 writes the second data to the field programmable gate array 10, the main controller 50 reads the second data stored in the flash memory chip array 60 and sends the second data to the field programmable gate array 10 through the data channel module 51. The field programmable gate array 10 receives the second data through the IO interface 101, thereby realizing high-speed data storage.

[0295] For details on the data interaction process between the main controller 50, the flash memory array 60, and the field-programmable gate array 10, please refer to the relevant content of the fifth type of storage system 100 above, which will not be repeated here.

[0296] In some embodiments, the fifth storage system 100 further includes a host connected to the main controller 50 via a PCIe interface, and the main controller 50 includes a PCIe interface. In this case, the storage system 100 employs... Figure 22 The structure of the sixth type of storage system in China.

[0297] The method further includes: acquiring first data stored in a flash memory array or field-programmable gate array via the host's PCIe interface; and / or sending second data stored in the host to the main controller via the host's PCIe interface, so that the main controller writes the second data into the field-programmable gate array or flash memory array.

[0298] Specifically, when the main controller 50 reads and stores the first data in the field-programmable gate array 10, after the main controller 50 writes the first data sent by the field-programmable gate array 10 into the flash memory array 60, the main controller 50 reads the first data stored in the flash memory array 60 through the second channel module 502 and sends the first data to the host 80 through the PCIe interface. The host 80 receives the first data through the PCIe interface, thereby obtaining the first data stored in the flash memory array 60.

[0299] Alternatively, the main controller 50 reads the first data stored in the field-programmable gate array 10 through the first channel module 501, and sends the first data to the host 80 through the PCIe interface. The host 80 receives the first data through the PCIe interface, thereby acquiring the first data stored in the field-programmable gate array 10.

[0300] When the host 80 sends the second data stored in the host 80 to the main controller 50 through the PCIe interface, the host 80 sends the second data stored in the host 80 to the main controller 50 through the PCIe interface. The main controller 50 receives the second data sent by the host 80 through the PCIe interface, and then writes the second data into the field programmable gate array 10 through the first channel module 501, or writes the second data into the flash memory chip array 60 through the second channel module 502.

[0301] For details on the specific data interaction process between the main controller 50, the field-programmable gate array 10, the flash memory chip array 60, and the host 80, please refer to the relevant content of the sixth type of storage system 100 above, which will not be repeated here.

[0302] In some embodiments, the fourth storage system 100 further includes at least one flash memory device 90 connected to a host controller 50, which also includes a PCIe interface. In this case, the storage system 100 employs... Figure 23 The structure of the seventh type of storage system in China.

[0303] The method further includes: reading second data stored in flash memory device 90 based on the PCIe interface of the main controller, and sending the second data to field programmable gate array 10; and / or sending first data to flash memory device 90 based on the PCIe interface of the main controller, so that flash memory device 90 stores the first data.

[0304] Specifically, when the main controller 50 writes second data to the field programmable gate array 10, the main controller 50 reads the second data stored in the flash memory device 90 through the PCIe interface and sends the second data to the field programmable gate array 10 through the data channel module 51.

[0305] When the main controller 50 reads and stores the first data in the field programmable gate array 10, after the main controller 50 receives the first data sent by the field programmable gate array 10, the main controller 50 sends the first data to the flash memory device 90 through the PCIe interface, and the flash memory device 90 receives and stores the first data.

[0306] For details on the specific data interaction process between the main controller 50, the field-programmable gate array 10, and the flash memory device 90, please refer to the relevant content of the seventh type of storage system 100 above, which will not be repeated here.

[0307] In some embodiments, the seventh storage system 100 further includes at least one flash memory array connected to the host controller. In this case, the storage system 100 employs... Figure 24 The structure of the eighth type of storage system in China.

[0308] The method further includes: reading second data stored in the flash memory chip array or flash memory device based on the main controller, and sending the second data to the field programmable gate array; and / or writing first data into the flash memory chip array and / or flash memory device based on the main controller.

[0309] Specifically, when the main controller 50 writes second data to the field-programmable gate array 10, the main controller 50 reads the second data stored in the flash memory chip array 60 and sends the second data to the field-programmable gate array. Alternatively, the main controller 50 reads the second data stored in the flash memory device 90 through the PCIe interface and sends the second data to the field-programmable gate array.

[0310] When the main controller 50 reads and stores the first data in the field-programmable gate array 10, the main controller 50 receives the first data sent by the field-programmable gate array 10 through the data channel module 51, and sends the first data to the flash memory device 90 through the PCIe interface. The flash memory device 90 receives and stores the first data. Alternatively, after receiving the first data, the main controller 50 sends the first data to the flash memory array 60 through the second channel module 502, and the flash memory array 60 receives and stores the first data. Alternatively, after receiving the first data, the main controller 50 divides the first data into two parts for storage. It sends one part of the first data to the flash memory array 60 through the second channel module 502, and sends the other part of the first data to the flash memory device 90 through the PCIe interface, so that the flash memory array 60 and the flash memory device 90 each store a portion of the first data. Alternatively, after receiving the first data, the main controller 50 sends the first data to the flash memory array 60 through the second channel module 502, and then sends the first data to the flash memory device 90 through the PCIe interface. The flash memory array 60 and the flash memory device 90 store the first data simultaneously, thereby achieving data backup.

[0311] For details on the specific data interaction process between the main controller 50, the field-programmable gate array 10, the flash memory chip array 60, and the flash memory device 90, please refer to the relevant content of the eighth type of storage system 100 above, which will not be repeated here.

[0312] In this embodiment, a storage method is provided, which is applied to the storage system in the above embodiments. The storage system includes a field-programmable gate array (FPGA) and a main controller. The FPGA includes an I / O interface, and the main controller includes a data channel module. The data channel module and the I / O interface communicate via a flash memory interface protocol. The storage method includes: sending first data to the main controller via the FPGA's I / O interface and receiving the first data via the main controller's data channel module; and / or sending second data to the FPGA via the main controller's data channel module and receiving the second data via the FPGA's I / O interface to store the second data in the FPGA.

[0313] By interacting with the main controller's data channel module through the I / O interface based on the field-programmable gate array (FPGA), the main controller in this application can replace the SoC and its external storage devices in existing solutions, eliminating the need to develop storage functions in the SoC separately, thereby reducing the hardware design complexity and overall cost of the system. On the other hand, the FPGA in this application uses a common I / O interface instead of a PCIe interface. Compared with FPGAs that support PCIe, FPGAs using a common I / O interface are cheaper, thereby reducing the system hardware cost. This application also provides a non-volatile computer storage medium storing computer-executable instructions that can be executed by one or more processors. For example, the one or more processors can execute the storage method in any of the above method embodiments, such as executing... Figure 26 The steps described.

[0314] This application also provides a computer program product comprising one or more lines of program code stored in a non-volatile computer-readable storage medium. A processor reads the program code from the non-volatile computer-readable storage medium and executes the program code to complete the method steps of the storage method provided in the above embodiments.

[0315] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program or program code related to hardware. The program can be stored in a non-volatile computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0316] The apparatus or device embodiments described above are merely illustrative. The unit modules described as separate components may or may not be physically separate, and the components shown as module units may or may not be physical units; that is, they may be located in one place or distributed across multiple network module units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0317] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general-purpose hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions for a computer device (which may be a personal computer, server, or network device, etc.) to execute the various embodiments or some parts of the embodiments.

[0318] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above. For the sake of brevity, they are not provided in detail; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A storage system, characterized in that, The storage system includes a field-programmable gate array (FPGA) and a main controller. The FPGA includes an I / O interface, and the main controller includes a data channel module. The data channel module communicates with the I / O interface via a flash memory interface protocol. The field-programmable gate array sends first data to the main controller through the I / O interface, and / or receives second data sent by the main controller; The main controller receives the first data through the data channel module and / or sends the second data to the field-programmable gate array.

2. The system according to claim 1, characterized in that, The number of data channel modules is at least one, and the field-programmable gate array includes a user logic module and at least one high-speed channel module, with each high-speed channel module connected to one of the data channel modules; The high-speed channel module includes the IO interface, and the high-speed channel module is also connected to the user logic module; The high-speed channel module receives the second data sent by the data channel module based on the flash memory interface protocol and writes the second data into the user logic module; and / or, the high-speed channel module reads the first data in the user logic module and sends the first data to the data channel module based on the flash memory interface protocol.

3. The system according to claim 2, characterized in that, The data channel module includes a first signal driving module, a second signal driving module, and a data interface module; the high-speed channel module includes a clock module, a command parsing module, a high-speed interface module, a first data interface, and a second data interface. The clock module receives the clock signal sent by the first signal driving module and sends the clock signal to the high-speed interface module; The command parsing module receives and parses the first write command or the first read command sent by the second signal driving module, generates the corresponding operation command, and sends the operation command to the high-speed interface module; The high-speed interface module receives and executes the operation instruction to write the second data sent by the data interface module into the user logic module, and / or read the first data and send the first data to the data channel module; The first data interface transmits the first data output by the user logic module to the high-speed interface module; The second data interface transmits the second data output by the high-speed interface module to the user logic module.

4. The system according to claim 3, characterized in that, The field-programmable gate array further includes a control module; the control module connects the main controller and the high-speed channel module, and the control module controls the high-speed channel module to delay the transmission of the first data and / or the second data; The high-speed interface module includes an input delay link, an output delay link, a transmitting module, a receiving module, and an adjustment module; The input delay link transmits the second data delay sent by the data interface module to the receiving module according to the input delay parameter; The receiving module receives the second data transmitted by the input delay link and transmits the second data to the second data interface; The sending module acquires the first data transmitted by the first data interface and sends the first data to the output delay link; The output delay link transmits the first data to the data interface module with a delay according to the output delay parameter; The adjustment module adjusts the input delay parameter and / or the output delay parameter; The input delay link includes the input delay link corresponding to the data strobe signal and the input delay link corresponding to the data signal, and the output delay link includes the output delay link corresponding to the data strobe signal and the output delay link corresponding to the data signal.

5. The system according to claim 4, characterized in that, When adjusting the input delay parameter: The main controller sends first preset data to the field-programmable gate array through the data channel module; The adjustment module sets the parameter value of the input delay parameter to a first preset value, reads sampled data from the receiving module, and compares the sampled data with the first preset data stored inside the adjustment module to obtain the determination result of the current input delay parameter. The sampled data is transmitted to the receiving module by the input delay link based on the first preset value delay, and the determination result includes a valid value or an invalid value. The adjustment module determines the judgment result as a valid value when the sampled data is the same as the first preset data; and determines the judgment result as an invalid value when the sampled data is different from the first preset data. When the number of updates to the input delay parameter is less than a first preset number, the adjustment module updates the parameter value of the input delay parameter. After the main controller resends the updated first preset data to the field programmable gate array, the module reads new sampled data from the receiving module and compares the new sampled data with the updated first preset data to obtain the determination result of the current input delay parameter. The new sampled data is transmitted to the receiving module by the input delay link based on the updated input delay parameter. When the number of updates to the input delay parameter equals a first preset number, the adjustment module stops updating the input delay parameter, determines a first target parameter, combines several first target parameters to obtain a first window, determines the median value of the first window, and sets the input delay parameter to the median value. Wherein, the first target parameter is the input delay parameter for which the determination result is valid, and the median value is the median of several first target parameters in the first window.

6. The system according to claim 4, characterized in that, When adjusting the output delay parameter: The adjustment module sets the output delay parameter value to a second preset value and sends a trigger signal and second preset data to the sending module, so that the sending module transmits the second preset data to the output delay link, thereby causing the output delay link to transmit the second preset data to the main controller with a delay based on the second preset value; The main controller receives the data transmitted by the output delay link and compares the data with the second preset data stored inside the main controller to obtain the determination result of the current output delay parameter, wherein the determination result includes a valid value or an invalid value; When the data is the same as the second preset data, the main controller determines that the determination result is a valid value; when the data is different from the second preset data, it determines that the determination result is an invalid value; and sends the determination result to the field programmable gate array through the data channel module. The adjustment module acquires and records the determination result of the current output delay parameter sent by the main controller; When the number of updates to the output delay parameter is less than a second preset number, the adjustment module updates the parameter value of the output delay parameter and the second preset data, and sends a trigger signal and the updated second preset data to the sending module, so that the output delay link transmits the updated second preset data to the main controller with a delay based on the updated output delay parameter; and obtains and records the determination result of the current output delay parameter sent by the main controller. When the number of updates to the output delay parameter equals a second preset number, the adjustment module stops updating the output delay parameter, determines a second target parameter, combines several second target parameters to obtain a second window, determines the median value of the second window, and sets the output delay parameter to the median value. Wherein, the second target parameter is the output delay parameter whose judgment result is valid, and the median value is the median of several output delay parameters in the second window.

7. The system according to any one of claims 3-6, characterized in that, The storage system includes a memory that stores second data and / or first data received by the main controller; When the amount of data stored in the memory is greater than or equal to a preset amount of data, the second signal driving module sends a pause transmission command to the field programmable gate array (FPGA) to cause the FPGA to pause transmitting the first data or pause writing the second data. The command parsing module receives and parses the pause transmission command to obtain the corresponding operation command, and sends the operation command to the high-speed interface module so that the high-speed interface module pauses the transmission of the first data or pauses the writing of the second data.

8. The system according to claim 1, characterized in that, The storage system further includes at least one flash memory array, and the data channel module includes a first channel module or a second channel module. The first channel module is a data channel module connected to the field-programmable gate array, and the second channel module is a data channel module connected to the flash memory array. Each flash memory array is connected to one second channel module. The main controller reads the second data stored in the flash memory array through the second channel module, and sends the second data to the field programmable gate array through the first channel module; and / or, the main controller sends the first data to the flash memory array through the second channel module, so that the flash memory array stores the first data.

9. The system according to claim 8, characterized in that, The storage system also includes a host connected to the main controller, and the host includes a PCIe interface; The host obtains the first data stored in the flash memory array or the field-programmable gate array through the PCIe interface; And / or, the host sends the second data stored in the host to the main controller through the PCIe interface, so that the main controller writes the second data into the field-programmable gate array or the flash memory array.

10. The system according to claim 1, characterized in that, The storage system further includes at least one flash memory device connected to the main controller, and the main controller further includes a PCIe interface; The main controller reads the second data stored in the flash memory device through the PCIe interface, and sends the second data to the field programmable gate array through the data channel module; And / or, the main controller sends the first data to the flash memory device through the PCIe interface, so that the flash memory device stores the first data.

11. The system according to claim 10, characterized in that, The storage system further includes at least one flash memory array, which is connected to the main controller; The main controller reads the second data stored in the flash memory array or the flash memory device and sends the second data to the field programmable gate array; and / or, the main controller writes the first data into the flash memory array and / or the flash memory device.

12. A storage method, characterized in that, Applied to the storage system according to any one of claims 1-11, the storage system comprising a field-programmable gate array (FPGA) and a main controller, the FPGA comprising an I / O interface, the main controller comprising a data channel module, the data channel module communicating with the I / O interface via a flash interface protocol, the method comprising: The first data is sent to the main controller via the I / O interface of the field-programmable gate array, and the first data is received via the data channel module of the main controller. And / or, send the second data to the field-programmable gate array based on the data channel module of the main controller, and receive the second data based on the IO interface of the field-programmable gate array to store the second data in the field-programmable gate array.

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