PCB schematic diagram generation method, PCB schematic diagram design method and storage medium

Abstract

The invention relates to the technical field of PCB automation, in particular to a PCB schematic diagram generation method, a PCB schematic diagram design method and a storage medium, and the method comprises the steps: obtaining electrical data of each device, and carrying out the structural processing of the electrical data, and obtaining a feature vector corresponding to each device; and inputting the feature vector into a neural network model, and outputting a PCB schematic diagram after the feature vector is analyzed and processed by the neural network model. According to the method, the generation efficiency and accuracy of the PCB schematic diagram can be improved, the subsequent PCB design process is effectively linked, and the overall design link efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of PCB automation technology, specifically to a PCB schematic generation method, design method, and storage medium. Background Technology

[0002] In the process of printed circuit board (PCB) design, circuit schematics are usually drawn to visually demonstrate the components, connections, and working principles of the circuit, making it easier for people to perform circuit analysis.

[0003] Currently, PCB schematic drawing involves operators placing the required components from the software's schematic library into the drawing area, using the software's wire tools to connect the component pins according to the actual circuit connections, forming electrical paths, and then adding labels to the components. Because PCBs involve a large number of components, manual drawing is inefficient, time-consuming, and prone to human error, resulting in poor accuracy. Furthermore, it is difficult to integrate with subsequent workflows. Summary of the Invention

[0004] The purpose of this invention is to provide a PCB schematic generation method, design method, and storage medium, which can improve the generation efficiency and accuracy of PCB schematics, effectively connect with subsequent PCB design processes, and improve the overall design chain efficiency.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention discloses a PCB schematic generation method, which includes:

[0007] Acquire the electrical data of each device, and perform structured processing on the electrical data to obtain the feature vector corresponding to each device;

[0008] The feature vectors are input into the neural network model, and after analysis and processing by the neural network model, the PCB schematic diagram is output.

[0009] Furthermore, the analysis and processing via the neural network model specifically includes: constructing a heterogeneous hypergraph using the graph neural network layer in the neural network model, where the vertices of the heterogeneous hypergraph represent different devices, the hyperedges of the heterogeneous hypergraph are used to define the collaborative constraint relationships between different devices, and the physical constraint relationships are embedded through a multi-level attention mechanism; then, using the multilayer perceptron in the neural network model, layout constraint rules are generated based on the input feature vectors and physical constraint relationships.

[0010] Furthermore, the hyperedges of the heterogeneous hypergraph include energy transmission hyperedges and signal transmission hyperedges. Vertices connected by the energy transmission hyperedges have cooperative constraints on energy transmission function, and vertices connected by the signal transmission hyperedges have cooperative constraints on signal transmission function.

[0011] Furthermore, the formula for calculating the attention coefficient of the multi-level attention mechanism is as follows: In the formula,

[0012] Let W be the attention coefficient between vertex i and vertex j, ReLU be the non-linear activation function, and W be the response coefficient between vertex i and vertex j. a T Let b be the attention weight matrix. M For physical rule bias terms;

[0013] h i Let h be the eigenvector of vertex i. j Let h be the eigenvector of vertex j. k Let N be the eigenvector of vertex k. i Let i be the set of vertices adjacent to vertex i.

[0014] h i ||h j h i ||h k Indicates feature concatenation, that is, h i and h j Connect the vectors end to end, and then connect h. i and h k The vectors are connected end to end.

[0015] Furthermore, the electrical data includes device electrical parameters, device physical attribute parameters, and device functional semantic tags. After the device functional semantic tags are converted into numerical form through one-hot encoding, they are added to the device's feature vector.

[0016] Furthermore, the feature encoding of the vertex is obtained based on the feature vector of the device, where the feature vector of the device is h. v = [X1,X2,X3]∈R, where X1 is the electrical parameter of the device, X2 is the physical attribute parameter of the device, X3 is the one-hot code corresponding to the functional semantic tag of the device, and R is the set of real numbers.

[0017] Furthermore, the loss function during the training of the neural network model is s = λ1·d s +λ1·T s In the formula,

[0018] d s The spacing loss is calculated as d. s =||d pred -d IPC||2,d pred d is the predicted distance between two vertices. IPC Let ||·||2 be the standard distance between the two vertices, and ||·||2 be the L2 norm.

[0019] T s The junction temperature loss is calculated as T. s =max(0,T) pred -T limit ), T pred T is the predicted junction temperature value at the vertex. limit The standard junction temperature value at the vertex.

[0020] λ1 is the weighting coefficient for spacing loss; λ2 is the weighting coefficient for junction temperature loss.

[0021] Secondly, this invention discloses a PCB design method, which includes:

[0022] Obtain the electrical data of each component and generate the PCB schematic using the PCB schematic generation method described above;

[0023] Generate a layout strategy based on the obtained PCB schematic;

[0024] A parasitic parameter-aware multi-objective decision-making model is established. Multiple bill of materials candidate schemes are input into the multi-objective decision-making model, and the optimal solution set among the multiple bill of materials candidate schemes is obtained by using a non-dominated sorting genetic algorithm. The obtained optimal solution set is used as the bill of materials candidate scheme for the layout strategy.

[0025] Furthermore, the optimization objective formula of the multi-objective decision model is min(f1,f2,f3), where f1 is the cost of the bill of materials scheme, f2 is the electromagnetic interference radiation value calculated based on parasitic parameters, and f3 is the quality factor, which is used to measure the ratio of energy storage to energy loss of circuit energy storage elements or resonant circuits.

[0026] Furthermore, it also includes: after obtaining the optimal solution set from multiple bill of materials candidate solutions, performing sensitivity analysis based on the calculation formula. The change in quality factor ΔQ corresponding to the alternative bill of materials is calculated, where Q is... rea The actual quality factor Q after introducing parasitic effects into the alternative bill of materials. rea =f3,Q dre The nominal quality factor for the alternatives in the bill of materials;

[0027] If the absolute value of ΔQ exceeds the preset threshold, an alarm message is generated; if the absolute value of ΔQ does not exceed the preset threshold, the bill of materials candidate solution is output as the bill of materials alternative solution for the layout strategy.

[0028] Furthermore, it also includes: when generating a layout strategy based on the obtained PCB schematic, constructing an electromagnetic susceptibility gradient field to quantify the distribution of electromagnetic interference intensity in space, and combining Monte Carlo tree search to realize the routing path planning of the layout strategy.

[0029] Fourthly, the present invention discloses a computer-readable storage medium storing computer instructions, which, when executed by a processor, implement the steps in the above-described PCB schematic generation method.

[0030] The present invention has the following unexpected beneficial effects:

[0031] 1. The PCB schematic generation method described in this invention significantly improves schematic generation efficiency and reduces labor costs. This method avoids the tedious process of manually inputting and organizing data by structuring the electrical data of components (converting it into feature vectors). The neural network model directly outputs the PCB schematic, eliminating the large amount of manual operation involved in traditional methods, such as placing components, manually connecting wires, and repeatedly adjusting. This is particularly suitable for complex circuits containing a large number of components, significantly shortening the design cycle. Furthermore, for similar circuits or commonly used modules, the neural network model can quickly generate corresponding schematic structures based on historical data, eliminating the need for redesign and supporting rapid circuit modification and expansion, thus improving design iteration efficiency.

[0032] 2. The PCB schematic generation method described in this invention improves the accuracy and standardization of schematics. Traditional manual drawing is prone to errors such as wiring mistakes and labeling errors due to negligence. This method, through structured analysis of electrical data using neural networks and combined with physical constraints, can automatically avoid basic electrical errors such as short circuits and floating pins, reducing later debugging costs. The component symbols, wiring layouts, and network labels generated by the neural network model follow preset rules, avoiding the problems of inconsistent symbols and chaotic layouts in manual drawing, improving the standardization and readability of the schematic, and facilitating team collaboration and later maintenance. Furthermore, traditional schematic design heavily relies on engineers' experience, while this method, through neural networks learning the patterns of historical high-quality designs, can assist less experienced designers in generating reasonable circuit structures, lowering the design threshold.

[0033] 3. The PCB schematic generation method described in this invention optimizes the rationality of circuit logic through a heterogeneous hypergraph and attention mechanism. The vertices of the heterogeneous hypergraph are defined as different devices, and the hyperedges define collaborative constraint relationships, enabling a more comprehensive expression of the complex relationships between multiple devices and ensuring the integrity of the circuit's functional logic. The multi-level attention mechanism assigns higher weights to key physical constraints, ensuring that the model prioritizes meeting core constraints when generating the schematic, avoiding design defects caused by neglecting key physical characteristics.

[0034] 4. The PCB schematic generation method described in this invention facilitates integration with PCB design software. The schematic generated by the neural network model can directly output structured data, seamlessly connecting with PCB layout and routing tools. This avoids errors caused by manually transcribing netlists in traditional methods, achieving automated workflow from schematic to PCB design. Furthermore, because the generated schematic contains accurate physical constraints and component coordination logic, it can be directly imported into circuit simulation software for functional verification and signal integrity analysis, identifying design problems early and reducing rework rates after physical prototype fabrication. Attached Figure Description

[0035] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention.

[0036] Figure 1 This is a flowchart illustrating the PCB schematic generation method provided in an embodiment of this application.

[0037] Figure 2 This is a schematic diagram of the neural network model analysis and processing provided in the embodiments of this application.

[0038] Figure 3 This is a flowchart illustrating one implementation of the PCB design method provided in this application.

[0039] Figure 4 This is a flowchart illustrating another implementation of the PCB design method provided in this application.

[0040] Figure 5 This is a schematic diagram of the hardware entity of an electronic device provided in an embodiment of this application. Detailed Implementation

[0041] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0042] In one embodiment, see Figure 1 As shown, the present invention provides a PCB schematic generation method, which includes:

[0043] Acquire the electrical data of each device, and perform structured processing on the electrical data to obtain the feature vector corresponding to each device;

[0044] The feature vectors are input into the neural network model, and after analysis and processing by the neural network model, the PCB schematic diagram is output.

[0045] The PCB schematic generation method described in this invention significantly improves schematic generation efficiency and reduces labor costs. This method avoids the tedious process of manually inputting and organizing data by structuring the electrical data of components (converting it into feature vectors). The neural network model directly outputs the PCB schematic, eliminating the extensive manual operations of placing components, manually connecting wires, and repeatedly adjusting as in traditional methods. This is particularly suitable for complex circuits containing a large number of components, significantly shortening the design cycle. Furthermore, for similar circuits or commonly used modules, the neural network model can quickly generate corresponding schematic structures based on historical data, eliminating the need for redesign and supporting rapid circuit modification and expansion, thus improving design iteration efficiency.

[0046] The PCB schematic generation method described in this invention improves the accuracy and standardization of schematics. Traditional manual drawing is prone to errors such as wiring mistakes and labeling errors due to negligence. This method, through structured analysis of electrical data using neural networks and combined with physical constraints, can automatically avoid basic electrical errors such as short circuits and floating pins, reducing later debugging costs. The component symbols, wiring layouts, and network labels generated by the neural network model follow preset rules, avoiding the inconsistencies and chaotic layouts of manual drawing, improving the standardization and readability of the schematics, and facilitating team collaboration and later maintenance. Furthermore, traditional schematic design heavily relies on engineers' experience, while this method, through neural networks learning from the patterns of historical high-quality designs, can assist less experienced designers in generating reasonable circuit structures, lowering the design threshold.

[0047] The PCB schematic generation method described in this invention facilitates integration with PCB design software. The schematic generated by the neural network model can directly output structured data, seamlessly connecting with PCB layout and routing tools. This avoids errors caused by manually transcribing netlists in traditional methods, achieving automated workflow from schematic to PCB design. Furthermore, because the generated schematic contains accurate physical constraints and component coordination logic, it can be directly imported into circuit simulation software for functional verification and signal integrity analysis, identifying design problems early and reducing rework rates after physical prototype fabrication.

[0048] As a preferred embodiment of the present invention, see Figure 2As shown, the analysis and processing by the neural network model specifically includes: constructing a heterogeneous hypergraph using the graph neural network layer in the neural network model, where the vertices of the heterogeneous hypergraph represent different devices, the hyperedges of the heterogeneous hypergraph are used to define the collaborative constraint relationship between different devices, and the physical constraint relationship is embedded through a multi-level attention mechanism; then, the multi-layer perceptron in the neural network model is used to generate layout constraint rules based on the input feature vector and the physical constraint relationship.

[0049] The PCB schematic generation method described in this invention optimizes the rationality of circuit logic through a heterogeneous hypergraph and attention mechanism. The vertices of the heterogeneous hypergraph are defined as different devices, and the hyperedges define collaborative constraint relationships, enabling a more comprehensive expression of the complex relationships between multiple devices and ensuring the integrity of the circuit's functional logic. The multi-level attention mechanism assigns higher weights to key physical constraints, ensuring that the model prioritizes meeting core constraints when generating the schematic, avoiding design defects caused by neglecting key physical characteristics.

[0050] In a preferred embodiment of the present invention, the hyperedges of the heterogeneous hypergraph include energy transmission hyperedges and signal transmission hyperedges. Vertices connected by the energy transmission hyperedges have cooperative constraints on energy transmission function, and vertices connected by the signal transmission hyperedges have cooperative constraints on signal transmission function.

[0051] For example, an energy transport superedge e is defined. energy ={MOSFET, Inductor, Capacitor}, these three types of devices constitute the core topology of a switching power supply. The model uses hyperedge constraints to force the MOSFET (switching transistor), inductor (energy storage), and capacitor (filtering) to work together in energy transfer. Specifically, the layout must meet rules such as placing the switching transistor and inductor close to reduce parasitic inductance, and ensuring the capacitor covers the input / output ripple frequency; parameter matching must meet electrical constraints such as MOSFET withstand voltage > input voltage, and inductor value matching the switching frequency. Compared to traditional methods that cannot accurately associate functional devices, the hyperedge directly binds the core energy transfer device group, ensuring the operability of the power supply circuit.

[0052] If energy transfer is abnormal, engineers can directly focus on the energy transfer superedge e. energy The included component groups eliminate the need to traverse the entire PCB, significantly shortening the debugging cycle.

[0053] Define signal transmission superedge e singnal ={MCU, CAN transceiver}, these two types of devices are the core of CAN bus communication. The MCU is responsible for protocol parsing, and the CAN transceiver is responsible for differential signal transmission and reception. Hyperedge constraints can be enforced:

[0054] Signal path rules, such as CAN_H / CAN_L requiring differential routing and impedance matching of 120Ω;

[0055] Electrical isolation requirements, such as surge protection via TVS between the MCU and the CAN transceiver;

[0056] Timing coordination is also important; for example, the baud rate of the CAN transceiver must be consistent with the MCU configuration.

[0057] This setup ensures that the schematic generated by the neural network model is naturally compatible with the CAN bus protocol requirements, avoiding design flaws caused by understanding circuits but not protocols, such as communication packet loss due to the lack of differential impedance matching.

[0058] If the system includes multiple CAN communication channels, the hyperedge can be expanded to e. singnal ={MCU, CAN transceiver, isolator}, corresponding to an isolated CAN bus. The model automatically adds isolation devices and adjusts wiring rules through hyperedge expansion, without the need for manual redefinition of constraints, adapting to complex scenarios.

[0059] In a preferred embodiment of the present invention, the calculation formula for the attention coefficient of the multi-level attention mechanism is as follows: In the formula,

[0060] Let W be the attention coefficient between vertex i and vertex j, ReLU be the non-linear activation function, and W be the response coefficient between vertex i and vertex j. a T is the attention weight matrix, b M For physical rule bias terms;

[0061] h i Let h be the eigenvector of vertex i. j Let h be the eigenvector of vertex j. k Let N be the eigenvector of vertex k. i Let i be the set of vertices adjacent to vertex i.

[0062] h i ||h j h i ||h k Indicates feature concatenation, that is, h i and h j Connect the vectors end to end, and then connect h. i and h k The vectors are connected end to end.

[0063] Feature concatenation h of vertices i and j i ||h j By fusing the full-dimensional features of devices, compared to traditional single-feature matching, correlations can be captured more comprehensively, such as the synergy between the thermal parameters of power domain devices and the EMC parameters of signal domain devices. For example, a power chip h with a high thermal sensitivity coefficient... i With signal amplifiers containing high EMC critical levels h jAfter being assembled, the model can identify the need to find a balance between thermal management and electromagnetic compatibility, avoiding the situation where one aspect is neglected for the other.

[0064] Physical rule bias term b M Embedded power devices must be kept away from high-frequency signals, and power supply ground must be connected nearby, among other engineering constraints. During model training, b M Guide attention towards directions that conform to physical laws.

[0065] For example,

[0066] It should be noted that the physical rule bias term b M Supports custom extensions; for different scenarios, only b needs to be adjusted. M It can adapt to constraint priorities without refactoring the model, thus improving the versatility of the solution.

[0067] N i (The set of neighboring vertices of vertex i) supports local neighborhood constraints, while multi-level mechanisms can be extended to global constraints. For example, for vertex pairs in a high-frequency signal chain, the attention coefficient can prioritize satisfying equal-length wiring, i.e., local constraints; for vertex pairs spanning the power-signal domain, ground plane partitioning is prioritized, i.e., global constraints, achieving dynamic balance of multiple constraints.

[0068] ReLU activation function and weight matrix W a T This allows neural network models to automatically learn which feature dimensions are more critical for vertex interactions. Compared to fixed weights, dynamic allocation can adapt to diverse circuit scenarios and improve the quality of schematic generation.

[0069] Attention visualization It can output an attention heatmap, allowing engineers to visually see which vertex pairs are receiving priority in the design. If the generated schematic has issues, it can trace back to areas with abnormal attention coefficients to quickly pinpoint design flaws.

[0070] In a preferred embodiment of the present invention, the electrical data includes device electrical parameters, device physical attribute parameters, and device functional semantic tags. After the device functional semantic tags are converted into numerical form through one-hot encoding, they are added to the feature vector of the device.

[0071] Compared to single-parameter inputs, multi-dimensional features allow the model to better understand devices in practice, more closely aligning with actual engineering needs. Traditional feature vectors may only contain electrical parameters and physical properties, but by adding device functional semantic labels, the feature vectors can simultaneously express the device's parametric characteristics and functional positioning. For devices with similar parameters but different functions, functional semantic labels help the model accurately distinguish their roles in the circuit, ensuring that device connections in the generated schematic conform to their functional definitions and reducing the problem of using the wrong device or connection logic conflicting with functionality.

[0072] The semantic labels for device functions are text-based information (such as string descriptions) and cannot be directly processed by neural networks. One-hot encoding transforms semantic labels into numerical vectors using a single effective encoding. For example, [1,0,0] represents the power domain, preserving the uniqueness of the semantics while adapting to the numerical input requirements of neural networks, ensuring that functional information can be effectively learned and utilized by the model. In one-hot encoding, the vector dimensions of each semantic label are independent and have equal weights, ensuring that the model treats devices with different functions equally and determines their connection relationships only based on circuit logic requirements.

[0073] In a preferred embodiment of the present invention, the feature encoding of the vertex is obtained based on the feature vector of the device, wherein the feature vector of the device is h. v = [X1,X2,X3]∈R, where X1 is the electrical parameter of the device, X2 is the physical attribute parameter of the device, X3 is the one-hot code corresponding to the functional semantic tag of the device, and R is the set of real numbers.

[0074] This preferred embodiment decomposes device characteristics into three dimensions: electrical parameters X1, physical attributes X2, and functional semantics X3, covering the core attributes that need to be considered in circuit design. Specifically, the electrical parameters X1 determine the device's electrical signal interaction rules, such as the chip's operating voltage and rated current; the physical attributes X2 relate to the physical implementation constraints of the PCB; and the functional semantics X3 defines the device's role in the system. Compared to single-parameter input, multi-dimensional integration allows for a more comprehensive understanding of the device in the model, avoiding design deviations caused by missing information.

[0075] Regardless of whether the device is a general-purpose component (such as a resistor or capacitor) or a custom chip (such as a dedicated sensor), it can be converted into a feature vector (h) of a unified format by extracting X1, X2, and X3. v (∈R). This standardization allows the model to handle design requirements for diverse device types without redefining input rules for specific devices, thus improving the model's generalization ability. Furthermore, structured feature decomposition allows engineers to trace the model's decision-making logic backward. For example, if the generated schematic has layout issues, the optimization direction can be quickly identified by analyzing whether physical attribute features are correctly identified and whether functional semantics match the scenario requirements, solving the pain points of traditional black-box models being difficult to debug and optimize.

[0076] For example, the electrical parameters of a device located in the power domain on a PCB are obtained as follows: maximum operating voltage of 1200V and rated current of 50A; physical attribute parameters include a thermal sensitivity coefficient of 1.2K / W and an EMC critical level of 5; the functional semantic tag is power domain. Then the feature vector of this device is represented as: h v= [1200,50,1.2,5,1,0,0], the one-hot encoding of the power domain is [1,0,0].

[0077] In a preferred embodiment of the present invention, the loss function during the training of the neural network model is s = λ1·d s +λ1·T s In the formula,

[0078] d s The spacing loss is calculated as d. s =||d pred -d IPC ||2,d pred d is the predicted distance between two vertices. IPC Let ||·||² be the standard spacing value between two vertices, and ||·||² be the L2 norm. The spacing loss is directly related to the physical spacing constraints of the PCB. During model training, the spacing loss forces the prediction of the spacing d. pred Close to standard spacing d IPC This avoids generating designs that are feasible in schematic but cannot be manufactured on PCB.

[0079] It should be noted that the standard spacing value d IPC It can be dynamically adjusted according to the scenario; only d needs to be replaced. IPC The numerical values ​​can be adapted to different manufacturing processes, thus improving the versatility of the solution.

[0080] T s The junction temperature loss is calculated as T. s =max(0,T) pred -T limit ), T pred T is the predicted junction temperature value at the vertex. limit The standard junction temperature value at the vertex.

[0081] When the predicted junction temperature value T pred Exceeding the standard junction temperature T limit At this time, the loss function increases sharply. This design forces the model to prioritize the safety of device junction temperature, such as keeping power devices away from heat sources and increasing heat dissipation vias to avoid hardware damage caused by thermal runaway.

[0082] λ1 is the weighting coefficient for spacing loss; λ2 is the weighting coefficient for junction temperature loss.

[0083] λ1 and λ2 support constraint priority configuration. For example, in consumer electronics scenarios, λ2 can be reduced and λ1 increased to prioritize miniaturization; in industrial control scenarios, λ2 can be increased and λ1 reduced to prioritize reliability. For different needs, performance, cost, and reliability can be balanced simply by adjusting the weights, without needing to refactor the model.

[0084] Spacing and junction temperature losses can be expanded into a loss function library, such as adding EMI loss and signal integrity loss. If new constraints need to be strengthened in the future, only new loss terms need to be added and weights configured, allowing for rapid adaptation to industry standard iterations.

[0085] In one embodiment, see Figure 3 As shown, the present invention provides a PCB design method, which includes:

[0086] Obtain the electrical data of each component and generate the PCB schematic using the PCB schematic generation method described above;

[0087] Generate a layout strategy based on the obtained PCB schematic;

[0088] A parasitic parameter-aware multi-objective decision-making model is established. Multiple bill of materials candidate schemes are input into the multi-objective decision-making model, and the optimal solution set among the multiple bill of materials candidate schemes is obtained by using a non-dominated sorting genetic algorithm. The obtained optimal solution set is used as the bill of materials candidate scheme for the layout strategy.

[0089] This embodiment starts with device electrical data, first generating a schematic (based on a heterogeneous hypergraph and attention mechanism), then deriving a placement strategy based on the schematic, and finally associating it with the bill of materials (BOM). The entire process shares device feature vectors, physical constraints, and other data, avoiding the disconnect between schematic and placement / materials in traditional designs. Furthermore, energy and signal constraints from the schematic generation stage can be directly passed to the placement stage, and then to the material selection stage. This layered constraint inheritance ensures consistency between design intent and the physical form.

[0090] In this embodiment, by establishing a multi-objective decision-making model that perceives parasitic parameters, material selection no longer relies solely on nominal values ​​in technical data, but instead focuses on parasitic effects in practical applications. For example, ceramic capacitors with low ESL are required in high-frequency circuits, and connectors with low contact resistance are required in high-current circuits, ensuring that design performance matches theoretical performance.

[0091] The non-dominated sorting genetic algorithm is used to obtain the optimal solution set among multiple bill of materials candidate schemes. It is adapted to multiple constraints in material selection, and engineers can make flexible decisions based on project priorities, avoiding global collapse caused by a single objective optimization.

[0092] In a preferred embodiment of the present invention, the optimization objective formula of the multi-objective decision model is min(f1,f2,f3), where f1 is the cost of the bill of materials scheme, f2 is the electromagnetic interference radiation value calculated based on parasitic parameters, and f3 is the quality factor, which is used to measure the ratio of energy storage to energy loss of circuit energy storage elements or resonant circuits.

[0093] The cost f1 of the bill of materials (BOM) scheme is directly related to business objectives, while the electromagnetic interference radiation value f2 and quality factor f3, calculated based on parasitic parameters, are related to technical objectives. Multi-objective optimization allows the model to simultaneously perceive business and technical constraints, avoiding the situation where technology is optimal but costs run out of control or cost is optimal but performance collapses.

[0094] f2 is based on parasitic parameters rather than solely on nominal values ​​in technical data, making material selection closer to actual applications, ensuring consistency between selection, design, and actual measurement, and reducing problems caused by parasitic parameters during the trial production stage.

[0095] f2 transforms electromagnetic interference into a calculable and optimizable numerical objective. During model optimization, priority is given to reducing the use of high-EMI materials, controlling EMI risks at the source, and avoiding reliance on later remediation.

[0096] f3 directly relates to circuit energy efficiency, and multi-objective optimization can balance cost and efficiency, making the generated bill of materials naturally suited to high-efficiency design requirements.

[0097] Multi-objective optimization can generate Pareto optimal solutions, such as multiple material combinations, each with different focuses on cost and performance. Engineers can choose according to the project stage. For example, in the pilot production stage, the performance-optimal solution is selected, which has high cost but low EMI; in the mass production stage, the cost-performance balanced solution is selected, which has moderate EMI but controllable cost. Compared with traditional single solutions, solution sets allow for more flexible cost control and avoid the waste of resources caused by a one-size-fits-all approach.

[0098] In a preferred embodiment of the present invention, the PCB design method further includes: after obtaining the optimal solution set among multiple bill of materials candidate schemes, performing sensitivity analysis based on the calculation formula. The change in quality factor ΔQ corresponding to the alternative bill of materials is calculated, where Q is... rea The actual quality factor Q after introducing parasitic effects into the alternative bill of materials. rea =f3,Q dre The nominal quality factor for the alternatives in the bill of materials;

[0099] If the absolute value of ΔQ exceeds the preset threshold, an alarm message is generated; if the absolute value of ΔQ does not exceed the preset threshold, the bill of materials candidate solution is output as the bill of materials alternative solution for the layout strategy.

[0100] The nominal quality factor Q in the bill of materials dre The actual quality factor Q after introducing the parasitic effect rea There is a deviation. By calculating the change in quality factor ΔQ, the parasitic effect is transformed from a latent risk into an explicit value, allowing the gap between actual performance and nominal value to be perceived during the design phase.

[0101] When the absolute value of ΔQ exceeds a preset threshold, an alarm is generated, forcing engineers to reassess material selection (e.g., replacing it with materials with lower parasitic parameters) or adjust the design (e.g., optimizing the layout to reduce parasitic effects). This hard interception avoids the risk of ignoring parasitic effects during the design phase and having to rework the product during mass production due to substandard performance.

[0102] It should be noted that the preset threshold can be dynamically adjusted based on industry standards or historical experience. As projects accumulate, the threshold can be compiled into a corporate design rule base, allowing for direct reuse in subsequent projects and improving design standardization. For example, the preset threshold is 15%.

[0103] As a preferred embodiment of the present invention, see Figure 4 As shown, the PCB design method further includes: when generating a layout strategy based on the obtained PCB schematic, constructing an electromagnetic susceptibility gradient field to quantify the distribution of electromagnetic interference intensity in space, and combining Monte Carlo tree search to realize routing path planning for the layout strategy.

[0104] In this preferred embodiment, by constructing an electromagnetic susceptibility gradient field, abstract electromagnetic interference can be transformed into spatially quantified data. For example, high-frequency devices are surrounded by high-intensity gradient fields and must be kept away from sensitive devices. The model guides the layout through the gradient field: power devices are placed in the weak interference region of the gradient field to avoid interfering with signal chains; sensitive devices are placed in the low-intensity region of the gradient field to ensure signal integrity. Compared to traditional empirical layout, the quantification method makes electromagnetic compatibility design more scientific and verifiable.

[0105] By combining Monte Carlo tree search with routing path planning for layout strategies, the system can adapt to the pluralistic nature of layout paths. During the search process, the priority is dynamically adjusted using gradient fields, resulting in layout schemes that satisfy EMI (Electromagnetic Interference) requirements while balancing constraints such as heat distribution and routing complexity. This avoids sacrificing heat dissipation for EMI, which could lead to excessively high junction temperatures.

[0106] The PCB design method will be explained in detail below with specific examples.

[0107] Example: A PCB design method that includes:

[0108] Step 1: Obtain the electrical data of each component and generate the PCB schematic using the PCB schematic generation method described above.

[0109] 1) Input parameters: Taking the silicon carbide metal-oxide semiconductor field-effect transistor (SiC MOSFET) in the PCB as an example, input the electrical requirements document, including voltage level, signal type, and EMC level.

[0110] 2) Input parameter structuring operations:

[0111] a. Electrical parameter extraction:

[0112]

[0113] b. Physical property labeling: Thermal sensitivity coefficient is 1.2K / W, EMC critical level is 5.

[0114] 3) Heterogeneous hypergraph modeling:

[0115] Vertex construction: The eigenvectors of this device are represented as: h v =[1200,50,1.2,5,1,0,0], that is, the feature vector of the hypergraph vertex is extracted as [1200,50,1.2,5,1,0,0].

[0116] Hyperedge definition: Defines an energy transport hyperedge e energy = {MOSFET, Inductor, Capacitor};

[0117] Define signal transmission superedge e singnal = {MCU, CAN transceiver}.

[0118] 4) Attention computation for physical rule embedding:

[0119] 5) Layout rule generation and mapping:

[0120] According to d final =max(MLP(h) v ), 0.01×V max The output yields the safety clearance d. final The distance is 12mm, and a 12mm high-voltage isolation zone is formed based on the output value of the safety distance.

[0121] In the formula, MLP(h) v This indicates that a multilayer perceptron (MLP) is used to process feature h. v After processing, a theoretical safe distance recommendation value is obtained through MLP calculation;

[0122] 0.01×V max Indicates based on the maximum operating voltage V max The baseline value for safety clearance is calculated as 1% of the baseline value.

[0123] max(MLP(h v ), 0.01×V max This means taking the larger of the two values ​​to ensure that the final safety distance both references the intelligent judgment of the AI ​​model and meets the basic safety requirements for voltage insulation (preventing the risk of the safety distance being too small due to model calculation deviation).

[0124] b) Isolation domain construction: A ring-shaped no-wiring zone is generated around the MOSFET, with an inner diameter of 3mm and an outer diameter of 12mm, and a protective ring grounding point is automatically added.

[0125] 6) Output: .SchDoc format schematic file, automatically annotating key networks, such as marking high-speed Ethernet signals in red, and generating PCB constraint rules.

[0126] Step 2: Generate a layout strategy based on the obtained PCB schematic.

[0127] 1) Input: .SchDoc format schematic file, component PCB footprint library, 3D model library.

[0128] 2) Operation:

[0129] a) Power device layout: Generate heat dissipation copper areas based on heat sensitivity.

[0130] b) High-speed signal planning: Automatic priority allocation of layers for high-frequency signal paths.

[0131] 3) Output: .PcbDoc layout file.

[0132] Step 3: Gradient-enhanced routing

[0133] 1) Input: .PcbDoc layout file, EMC constraint rules.

[0134] 2) Operation:

[0135] a) By constructing an electromagnetic susceptibility gradient field, the voltage-sensitive region is defined as a high-potential restricted area, and the spatial electromagnetic interference intensity distribution is quantified;

[0136] b) Perform Monte Carlo tree search to iteratively optimize the wiring path planning;

[0137] c) Optimize differential pairs. A differential pair consists of two parallel, equal-length, equal-width, and closely spaced signal lines specifically designed to transmit differential signals. Differential pair optimization involves adjusting the structure, controlling impedance, and mitigating interference to ensure fast and stable transmission of differential signals, thus resolving transmission errors in high-speed and high-frequency signals.

[0138] 3) Output: Manufacturing documents for completed wiring.

[0139] Step 4, Component Selection and Verification: Establish a parasitic parameter-aware multi-objective decision-making model, input multiple bill of materials candidate schemes into the multi-objective decision-making model, and use a non-dominated sorting genetic algorithm to solve for the optimal solution set among the multiple bill of materials candidate schemes. The obtained optimal solution set is used as the bill of materials candidate scheme for the layout strategy.

[0140] 1) Input multiple Bill of Materials (BOM) candidate schemes into the multi-objective decision model.

[0141] 2) Operation:

[0142] a) Extract the parasitic RLC parameters of the device package and use the non-dominated sorting genetic algorithm (NSGA-II) to obtain the Pareto optimal solution set among multiple bill of materials candidate schemes.

[0143] b) Perform sensitivity analysis: Quantify the impact of layout on the Q value. When the absolute value of ΔQ exceeds 15%, an alarm is triggered and an alarm message is generated. When the absolute value of ΔQ does not exceed a preset threshold, the candidate bill of materials solution is output as an alternative bill of materials solution for the layout strategy.

[0144] 3) Output: Use the obtained optimal solution set as the alternative bill of materials for the layout strategy, and output parasitic parameter compensation suggestions.

[0145] In one embodiment, the present invention provides an electronic device including a processor and a memory, the memory storing a computer program, characterized in that the processor executes the computer program stored in the memory to implement the steps in the above-described PCB schematic generation method.

[0146] like Figure 5 As shown, the hardware entity of the electronic device 10 includes: a processor 11, a memory 12, and a communication interface 13, wherein:

[0147] The processor 11 typically controls the overall operation of the electronic device 10.

[0148] The memory 12 is configured to store instructions and applications executable by the processor 11, and can also cache data to be processed or already processed by the processor 11 and the various modules in the electronic device 10, which can be implemented through flash memory or random access memory.

[0149] Communication interface 13 enables electronic devices to communicate with other terminals or servers via a network.

[0150] Data can be transferred between the processor 11, memory 12 and communication interface 13 via bus 14.

[0151] In one embodiment, the present invention discloses a computer-readable storage medium storing computer instructions, which are used to cause a processor to execute the steps in the above-described PCB schematic generation method.

[0152] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection between devices or units can be electrical, mechanical, or other forms.

[0153] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units. They may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0154] In addition, each functional unit in the various embodiments of this application can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in hardware or in the form of hardware plus software functional units.

[0155] The above description is merely an embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A method for generating PCB schematic diagrams, characterized in that, include: Acquire the electrical data of each device, and perform structured processing on the electrical data to obtain the feature vector corresponding to each device; The feature vectors are input into the neural network model, and after analysis and processing by the neural network model, the PCB schematic diagram is output.

2. The PCB schematic generation method according to claim 1, characterized in that, The analysis and processing via the neural network model specifically includes: constructing a heterogeneous hypergraph using the graph neural network layer in the neural network model, where the vertices of the heterogeneous hypergraph represent different devices, the hyperedges of the heterogeneous hypergraph are used to define the collaborative constraint relationship between different devices, and the physical constraint relationship is embedded through a multi-level attention mechanism; then, using the multilayer perceptron in the neural network model, layout constraint rules are generated based on the input feature vector and the physical constraint relationship.

3. The PCB schematic generation method according to claim 2, characterized in that: The hyperedges of the heterogeneous hypergraph include energy transmission hyperedges and signal transmission hyperedges. Vertices connected by the energy transmission hyperedge have cooperative constraints on energy transmission function, and vertices connected by the signal transmission hyperedge have cooperative constraints on signal transmission function.

4. The PCB schematic generation method according to claim 2, characterized in that: The formula for calculating the attention coefficient of the multi-level attention mechanism is as follows: In the formula, Let be the attention coefficient between vertex i and vertex j, and ReLU be the non-linear activation function. Let b be the attention weight matrix. M For physical rule bias terms; h i Let h be the eigenvector of vertex i. j Let h be the eigenvector of vertex j. k Let N be the eigenvector of vertex k. i Let i be the set of vertices adjacent to vertex i. h i ||h j h i ||h k Indicates feature concatenation, that is, h i and h j Connect the vectors end to end, and then connect h. i and h k The vectors are connected end to end.

5. The PCB schematic generation method according to claim 1, characterized in that: The electrical data includes device electrical parameters, device physical attribute parameters, and device functional semantic tags. After the device functional semantic tags are converted into numerical form through one-hot encoding, they are added to the device's feature vector.

6. The PCB schematic generation method according to claim 5, characterized in that: The feature encoding of the vertex is obtained based on the feature vector of the device, and the feature vector of the device is h. v = [X1,X2,X3]∈R, where X1 is the electrical parameter of the device, X2 is the physical attribute parameter of the device, X3 is the one-hot code corresponding to the functional semantic tag of the device, and R is the set of real numbers.

7. The PCB schematic generation method according to claim 1, characterized in that: The loss function during the training of the neural network model is s = λ1·d s +λ1·T s In the formula, d s The spacing loss is calculated as d. s =||d pred -d IPC ||2,d pred d is the predicted distance between two vertices. IPC Let ||·||2 be the standard distance between the two vertices, and ||·||2 be the L2 norm. T s The junction temperature loss is calculated as T. s =max(0,T) pred -T limit ), T pred T is the predicted junction temperature value at the vertex. limit The standard junction temperature value at the vertex. λ1 is the weighting coefficient for spacing loss; λ2 is the weighting coefficient for junction temperature loss.

8. A PCB design method, characterized in that, include: Obtain the electrical data of each component, and obtain the PCB schematic diagram according to the PCB schematic diagram generation method according to any one of claims 1 to 7; Generate a layout strategy based on the obtained PCB schematic; A parasitic parameter-aware multi-objective decision-making model is established. Multiple bill of materials candidate schemes are input into the multi-objective decision-making model, and the optimal solution set among the multiple bill of materials candidate schemes is obtained by using a non-dominated sorting genetic algorithm. The obtained optimal solution set is used as the bill of materials candidate scheme for the layout strategy.

9. The PCB design method according to claim 8, characterized in that: The optimization objective formula of the multi-objective decision model is min(f1,f2,f3), where f1 is the cost of the bill of materials scheme, f2 is the electromagnetic interference radiation value calculated based on parasitic parameters, and f3 is the quality factor, which is used to measure the ratio of energy storage to energy loss of circuit energy storage elements or resonant circuits.

10. The PCB design method according to claim 9, characterized in that, Also includes: After obtaining the optimal solution set from multiple bill of materials candidate solutions, sensitivity analysis is performed based on the calculation formula. The change in quality factor ΔQ corresponding to the alternative bill of materials is calculated, where Q is... rea The actual quality factor Q after introducing parasitic effects into the alternative bill of materials. rea =f3,Q dre The nominal quality factor for the alternatives in the bill of materials; If the absolute value of ΔQ exceeds the preset threshold, an alarm message is generated; if the absolute value of ΔQ does not exceed the preset threshold, the bill of materials candidate solution is output as the bill of materials alternative solution for the layout strategy.

11. The PCB design method according to claim 8, characterized in that, Also includes: When generating a layout strategy based on the obtained PCB schematic, an electromagnetic susceptibility gradient field is constructed to quantify the distribution of electromagnetic interference intensity in space, and Monte Carlo tree search is combined to realize the routing path planning of the layout strategy.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the steps in the PCB schematic generation method as described in any one of claims 1 to 7.

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