Deployment method of solid state disk, storage medium, electronic equipment and program product

Abstract

The embodiment of the invention provides a deployment method of a solid state disk, a storage medium, electronic equipment and a program product, and relates to the field of computers.The method comprises the steps that first analysis operation is conducted on a hardware configuration file to obtain a storage area of an interface connector on a hard board, and second analysis operation is conducted on a software configuration file to obtain a storage area of the interface connector on the hard board; obtaining a first vertical distance between the main control chip and the interface connector, a horizontal distance between the main control chip and the right side board edge of the hard board, and a second vertical distance between the main control chip and the flash memory module to be deployed; based on the storage area, the first vertical distance, the second vertical distance and the horizontal distance, determining a first hard board area corresponding to the main control chip, a second hard board area corresponding to the memory module to be deployed and a third hard board area corresponding to the flash memory module on the hard board; and deploying a main control chip in the first hard board area, deploying a memory module in the second hard board area, and deploying a flash memory module in the third hard board area.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a method for deploying a solid-state drive, a storage medium, an electronic device, and a software product. Background Technology

[0002] In the design of solid-state drives (SSDs), traditional layout methods often employ a rigid-flex PCB. This requires power to repeatedly cross the flexible PCB, resulting in long power supply and return paths. This approach fails to adequately consider best practices for signal paths and power distribution, leading to degraded signal quality and increased power consumption. This can potentially cause poor heat dissipation, impacting the overall performance and lifespan of the SSD. Therefore, related technologies suffer from the technical challenge of high power consumption in SSDs. Summary of the Invention

[0003] This application provides a method for deploying a solid-state drive (SSD), as well as a storage medium, electronic device, and software product, to at least address the technical problem of high power consumption in SSDs in related technologies.

[0004] According to one embodiment of this application, a method for deploying a solid-state drive (SSD) is provided, comprising: performing a first parsing operation on a hardware configuration file to obtain a storage area of ​​an interface connector on a hard board; and performing a second parsing operation on a software configuration file to obtain a first vertical distance between a main controller chip and an interface connector, a horizontal distance between a main controller chip and the right edge of the hard board, and a second vertical distance between a main controller chip and a flash memory module to be deployed; determining a first hard board area corresponding to the main controller chip, a second hard board area corresponding to the memory module to be deployed, and a third hard board area corresponding to the flash memory module on the hard board based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance; and deploying the main controller chip in the first hard board area, the memory module in the second hard board area, and the flash memory module in the third hard board area.

[0005] According to one embodiment of this application, a deployment apparatus for a solid-state drive (SSD) is provided, comprising: a parsing unit, configured to perform a first parsing operation on a hardware configuration file to obtain a storage area of ​​an interface connector on a hard board, and a second parsing operation on a software configuration file to obtain a first vertical distance between a main control chip and an interface connector, a horizontal distance between the main control chip and the right edge of the hard board, and a second vertical distance between the main control chip and a flash memory module to be deployed; a determining unit, configured to determine, based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance, a first hard board area corresponding to the main control chip, a second hard board area corresponding to the memory module to be deployed, and a third hard board area corresponding to the flash memory module on the hard board; and a deployment unit, configured to deploy the main control chip in the first hard board area, deploy the memory module in the second hard board area, and deploy the flash memory module in the third hard board area.

[0006] According to yet another embodiment of this application, a computer-readable storage medium is also provided, in which a computer program is stored, wherein the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0007] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein a computer program is stored in the memory and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0008] The embodiments provided in this application parse the hardware configuration file through a first parsing operation to obtain the precise location of the interface connector, and parse the software configuration file through a second parsing operation to obtain the first vertical distance between the main control chip and the interface connector, the horizontal distance between the main control chip and the right edge of the hard board, and the second vertical distance between the main control chip and the NAND Flash module to be deployed. Based on these precise parameters, the optimal deployment positions of the main control chip, memory module, and flash memory module on the hard board can be determined more scientifically. This ensures that the signal path between the main control chip, memory module, and flash memory module is minimized, reducing unnecessary signal loop lengths and significantly improving signal integrity. Furthermore, by optimizing the distance between the main control chip and the power module, the power distribution and return path are improved, thereby increasing power efficiency and reducing power consumption. This achieves the technical effect of reducing the power consumption of the solid-state drive and solves the technical problem of high power consumption of solid-state drives in related technologies. Attached Figure Description

[0009] Figure 1 This is a hardware structure block diagram of a solid-state drive deployment method according to an embodiment of this application.

[0010] Figure 2 This is a flowchart of a solid-state drive deployment method according to an embodiment of this application.

[0011] Figure 3 This is a schematic diagram of the operation flow of DXF modular partitioning according to an embodiment of this application.

[0012] Figure 4 This is a schematic diagram of the PCB structure of an SSD according to an embodiment of this application.

[0013] Figure 5 This is a schematic diagram of the operation flow of device layout in each area according to an embodiment of this application.

[0014] Figure 6 This is a schematic diagram of the PCB structure of an SSD according to an embodiment of this application.

[0015] Figure 7 This is a diagram of a Skip via and a second-order micro-blind hole structure according to an embodiment of this application.

[0016] Figure 8 This is a schematic diagram of the operation flow of a layer and wiring design according to an embodiment of this application.

[0017] Figure 9 This is a schematic diagram illustrating the layer definition of a signal according to an embodiment of this application.

[0018] Figure 10 This is a structural block diagram of a data storage device for an edge node according to an embodiment of this application. Detailed Implementation

[0019] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0020] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0021] The methods and embodiments provided in this application can be executed on a computer terminal or similar computing device. Taking running on a computer terminal as an example, Figure 1 This is a hardware structure block diagram of a computer terminal for a solid-state drive deployment method according to an embodiment of this application. For example... Figure 1 As shown, a computer terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The computer terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the computer terminal described above. For example, the computer terminal may also include components that are more complex than those described above. Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0022] The memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the solid-state drive deployment method in this embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, thus implementing the above-described method. The memory 104 may include high-speed random access memory and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0023] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0024] As an optional solution, this embodiment provides a method for deploying a solid-state drive, such as... Figure 2 As shown, it includes:

[0025] S202, perform a first parsing operation on the hardware configuration file to obtain the storage area of ​​the interface connector on the hard board, and perform a second parsing operation on the software configuration file to obtain the first vertical distance between the main control chip and the interface connector, the horizontal distance between the main control chip and the right edge of the hard board, and the second vertical distance between the main control chip and the flash memory module to be deployed.

[0026] S204, based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance, determines on the hard board the first hard board area corresponding to the main control chip, the second hard board area corresponding to the memory module to be deployed, and the third hard board area corresponding to the flash memory module.

[0027] S206 deploys the main control chip in the first hard board area, the memory module in the second hard board area, and the flash memory module in the third hard board area.

[0028] Optionally, in this embodiment, the hardware configuration file refers to a file containing information such as the physical layout of the circuit board, component locations, connector types and locations, usually in DXF (Drawing Exchange Format) format, used to guide the physical design of the circuit board.

[0029] Optionally, in this embodiment, the software configuration file refers to a file containing information such as device logic configuration, signal type, signal trace width, signal frequency and power consumption, usually a flexible board .brd file, used to determine the parameters of signal path and component layout.

[0030] Optionally, in this embodiment, the interface connector is a component used to connect the SSD to other devices (such as the motherboard), such as a U.2 connector, which is the physical interface for communication between the SSD and the host system.

[0031] Optionally, in this embodiment, the first vertical distance represents the vertical distance between the main control chip and the interface connector, used to determine the vertical boundary of the main control chip and the starting point of the DQ signal traces. The horizontal distance refers to the horizontal distance between the main control chip and the right edge of the rigid board, used to determine the lateral boundary of the main control chip and the range of the DDR signal traces. The second vertical distance represents the vertical distance between the main control chip and the flash memory module, used to define the placement area of ​​the NAND Flash. The main control chip is the core control unit of the SSD, responsible for managing and coordinating data read and write operations. The memory module refers to the DDR memory module, used to improve the read and write speed of the SSD. The flash memory module refers to the NAND Flash module, the main storage component of the solid-state drive.

[0032] Optionally, in this embodiment, a first parsing operation is performed on the hardware configuration file to extract physical layout information such as the board outline and connector positions from the DXF file, laying the foundation for subsequent layout planning.

[0033] Optionally, in this embodiment, key signal routing parameters, such as signal width, frequency, and power requirements, are parsed from the PCB's BRD file to determine the relative position and signal path length between the main control chip and other key components.

[0034] Based on the obtained connector storage area and vertical and horizontal distances, the hard board is intelligently divided into three specific areas for deploying the main control chip, memory modules, and flash memory modules. This step ensures a reasonable layout, minimizes signal line length, and thus optimizes signal quality and power efficiency.

[0035] Optionally, in this embodiment, the main control chip is deployed in the designated first hard board area, the memory module (such as DDR) is deployed in the second hard board area, and the flash memory module (such as NAND Flash) is deployed in the third hard board area to achieve an efficient and compact layout.

[0036] It should be noted that this embodiment aims to overcome the shortcomings of existing rigid-flex PCB designs, such as poor signal integrity, inefficient power distribution, and significant heat dissipation issues. By accurately analyzing hardware and software configuration files, the ideal locations of interface connectors, the main control chip, memory modules, and flash memory modules can be determined, achieving the shortest path for signal lines and the optimal layout of the power modules. This method not only effectively solves the problems of signal interference and low power efficiency but also optimizes heat dissipation design by placing backup capacitors on the board side, further improving the performance and stability of the SSD. In addition, the pure rigid PCB design strategy simplifies the manufacturing process, reduces costs, and shortens the production cycle, bringing significant technological advancements to the SSD industry.

[0037] The embodiments provided in this application parse the hardware configuration file through a first parsing operation to obtain the precise location of the interface connector, and parse the software configuration file through a second parsing operation to obtain the first vertical distance between the main control chip and the interface connector, the horizontal distance between the main control chip and the right edge of the hard board, and the second vertical distance between the main control chip and the NAND flash memory module to be deployed. Based on these precise parameters, the optimal deployment positions of the main control chip, memory module, and flash memory module on the hard board can be determined more scientifically. This ensures that the signal path between the main control chip, memory module, and flash memory module is minimized, reducing unnecessary signal loop lengths and significantly improving signal integrity. Furthermore, by optimizing the distance between the main control chip and the power module, the power distribution and return path are improved, thereby increasing power efficiency and reducing power consumption, thus achieving the technical effect of reducing the power consumption of the solid-state drive.

[0038] As an optional approach, based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance, the following are defined on the hardboard: the first hardboard area corresponding to the main control chip, the second hardboard area corresponding to the memory module to be deployed, and the third hardboard area corresponding to the flash memory module:

[0039] A first horizontal line, a second horizontal line, and a vertical line are defined on the hard board. The first horizontal line is a first vertical distance away from the storage area in the vertical direction, and the second horizontal line is a third vertical distance away from the storage area in the vertical direction. The third vertical distance is the sum of the first vertical distance, the second vertical distance, and the vertical length of the main control chip. The vertical line is a horizontal distance away from the right edge of the board in the horizontal direction.

[0040] The closed area between the first horizontal line, the second horizontal line, the vertical line and the left edge of the rigid plate is defined as the first rigid plate area;

[0041] The enclosed area between the first horizontal line, the second horizontal line, the vertical line, and the right side edge of the board is defined as the second rigid board area;

[0042] The closed area between the second horizontal line, the vertical line, the left side edge of the board, and the lower side edge of the hard board is defined as the third hard board area.

[0043] Optionally, in this embodiment, the first rigid board area is the area on the rigid board used to deploy the main control chip, and is determined based on the position of the interface connector and the first vertical distance between the main control chip and the connector. The second rigid board area is the area on the rigid board used to deploy memory modules (e.g., DDR), and is determined by the closed area enclosed by the position of the main control chip, the first horizontal line, the second horizontal line, the vertical line, and the right side edge of the board. The third rigid board area is the area on the rigid board used to deploy flash memory modules (NANDFlash), and is determined based on the closed area enclosed by the main control chip, the second horizontal line, the vertical line, the left side edge of the board, and the lower side edge of the board.

[0044] Optionally, in this embodiment, the first vertical distance is the vertical distance between the interface connector and the main control chip, used to determine the upper edge of the main control chip. The second vertical distance is the vertical distance between the main control chip and the NAND Flash module, affecting the lower boundary of the NAND Flash module. The third vertical distance is the sum of the first vertical distance, the second vertical distance, and the height of the main control chip, used to determine the vertical span from the interface to the NAND Flash module.

[0045] Optionally, in this embodiment, the first horizontal line is a virtual line maintaining a first vertical distance from the lower edge of the interface connector, used to define the upper boundary of the main control chip. The second horizontal line is a virtual line maintaining a third vertical distance from the upper edge of the NAND Flash module, used to define the lower boundary of the NAND Flash module and the upper boundary of the memory module. A vertical line is located at the right edge of the rigid board, a virtual line measuring the horizontal distance between the main control chip and the right edge, used to define the right boundary of the memory module.

[0046] Optionally, in this embodiment, a first horizontal line, a second horizontal line, and a vertical line are drawn on the rigid board. The first horizontal line is a first vertical distance away from the interface connector, the second horizontal line is a third vertical distance away from the connector, and the vertical line is a horizontal distance away from the right edge of the board. These auxiliary lines are used to guide the layout of the components.

[0047] Using auxiliary lines and rigid board boundaries, enclosed areas are demarcated to determine the deployment areas for the main control chip, memory modules, and flash memory modules. Specifically: the first rigid board area is bounded by a first horizontal line, the left edge of the rigid board, and a vertical line; this is the deployment area for the main control chip. The second rigid board area is bounded by a first horizontal line, a second horizontal line, a vertical line, and the right edge of the rigid board; this is the deployment area for memory modules (such as DDR). The third rigid board area is bounded by a second horizontal line, a vertical line, the left edge of the rigid board, and the bottom edge of the rigid board; this is the deployment area for flash memory modules (NAND Flash).

[0048] Based on the definition of the enclosed area, the devices are deployed on their respective corresponding rigid board areas, achieving layout optimization, ensuring the shortest signal line path, efficient power management, and taking into account the rationality of heat dissipation design.

[0049] The embodiments provided in this application precisely define the deployment areas of the main control chip, memory module, and flash memory module by utilizing their relative positional relationships. This method not only ensures the rationality of the device layout but also effectively utilizes the space on the hard board, reducing the length of signal lines and thus improving signal integrity and power efficiency.

[0050] As an optional solution, deploying the main control chip in the first hard board area includes:

[0051] A rigid board region is determined from the first rigid board region, wherein the rigid board region is a second vertical distance away from the third rigid board region in the vertical direction and is adjacent to the second rigid board region in the horizontal direction;

[0052] The main control chip is deployed in the hard board area.

[0053] Optionally, in this embodiment, the first hardboard area is the area on the hardboard determined for deploying the main control chip based on the interface connector location and related parameters. The hardboard sub-area is a further subdivision of the first hardboard area. Specifically, this sub-area is separated from the third hardboard area (NANDFlash area) by a second vertical distance in the vertical direction and is adjacent to the second hardboard area (memory module area) in the horizontal direction.

[0054] Optionally, in this embodiment, the second vertical distance represents the vertical distance between the main control chip and the NAND Flash module, and is used to define the lower boundary of the main control chip and the upper boundary of the NAND Flash module.

[0055] Optionally, in this embodiment, the vertical boundary of the rigid board sub-region is determined from the first rigid board region based on a second vertical distance. This typically means that a certain distance needs to be maintained between the lower edge of the main control chip and the upper edge of the NAND Flash module to ensure proper wiring of the signal lines.

[0056] The horizontal boundary of the rigid board area should be close to the second rigid board area (memory module area) to ensure the tightest connection between the main control chip and the memory module, while avoiding unnecessary signal path extension.

[0057] Within the defined area of ​​the rigid board, the main control chip is precisely deployed. This step ensures that the main control chip is in the optimal position, optimizing signal transmission with the memory and NAND flash modules, while also considering power management efficiency and the overall heat dissipation design of the board.

[0058] The embodiments provided in this application refine the layout within the first rigid board area, precisely locating the main control chip by defining rigid board sub-regions. The design principle of the rigid board sub-regions is to maintain a second vertical distance from the NAND Flash module in the vertical direction, ensuring the shortest signal trace paths and maximizing signal integrity and data transmission speed. Simultaneously, in the horizontal direction, the rigid board area is closely adjacent to the memory module area, reducing signal trace length and ensuring the reliability of high-speed data transmission.

[0059] As an optional approach, a second parsing operation is performed on the software configuration file to obtain the first vertical distance between the main control chip and the interface connector, the horizontal distance between the main control chip and the right edge of the hard board, and the second vertical distance between the main control chip and the flash memory module to be deployed, including:

[0060] Obtain the number of signals connected between the main control chip and the interface connector, and obtain the trace width corresponding to each signal;

[0061] The first vertical distance is determined based on the number of connections and the width of the wiring.

[0062] Optionally, in this embodiment, firstly, the number of signal connections between the main control chip and the interface connector is obtained from the software configuration file, which will affect the total width of the signal lines. Then, the trace width corresponding to each signal is further obtained, which is the core parameter for calculating the first vertical distance.

[0063] Based on the number of signal connections and the trace width of each signal, the total width of the signal lines required between the main control chip and the interface connector is calculated. Taking into account the minimum safe spacing between signal lines and the size of the main control chip, the total width of the signal lines and the safe spacing are added to the calculation, ultimately yielding the first vertical distance. This distance will ensure that the signal lines can be correctly routed while avoiding signal interference and power loss.

[0064] Through the embodiments provided in this application, by accurately acquiring the signal connection information between the main control chip and the interface connector, the width requirements of each signal trace can be calculated, thereby determining the first vertical distance to ensure the shortest signal path and maximize signal integrity and power efficiency. This process fully considers the minimum safe distance between signals, avoids signal interference caused by improper layout, and optimizes power management to reduce power consumption.

[0065] As an optional approach, a second parsing operation is performed on the software configuration file to obtain the first vertical distance between the main control chip and the interface connector, the horizontal distance between the main control chip and the right edge of the hard board, and the second vertical distance between the main control chip and the flash memory module to be deployed, including:

[0066] Obtain the first configuration distance between the main control chip and the memory module, the configuration length of the memory module, and the second configuration distance between the memory module and the right side edge of the board;

[0067] The sum of the first configuration distance, the configuration length, and the second configuration distance is determined as the horizontal distance.

[0068] Optionally, in this embodiment, the first configuration distance between the main control chip and the memory module is obtained from the software configuration file; that is, the width and number of signal paths determine the necessary interval between them. The configuration length of the memory module is obtained, which is the lateral dimension of the memory module, used to calculate its occupied space on the rigid board. The second configuration distance between the memory module and the right edge of the rigid board is calculated to ensure the safety of the memory module layout and the feasibility of signal line routing.

[0069] Optionally, in this embodiment, the first configuration distance, the configuration length of the memory module, and the second configuration distance are added together to obtain the horizontal distance. This horizontal distance calculation ensures a reasonable layout between the main control chip, the memory module, and the right side of the board, avoids unnecessary signal interference, and guarantees the shortest path for signal lines, thereby improving signal integrity and power efficiency.

[0070] The second parsing operation on the software configuration file provided in this application is not limited to obtaining the width and number of signal lines, but also involves the first configuration distance between the main control chip and the memory module, the configuration length of the memory module, and the second configuration distance between the memory module and the right side edge of the board. The comprehensive consideration of these configuration parameters allows for a more accurate calculation of the horizontal distance between the main control chip and the right side edge of the hard board. By adding these three configuration parameters, the resulting horizontal distance ensures sufficient layout space between the main control chip and the right side edge of the board, while optimizing the signal transmission path between the memory module and the main control chip, thus avoiding signal integrity issues caused by excessively long signal lines.

[0071] As an optional approach, a second parsing operation is performed on the software configuration file to obtain the first vertical distance between the main control chip and the interface connector, the horizontal distance between the main control chip and the right edge of the hard board, and the second vertical distance between the main control chip and the flash memory module to be deployed, including:

[0072] Obtain the third configuration distance between the main control chip and the flash memory module;

[0073] The third configuration distance is determined as the second vertical distance.

[0074] Optionally, in this embodiment, a third configuration distance between the main control chip and the flash memory module is read from the software configuration file. This distance reflects the minimum vertical layout requirements between the two, aiming to ensure reasonable signal line lengths and unaffected signal integrity. The obtained third configuration distance is directly determined as the second vertical distance, i.e., the vertical layout distance between the main control chip and the flash memory module. This distance determination follows layout optimization principles, ensuring that the flash memory module can be closely positioned near the main control chip, thereby reducing signal line lengths and improving signal quality and data transmission speed.

[0075] The second parsing operation of the software configuration file provided in this application involves not only the layout parameters between the main control chip and the interface connector, but also focuses on the distance optimization between the main control chip and the flash memory module. By accurately obtaining the third configuration distance from the configuration file, this step directly determines it as the second vertical distance, i.e., the vertical distance between the main control chip and the flash memory module. By reducing the signal transmission path between the main control chip and the flash memory module, the signal integrity and data transmission efficiency are significantly improved, and the possibility of data latency and read / write errors is reduced. At the same time, reasonable layout spacing helps to reduce the complexity of the circuit board and reduce unnecessary trace layers.

[0076] As an optional approach, the method further includes the following steps before deploying the memory module in the second hardboard area:

[0077] A third parsing operation is performed on the software configuration file to obtain the first number of configured memory chips, the first capacity of a single configured memory chip, and the first distribution width of the configured memory chips.

[0078] When the vertical distance between the first horizontal line and the second horizontal line is determined as the second distribution width of the memory particle, the distribution parameter is determined based on the second distribution width and the first distribution width, wherein the distribution parameter is greater than or equal to 2.

[0079] Based on the first quantity, the first capacity, and the distribution parameters, determine the second quantity of memory chips to be deployed in the second rigid board area and the second capacity of a single memory chip.

[0080] Deploying memory modules in the second rigid board area includes:

[0081] A second number of memory chips of the second capacity are deployed in the second hard board area.

[0082] Optionally, in this embodiment, the first quantity is the total number of configured memory chips, i.e., the number of chips in the storage module in the original design. The first capacity is the capacity of a single configured memory chip, used to calculate the total storage capacity of the storage module. The first distribution width is the total distribution width of the memory chips on the circuit board, affecting the compactness of the layout and the routing efficiency.

[0083] Optionally, in this embodiment, the second distribution width is determined by the vertical distance between the first and second horizontal lines, and is used to guide the vertical layout of the memory chips. The distribution parameters are parameters calculated based on the second and first distribution widths, used to determine the layout density of the memory chips on the circuit board, ensuring the rationality of the layout. The second quantity is the adjusted number of memory chips to be deployed in the second rigid board area, which may differ from the original first quantity to adapt to the optimization requirements of the circuit board layout. The second capacity is the adjusted capacity of a single memory chip, used to ensure that the SSD's storage capacity meets the requirements while optimizing the circuit board layout.

[0084] Optionally, in this embodiment, a first quantity, i.e., the total number of memory chips in the original design, is obtained from the software configuration file. A first capacity, i.e., the original capacity of a single memory chip, is obtained. A first distribution width, which is the total lateral distribution width of the memory chips on the circuit board, is calculated to evaluate layout compactness.

[0085] Based on the second distribution width (i.e., the vertical distance between the first and second horizontal lines) and the first distribution width, distribution parameters are calculated. These parameters are used to determine the layout density of memory chips, ensuring a reasonable layout and the shortest path for signal lines.

[0086] Based on the distribution parameters, the first quantity, and the first capacity, the second quantity (number of memory chips) and the second capacity (capacity of a single memory chip) are redefined to achieve optimal board utilization efficiency and signal integrity.

[0087] In the second rigid board area, which is the part of the circuit board used to install memory modules, memory chips are deployed according to the adjusted second quantity and second capacity to achieve an optimized layout.

[0088] Through the embodiments provided in this application, the rationality and efficiency of the original layout are evaluated by parsing the original configuration information, including the total number of memory chips, the capacity of each chip, and their lateral distribution width on the circuit board. Subsequently, distribution parameters are calculated based on the vertical distribution width (second distribution width) and lateral distribution width of the memory chips on the circuit board. This parameter reflects the layout density of the memory chips on the circuit board, ensuring that the layout of the memory chips is both compact and meets signal integrity requirements within a limited space. Based on this, the present invention recalculates and determines the second quantity and second capacity to be deployed according to the distribution parameters, the original number and capacity of the memory chips, to achieve a more rational layout. Finally, in the second rigid board area (i.e., the memory module deployment area), memory chips are deployed according to the optimized second quantity and second capacity, ensuring the high performance and stability of the SSD under high-density layout.

[0089] As an optional approach, determining the distribution parameters based on the second distribution width and the first distribution width includes:

[0090] Divide the second distribution width by the first distribution width to obtain the first value;

[0091] Obtain the target even number corresponding to the first value, where the target even number is the smallest even number greater than the first value;

[0092] The target even number is determined as the distribution parameter.

[0093] Optionally, in this embodiment, the second distribution width is determined by the vertical distance between the first and second horizontal lines in the circuit board design, representing the distribution width of the memory chips in the vertical direction, and is used to guide the vertical layout of the memory modules. The first distribution width is the total lateral distribution width of the memory chips on the circuit board, reflecting the horizontal distribution of the chips in the original layout.

[0094] Optionally, in this embodiment, the first value is the value obtained by dividing the second distribution width by the first distribution width, used to initially evaluate the vertical and horizontal distribution ratio of the memory chip layout. The target even number is the smallest even number greater than the first value; it serves as a distribution parameter used to adjust the layout density of the memory chips on the circuit board, ensuring the rationality of the layout and the shortest path for signal traces. The distribution parameter, i.e., the target even number, is used to guide the rearrangement of the memory chips, ensuring layout optimization and signal integrity.

[0095] Optionally, in this embodiment, the second distribution width (the vertical distribution width of the memory chips) is divided by the first distribution width (the horizontal distribution width of the memory chips) to obtain a first value representing the layout ratio.

[0096] Based on the calculated first value, find the first smallest even number greater than it. This step ensures the rationality of the distribution parameters, so that the layout of the memory chips can not only meet the vertical distribution requirements of the circuit board, but also facilitate wiring and signal integrity considerations in the circuit board design.

[0097] The target even number is formally determined as the distribution parameter. This parameter will guide the relocation of memory chips, including adjustments to the number and optimization of the capacity of individual memory chips, thereby achieving a more compact, efficient and signal-complete board layout.

[0098] The embodiments provided in this application firstly calculate the ratio between the second distribution width and the first distribution width to obtain a preliminary value reflecting the vertical density of the memory chip layout. This calculation provides a quantitative basis for subsequent adjustments to the memory chip layout. Subsequently, to ensure that the optimization of the memory chip layout considers both the vertical layout requirements of the circuit board and maintains the uniformity of the layout and the orderliness of the signal lines, this invention introduces the concept of a target even number. Specifically, the smallest even number greater than the first value is found as the distribution parameter. This parameter selection follows mathematical rationality and considers the requirements of symmetry and regularity in circuit design, ensuring that the memory module layout is not overly complex or irregular, thereby reducing the risk of signal interference. Finally, the determination of the distribution parameter provides guidance for the re-layout of the memory chips, including adjusting the number of chips and optimizing the capacity of individual chips, making the memory module layout on the circuit board more compact and the signal lines shorter, which helps improve the signal integrity and overall performance of the SSD.

[0099] As an optional approach, determining the second number of memory chips to be deployed in the second rigid board area and the second capacity of a single memory chip, based on the first quantity, first capacity, and distribution parameters, includes:

[0100] Divide the first quantity by the distribution parameter to obtain the second quantity;

[0101] The second capacity is obtained by multiplying the first capacity by the distribution parameter.

[0102] Optionally, in this embodiment, the first quantity is divided by the distribution parameter to obtain the adjusted second quantity. This adjustment aims to reduce the total number of memory chips by increasing the load on individual memory chips, thereby saving board space, simplifying wiring, and improving signal integrity.

[0103] The adjusted second capacity is obtained by multiplying the first capacity by the distribution parameter. By increasing the capacity of a single chip, the overall storage capacity of the memory module can be maintained or improved while reducing the total number of memory chips, achieving a more efficient layout.

[0104] The embodiments provided in this application utilize distribution parameters to optimize the layout density of memory chips on the circuit board while ensuring that the total storage capacity of the memory module remains unaffected. Specifically, firstly, an adjusted second quantity, representing the actual number of memory chips deployed on the circuit board, is calculated by dividing a first quantity (the total number of memory chips in the original design) by the distribution parameter (a target even number). This adjustment reduces the total number of memory chips, freeing up more circuit board space, creating conditions for proper signal routing, and improving signal integrity. Next, to maintain the overall storage capacity of the memory module, the first capacity (the initial capacity of a single memory chip) is multiplied by the distribution parameter to obtain the adjusted second capacity, representing the capacity of a single memory chip. This increased capacity means that each memory chip undertakes more data storage tasks, while the reduced total number simplifies the circuit board layout. The combination of these two factors achieves the goal of deploying a high-performance memory module in a smaller space.

[0105] As an optional solution, deploying flash memory modules in the third hardboard area includes:

[0106] 2N flash memory chips are deployed in the third hard board area. The 2N flash memory chips include N flash memory chips deployed in the front area of ​​the hard board corresponding to the third hard board area and N flash memory chips deployed in the back area of ​​the hard board corresponding to the third hard board area. The N flash memory chips deployed in the front area of ​​the hard board and the N flash memory chips deployed in the back area of ​​the hard board correspond one-to-one in terms of hard board position.

[0107] Optionally, in this embodiment, a total of 2N flash memory chips are deployed in the third rigid board area, i.e., the dedicated deployment area for flash memory modules on the SSD circuit board. This deployment number is the result of comprehensive consideration of the circuit board space, signal line layout requirements, and storage capacity requirements.

[0108] In this configuration, N flash memory chips are deployed on the front side of the rigid board, while another N flash memory chips are deployed on the back side. This symmetrical, face-to-face deployment not only makes full use of the double-sided space of the circuit board but also facilitates the routing and management of signal lines. In particular, by using SkipVIA technology, efficient signal transmission between the front and back chips can be achieved without interfering with other important traces.

[0109] Each NAND Flash chip deployed on the front side of the rigid board has a corresponding NAND Flash chip on the back side of the rigid board. They correspond one-to-one in their positions on the rigid board, ensuring signal accuracy and data consistency.

[0110] This application provides an embodiment for SSD circuit board design that proposes a strategy for symmetrically deploying flash memory modules in a third rigid board area. This aims to maximize circuit board space utilization while ensuring reasonable signal line layout and efficient data transmission. Specifically, the invention suggests deploying a total of 2N flash memory chips in the third rigid board area, with half (N) deployed on the front side of the rigid board and the other half (N) deployed on the back side. This double-sided deployment not only solves the problem of limited circuit board space but also optimizes the signal line routing path through a one-to-one correspondence between the front and back chips. In particular, by utilizing SkipVIA technology, it enables fast and stable signal transmission between chips without increasing excessive layout complexity. By ensuring a one-to-one correspondence of chips in the rigid board location, this embodiment further improves the signal integrity and data consistency of the SSD, which is crucial for maintaining the high-speed read / write capabilities and long-term reliability of the SSD.

[0111] As an alternative approach, after deploying 2N flash memory chips in the third hardboard area, the method also includes:

[0112] Get the trace widths corresponding to local pins of data types and all pins of command types in the front area of ​​the hard board;

[0113] Obtain the first spacing between two flash memory chips in the front area of ​​the hard board, and obtain the nearest second spacing between the flash memory chip and the vertical line in the front area of ​​the hard board, wherein the vertical line and the right edge of the board are horizontally different in the horizontal direction.

[0114] Given the sum of the first and second spacing values, the number of routing layers is determined by dividing the routing width by the sum of the spacing values.

[0115] The number of inner layers of the routing layer is deployed on the front area of ​​the rigid board, and the number of inner layers of the routing layer is deployed on the back area of ​​the rigid board.

[0116] Optionally, in this embodiment, 2N flash memory chips represent the total number of flash memory chips deployed in the third hard board area, with half deployed on the front side of the hard board and the other half on the back side.

[0117] Optionally, in this embodiment, the front area of ​​the rigid board is the top layer area of ​​the circuit board, which is used to place some flash memory chips and signal connection lines.

[0118] Optionally, in this embodiment, the local pins for data types are the pins on the flash memory chip used to transmit data signals. Not all of these pins participate in data transmission; rather, they are partially enabled according to specific data transmission requirements. The all pins for command types are all the pins on the flash memory chip used to receive and send command signals. To ensure signal integrity, these pins all need to be traced.

[0119] Optionally, in this embodiment, the first spacing is the distance between two adjacent flash memory chips in the front area of ​​the rigid board, which affects the difficulty and complexity of the routing. The second spacing is the closest distance between the flash memory chip and the vertical line, which is a certain horizontal distance away from the right edge of the board to ensure the openness of the routing channel. The number of routing layers is the number of inner layer routing layers calculated based on the routing width and available spacing, which directly affects the complexity and cost of the board.

[0120] Optionally, in this embodiment, the trace widths corresponding to local pins of data types and all pins of command types in the front area of ​​the rigid board are measured, which is the basic data for calculating the number of trace layers.

[0121] The first spacing between two flash memory chips in the front area of ​​the hard board is measured, as well as the second spacing between the flash memory chips and a specific vertical line. The vertical line is horizontally spaced from the right edge of the board to ensure clear trace paths.

[0122] Divide the trace width by the sum of the first and second spacing (the sum of the spacing values), and round the result up to obtain the number of trace layers. This calculation ensures that signal lines can be reasonably allocated and laid out within the available space, while meeting the requirements of signal integrity and maximizing space utilization.

[0123] Based on the calculated number of routing layers, a corresponding number of inner layers are deployed on both the front and back of the rigid board to carry data type and command type signal lines, ensuring efficient signal transmission and compact layout.

[0124] The embodiments provided in this application, by measuring the trace widths of local pins for data types and all pins for command types on the flash memory chips, establish the basic requirements for signal line routing. Next, the first spacing between two flash memory chips in the front area of ​​the rigid board, and the second spacing between the flash memory chip and the vertical line are measured. The latter maintains a safe horizontal distance from the right edge of the board, ensuring sufficient space for trace routing. The number of trace layers calculated based on the trace width and the sum of these two spacings determines the layout structure of the inner layers of the board, which is crucial for balancing signal integrity and board complexity. Finally, based on the calculated number of trace layers, a corresponding number of inner layers are deployed in the front and back areas of the rigid board. This not only achieves efficient signal line routing but also effectively utilizes the space of the double-sided board, reduces signal interference, and improves the signal integrity and overall performance of the SSD.

[0125] As an optional solution, the number of inner layers for routing on the front side of the rigid board includes:

[0126] On the front side of the hard board, the first type of inner layer is configured for local pins of data types, and the second type of inner layer is configured for all pins of command types;

[0127] In the case of insufficient inner space of the first type, the first pin of the data type that is less than the distance to the main control chip from the local pins of the data type is determined;

[0128] Configure the second type of inner layer for the first pin of the data type.

[0129] Optionally, in this embodiment, firstly, a "first-type inner layer" is configured for local pins of data types in the front area of ​​the rigid board. This inner layer is specifically used to carry data signals to ensure high-speed and low-distortion data transmission.

[0130] At the same time, all pins of the command type are configured with "second-type inner layers". These inner layers are responsible for the transmission of command signals. Considering the characteristics of command signals and wiring requirements, they may require different processing than the data signal inner layers.

[0131] When it is found that the inner space of the first type is insufficient to accommodate the local pins of all data types, the "first pin" is selected from these pins whose distance from the main control chip is less than a preset distance threshold.

[0132] For the first selected pin, its routing is upgraded to "Type II inner layer". The reason for this is that the signal quality of pins that are closer to the main control chip is more susceptible to interference, so higher quality inner layer routing is required to ensure signal integrity and stability.

[0133] The embodiments provided in this application first configure a "first-type inner layer" for local pins of data types. This inner layer design focuses on fast data signal transmission and signal integrity to meet the speed requirements of data processing. Simultaneously, a "second-type inner layer" is configured for all pins of command types. This inner layer takes into account the characteristics of command signals and routing requirements to ensure accurate command transmission. When there is insufficient space in the first-type inner layer, this invention proposes a fine-tuning strategy: identifying data type pins (first pins) whose distance from the main control chip is less than a preset distance threshold, and upgrading the routing of these pins to the second-type inner layer. This approach not only solves the routing difficulties caused by layout limitations but also ensures the transmission quality of close-range data signals, avoiding signal interference and distortion. Through this layered routing and fine-tuning method, this invention successfully finds a balance between the complexity of circuit board design and the high performance of signal lines, providing necessary technical support for the high-performance operation of SSDs.

[0134] As an optional solution, the number of inner layers for routing on the reverse side of the rigid board includes:

[0135] On the reverse side of the hard board, a third type of inner layer is configured for local pins of data types, and a fourth type of inner layer is configured for all pins of command types;

[0136] In the case of insufficient inner space of the third type, the second pin of the data type that is less than the distance to the main control chip from the local pin of the data type is determined;

[0137] Configure the second pin of the data type with the inner layer of the fourth type.

[0138] In this embodiment, the number of inner layers for routing can be deployed in the front area of ​​the rigid board as described above.

[0139] As an alternative, the above-mentioned SSD deployment method can be applied to SSD PCB design scenarios. In this scenario, most SSD products in storage projects are rigid-flex PCBs. Compared to purely rigid PCBs, rigid-flex PCBs have the following disadvantages: Power supply needs to repeatedly cross the flexible board, resulting in longer power supply and return paths, affecting power integrity. Flash signals require longer traces across the flexible board from the controller chip to the left-side board, leading to discontinuous signal reference planes and return paths, affecting signal integrity. The manufacturing process of rigid-flex PCBs is complex and time-consuming, and there is a risk of open circuits at the connection points, which are difficult to repair and render the entire board unusable. When assembling the board into the drive enclosure, the flexible board area needs to be bent, resulting in poor heat dissipation between the upper and lower boards, generally requiring the addition of heat sinks. The overall cost of the PCB is higher than that of a rigid PCB.

[0140] To overcome the aforementioned shortcomings, this embodiment proposes a pure rigid board design approach. Based on rigid board DXF, the entire rigid board is divided into several important functional modules. While meeting performance requirements, each functional module is miniaturized. Within the constraints of layout space, special PCB processes are employed, and layer designs for important traces are specified to further meet requirements such as the number of wiring layers and board thickness limitations. Simultaneously, the heat dissipation problem of the PCB is addressed by adjusting the location of the backup capacitor. A method for rapidly designing such a PCB is also provided, mainly consisting of three modules and steps: DXF modular division, component layout and layer stack-up design within each area, and trace design.

[0141] (I) DXF modular partitioning

[0142] A schematic diagram of the operation flow for DXF modular partitioning, as follows: Figure 3As shown, click on DXF modular division, then click on hard board DXF import, soft board brd import, main chip location confirmation, DDR and Flash area division, and the background will automatically load the program to divide the hard board DXF into several large area modules.

[0143] Optionally, in this embodiment, click "Import Rigid PCB DXF," where the DXF needs to include the PCB edges and connector locations. Click "Import Flexible PCB BRD." Click "Confirm Main Chip Location," and the backend will determine the main chip's location based on its size, the number of main signals, and pin distribution. Click "DDR and Flash Area Division," and the backend will divide a general area for DDR and Flash based on the main chip's location and the distribution of DDR and Flash signals.

[0144] Optionally, in this embodiment, the rigid board DXF is imported, and the DXF needs to contain the rigid board's outline and connector locations. The flexible board BRD is imported mainly to obtain information about the main chip and Nand Flash in the flexible board BRD. Main chip location confirmation: Access the flexible board's BRD file, obtain the number of signal connections between the main chip and U.2, and estimate the total required trace width for these signals based on the number of signals and the trace width of each signal, denoted as H1. Access the flexible board's BRD file from step 2, obtain the width required for the main chip to connect to the DDR on the right side, denoted as W1, the long side of the DDR chip, denoted as W2, and the safety distance from the DDR to the board edge is 2mm. Then, the distance from the main chip to the right side of the board edge can be obtained as H2 = W1 + W2 + 2. Figure 4 As shown, using the lower edge of the connector in the DXF as a reference, measure downwards H1 and draw a dashed line parallel to it, denoted as L1; using the right edge of the board in the DXF as a reference, measure the distance H2 into the board and draw a line parallel to the right edge of the board, denoted as L2. The coordinates of the intersection of the two lines L1 and L2 can be used as the position of a corner of the main chip.

[0145] It should be noted that the measurement unit for the width and distance of the above wiring is uniformly mm.

[0146] DDR and Flash area division: Access the BRD file of the flexible board to obtain the width required for the main chip to connect with the Nand Flash signal, denoted as H3.

[0147] A schematic diagram of a PCB structure for an SSD, as shown below. Figure 4 As shown, measure downwards from the bottom edge of the main chip to H3, and draw a straight line parallel to it, denoted as L3. The area enclosed by L1, L2, L3, and the right side of the board is the DDR placement area, denoted as S1. The area enclosed by L2, L3, the left side of the board, and the bottom side of the board is the Nand Flash placement area, denoted as S2.

[0148] (ii) Layout of devices in each area

[0149] A schematic diagram of the operation flow for device layout in various regions, such as Figure 5 As shown, click on the device layout in each area; then click on DDR selection and layout, NAND Flash layout, backup capacitor layout, and power module layout in sequence. The background program will then load to automate the device layout in each area.

[0150] DDR Selection and Layout: Obtain the capacity of a single DDR chip in the flexible circuit board, denoted as T1, and obtain the quantity of DDR chips in the flexible circuit board, denoted as M1. For example... Figure 4 As shown, the distance between line segments L1 and L3 in the diagram is measured and denoted as H4; the total width of the DDR chip layout in the flexible board is obtained and denoted as H5 (the total width of the DDR chip layout in the original scheme). Figure 4 (not shown in the image)

[0151] Divide H5 by H4 and take the even number that is closest to and larger than this number. For example, if the result is 1.3, then take the value 2; if the result is 2.3, then take the value 4. Record this result as M.

[0152] The value obtained by T1*M is the capacity value of a single DDR chip on the new board, denoted as T2 (common DDR chip basic capacity specifications include 2Gb, 4Gb, 8Gb and 16Gb); the result of M1 / M is denoted as M2.

[0153] In area S1, with the top left corner as the starting position of the layout, place M2 DDR chips with a capacity of T2.

[0154] NAND Flash Layout: The front and back sides of the device are completely stacked to reduce layout space. A schematic diagram of an SSD PCB structure is shown below. Figure 6 As shown, Nand Flash1 and Nand Flash2 are placed on the top and bottom sides, respectively; Nand Flash3 and Nand Flash4 are placed on the top and bottom sides, respectively...

[0155] All NAND flash memory should be placed as close as possible to the bottom left edge of the board to accommodate the power module layout. Since the front and back components need to be overlapped because pins at the same location on the front and back sides carry different signals, using through-holes would require extending the pin area, necessitating significant layout and routing space, and increasing the number of routing layers and board thickness. Therefore, a Skip VIA design is proposed. The advantages of using Skip VIA are as follows: compared to traditional through-hole technology, it only adds one laser blind via processing step, does not increase the number of lamination steps, and only increases the cost by about 10%. Skip VIA, like micro-blind vias, can achieve the layer division described above, thus achieving complete overlap of the front and back components. Figure 7 The diagram shows the Skip via and second-order micro-blind via structures. If the micro-blind via process is used, connecting the first to the third layer requires two laser blind vias and an additional lamination process. The micro-blind via process increases the cost by 20% compared to Skip via and also increases the board manufacturing cycle.

[0156] Backup capacitor layout: such as Figure 6 As shown, the backup power capacitor is placed on the side of the board. Since the SSD draws air in from the vertical direction shown in the diagram, placing the backup power capacitor on the side will not obstruct the airflow and will help with the overall heat dissipation.

[0157] Power module layout: A separate power supply solution is used, which breaks down large power modules into smaller modules based on available space. This offers greater layout flexibility. Each power supply group is rationally positioned according to the current requirements of each functional module, facilitating troubleshooting and analysis, reducing unnecessary testing, shortening the overall product development cycle, and lowering PCB manufacturing costs. Simultaneously, the power supply layout principle is to place them as close as possible to power-consuming components and avoid important routing paths such as DDR and NAND Flash. Figure 6 As shown, the CORE power supply P0V83 of the main control chip is placed above the main control chip, making the distance between the CORE power supply and the main control chip relatively short. P1V2 is placed in the lower right corner of the main control chip, and P2V5 is placed below P1V2, to the right of the NAND Flash chip. This is because P1V2 needs to power the main control chip, DDR, and NAND Flash, with DDR requiring the largest current from P1V2. P2V5 needs to power both DDR and NAND Flash. This placement of P1V2 and P2V5 ensures the most reasonable power path and current flow for each functional module. The 12V_VPP power supply is only used by the NAND Flash, so it is placed in the lower left corner of the main control chip, above the NAND Flash chip.

[0158] (III) Layering and wiring design

[0159] A schematic diagram of the operation flow of a layer stack and routing design, as shown below. Figure 8 As shown, click on Layer and Routing Design; then click on Routing Layer Estimation and Routing Layer and Path Design in sequence. The background program will then load to automate the estimation of the number of routing layers and the routing path.

[0160] Trace Layer Estimation: Since most of the traces on this PCB are from the main control chip to the Nand Flash, we only need to estimate the number of trace layers required for this part to obtain the total number of trace layers required for the entire PCB. The steps are as follows:

[0161] Traverse the pin distribution of the top-layer Nand Flash, dividing the chip into two main categories based on signal type: DQ and CMD. For the top layer, excluding the two DQ traces closest to the main controller chip, calculate the required width (W) for the remaining DQ and CMD traces. Measure the effective routing space on the PCB board, such as... Figure 6 The sum of H5 and H6 is denoted as W1. H5 is the spacing between the two Nand Flash chips; H6 is the spacing between the rightmost Nand Flash chip and line segment L5. W / W1 represents the number of layers required for the top layer Nand Flash chip, denoted as N (rounded to the nearest integer). Similarly, the bottom layer also requires N layers, and the entire PCB requires 2N inner layers. By connecting to the layer stack-up library, the corresponding layer stack-up can be obtained based on the routing layers and board thickness.

[0162] It should be noted that the above layer stacking is due to the limitation of board thickness, which makes it impossible to add another GND routing layer between L5 and L6, or between L7 and L8.

[0163] Routing Layers and Path Design: Similarly, constraints are applied only to the routing layers of the NAND Flash. For the NAND flash chips located in the top layer, use L3 layer routing as much as possible; for the devices located in the bottom layer, use L10 layer routing as much as possible. Use skip vias from the top layer to L3, connecting only the top and L3 layers. This via has no impact on the routing from Layer 4 to the bottom layer or on the devices. Likewise, skip vias from the bottom layer to L10 also only connect the bottom and L10 layers. This via has no impact on the routing from Layer 9 to the top layer or on the devices.

[0164] Because DQ signals outnumber CMD signals, and DQ signals have higher signal integrity requirements, the DQ signal layers are preferentially defined as L3 and L10, while the CMD signal layers are defined as L5 and L8. If the space in layers L3 and L10 is insufficient to accommodate all DQ signals, the shorter DQ traces closer to the main control chip are placed on layers L5 and L8. Here, both near and far ends of L3 and L10 reference GND, while the near ends of L5 and L8 reference GND, and the far ends reference power. This layer division and stack-up design ensures that most DQ lines are completely referenced to the ground plane, while a portion of the larger DQ and CMD signals are referenced to the ground plane near their ends, achieving good signal integrity. Figure 9 As shown, taking the top-layer Nand Flash as an example, the DQ signal is preferentially routed on the L3 layer, and the CMD signal is routed on the L5 layer. If space is insufficient, the DQ signal, which is closer to the main chip and has a shorter trace, will be routed on the L5 layer.

[0165] The embodiments provided in this application propose a pure rigid PCB design concept that improves heat dissipation performance while meeting hard drive capacity requirements, and also reduces PCB manufacturing costs and production cycle. A method for rapidly designing such PCBs is also given, improving work efficiency.

[0166] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0167] This embodiment also provides a data storage device for edge nodes, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0168] Figure 10 This is a structural block diagram of a solid-state drive deployment apparatus according to an embodiment of this application, such as... Figure 10 As shown, the device includes:

[0169] The parsing unit 1002 is used to perform a first parsing operation on the hardware configuration file to obtain the storage area of ​​the interface connector on the hard board, and to perform a second parsing operation on the software configuration file to obtain the first vertical distance between the main control chip and the interface connector, the horizontal distance between the main control chip and the right edge of the hard board, and the second vertical distance between the main control chip and the flash memory module to be deployed.

[0170] The determining unit 1004 is used to determine, based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance, the first hardboard area corresponding to the main control chip, the second hardboard area corresponding to the memory module to be deployed, and the third hardboard area corresponding to the flash memory module on the hardboard.

[0171] Deployment unit 1006 is used to deploy the main control chip in the first hard board area, the memory module in the second hard board area, and the flash memory module in the third hard board area.

[0172] As an optional solution, determining unit 1004 includes:

[0173] The first determining module is used to determine a first horizontal line, a second horizontal line, and a vertical line on the hard board. The first horizontal line is a first vertical distance away from the storage area in the vertical direction, and the second horizontal line is a third vertical distance away from the storage area in the vertical direction. The third vertical distance is the sum of the first vertical distance, the second vertical distance, and the vertical length of the main control chip. The vertical line is a horizontal distance away from the right edge of the board in the horizontal direction.

[0174] The second determining module is used to determine the closed area between the first horizontal line, the second horizontal line, the vertical line and the left edge of the rigid plate as the first rigid plate area;

[0175] The third determining module is used to determine the closed area between the first horizontal line, the second horizontal line, the vertical line and the right side edge of the plate as the second rigid plate area;

[0176] The fourth determining module is used to define the closed area between the second horizontal line, the vertical line, the left side edge of the plate, and the lower side edge of the rigid plate as the third rigid plate area.

[0177] As an optional solution, deployment unit 1006 includes:

[0178] The fifth determining module is used to determine a rigid board sub-region from the first rigid board region, wherein the rigid board region is a second vertical distance away from the third rigid board region in the vertical direction and is adjacent to the second rigid board region in the horizontal direction.

[0179] The first deployment module is used to deploy the main control chip in the hard board area.

[0180] As an optional solution, the parsing unit 1002 includes:

[0181] The first acquisition module is used to acquire the number of signals connected between the main control chip and the interface connector, and to acquire the trace width corresponding to each signal.

[0182] The sixth determining module is used to determine the first vertical distance based on the number of connections and the width of the trace.

[0183] As an optional solution, the parsing unit 1002 includes:

[0184] The second acquisition module is used to acquire the first configuration distance between the main control chip and the memory module, the configuration length of the memory module, and the second configuration distance between the memory module and the right side of the board.

[0185] The seventh determining module is used to determine the sum of the first configuration distance, the configuration length, and the second configuration distance as the horizontal distance.

[0186] As an optional solution, the parsing unit 1002 includes:

[0187] The third acquisition module is used to acquire the third configuration distance between the main control chip and the flash memory module;

[0188] The eighth determining module is used to determine the third configuration distance as the second vertical distance.

[0189] As an optional solution, the device also includes:

[0190] The parsing module is used to perform a third parsing operation on the software configuration file before deploying the memory module in the second hardboard area, to obtain the first number of configured memory chips, the first capacity of a single configured memory chip, and the first distribution width of the configured memory chips.

[0191] The ninth determining module is used to determine the distribution parameters based on the second distribution width and the first distribution width when the vertical distance between the first horizontal line and the second horizontal line is determined as the second distribution width of the memory chip, wherein the distribution parameters are greater than or equal to 2;

[0192] The tenth determining module is used to determine the second number of memory chips to be deployed in the second rigid board area and the second capacity of a single memory chip based on the first quantity, the first capacity and the distribution parameters.

[0193] The deployment unit includes:

[0194] The second deployment module is used to deploy a second number of memory chips of a second capacity in the second hardboard area.

[0195] As an optional solution, the ninth determining module includes:

[0196] The first calculation submodule is used to divide the second distribution width by the first distribution width to obtain the first value;

[0197] The acquisition submodule is used to acquire the target even number corresponding to the first value, where the target even number is the smallest even number greater than the first value;

[0198] The first determination submodule is used to determine the target even number as the distribution parameter.

[0199] As an optional solution, the tenth determining module includes:

[0200] The second calculation submodule is used to divide the first quantity by the distribution parameter to obtain the second quantity;

[0201] The third calculation submodule is used to multiply the first capacity by the distribution parameter to obtain the second capacity.

[0202] As an optional solution, deployment unit 1006 includes:

[0203] The third deployment module is used to deploy 2N flash memory chips in the third hard board area. The 2N flash memory chips include N flash memory chips deployed on the front side of the hard board corresponding to the third hard board area and N flash memory chips deployed on the back side of the hard board corresponding to the third hard board area. The N flash memory chips deployed on the front side of the hard board and the N flash memory chips deployed on the back side of the hard board correspond one-to-one in terms of hard board position.

[0204] As an optional solution, the device also includes:

[0205] The fourth acquisition module is used to acquire the trace widths corresponding to local pins of data types and all pins of command types in the front area of ​​the hard board after deploying 2N flash memory chips in the third hard board area.

[0206] The fifth acquisition module is used to acquire the first spacing between two flash memory chips in the front area of ​​the hard board after deploying 2N flash memory chips in the third hard board area, and to acquire the closest second spacing between the flash memory chip and the vertical line in the front area of ​​the hard board, wherein the vertical line and the right side of the board edge are horizontally different.

[0207] The eleventh determining module is used to determine the number of trace layers by dividing the trace width by the sum of the spacing values ​​after deploying 2N flash memory chips in the third hard board area, given the sum of the spacing values ​​of the first and second spacings.

[0208] The fourth deployment module is used to deploy 2N flash memory chips in the third hard board area, and then deploy the number of inner layers of the routing layer in the front area of ​​the hard board and the number of inner layers of the routing layer in the back area of ​​the hard board.

[0209] As an optional solution, the fourth deployment module includes:

[0210] The first configuration submodule is used to configure the inner layer of the first type for local pins of data types and the inner layer of the second type for all pins of the command type on the front side of the hard board.

[0211] The second determining submodule is used to determine, in the case of insufficient inner space of the first type, the first pin of the data type whose distance from the main control chip is less than a preset distance threshold from the local pins of the data type.

[0212] The second configuration submodule is used to configure the inner layer of the second type for the first pin of the data type.

[0213] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0214] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0215] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0216] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0217] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0218] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0219] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0220] Embodiments of this application also provide a computer program product, including a non-volatile computer-readable storage medium storing the computer program product, wherein the computer program, when executed by a processor, implements the steps of the methods in various embodiments of this application.

[0221] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0222] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular hardware and software combination.

[0223] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for deploying a solid-state drive, characterized in that, include: A first parsing operation is performed on the hardware configuration file to obtain the storage area of ​​the interface connector on the hard board, and a second parsing operation is performed on the software configuration file to obtain the first vertical distance between the main control chip and the interface connector, the horizontal distance between the main control chip and the right edge of the hard board, and the second vertical distance between the main control chip and the flash memory module to be deployed. Based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance, the first hardboard area corresponding to the main control chip, the second hardboard area corresponding to the memory module to be deployed, and the third hardboard area corresponding to the flash memory module are determined on the hardboard. The main control chip is deployed in the first hard board area, the memory module is deployed in the second hard board area, and the flash memory module is deployed in the third hard board area.

2. The method according to claim 1, characterized in that, The step of determining, based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance, the first hardboard area corresponding to the main control chip, the second hardboard area corresponding to the memory module to be deployed, and the third hardboard area corresponding to the flash memory module on the hardboard includes: A first horizontal line, a second horizontal line, and a vertical line are defined on the rigid board. The first horizontal line is a first vertical distance away from the storage area in the vertical direction. The second horizontal line is a third vertical distance away from the storage area in the vertical direction. The third vertical distance is the sum of the first vertical distance, the second vertical distance, and the vertical length of the main control chip. The vertical line is a horizontal distance away from the right edge of the board in the horizontal direction. The enclosed area between the first horizontal line, the second horizontal line, the vertical line, and the left edge of the rigid plate is defined as the first rigid plate area; The enclosed area between the first horizontal line, the second horizontal line, the vertical line, and the right side edge of the board is defined as the second rigid board area; The closed area between the second horizontal line, the vertical line, the left side edge of the plate, and the lower side edge of the rigid plate is defined as the third rigid plate area.

3. The method according to claim 2, characterized in that, Deploying the main control chip in the first rigid board area includes: A rigid board region is determined from the first rigid board region, wherein the rigid board region is vertically separated from the third rigid board region by the second vertical distance and is horizontally adjacent to the second rigid board region; The main control chip is deployed in the area of ​​the hard board.

4. The method according to claim 1, characterized in that, The second parsing operation on the software configuration file, to obtain the first vertical distance between the main control chip and the interface connector, the horizontal distance between the main control chip and the right edge of the hard board, and the second vertical distance between the main control chip and the flash memory module to be deployed, includes: The number of signals connected between the main control chip and the interface connector is obtained, as well as the trace width corresponding to each signal; The first vertical distance is determined based on the number of connections and the width of the wiring.

5. The method according to claim 1, characterized in that, The second parsing operation on the software configuration file, to obtain the first vertical distance between the main control chip and the interface connector, the horizontal distance between the main control chip and the right edge of the hard board, and the second vertical distance between the main control chip and the flash memory module to be deployed, includes: Obtain the first configuration distance between the main control chip and the memory module, the configuration length of the memory module, and the second configuration distance between the memory module and the right side panel edge; The sum of the first configuration distance, the configuration length, and the second configuration distance is determined as the horizontal distance.

6. The method according to claim 1, characterized in that, The second parsing operation on the software configuration file, to obtain the first vertical distance between the main control chip and the interface connector, the horizontal distance between the main control chip and the right edge of the hard board, and the second vertical distance between the main control chip and the flash memory module to be deployed, includes: Obtain the third configuration distance between the main control chip and the flash memory module; The third configuration distance is determined as the second vertical distance.

7. The method according to claim 2, characterized in that, Before deploying the memory module in the second hardboard area, the method further includes: A third parsing operation is performed on the software configuration file to obtain the first number of configured memory particles, the first capacity of a single configured memory particle, and the first distribution width of the configured memory particles. When the vertical distance between the first horizontal line and the second horizontal line is determined as the second distribution width of the memory chip, a distribution parameter is determined based on the second distribution width and the first distribution width, wherein the distribution parameter is greater than or equal to 2; Based on the first quantity, the first capacity, and the distribution parameters, a second quantity of memory chips to be deployed in the second rigid board area and a second capacity of a single memory chip are determined. Deploying the memory module in the second rigid board area includes: The second number of memory chips of the second capacity are deployed in the second hard board area.

8. The method according to claim 7, characterized in that, The step of determining the distribution parameters based on the second distribution width and the first distribution width includes: Divide the second distribution width by the first distribution width to obtain the first value; Obtain the target even number corresponding to the first value, wherein the target even number is the smallest even number greater than the first value; The target even number is determined as the distribution parameter.

9. The method according to claim 7, characterized in that, The step of determining the second number of memory chips to be deployed in the second rigid board area and the second capacity of a single memory chip based on the first quantity, the first capacity, and the distribution parameters includes: The second quantity is obtained by dividing the first quantity by the distribution parameter; The second capacity is obtained by multiplying the first capacity by the distribution parameter.

10. The method according to claim 1, characterized in that, Deploying the flash memory module in the third rigid board area includes: 2N flash memory chips are deployed in the third rigid board area, wherein the 2N flash memory chips include N flash memory chips deployed in the front area of ​​the rigid board corresponding to the third rigid board area and N flash memory chips deployed in the back area of ​​the rigid board corresponding to the third rigid board area. The N flash memory chips deployed in the front area of ​​the rigid board and the N flash memory chips deployed in the back area of ​​the rigid board correspond one-to-one in terms of the rigid board position.

11. The method according to claim 10, characterized in that, After deploying 2N flash memory chips in the third hardboard region, the method further includes: Obtain the trace widths corresponding to local pins of data types and all pins of command types in the front area of ​​the hard board; Obtain the first spacing between two flash memory chips in the front area of ​​the hard board, and obtain the closest second spacing between the flash memory chip and the vertical line in the front area of ​​the hard board, wherein the vertical line and the right side edge of the board differ by the horizontal distance in the horizontal direction; Given the sum of the first spacing and the second spacing, the number of routing layers is determined by dividing the routing width by the sum of the spacings. The number of inner layers of the routing layer are deployed in the front area of ​​the rigid board, and the number of inner layers of the routing layer are deployed in the back area of ​​the rigid board.

12. The method according to claim 11, characterized in that, The number of inner layers for deploying the trace layers on the front side of the rigid board includes: In the front area of ​​the rigid board, a first type of inner layer is configured for local pins of the data type, and a second type of inner layer is configured for all pins of the command type; In the case of insufficient inner space of the first type, a first pin of the data type is determined from the local pins of the data type whose distance from the main control chip is less than a preset distance threshold. Configure the inner layer of the second type for the first pin of the data type.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method according to any one of claims 1 to 12.

14. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 12.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 12.

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