Deployment method and storage medium for solid state drive, electronic device, and program product

Abstract

This application provides a method for deploying a solid-state drive (SSD), a storage medium, an electronic device, and a software product, relating to the computer field. The method includes: performing a first parsing operation on a hardware configuration file to obtain a storage area of ​​an interface connector on a hardboard; and performing a second parsing operation on a software configuration file to obtain a first vertical distance between the main control chip and the interface connector, a horizontal distance between the main control chip and the right edge of the hardboard, and a second vertical distance between the main control chip and a flash memory module to be deployed; based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance, determining a first hardboard area corresponding to the main control chip, a second hardboard area corresponding to the memory module to be deployed, and a third hardboard area corresponding to the flash memory module on the hardboard; and deploying the main control chip in the first hardboard area, the memory module in the second hardboard area, and the flash memory module in the third hardboard area.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the computer field, in particular, to a solid state disk deployment method and storage medium, electronic device and program product. BACKGROUND

[0002] In the design of a solid state disk (SSD), a traditional layout method often adopts the form of a soft and hard combination board, so that the power supply needs to repeatedly cross the soft board, the power supply and backflow path is long, and the best practices of signal path and power distribution are not fully considered, leading to signal quality degradation and power loss increase, which may cause poor heat dissipation and affect the overall performance and service life of the SSD. Therefore, there is a technical problem of high use power consumption of the solid state disk in the related art. SUMMARY

[0003] Embodiments of the present application provide a solid state disk deployment method and storage medium, electronic device and program product to at least solve the technical problem of high use power consumption of the solid state disk in the related art.

[0004] According to an embodiment of the present application, a solid state disk deployment method is provided, comprising: performing a first parsing operation on a hardware configuration file to obtain a storage area of an interface connector on a hard board, and performing a second parsing operation on a software configuration file to obtain a first vertical distance between a master control chip and the interface connector, a horizontal distance between the master control chip and a right side board edge of the hard board, and a second vertical distance between the master control chip and a flash memory module to be deployed; determining a first hard board area corresponding to the master control chip, a second hard board area corresponding to the memory module to be deployed, and a third hard board area corresponding to the flash memory module on the hard board based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance; deploying the master control chip in the first hard board area, deploying the memory module in the second hard board area, and deploying the flash memory module in the third hard board area.

[0005] According to an embodiment of the present application, a solid state disk deployment apparatus is provided, comprising: a parsing unit configured to perform a first parsing operation on a hardware configuration file to obtain a storage area of an interface connector on a hard board, and perform a second parsing operation on a software configuration file to obtain a first vertical distance between a master control chip and the interface connector, a horizontal distance between the master control chip and a right side board edge of the hard board, and a second vertical distance between the master control chip and a flash memory module to be deployed; a determining unit configured to determine a first hard board area corresponding to the master control chip, a second hard board area corresponding to the memory module to be deployed, and a third hard board area corresponding to the flash memory module on the hard board based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance; and a deployment unit configured to deploy the master control chip in the first hard board area, deploy the memory module in the second hard board area, and deploy the flash memory module in the third hard board area.

[0006] According to still another embodiment of the present application, a computer readable storage medium is also provided, in which a computer program is stored, wherein the computer program is configured to perform the steps of any of the method embodiments described above when executed.

[0007] According to still another embodiment of the present application, an electronic device is also provided, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps of any of the method embodiments described above.

[0008] Through the embodiments provided by the present application, the hardware configuration file is parsed through a first parsing operation to obtain the accurate position of the interface connector, and the software configuration file is parsed through a second parsing operation to obtain the first vertical distance between the host chip and the interface connector, the horizontal distance between the host chip and the right side plate edge of the hard plate, and the second vertical distance between the host chip and the to-be-deployed flash memory module (NAND Flash). Based on these accurate parameters, the optimal deployment positions of the host chip, the memory module and the flash memory module on the hard plate can be determined more scientifically. In turn, the signal path between the host chip, the memory module and the flash memory module is ensured to be the shortest, the unnecessary signal loop length is reduced, and the signal integrity is significantly improved. In addition, by optimizing the distance between the host chip and the power module, the power distribution and the backflow path are improved, thereby improving the power efficiency and reducing the power consumption, thereby achieving the technical effect of reducing the use power consumption of the solid state disk and solving the technical problem of high use power consumption of the solid state disk in the related art. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a hardware structure block diagram of a deployment method of a solid state disk according to an embodiment of the present application.

[0010] Figure 2 is a flowchart of a deployment method of a solid state disk according to an embodiment of the present application.

[0011] Figure 3 is an operation flowchart of a DXF modularization according to an embodiment of the present application.

[0012] Figure 4 is a PCB structure diagram of a SSD according to an embodiment of the present application.

[0013] Figure 5 is an operation flowchart of device layout in each region according to an embodiment of the present application.

[0014] Figure 6 is a PCB structure diagram of a SSD according to an embodiment of the present application.

[0015] Figure 7 is a Skip via and second-order micro-blind hole structure diagram according to an embodiment of the application.

[0016] Figure 8 is an operation flow diagram of a laminated and wiring design according to an embodiment of the application.

[0017] Figure 9 is a layer definition diagram of a signal according to an embodiment of the application.

[0018] Figure 10 is a structure block diagram of a data storage device of an edge node according to an embodiment of the application. DETAILED DESCRIPTION

[0019] Hereinafter, the embodiments of the present application will be described in detail with reference to the accompanying drawings and in conjunction with embodiments.

[0020] It should be noted that the terms "first", "second", and the like in the description and claims of the present application and the above drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the application described herein can be implemented in other than the order illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to include only those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0021] The method embodiments provided in the embodiments of the present application can be executed in a computer terminal or similar computing device. Taking a computer terminal as an example, Figure 1 is a hardware structure block diagram of a computer terminal of a deployment method of a solid state disk according to an embodiment of the present application. As shown in Figure 1 , the computer terminal can include one or more (only one is shown in Figure 1 ) processor 102 (the processor 102 can include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above computer terminal can further include a transmission device 106 for communication function and an input and output device 108. Those skilled in the art can understand that Figure 1 the structure shown is only schematic, which does not limit the structure of the above computer terminal. For example, the computer terminal can include more or fewer components than those shown in Figure 1 , or have a different configuration from that shown in Figure 1 .

[0022] The memory 104 can be used to store computer programs, such as software programs of application software and modules, such as a computer program corresponding to the deployment method of the solid state disk in the embodiments of the present application. The processor 102 performs various functional applications and data processing by running the computer programs stored in the memory 104, that is, implements the above-mentioned method. The memory 104 can include a high-speed random access memory, and can also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid state memories. In some examples, the memory 104 can further include a memory remotely arranged with respect to the processor 102, which can be connected to the computer terminal through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0023] The transmission device 106 is used to receive or send data via a network. The specific examples of the above-mentioned network can include a wireless network provided by a communication service provider of the computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, NIC) which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (Radio Frequency, RF) module which is used to communicate with the Internet in a wireless manner.

[0024] As an optional solution, the embodiments provide a deployment method of a solid state disk, as shown in Figure 2 The method comprises the following steps:

[0025] S202, performing a first parsing operation on a hardware configuration file to obtain a storage area of an interface connector on a hard board, and performing a second parsing operation on a software configuration file to obtain a first vertical distance between a main control chip and the interface connector, a horizontal distance between the main control chip and a right side board edge of the hard board, and a second vertical distance between the main control chip and a flash memory module to be deployed;

[0026] S204, determining a first hard board area corresponding to the main control chip, a second hard board area corresponding to the memory module to be deployed, and a third hard board area corresponding to the flash memory module on the hard board based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance;

[0027] S206, deploying the main control chip in the first hard board area, deploying the memory module in the second hard board area, and deploying the flash memory module in the third hard board area.

[0028] Optionally, in this embodiment, the hardware configuration file refers to a file containing information about the physical layout of the circuit board, the location of components, the type and location of connectors, etc., usually in DXF (Drawing Exchange Format), to guide the physical design of the circuit board.

[0029] Optionally, in this embodiment, the software configuration file refers to a file containing information about the logical configuration of the device, the type of signal, the width of the signal trace, the frequency of the signal, and the power consumption, etc., usually a soft board brd file, to determine the parameters of signal path and component layout.

[0030] Optionally, in this embodiment, the interface connector is a component used to connect the SSD and other devices (such as the motherboard), such as the U.2 connector, which is the physical interface for communication between the SSD and the host system.

[0031] Optionally, in this embodiment, the first vertical distance represents the vertical distance between the host chip and the interface connector, used to determine the vertical boundary of the host chip and the starting point of the DQ signal trace. The horizontal distance refers to the horizontal distance between the host chip and the right edge of the hard board, used to determine the lateral boundary of the host chip and the range of the DDR signal trace. The second vertical distance represents the vertical distance between the host chip and the flash module, used to define the placement area of the NANDFlash. The host chip is the core control unit of the SSD, responsible for managing and coordinating data read and write operations. The memory module refers to the DDR memory module, used to improve the read and write speed of the SSD. The flash module refers to the NANDFlash module, which is the main storage element of the solid state disk.

[0032] Optionally, in this embodiment, the first parsing operation is performed on the hardware configuration file, aiming to extract the physical layout information such as the board frame and connector location of the hard board from the DXF file, laying the foundation for subsequent layout planning.

[0033] Optionally, in this embodiment, key signal trace parameters such as signal width, frequency, and power requirements are parsed from the brd file of the soft board to determine the relative position and signal path length between the host chip and other key components.

[0034] Based on the obtained connector storage area, vertical and horizontal distance, the hard board is intelligently divided into three specific areas for deploying the host chip, memory module, and flash module, which ensures the rationality of the layout and minimizes the signal line length, thereby optimizing the signal quality and power efficiency.

[0035] Optionally, in this embodiment, the host chip is deployed in the first hard board area, the memory module (such as DDR) is deployed in the second hard board area, and the flash module (such as NANDFlash) is deployed in the third hard board area, achieving an efficient and compact layout.

[0036] It should be noted that the embodiment is aimed at overcoming the defects brought by the combination of soft and hard boards in the prior art, such as poor signal integrity, low power distribution efficiency, and prominent heat dissipation problems. By accurately analyzing the hardware and software configuration files, the ideal positions of the interface connector, the master control chip, the memory module, and the flash memory module can be determined, and the shortest path of the signal line and the best layout of the power module can be realized. This method not only effectively solves the problems of signal interference and low power efficiency, but also optimizes the heat dissipation design by placing the standby capacitor on the board side, further improving the performance and stability of the SSD. In addition, the pure hard board design strategy simplifies the manufacturing process, reduces the cost, shortens the production cycle, and brings significant technical progress to the SSD industry.

[0037] Through the embodiments provided in the present application, the first analysis operation is used to analyze the hardware configuration file to obtain the accurate position of the interface connector, and the second analysis operation is used to analyze the software configuration file to obtain the first vertical distance between the master control chip and the interface connector, the horizontal distance between the master control chip and the right side of the hard board, and the second vertical distance between the master control chip and the to-be-deployed flash memory module (NAND Flash). Based on these accurate parameters, the optimal deployment positions of the master control chip, the memory module, and the flash memory module on the hard board can be determined more scientifically. Furthermore, the shortest signal path between the master control chip, the memory module, and the flash memory module is ensured, the unnecessary signal loop length is reduced, and the signal integrity is significantly improved. In addition, by optimizing the distance between the master control chip and the power module, the power distribution and the backflow path are improved, thereby improving the power efficiency and reducing the power consumption, thereby achieving the technical effect of reducing the power consumption of the solid state disk.

[0038] As an optional solution, based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance, the first hard board area corresponding to the master control chip, the second hard board area corresponding to the to-be-deployed memory module, and the third hard board area corresponding to the flash memory module are determined on the hard board, which includes:

[0039] A first horizontal line, a second horizontal line, and a vertical line are determined on the hard board, wherein the first horizontal line is different from the storage area by the first vertical distance in the vertical direction, the second horizontal line is different from the storage area by the third vertical distance in the vertical direction, the third vertical distance is the sum of the first vertical distance, the second vertical distance, and the vertical length of the master control chip, and the vertical line is different from the right side of the board by the horizontal distance in the horizontal direction;

[0040] The closed area between the first horizontal line, the second horizontal line, the vertical line, and the left side of the hard board is determined as the first hard board area;

[0041] The closed area between the first horizontal line, the second horizontal line, the vertical line, and the right side of the hard board is determined as the second hard board area;

[0042] A closed area between the second horizontal line, the vertical line, the left side board edge and the lower side board edge of the hard board is determined as a third hard board area.

[0043] Optionally, in the embodiment, the first hard board area is an area on the hard board for disposing the master control chip, which is determined according to the position of the interface connector and the first vertical distance between the master control chip and the connector. The second hard board area is an area on the hard board for disposing the memory module (e.g. DDR), which is determined by the closed area surrounded by the position of the master control chip, the first horizontal line, the second horizontal line, the vertical line and the right side board edge. The third hard board area is an area on the hard board for disposing the flash memory module (NAND Flash), which is determined by the closed area surrounded by the master control chip, the second horizontal line, the vertical line, the left side board edge and the lower side board edge.

[0044] Optionally, in the embodiment, the first vertical distance is the vertical distance between the interface connector and the master control chip, which is used to determine the upper edge of the master control chip. The second vertical distance is the vertical distance between the master control chip and the NAND Flash module, which affects the lower boundary of the NAND Flash module. The third vertical distance is the sum of the first vertical distance and the second vertical distance and the height of the master control chip, which is used to determine the vertical span from the interface to the NAND Flash module.

[0045] Optionally, in the embodiment, the first horizontal line is a virtual line maintaining the first vertical distance with the lower edge of the interface connector, which is used to define the upper boundary of the master control chip. The second horizontal line is a virtual line maintaining the third vertical distance with the upper edge of the NAND Flash module, which is used to define the lower boundary of the NAND Flash module and the upper boundary of the memory module. The vertical line is a virtual line on the right side edge of the hard board, which is used to define the right boundary of the memory module by measuring the horizontal distance between the master control chip and the right side edge horizontally inward.

[0046] Optionally, in the embodiment, the first horizontal line, the second horizontal line and the vertical line are drawn on the hard board, wherein the first horizontal line is vertically different from the interface connector by the first vertical distance, the second horizontal line is vertically different from the connector by the third vertical distance, and the vertical line is horizontally different from the right side board edge by the horizontal distance. These auxiliary lines are used to guide the layout of the device.

[0047] With the help of auxiliary lines and hardboard boundaries, closed areas are divided to determine the deployment areas of the master chip, memory module and flash module. Specifically, the first hardboard area is surrounded by the first horizontal line, the left side of the hardboard and the vertical line, which is the deployment area of the master chip. The second hardboard area is surrounded by the first horizontal line, the second horizontal line, the vertical line and the right side of the hardboard, which is the deployment area of the memory module (such as DDR). The third hardboard area is surrounded by the second horizontal line, the vertical line, the left side of the hardboard and the lower side of the hardboard, which is the deployment area of the flash module (NAND Flash).

[0048] According to the above definition of the closed area, the device is deployed on the corresponding hardboard area, which optimizes the layout, ensures the shortest signal line path, efficient power management, and considers the rationality of the heat dissipation design.

[0049] Through the embodiments provided in the present application, the deployment areas of the master chip, memory module and flash module are accurately defined by using the relative position relationship. This method not only ensures the rationality of the device layout, but also effectively utilizes the space of the hardboard, reduces the length of the signal line, and thus improves the signal integrity and power efficiency.

[0050] As an optional solution, deploying the master chip in the first hardboard area includes:

[0051] Determining a hardboard sub-area from the first hardboard area, wherein the hardboard sub-area is second vertically away from the third hardboard area in the vertical direction and is in close proximity to the second hardboard area in the horizontal direction;

[0052] Deploying the master chip in the hardboard sub-area.

[0053] Optionally, in the present embodiment, the first hardboard area is a region determined on the hardboard for deploying the master chip according to the interface connector position and related parameters. The hardboard sub-area is a further subdivided sub-area within the first hardboard area, specifically, this sub-area is second vertically away from the third hardboard area (NAND Flash area) in the vertical direction and is in close proximity to the second hardboard area (memory module area) in the horizontal direction.

[0054] Optionally, in the present embodiment, the second vertical distance represents the vertical distance between the master chip and the NAND Flash module, which is used to define the lower boundary of the master chip and the upper boundary of the NAND Flash module.

[0055] Optionally, in the present embodiment, the vertical limit of the hardboard sub-area is determined from the first hardboard area according to the second vertical distance. This generally means that a certain distance needs to be maintained between the lower edge of the master chip and the upper edge of the NAND Flash module to ensure correct wiring of the signal line.

[0056] The horizontal boundary of the hardboard sub-area should be close to the second hardboard area (memory module area) to ensure the closest connection between the master control chip and the memory module, while avoiding unnecessary signal path lengthening.

[0057] In the determined hardboard sub-area, the master control chip is precisely deployed. This step ensures that the master control chip can be in the best position, not only optimizing the signal transmission with the memory module and the NANDFlash module, but also considering the efficiency of power management and the heat dissipation design of the entire circuit board.

[0058] Through the embodiments provided in the present application, the layout in the first hardboard area is refined, and the master control chip is precisely positioned by determining the hardboard sub-area. The design principle of the hardboard sub-area is to maintain a second vertical distance with the NANDFlash module in the vertical direction, ensuring the shortest signal wiring path, thereby maximizing signal integrity and data transmission speed. At the same time, in the horizontal direction, the hardboard sub-area is closely adjacent to the memory module area, reducing the length of the signal wiring and ensuring the reliability of high-speed data transmission.

[0059] As an optional solution, a second parsing operation is performed on the software configuration file to obtain the first vertical distance between the master control chip and the interface connector, the horizontal distance between the master control chip and the right side of the hardboard, and the second vertical distance between the master control chip and the flash memory module to be deployed.

[0060] The number of signal connections between the master control chip and the interface connector is obtained, and the wiring width corresponding to each signal is obtained.

[0061] The first vertical distance is determined according to the number of connections and the wiring width.

[0062] Optionally, in this embodiment, first, the number of signal connections between the master control chip and the interface connector is obtained from the software configuration file, which will affect the total width of the signal lines. Then, the wiring width corresponding to each signal is further obtained, which is the core parameter for calculating the first vertical distance.

[0063] According to the number of signal connections and the wiring width of each signal, the total width of the signal lines required between the master control chip and the interface connector is calculated. Considering the minimum safety distance between the signal lines and the size of the master control chip, the total width of the signal lines and the safety distance are added to the calculation, and finally the first vertical distance is obtained. This distance will ensure that the signal lines can be correctly wired, while avoiding signal interference and power loss.

[0064] Through the embodiments provided in the present application, by accurately obtaining the signal connection information between the master control chip and the interface connector, the width requirement of each signal wire can be calculated, and then the first vertical distance is determined, so as to ensure that the signal line path is the shortest, and the signal integrity and power efficiency are maximized. This process fully considers the minimum safety distance between signals, avoids signal interference caused by improper layout, and optimizes power management and reduces power consumption.

[0065] As an optional solution, the second parsing operation is performed on the software configuration file to obtain the first vertical distance between the master control chip and the interface connector, the horizontal distance between the master control chip and the right side plate edge of the hard board, and the second vertical distance between the master control chip and the flash module to be deployed.

[0066] The first configuration distance between the master control chip and the memory module, the configuration length of the memory module, and the second configuration distance between the memory module and the right side plate edge are obtained.

[0067] The sum of the first configuration distance, the configuration length and the second configuration distance is determined as the horizontal distance.

[0068] Optionally, in the present embodiment, the first configuration distance between the master control chip and the memory module is obtained from the software configuration file, that is, the width and number of the signal path determine the necessary distance therebetween. The configuration length of the memory module is obtained, which is the transverse dimension of the memory module and is used to calculate the occupied space of the memory module on the hard board. The second configuration distance between the memory module and the right side plate edge of the hard board is calculated to ensure the safety of the memory module layout and the feasibility of the signal wire layout.

[0069] Optionally, in the present embodiment, the first configuration distance, the configuration length of the memory module and the second configuration distance obtained above are added to obtain the total sum, which is the horizontal distance. The calculation of the horizontal distance ensures that the layout between the master control chip, the memory module and the right side plate edge is reasonable, avoids unnecessary signal interference, and at the same time ensures the shortest path of the signal line, improves the signal integrity and power efficiency.

[0070] Through the embodiments provided in the present application, the second parsing operation performed on the software configuration file is not limited to obtaining the width and number of the signal line, but also involves the first configuration distance between the master control chip and the memory module, the configuration length of the memory module and the second configuration distance between the memory module and the right side plate edge. The comprehensive consideration of these configuration parameters enables the horizontal distance between the master control chip and the right side plate edge of the hard board to be calculated more accurately. By adding the three configuration parameters, the horizontal distance obtained ensures that the layout space between the master control chip and the right side plate edge is sufficient, and at the same time optimizes the signal transmission path between the memory module and the master control chip, avoiding the signal integrity problem caused by too long signal line.

[0071] As an optional solution, the second parsing operation is performed on the software configuration file to obtain a first vertical distance between the master control chip and the interface connector, a horizontal distance between the master control chip and a right side plate edge of the hard board, and a second vertical distance between the master control chip and the to-be-deployed flash memory module.

[0072] The third configuration distance between the master control chip and the flash memory module is obtained.

[0073] The third configuration distance is determined as the second vertical distance.

[0074] Optionally, in the embodiment, the third configuration distance between the master control chip and the flash memory module is read from the software configuration file, which reflects the minimum layout requirement in the vertical direction, and is intended to ensure that the wiring length of the signal line is reasonable and the signal integrity is not affected. The third configuration distance obtained above is directly determined as the second vertical distance, i.e., the vertical layout distance between the master control chip and the flash memory module. The determination of this distance follows the layout optimization principle, ensuring that the flash memory module can be closely close to the master control chip, thereby reducing the length of the signal line and improving the signal quality and data transmission speed.

[0075] Through the embodiments provided in the present application, the second parsing operation of the software configuration file not only involves the layout parameters between the master control chip and the interface connector, but also focuses on the distance optimization between the master control chip and the flash memory module. By accurately obtaining the third configuration distance from the configuration file, this step directly determines it as the second vertical distance, i.e., the vertical distance between the master control chip and the flash memory module. By reducing the signal transmission path between the master control chip and the flash memory module, the signal integrity and data transmission efficiency are greatly improved, and the possibility of data delay and read / write error is reduced. At the same time, the reasonable layout distance helps to reduce the complexity of the circuit board and reduce unnecessary wiring layers.

[0076] As an optional solution, before deploying the memory module in the second hard board area, the method further comprises:

[0077] performing a third parsing operation on the software configuration file to obtain a first number of configured memory particles, a first capacity of a single configured memory particle, and a first distribution width of the configured memory particles;

[0078] In a case where the vertical distance between the first horizontal line and the second horizontal line is determined as a second distribution width of the memory particles, a distribution parameter is determined based on the second distribution width and the first distribution width, wherein the distribution parameter is greater than or equal to 2;

[0079] Based on the first number, the first capacity, and the distribution parameter, a second number of the memory particles to be deployed in the second hard board area and a second capacity of a single memory particle are determined.

[0080] deploying the memory modules in the second hardboard area comprises:

[0081] deploying a second number of memory particles of a second capacity in the second hardboard area.

[0082] Optionally, in the embodiment, the first number is the total number of configured memory particles, i.e. the number of particles of the memory module in the original design scheme. The first capacity is the capacity of a single configured memory particle, which is used to calculate the total storage capacity of the memory module. The first distribution width is the total distribution width of the memory particles on the circuit board, which affects the compactness of the layout and the efficiency of the wiring.

[0083] Optionally, in the embodiment, the second distribution width is determined by the vertical distance between the first horizontal line and the second horizontal line, which is used to guide the vertical layout of the memory particles. The distribution parameter is a parameter calculated based on the second distribution width and the first distribution width, which is used to determine the layout density of the memory particles on the circuit board, to ensure the rationality of the layout. The second number is the number of memory particles to be deployed in the second hardboard area after adjustment, which may be different from the first number in the original design, to adapt to the optimization requirements of the circuit board layout. The second capacity is the capacity of a single memory particle after adjustment, which is used to ensure that the storage capacity of the SSD meets the requirements while optimizing the circuit board layout.

[0084] Optionally, in the embodiment, the first number is obtained from the software configuration file, i.e. the total number of memory particles in the original design scheme. The first capacity is obtained, i.e. the original capacity of a single memory particle. The first distribution width is calculated, which is the total horizontal distribution width of the memory particles on the circuit board, used to evaluate the compactness of the layout.

[0085] Based on the second distribution width (i.e. the vertical distance between the first horizontal line and the second horizontal line) and the first distribution width, the distribution parameter is calculated. This parameter is used to determine the layout density of the memory particles, to ensure the rationality of the layout and the shortest path of the signal lines.

[0086] According to the distribution parameter, the first number and the first capacity, the second number (the number of memory particles) and the second capacity (the capacity of a single memory particle) are re-determined, to achieve the best circuit board utilization efficiency and signal integrity.

[0087] In the second hardboard area, i.e. the part of the circuit board used to install the memory module, the memory particles are deployed according to the adjusted second number and second capacity, to realize the optimized layout.

[0088] By the embodiments provided in the present application, the rationality and efficiency of the original layout are evaluated by analyzing the original configuration information, including the total number of memory particles, the capacity of a single particle, and the transverse distribution width of the memory particles on the circuit board. Subsequently, based on the vertical distribution width (second distribution width) and the transverse distribution width of the memory particles on the circuit board, a distribution parameter is calculated. This parameter reflects the layout density of the memory particles on the circuit board, ensuring that the layout of the memory particles in the limited space is both compact and meets the requirements of signal integrity. On this basis, the second number and the second capacity to be deployed are recalculated and determined according to the distribution parameter, the original number and the capacity of the memory particles, so as to realize a more reasonable layout. Finally, the memory particles are deployed in the second hard board area (i.e., the memory module deployment area) according to the optimized second number and the second capacity, ensuring the high performance and stability of the SSD under high-density layout.

[0089] As an optional solution, determining the distribution parameter based on the second distribution width and the first distribution width comprises:

[0090] dividing the second distribution width by the first distribution width to obtain a first value;

[0091] obtaining a target even number corresponding to the first value, wherein the target even number is the smallest even number greater than the first value;

[0092] determining the target even number as the distribution parameter.

[0093] Optionally, in the present embodiment, the second distribution width is determined by the vertical distance between the first horizontal line and the second horizontal line in the circuit board design, representing the distribution width of the memory particles in the vertical direction, and is used to guide the vertical layout of the memory module. The first distribution width is the total transverse distribution width of the memory particles on the circuit board, reflecting the horizontal distribution of the particles in the original layout.

[0094] Optionally, in the present embodiment, the first value is obtained by dividing the second distribution width by the first distribution width, and is used to preliminarily evaluate the vertical and horizontal distribution ratio of the memory particle layout. The target even number is the smallest even number greater than the first value, which is used as the distribution parameter to adjust the layout density of the memory particles on the circuit board, ensuring the rationality of the layout and the shortest path of the signal trace. The distribution parameter, i.e., the target even number, is used to guide the re-layout of the memory particles, ensuring the layout optimization and signal integrity.

[0095] Optionally, in the present embodiment, a first value representing the layout ratio is obtained by dividing the second distribution width (the distribution width of the memory particles in the vertical direction) by the first distribution width (the distribution width of the memory particles in the horizontal direction).

[0096] According to the calculated first value, find the smallest even number greater than it. This step ensures the rationality of the distribution parameter, that is, to make the layout of the memory particles adapt to the vertical distribution requirements of the circuit board and facilitate the wiring and signal integrity considerations in the circuit board design.

[0097] Formally determine the target even number as the distribution parameter, which will guide the re-layout of the memory particles, including the adjustment of the number and the optimization of the capacity of individual memory particles, so as to realize a more compact, efficient and signal integrity circuit board layout.

[0098] Through the embodiments provided in the present application, first, by calculating the ratio between the second distribution width and the first distribution width, a first value is obtained, which preliminarily reflects the vertical layout density of the memory particles. The calculation of this value provides a quantitative basis for the subsequent adjustment of the layout of the memory particles. Subsequently, in order to ensure that the optimization of the layout of the memory particles takes into account the vertical layout requirements of the circuit board and maintains the uniformity of the layout and the orderliness of the signal lines, the present application introduces the concept of a target even number. Specifically, find the smallest even number greater than the first value as the distribution parameter. The selection of this parameter not only follows the mathematical rationality, but also takes into account the requirements of symmetry and regularity in circuit design, ensuring that the layout of the memory module will not be too complex or irregular, thereby reducing the risk of signal interference. Finally, the determination of the distribution parameter provides guidance for the re-layout of the memory particles, including adjusting the number of particles and optimizing the capacity of individual particles, so that the layout of the memory module on the circuit board is more compact and the signal lines are shorter, which helps to improve the signal integrity and overall performance of the SSD.

[0099] As an optional solution, based on the first number, the first capacity and the distribution parameter, determining the second number of memory particles to be deployed in the second hard board area and the second capacity of individual memory particles includes:

[0100] Using the first number divided by the distribution parameter to obtain the second number;

[0101] Using the first capacity multiplied by the distribution parameter to obtain the second capacity.

[0102] Optionally, in the present embodiment, the first number is divided by the distribution parameter to obtain the adjusted second number. This adjustment aims to reduce the total number of memory particles by increasing the load of individual memory particles, thereby saving circuit board space, simplifying wiring and improving signal integrity.

[0103] Using the first capacity multiplied by the distribution parameter to obtain the adjusted second capacity. By increasing the capacity of individual particles, the overall storage capacity of the memory module can be maintained or improved while reducing the total number of memory particles, realizing a more efficient layout.

[0104] Through the distribution parameter, the layout density of the memory particles on the circuit board can be optimized, and the total storage capacity of the memory module can be ensured. Specifically, first, the first number (the total number of memory particles in the original design) is divided by the distribution parameter (an even number), and the adjusted second number, i.e., the number of memory particles actually deployed on the circuit board, is calculated. This adjustment reduces the total number of memory particles, thereby releasing more circuit board space and creating conditions for reasonable wiring of signal lines and improving signal integrity. Then, in order to maintain the overall storage capacity of the memory module, the first capacity (the initial capacity of a single memory particle) is multiplied by the distribution parameter, and the adjusted second capacity, i.e., the capacity of a single memory particle, is obtained. The increase in capacity means that each memory particle bears more data storage tasks, and the reduction in total number simplifies the circuit board layout, both of which achieve the goal of deploying a high-performance memory module in a smaller space.

[0105] As an optional solution, deploying the flash memory module in the third hard board area includes:

[0106] Deploying 2N flash memory particles in the third hard board area, wherein the 2N flash memory particles include N flash memory particles deployed in the hard board front surface area corresponding to the third hard board area and N flash memory particles deployed in the hard board back surface area corresponding to the third hard board area, and the N flash memory particles deployed in the hard board front surface area and the N flash memory particles deployed in the hard board back surface area correspond one-to-one in the hard board position.

[0107] Optionally, in this embodiment, a total of 2N flash memory particles are deployed in the third hard board area, i.e., the flash memory module dedicated deployment area on the SSD circuit board. This deployment quantity is the result of comprehensive consideration of the space of the circuit board, the signal line layout requirement, and the storage capacity requirement.

[0108] Among them, N flash memory particles are deployed in the front surface area of the hard board, and another N flash memory particles are deployed in the back surface area of the hard board. This symmetrical deployment method not only fully utilizes the double surface space of the circuit board, but also facilitates the layout and management of signal lines, especially through the use of SkipVIA technology, efficient transmission of signals between front and back particles can be achieved without interfering with other important wiring.

[0109] Each NANDFlash particle deployed in the front surface area of the hard board has a corresponding NANDFlash particle in the back surface area of the hard board, and they correspond one-to-one in the hard board position, ensuring the accuracy of the signal and the consistency of the data.

[0110] Through the embodiments provided in the present application, in the design of the SSD circuit board, the embodiments propose a strategy of deploying flash memory modules in the third hard plate area symmetrically, aiming to maximize the space utilization of the circuit board while ensuring the reasonable layout of the signal lines and the efficient data transmission. Specifically, the present application suggests deploying a total of 2N flash memory particles in the third hard plate area, half (N) of which are deployed in the front area of the hard plate, and the other half (N) are deployed in the back area of the hard plate. This double-sided deployment mode not only solves the problem of limited space of the circuit board, but also optimizes the wiring path of the signal lines through the one-to-one correspondence of the front and back particles. In particular, by using the SkipVIA technology, fast and stable transmission of signals between particles can be achieved without increasing the complexity of the layout. By ensuring one-to-one correspondence of the particles in the hard plate position, the embodiments further improve the signal integrity and data consistency of the SSD, which is crucial for maintaining the high-speed read-write capability and long-term reliability of the SSD.

[0111] As an optional solution, after deploying 2N flash memory particles in the third hard plate area, the method further includes:

[0112] Obtaining the trace width corresponding to the local pins of the data type and all pins of the command type in the front area of the hard plate;

[0113] Obtaining the first spacing between two flash memory particles in the front area of the hard plate, and obtaining the nearest second spacing between the flash memory particles and the vertical line in the front area of the hard plate, the vertical line being different from the right plate edge in the horizontal direction by a horizontal distance;

[0114] In the case of obtaining the spacing sum of the first spacing and the second spacing, the result of dividing the trace width by the spacing sum is determined as the number of trace layers;

[0115] Deploying N inner layers in the front area of the hard plate, and deploying N inner layers in the back area of the hard plate.

[0116] Optionally, in the present embodiment, the 2N flash memory particles are the total number of flash memory particles deployed in the third hard plate area, half of which are deployed in the front area of the hard plate and the other half in the back area.

[0117] Optionally, in the present embodiment, the front area of the hard plate is the top area of the circuit board, used to place part of the flash memory particles and signal connection lines.

[0118] Optionally, in the present embodiment, the local pins of the data type are the pins on the flash memory particles used to transmit data signals, not all of which participate in data transmission, but are locally enabled according to specific data transmission requirements. All pins of the command type are all pins on the flash memory particles used to receive and send command signals, in order to ensure signal integrity, these pins need to be wired.

[0119] Optionally, in the embodiment, the first distance is the distance between two adjacent flash memory particles in the front area of the hard board, which affects the difficulty and complexity of the wiring. The second distance is the closest distance between the flash memory particles and a vertical line, which is horizontally separated from the right side of the board by a certain horizontal distance, to ensure the openness of the wiring path. The number of wiring layers is the number of inner layers calculated according to the wiring width and the available distance, which directly affects the complexity and cost of the circuit board.

[0120] Optionally, in the embodiment, the wiring width corresponding to the data type local pin and the command type all pin in the front area of the hard board is measured, which is the basic data for calculating the number of wiring layers.

[0121] The first distance between two flash memory particles in the front area of the hard board is measured, as well as the second distance between the flash memory particles and a certain vertical line, which is horizontally separated from the right side of the board by a certain horizontal distance, to ensure the clarity of the wiring path.

[0122] The wiring width is divided by the sum of the first distance and the second distance (distance sum value), and the result is rounded up to obtain the number of wiring layers. This calculation ensures that the signal lines can be reasonably allocated and laid out in the available space, while meeting the requirements of signal integrity and maximum space utilization.

[0123] According to the calculated number of wiring layers, a corresponding number of inner layers are deployed in the front area and the back area of the hard board respectively, for carrying data type and command type signal lines, to ensure efficient transmission of signals and compactness of layout.

[0124] Through the embodiments provided in the present application, the basic requirements for laying signal lines are mastered by measuring the wiring width of the data type local pin and the command type all pin on the flash memory particles. Then, the first distance between two flash memory particles in the front area of the hard board is measured, as well as the second distance between the flash memory particles and a vertical line, which is horizontally separated from the right side of the board by a certain safety distance, to ensure sufficient space for wiring. The number of wiring layers calculated based on the sum of the wiring width and the two distances determines the layout structure of the inner layers of the circuit board, which is the key to balancing signal integrity and circuit board complexity. Finally, according to the calculated number of wiring layers, a corresponding number of inner layers are deployed in the front area and the back area of the hard board, which not only realizes efficient layout of signal lines, but also effectively utilizes the space of the double-sided circuit board, reduces signal interference, and improves the signal integrity and overall performance of the SSD.

[0125] As an optional solution, deploying a number of wiring layers in the front area of the hard board includes:

[0126] In the front area of the hard board, a first type of inner layer is configured for partial pins of the data type, and a second type of inner layer is configured for all pins of the command type;

[0127] In the case of insufficient space of the first type of inner layer, a first pin of the data type with a distance less than a preset distance threshold from the master chip is determined from the partial pins of the data type;

[0128] The first pin of the data type is configured with the second type of inner layer.

[0129] Optionally, in the embodiment, first, a first type of inner layer is configured for partial pins of the data type in the front area of the hard board, and this part of the inner layer is specially used to carry data signals, ensuring high speed and low distortion of data transmission.

[0130] Meanwhile, a second type of inner layer is configured for all pins of the command type, and these inner layers are responsible for the transmission of command signals. Considering the characteristics and wiring requirements of the command signals, different processing may be required from the data signal inner layer.

[0131] When it is found that the first type of inner layer is insufficient to accommodate all partial pins of the data type, a first pin with a distance less than a preset distance threshold from the master chip is selected from the pins.

[0132] For the selected first pin, the wiring is upgraded to the second type of inner layer. The reason for this is that the pin closer to the master chip is more susceptible to interference, and therefore requires higher quality inner layer wiring to ensure signal integrity and stability.

[0133] Through the embodiments provided in the present application, first, a first type of inner layer is configured for partial pins of the data type, and this part of the inner layer design focuses on the fast transmission of data signals and signal integrity to meet the speed requirements of data processing. Meanwhile, a second type of inner layer is configured for all pins of the command type, and this part of the inner layer takes into account the characteristics and wiring requirements of the command signals to ensure accurate command transmission. In the case of insufficient space of the first type of inner layer, the present application proposes a fine adjustment strategy: identifying data type pins (first pins) with a distance less than a preset distance threshold from the master chip, and upgrading the wiring of these pins to the second type of inner layer. This approach not only solves the wiring problem caused by layout restrictions, but also ensures the transmission quality of close-range data signals, avoiding signal interference and distortion. Through this layered wiring and fine adjustment, the present application successfully balances the complexity of the circuit board design and the high performance of the signal line, providing necessary technical support for the high-performance operation of the SSD.

[0134] As an optional solution, the number of inner layers of the wiring layer is arranged in the hard board reverse area region includes:

[0135] In the hard board reverse area region, the third type of inner layer is configured for the partial pin of the data type, and the fourth type of inner layer is configured for all pins of the command type;

[0136] In the case of insufficient space of the third type of inner layer, the second pin of the data type is determined from the partial pin of the data type, and the distance between the master chip is less than the preset distance threshold;

[0137] The fourth type of inner layer is configured for the second pin of the data type.

[0138] The embodiment can refer to the arrangement of the number of inner layers of the wiring layer in the hard board front area region described above.

[0139] As an optional solution, the deployment method of the solid state disk is applied to the PCB design scene of the SSD. In this scene, most of the SSD products in the storage project are soft and hard combination boards. Compared with pure hard boards, the soft and hard combination boards have the following disadvantages: the power supply needs to cross the soft board repeatedly, the power supply and backflow path is long, and the power integrity is affected. The signal from the master chip to the left card needs to cross the soft board with a long length, the signal reference surface and the backflow path are discontinuous, and the signal integrity is affected. The soft and hard combination board manufacturing process is complex, the cycle is long, and there is an open circuit risk at the soft and hard combination. Once the open circuit is difficult to repair, the entire card will be scrapped. When the card is assembled into the hard disk shell, the soft board area needs to be bent, and the heat dissipation performance of the middle of the upper and lower cards is poor. Generally, a heat sink needs to be added, and the overall cost of the PCB is higher than that of the hard board.

[0140] In order to overcome the above defects, the embodiment proposes a pure hard board design idea. Based on the hard board DXF, the entire hard board is divided into several important functional modules. Under the premise of meeting the performance, each functional module is miniaturized. Under the condition of meeting the layout space, special processes of the PCB are adopted, and the layer design of important wires is specified to further meet the requirements of the number of wiring layers and the thickness of the board. At the same time, the position of the standby capacitor is adjusted to solve the heat dissipation problem of the PCB. A method for quickly designing such a PCB is given, which mainly includes three modules and steps: DXF modular division, device layout and layering in each region, and wiring design.

[0141] (I) DXF modular division

[0142] An operation flowchart of a DXF modular division is shown in Figure 3As shown, click the DXF modular division, and then click the hard plate DXF import, soft plate brd import, main chip position confirmation, DDR and Flash area division in turn. The background will automatically load the program, and the DXF of the hard plate will be divided into several large area modules.

[0143] Optionally, in the embodiment, click the hard plate DXF import, and the DXF needs to contain the position of the PCB board edge and the connector. Click the soft plate brd import. Click the main chip position confirmation, and the background will determine the position of the main chip according to the size of the chip and the number and pin distribution of the main signal. Click the DDR and Flash area division, and the background will divide a rough area of DDR and Flash according to the position of the main chip and the distribution of DDR signals and Flash signals.

[0144] Optionally, in the embodiment, the hard plate DXF import, the DXF needs to contain the hard plate frame and the connector position. The soft plate brd import is mainly to obtain the information of the main chip and the Nand Flash in the soft plate brd. The main chip position confirmation: access the brd file of the soft plate to obtain the number of signal connections between the main chip and the U.2, and estimate the total width of the wires required by these signals according to the number of signals and the width of each signal, which is recorded as H1. Access the brd file of the soft plate in step 2 to obtain the width required for the right side of the main chip to be connected with the DDR, which is recorded as W1, the long side of the DDR particle is recorded as W2, and the safe distance of the DDR to the board edge is 2mm, so the distance H2 of the main chip to the right side of the board edge can be obtained = W1+W2+2. As shown, Figure 4 As shown, respectively measure H1 downward from the lower edge of the connector in the DXF, draw a virtual line parallel to it, and record it as L1; measure the distance of H2 inward from the right edge of the DXF, also draw a line parallel to the right edge, and record it as L2. The coordinates of the intersection of the two straight lines L1 and L2 can be used as the position of one corner of the main chip.

[0145] It should be noted that the width and distance of the above wire are measured in mm.

[0146] DDR and Flash area division: access the brd file of the soft plate to obtain the width required for the main chip to be connected with the Nand Flash signal, which is recorded as H3.

[0147] A schematic diagram of the PCB structure of an SSD is shown in Figure 4 As shown, measure H3 downward from the lower edge of the main chip, draw a straight line parallel to it, and record it as L3. The area surrounded by L1, L2, L3, and the right side of the board is the placement area of the DDR, which is recorded as S1. The area surrounded by L2, L3, and the left and lower edges of the board is the placement area of the Nand Flash, which is recorded as S2.

[0148] (II) Device layout in each region

[0149] An operation flow diagram of device layout in each region is shown in FIG. 1, in which the device layout in each region is clicked; DDR selection and layout, NAND Flash layout, backup capacitor layout, and each power module layout are clicked in sequence, and the background will load the program to realize the automation of device layout in each region. Figure 5

[0150] DDR selection and layout: the capacity of a single DDR in the soft board is obtained and recorded as T1, and the number of DDRs in the soft board is recorded as M1. As shown in FIG. 2, the distance between the L1 line segment and the L3 line segment in the measurement diagram is recorded as H4, and the total width of the DDR particle layout in the soft board is recorded as H5 (the total width of the DDR particle layout in the original scheme is not shown in FIG. 1). Figure 4 Figure 4

[0151] H5 is divided by H4 to obtain a number, and the nearest even number greater than this number is taken, for example, if the obtained number is 1.3, the value is taken as 2, and if the obtained number is 2.3, the value is taken as 4; this obtained number is recorded as M.

[0152] The value obtained by T1*M is the new board card single DDR capacity value, which is recorded as T2 (commonly used DDR particle basic capacity specifications include 2Gb, 4Gb, 8Gb, and 16Gb); the value obtained by M1 / M is recorded as M2.

[0153] In the S1 region, the left upper corner vertex is taken as the starting position of the layout, and M2 DDR particles with a capacity of T2 are placed.

[0154] NAND Flash layout: the device front and back are completely placed in opposite positions to reduce the layout space. A schematic diagram of a PCB structure of an SSD is shown in FIG. 3, in which Nand Flash 1 and Nand Flash 2 are placed on the top face and the bottom face, respectively; Nand Flash 3 and Nand Flash 4 are placed on the top face and the bottom face, respectively; and so on. Figure 6

[0155] ​​​​All Nand Flash is placed as close to the left lower board edge as possible to give the layout of the power module. Based on the above front and back device needs to overlap, because the same position of the pin of the front and back particles is different signal, if the through hole is pulled out, the pin area needs to be pulled out, which requires a large amount of layout and wiring space, the number of layers and the thickness of the board will also increase. Therefore, the use of Skip VIA design is proposed here; the advantages of using Skip VIA are as follows: compared with the traditional through hole process, only one laser blind hole processing is added, the pressing frequency is not increased, and the cost is only increased by about 10%. Skip VIA compared with micro blind hole, both can achieve the purpose of completely overlapping the front and back of the device as described above, as shown in Figure 7 , Skip via and second-order micro blind hole structure diagram, if the micro blind hole process needs to be connected from the first layer to the third layer, it needs to be processed twice by laser blind hole, and needs to increase the pressing process once. The micro blind hole process needs to increase the cost by 20% compared with Skip VIA, and the board manufacturing cycle will be increased.

[0156] Backup capacitor layout: as shown in Figure 6 , the backup capacitor is laid out on the side of the board, because the SSD is vertically in the figure, the backup capacitor is placed on the side, which will not exist the problem of wind resistance, which is conducive to the heat dissipation of the whole machine.

[0157] Each power module layout: use separate power supply scheme, that is, split the large power module into small modules according to the layout space, the advantages are higher layout flexibility, each group of power supply is reasonably laid out according to the current size required by each functional module, the problem is easy to locate and analyze, unnecessary test work is reduced, the development cycle of the whole product is shortened, and the manufacturing cost of the PCB is reduced. At the same time, the layout principle of the power supply is to be as close to the power consumption end as possible and to avoid important wiring channels such as DDR and NandFlash. As shown in Figure 6 , the CORE electric P0V83 of the main control chip is laid out above the main control chip, so that the CORE electric distance to the main control is relatively short. P1V2 is laid out at the lower right corner of the main control chip, P2V5 is laid out below P1V2, and NAND Flash particles are laid out on the right side of P1V2. Among them, P1V2 needs to supply power to the main control, DDR and NAND Flash, of which DDR needs the largest current of P1V2, P2V5 needs to supply power to DDR and NAND Flash, and the layout position of P1V2 and P2V5 can ensure that the power supply path and current of each functional module are the most reasonable. And 12V_VPP this electricity only NAND Flash, we layout in the left lower NAND Flash above the main control.

[0158] (Three) layer and wiring design

[0159] An operation flowchart of a layer and wiring design is shown inFigure 8 As shown, click the stack and the design of the line; in turn, click the number of layers of the line estimates and the line layer and path design, the background will load the program, the realization of the number of layers of the line estimates and the line path of the automation.

[0160] The number of layers of the line estimates: because most of the lines of this PCB are the lines of the master control chip to the Nand Flash, so we only need to evaluate the number of layers of the line required by this part of the line, we can get the number of layers of the line required by the entire PCB. The steps are as follows:

[0161] Traverse the pin distribution of the top layer Nand Flash, and divide the chips into two categories according to the different signal types: DQ and CMD. In addition to the two groups of DQ lines closest to the master control chip, calculate the width required by the remaining DQ and CMD lines in the top layer, and mark it as W. The effective wiring space on the quantity side PCB board, such as Figure 6 H5+H6 is marked as W1. H5 is the spacing between two Nand Flash; H6 is the spacing between the rightmost Nand Flash and the line segment L5. W / W1 is the layer of the line required by the top layer Nand Flash, marked as N (rounded to an integer). Similarly, the bottom layer also needs N layers, and the entire PCB needs 2N inner layers. Connect the stack library data, and you can get the corresponding stack according to the line layer and the board thickness.

[0162] It should be noted that the above stack is due to the limitation of the board thickness, which cannot be added between L5 and L6 layers; L7 and L8 layers.

[0163] The line layer and path design: similarly, only the line layer of the Nand Flash is constrained. The line layer of the grain located in the top layer tries to choose the L3 layer line as much as possible, and the line layer of the device located in the bottom layer tries to choose the L10 layer line as much as possible. The top layer to L3 uses skip via, which only connects the top and L3 layers. This via has no effect on Layer4 to the bottom layer line and device, and similarly, the skip via hole of the bottom layer to L10 only connects the bottom and L10, and this via has no effect on Layer9 to the top line and device.

[0164] Because the DQ signals are more than the CMD signals, and the DQ signals have higher requirements on signal integrity, the levels of the DQ signals are defined as L3 and L10, and the levels of the CMD signals are defined as L5 and L8; if the space of the L3 and L10 layers is insufficient to pass the DQ signals, the DQ signals close to the host chip and having shorter lines are arranged on the L5 and L8 layers; here, the near end and the far end of the L3 and L10 layers refer to GND, the near end of the L5 and L8 layers refers to GND, and the far end refers to a power supply. The above layer division and laminated design can ensure that most of the DQ lines completely refer to the ground plane, and a part of the DQ signals and the CMD signals near the end refer to the ground plane, achieving good signal integrity. For example, as shown in FIG. 8, taking the Nand Flash of the top layer as an example, the DQ signals are preferentially passed on the L3 layer, the CMD signals are passed on the L5 layer, and if the space is insufficient, the DQ signals close to the host chip and having shorter lines are passed on the L5 layer. Figure 9 As shown in FIG. 8, taking the Nand Flash of the top layer as an example, the DQ signals are preferentially passed on the L3 layer, the CMD signals are passed on the L5 layer, and if the space is insufficient, the DQ signals close to the host chip and having shorter lines are passed on the L5 layer.

[0165] Through the embodiments provided in the present application, by proposing a pure hard plate design idea, the heat dissipation performance is also improved under the premise of meeting the hard disk capacity, and the manufacturing cost and manufacturing period of the PCB are also reduced. A method for quickly designing such a PCB is given, and the work efficiency is improved.

[0166] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and a necessary general hardware platform, and of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disc), and includes a plurality of instructions for causing a terminal device (which can be a mobile phone, a computer, a server, or a network device) to execute the methods of the embodiments of the present application.

[0167] In the present embodiment, a data storage device of an edge node is also provided, which is used to implement the above embodiments and preferred embodiments, and will not be described again. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, hardware, or a combination of software and hardware is also possible and contemplated.

[0168] Figure 10 FIG. 1 is a structural block diagram of a deployment device of a solid state disk according to an embodiment of the present application, as shown in FIG. 1, the device includes: Figure 10

[0169] ​The analysis unit 1002 is configured to perform a first parsing operation on the hardware configuration file to obtain a storage area of the interface connector on the hard board, and perform a second parsing operation on the software configuration file to obtain a first vertical distance between the interface connector and the main control chip, a horizontal distance between the main control chip and a right side plate edge of the hard board, and a second vertical distance between the main control chip and the flash memory module to be deployed;

[0170] The determination unit 1004 is configured to determine, based on the storage area, the first vertical distance, the second vertical distance, and the horizontal distance, a first hard board area corresponding to the main control chip, a second hard board area corresponding to the memory module to be deployed, and a third hard board area corresponding to the flash memory module on the hard board.

[0171] The deployment unit 1006 is configured to deploy the main control chip in the first hard board area, deploy the memory module in the second hard board area, and deploy the flash memory module in the third hard board area.

[0172] As an optional solution, the determination unit 1004 includes:

[0173] The first determination module is configured to determine a first horizontal line, a second horizontal line, and a vertical line on the hard board, wherein the first horizontal line is different from the storage area by a first vertical distance in the vertical direction, the second horizontal line is different from the storage area by a third vertical distance in the vertical direction, the third vertical distance is a sum of the first vertical distance, the second vertical distance, and a vertical length of the main control chip, and the vertical line is different from the right side plate edge by the horizontal distance in the horizontal direction.

[0174] The second determination module is configured to determine a closed area between the first horizontal line, the second horizontal line, the vertical line, and a left side plate edge of the hard board as the first hard board area.

[0175] The third determination module is configured to determine a closed area between the first horizontal line, the second horizontal line, the vertical line, and the right side plate edge as the second hard board area.

[0176] The fourth determination module is configured to determine a closed area between the second horizontal line, the vertical line, the left side plate edge, and a lower side plate edge of the hard board as the third hard board area.

[0177] As an optional solution, the deployment unit 1006 includes:

[0178] The fifth determination module is configured to determine a hard board sub-area from the first hard board area, wherein the hard board sub-area is different from the third hard board area by the second vertical distance in the vertical direction and is close to the second hard board area in the horizontal direction.

[0179] The first deployment module is configured to deploy the main control chip in the hard board sub-area.

[0180] As an optional solution, the analysis unit 1002 includes:

[0181] The first obtaining module is configured to obtain a number of connections of signals between the host chip and the interface connector, and obtain a width of a wire corresponding to each signal.

[0182] The sixth determining module is configured to determine the first vertical distance according to the number of connections and the width of the wire.

[0183] As an optional solution, the parsing unit 1002 includes:

[0184] The second obtaining module is configured to obtain a first configuration distance between the host chip and the memory module, a configuration length of the memory module, and a second configuration distance between the memory module and the right side of the board;

[0185] The seventh determining module is configured to determine a sum of the first configuration distance, the configuration length, and the second configuration distance as the horizontal distance.

[0186] As an optional solution, the parsing unit 1002 includes:

[0187] The third obtaining module is configured to obtain a third configuration distance between the host chip and the flash memory module;

[0188] The eighth determining module is configured to determine the third configuration distance as the second vertical distance.

[0189] As an optional solution, the apparatus further includes:

[0190] The parsing module is configured to, before deploying the memory module in the second hard board area, perform a third parsing operation on the software configuration file to obtain a first number of configured memory particles, a first capacity of a single configured memory particle, and a first distribution width of the configured memory particles.

[0191] The ninth determining module is configured to, in a case where a vertical distance between the first horizontal line and the second horizontal line is determined as a second distribution width of the memory particles, determine a distribution parameter based on the second distribution width and the first distribution width, where the distribution parameter is greater than or equal to 2.

[0192] The tenth determining module is configured to determine, based on the first number, the first capacity, and the distribution parameter, a second number of the memory particles and a second capacity of a single memory particle to be deployed in the second hard board area.

[0193] The deployment unit includes:

[0194] The second deployment module is configured to deploy the second number of the memory particles with the second capacity in the second hard board area.

[0195] As an optional solution, the ninth determining module includes:

[0196] The first calculating sub-module is configured to divide the second distribution width by the first distribution width to obtain a first numerical value;

[0197] The obtaining sub-module is configured to obtain a target even number corresponding to the first numerical value, wherein the target even number is the smallest even number greater than the first numerical value.

[0198] The first determining sub-module is configured to determine the target even number as the distribution parameter.

[0199] As an optional solution, the tenth determining module comprises:

[0200] The second calculating sub-module is configured to divide the first number by the distribution parameter to obtain a second number.

[0201] The third calculating sub-module is configured to multiply the first capacity by the distribution parameter to obtain a second capacity.

[0202] As an optional solution, the deployment unit 1006 comprises:

[0203] The third deployment module is configured to deploy 2N flash memory particles in the third hard board area, wherein the 2N flash memory particles comprise N flash memory particles deployed in the hard board front area corresponding to the third hard board area and N flash memory particles deployed in the hard board back area corresponding to the third hard board area, and the N flash memory particles deployed in the hard board front area and the N flash memory particles deployed in the hard board back area correspond to each other in the hard board position.

[0204] As an optional solution, the apparatus further comprises:

[0205] The fourth obtaining module is configured to, after the 2N flash memory particles are deployed in the third hard board area, obtain a wiring width corresponding to the local pins of the data type and the whole pins of the command type in the hard board front area.

[0206] The fifth obtaining module is configured to, after the 2N flash memory particles are deployed in the third hard board area, obtain a first spacing between two flash memory particles in the hard board front area, and obtain a second spacing between the flash memory particle and the vertical line in the hard board front area, the vertical line being different from the right side board edge by a horizontal distance in the horizontal direction.

[0207] The eleventh determining module is configured to, after the 2N flash memory particles are deployed in the third hard board area, determine, when the first spacing and the second spacing are obtained, a wiring layer number as a result of dividing the wiring width by the sum of the first spacing and the second spacing.

[0208] The fourth deployment module is configured to, after the 2N flash memory particles are deployed in the third hard board area, deploy the wiring layer number of inner layers in the hard board front area and deploy the wiring layer number of inner layers in the hard board back area.

[0209] As an optional solution, the fourth deployment module comprises:

[0210] The first configuration sub-module is configured to configure the inner layer of the first type for the local pins of the data type and configure the inner layer of the second type for all the pins of the command type in the front area of the hard board.

[0211] The second determination sub-module is configured to determine, in the case that the inner layer space of the first type is insufficient, a first pin of the data type from the local pins of the data type, the distance between which and the master control chip being less than the preset distance threshold.

[0212] The second configuration sub-module is configured to configure the inner layer of the second type for the first pin of the data type.

[0213] The specific examples in the embodiment can refer to the examples described in the above embodiments and exemplary embodiments, and the embodiment will not be described here again.

[0214] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and the necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, an optical disk), and includes a plurality of instructions for causing a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of various embodiments of the present application.

[0215] It should be noted that the above various modules can be realized by software or hardware, and for the latter, the following implementation manners can be used, but are not limited thereto: all the above modules are located in the same processor; or the above various modules are located in different processors in any combination.

[0216] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when running.

[0217] In an exemplary embodiment, the above computer readable storage medium can include, but is not limited to: a U disk, a read-only memory (Read-Only Memory, ROM for short), a random access memory (Random Access Memory, RAM for short), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0218] The embodiments of the present application further provide an electronic device, comprising a memory and a processor, the memory stores a computer program, and the processor is configured to execute the computer program to perform the steps in any of the method embodiments.

[0219] In an example embodiment, the electronic device further comprises a transmission device connected to the processor and an input / output device connected to the processor.

[0220] The embodiments of the present application further provide a computer program product, comprising a non-volatile computer readable storage medium, the non-volatile computer readable storage medium stores a computer program product, and the computer program is executed by a processor to implement the steps in the method of the embodiments of the present application.

[0221] The specific examples in the embodiments can refer to the examples described in the above embodiments and example embodiments, and the embodiments will not be described here again.

[0222] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be realized by general computing devices, which can be concentrated on a single computing device or distributed on a network composed of multiple computing devices, and they can be realized by program codes executable by computing devices, so that they can be stored in storage devices and executed by computing devices, and in some cases, the steps shown or described can be executed in different order, or they can be manufactured into individual integrated circuit modules, or multiple modules or steps can be manufactured into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

[0223] The above is only the preferred embodiments of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for deploying a solid state drive, the method comprising: The method comprises the following steps: performing a first parsing operation on a hardware configuration file to obtain a storage area of an interface connector on a hard board, and performing a second parsing operation on a software configuration file to obtain a first vertical distance between a main control chip and the interface connector, a horizontal distance between the main control chip and a right side board edge of the hard board, and a second vertical distance between the main control chip and a flash memory module to be deployed; determining a first horizontal line, a second horizontal line and a vertical line on the hard board, wherein the first horizontal line is different from the storage area by the first vertical distance in the vertical direction, the second horizontal line is different from the storage area by a third vertical distance in the vertical direction, the third vertical distance is a sum of the first vertical distance, the second vertical distance and a vertical length of the main control chip, and the vertical line is different from the right side board edge by the horizontal distance in the horizontal direction; determining a closed area between the first horizontal line, the second horizontal line, the vertical line and a left side board edge of the hard board as a first hard board area corresponding to the main control chip; determining a closed area between the first horizontal line, the second horizontal line, the vertical line and the right side board edge as a second hard board area corresponding to the memory module to be deployed; determining a closed area between the second horizontal line, the vertical line, the left side board edge and a lower side board edge of the hard board as a third hard board area corresponding to the flash memory module; deploying the main control chip in the first hard board area, deploying the memory module in the second hard board area, and deploying the flash memory module in the third hard board area.

2. The method of claim 1, wherein, The method comprises the following steps: determining a hard board sub-area from the first hard board area, wherein the hard board sub-area is different from the third hard board area by the second vertical distance in the vertical direction and is close to the second hard board area in the horizontal direction; deploying the main control chip in the hard board sub-area.

3. The method of claim 1, wherein, The second parsing operation on the software configuration file comprises the following steps: obtaining a connection number of signals between the main control chip and the interface connector, and obtaining a wiring width corresponding to each signal; determining the first vertical distance according to the connection number and the wiring width.

4. The method of claim 1, wherein, The second parsing operation on the software configuration file comprises the following steps: obtaining a first configuration distance between the main control chip and the memory module, a configuration length of the memory module and a second configuration distance between the memory module and the right side board edge; determining a sum value of the first configuration distance, the configuration length and the second configuration distance as the horizontal distance.

5. The method of claim 1, wherein, The second parsing operation is performed on the software configuration file to obtain a first vertical distance between the master control chip and the interface connector, a horizontal distance between the master control chip and a right side plate edge of the hard board, and a second vertical distance between the master control chip and the flash memory module to be deployed. A third configuration distance between the master control chip and the flash memory module is obtained. The third configuration distance is determined as the second vertical distance.

6. The method of claim 1, wherein, before deploying the memory module in the second hard board area, the method further comprises: performing a third parsing operation on the software configuration file to obtain a first number of configured memory particles, a first capacity of a single configured memory particle, and a first distribution width of the configured memory particles; determining a distribution parameter based on the second distribution width and the first distribution width, in a case that a vertical distance between the first horizontal line and the second horizontal line is determined as a second distribution width of the memory particles, wherein the distribution parameter is greater than or equal to 2; determining a second number of the memory particles and a second capacity of a single memory particle to be deployed in the second hard board area based on the first number, the first capacity, and the distribution parameter; the deploying the memory module in the second hard board area comprises: deploying the second number of the second capacity of the memory particles in the second hard board area.

7. The method of claim 6, wherein, the determining the distribution parameter based on the second distribution width and the first distribution width comprises: dividing the second distribution width by the first distribution width to obtain a first numerical value; obtaining a target even number corresponding to the first numerical value, wherein the target even number is a smallest even number greater than the first numerical value; determining the target even number as the distribution parameter.

8. The method of claim 6, wherein, the determining the second number of the memory particles and the second capacity of a single memory particle to be deployed in the second hard board area based on the first number, the first capacity, and the distribution parameter comprises: dividing the first number by the distribution parameter to obtain the second number; multiplying the first capacity by the distribution parameter to obtain the second capacity.

9. The method of claim 1, wherein, the deploying the flash memory module in the third hard board area comprises: deploying 2N flash memory particles in the third hard board area, wherein the 2N flash memory particles include N flash memory particles deployed in a front hard board area corresponding to the third hard board area and N flash memory particles deployed in a back hard board area corresponding to the third hard board area, and the N flash memory particles deployed in the front hard board area and the N flash memory particles deployed in the back hard board area one-to-one correspond in a hard board position.

10. The method of claim 9, wherein, after deploying the 2N flash memory particles in the third hard board area, the method further comprises: obtaining a wiring width corresponding to local pins of a data type and all pins of a command type in the front hard board area; obtaining a first spacing between two flash memory particles in the front hard board area, and obtaining a nearest second spacing between a flash memory particle and a vertical line in the front hard board area, the vertical line being different from the right side plate edge in a horizontal direction by the horizontal distance. In a case where the pitch sum of the first pitch and the second pitch is obtained, the wiring width is divided by the pitch sum to determine a number of wiring layers; The number of wiring layers is arranged in the front area of the hard board, and the number of wiring layers is arranged in the back area of the hard board.

11. The method of claim 10, wherein, Arranging the number of wiring layers in the front area of the hard board includes: In the front area of the hard board, a first type of inner layer is configured for the local pins of the data type, and a second type of inner layer is configured for all pins of the command type; In a case where the first type of inner layer is insufficient, a first pin of the data type is determined from the local pins of the data type, the distance between the first pin and the master chip being less than a preset distance threshold; The first pin of the data type is configured with the second type of inner layer.

12. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, wherein the computer program is executed by a processor to implement the steps of the method in any one of claims 1 to 11.

13. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the steps of the method in any one of claims 1 to 11.

14. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 11.

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