Preparation method of bicrystal Josephson junction array chip and bicrystal Josephson junction array chip

Abstract

The invention discloses a preparation method of a bicrystal Josephson junction array chip and the bicrystal Josephson junction array chip, relates to the technical field of electronic information, and solves the problems of poor geometric parameter consistency and serious high-frequency loss of a common bicrystal Josephson junction array chip. According to the method, the pattern design of the series bicrystal Josephson junction is optimized through geometric topology, and the problem of geometric parameter fluctuation caused by traditional manual design is solved, so that the critical current consistency of a series structure is improved, and the chip performance is improved; by simulating and optimizing parameters of the microwave coupled antenna, high signal fidelity of the microwave coupled antenna and the series bicrystal Josephson junction in a scene of receiving and transmitting high-frequency radio-frequency signals is realized, the upper limit of the working frequency of the bicrystal Josephson junction array chip is improved, the signal transmission loss is reduced, and the high-frequency detection requirement of a quantum computing chip can be met.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic information technology, and in particular to a preparation method of a bicrystal Josephson junction array chip and the bicrystal Josephson junction array chip. BACKGROUND

[0002] As the core device of quantum voltage standard, Josephson junction array has important application value in the fields of precision measurement and quantum circuit. However, the traditional series Josephson junction array technology faces significant technical bottlenecks in practical applications.

[0003] On the one hand, the preparation of the traditional series Josephson junction array highly depends on manual design and processing technology, such as junction array construction based on photolithography or electron beam exposure. In this mode, the geometric parameters of the junction unit (such as junction area, electrode spacing, insulating layer thickness, etc.) are difficult to achieve precise control: the size deviation of the junction caused by manual operation can reach ±50 nm, which in turn leads to the dispersion of junction capacitance and critical current. Experimental data show that such dispersion can cause the output voltage deviation of the junction array to exceed 10%, seriously affecting the accuracy and reliability of the quantum voltage standard. In the measurement system based on superconducting quantum interference devices, the voltage deviation of the junction array will introduce measurement errors, and even cause the system to fail to meet the high-precision metrology requirements. In addition, the fluctuation of geometric parameters also destroys the phase synchronization characteristics of the junction array, which weakens the quantum interference effect of the series structure and further aggravates the performance degradation.

[0004] On the other hand, the current traditional technology has serious deficiencies in the integration of radio frequency signals, which restricts the application of Josephson junction array in the high frequency field. Specifically, there are compatibility problems in the integration process of the junction array and the radio frequency circuit, which limits the upper limit of the working frequency to 30 GHz, far below the application requirements of the millimeter wave frequency band. At the same time, due to the design defects of the matching network and the superconducting-normal state transition loss, the signal loss is greater than 2 dB during transmission, causing the signal-to-noise ratio of the quantum voltage signal to decrease. In the microwave quantum communication system, the signal transmission loss above 30 GHz will cause the quantum voltage waveform output by the junction array to be distorted, which cannot realize high-speed quantum state regulation. In addition, the low integration also makes it difficult to expand the scale of the junction array, limiting the construction of multi-bit quantum circuits, and hindering the further development of Josephson junction array in the fields of quantum computing and high-frequency precision measurement.

[0005] Therefore, the manual design mode and low integration process of the traditional series Josephson junction array are essentially difficult to meet the needs of modern quantum devices for high precision and high frequency. It is urgent to develop a preparation method of a bicrystal Josephson junction array chip and the bicrystal Josephson junction array chip to solve the problems of geometric parameter consistency and high frequency loss, so as to promote the practical application of Josephson junction array in the fields of quantum metrology, quantum communication and quantum computing. SUMMARY

[0006] In view of the problems of poor geometric parameter consistency and serious high-frequency loss of the existing bicrystal Josephson junction array chip, the application provides a preparation method of a bicrystal Josephson junction array chip and a bicrystal Josephson junction array chip, which can improve the geometric consistency of the bicrystal Josephson junction array chip and reduce the high-frequency loss. The specific technical solutions are as follows:

[0007] In the first aspect, the application provides a preparation method of a bicrystal Josephson junction array chip, comprising:

[0008] The physical relationship of the bicrystal Josephson junction is taken as a constraint condition, the maximum critical current is taken as a target, a first geometric pattern of the series bicrystal Josephson junction is generated through a geometric topology optimization algorithm; based on the junction array area and the antenna area arranged in the substrate area, the signal fidelity of the microwave coupling antenna in the scene of receiving and sending high-frequency radio frequency signals is tested through simulation software; wherein the series bicrystal Josephson junction is arranged in the junction array area in the form of the first geometric image, the microwave coupling antenna is arranged in the antenna area, and the microwave coupling antenna is used to concentrate the radio frequency signals in the junction array area; based on the signal fidelity, the design parameters of the microwave coupling antenna and the series bicrystal Josephson junction are adjusted to obtain a second geometric pattern containing the microwave coupling antenna and the series bicrystal Josephson junction; based on the second geometric pattern and the substrate area, a mask plate design file is generated; a pattern is engraved on a strontium titanate bicrystal on which a yttrium barium copper oxide (YBCO) high-temperature superconducting film is grown through a mask plate to obtain a bicrystal Josephson junction array chip, and the mask plate is produced based on the mask plate design file.

[0009] Preferably, the junction area shape of the bicrystal Josephson junction is rectangular, the constraint condition includes that the product of the critical current density and the junction area of the bicrystal Josephson junction is equal to the critical current, and the distance between adjacent junction areas of the series Josephson junction is greater than or equal to 100 mu m.

[0010] Preferably, based on the junction array area and the antenna area arranged in the substrate area, the signal fidelity of the microwave coupling antenna in the scene of receiving and sending high-frequency radio frequency signals is tested through simulation software, including: through the simulation software, based on the junction array area and the antenna area, the radio frequency response characteristics of the microwave coupling antenna in the 30-80 GHz frequency band are simulated, and the signal fidelity is obtained; based on the signal fidelity, the test result is used to adjust the design parameters of the microwave coupling antenna and the series bicrystal Josephson junction to obtain a second geometric pattern containing the microwave coupling antenna and the series bicrystal Josephson junction, including: based on the signal fidelity, the design parameters are adjusted, and the step of simulating the radio frequency response characteristics of the microwave coupling antenna in the 30-80 GHz frequency band and obtaining the signal fidelity is returned until the signal fidelity is greater than or equal to 0.85; under the condition that the signal fidelity is greater than or equal to 0.85, the second geometric pattern is generated based on the design parameters obtained by the last adjustment.

[0011] Preferably, the adjusting the design parameter based on the signal fidelity comprises: adjusting the number of bicrystal Josephson junctions in the series bicrystal Josephson junction by steps of 40 junctions.

[0012] Preferably, the patterning the bicrystal Josephson junction array chip by the mask on the strontium titanate bicrystal on which the yttrium barium copper oxide YBCO high-temperature superconducting thin film is grown comprises: copying the pattern on the mask to the strontium titanate bicrystal by ultraviolet exposure lithography technology to obtain the bicrystal Josephson junction array chip.

[0013] Preferably, the copying the pattern on the mask to the strontium titanate bicrystal by ultraviolet exposure lithography technology to obtain the bicrystal Josephson junction array chip comprises: taking a mercury lamp with a wavelength of 365 nm and a resolution of 0.5 microns as a light source, copying the pattern on the mask to the strontium titanate bicrystal by the ultraviolet exposure lithography technology to obtain the bicrystal Josephson junction array chip.

[0014] Preferably, the substrate region further comprises an electrode region for connecting an external circuit; the area of the junction array region accounts for 30% of the area of the substrate region, the area of the electrode region accounts for 50% of the area of the substrate region, and the area of the antenna region accounts for 5% of the area of the substrate region.

[0015] Preferably, the size of the substrate region is 10 mm x 10 mm.

[0016] Preferably, before the signal fidelity of the microwave coupling antenna in the high-frequency radio frequency signal receiving and sending scene is tested by simulation software, the method further comprises: dividing the substrate region into a plurality of regions by CAD software, the plurality of regions comprising the junction array region, the antenna region and the electrode region.

[0017] In a second aspect, the embodiments of the present application also provide a bicrystal Josephson junction array chip, which is prepared based on the method of any one of the first aspect.

[0018] Compared with the prior art, the present application has the following beneficial effects: by geometric topology optimization of the pattern design of the series bicrystal Josephson junction, the problem of geometric parameter fluctuation caused by traditional manual design is solved, so that the critical current consistency of the series structure is improved, and the chip performance is improved; by simulation optimization of the parameters of the microwave coupling antenna, the signal high fidelity of the microwave coupling antenna and the series bicrystal Josephson junction in the high-frequency radio frequency signal receiving and sending scene is realized, the upper limit of the working frequency of the bicrystal Josephson junction array chip is improved, and the signal transmission loss is reduced, which can meet the high-frequency detection demand of the quantum computing chip. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the drawings needed to be used in the specific embodiments or prior art description will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference signs. In the drawings, each element or part is not necessarily drawn according to the actual proportion.

[0020] Figure 1 A flowchart of a preparation method of a bicrystal Josephson junction array chip provided by an embodiment of the present application is shown in the figure.

[0021] Figure 2 A schematic diagram of region division of a substrate region provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative effort fall within the scope of the present application.

[0023] It should be understood that, when used in the specification and the appended claims, the terms “comprise” and “include” indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] It should also be understood that the terms used in the present application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the present application specification and the appended claims, the singular forms “a”, “an” and “the” are intended to include the plural forms, unless the context clearly indicates otherwise.

[0025] It should be further understood that the term “and / or” used in the present application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0026] To solve the problems of poor geometric parameter consistency and serious high-frequency loss of a traditional bicrystal Josephson junction array chip, the present application provides a preparation method of a bicrystal Josephson junction array chip and a bicrystal Josephson junction array chip, which can improve design consistency and reduce high-frequency loss.

[0027] Please refer to Figure 1 , Figure 1A flowchart of a preparation method of a bicrystal Josephson junction array chip is provided for an embodiment of the present application. The method is applied to a computing device. As shown in Figure 1 The method comprises the following steps.

[0028] In step 101, the computing device generates a first geometric pattern of a series of bicrystal Josephson junctions by a geometric topology optimization algorithm, with the physical relationship of the bicrystal Josephson junctions as a constraint condition and the maximum critical current as a target.

[0029] The computing device can be a server or a terminal. Specifically, the computing device can be connected to a lithography device in a wired or wireless manner and be built-in with a CST Microwave Studio simulation platform. Thus, the computing device can perform chip simulation based on the CST Microwave Studio simulation platform to achieve design parameter optimization, and after obtaining a design scheme of the bicrystal Josephson junction array chip, the computing device can directly instruct the lithography device to perform chip lithography according to the design scheme.

[0030] The Josephson junction is a superconducting device based on quantum tunneling effect, which is composed of two superconductors with a thin insulating layer or weak connection region in between. The core is to realize the quantum tunneling effect of superconducting electron pairs (Cooper pairs). The bicrystal Josephson junction is a Josephson junction prepared based on a bicrystal substrate. The core is a grain boundary formed by splicing two single-crystal substrates (such as yttrium-stabilized zirconia YSZ) with different crystal orientations. After depositing a superconducting thin film (such as YBCO) on the grain boundary, a weak connection region will naturally form at the grain boundary, thereby constituting a Josephson junction.

[0031] The junction region of the Josephson junction refers to the connection region between the two superconductors, which is the core part for realizing the quantum tunneling effect of Cooper pairs.

[0032] Preferably, the junction region of the bicrystal Josephson junction is rectangular, the constraint condition includes that the product of the critical current density Jc and the junction region area S of the bicrystal Josephson junction is equal to the critical current Ic, and the distance d between adjacent junction regions of the series of Josephson junctions is greater than or equal to 100 μm.

[0033] The critical current Ic of the bicrystal Josephson junction refers to the maximum superconducting current that can pass through when a voltage drop starts to appear at both ends of the junction under zero external magnetic field. It reflects the strength of the Cooper pair tunneling effect in the junction and is a core characteristic quantity of the Josephson effect.

[0034] The critical current density refers to the maximum superconducting current that can be carried per unit area of the junction region. The junction region refers to the effective physical area of the Josephson junction that enables superconducting quantum tunneling. The critical current density Jc of a small-area junction is relatively high, but the junction capacitance C is small, which is beneficial for high-frequency applications (such as quantum bits), but the manufacturing difficulty is high. The critical current Ic of a large-area junction is relatively high, which is suitable for high sensitivity, but the phase coherence is poor and is easily affected by environmental noise.

[0035] Therefore, the computing device can pre-set the maximum and minimum values of the junction area, and determine the target junction area through simulation testing.

[0036] By constraining the distance d between adjacent junction regions, the parasitic capacitance can be suppressed. For example, the target value of the parasitic capacitance Cp is less than or equal to 0.1 pF. At the same time, the consistency of the critical current Ic of the series structure can be improved, and the yield of the chip can be improved.

[0037] For example, the shape of the bicrystal Josephson junction can also be circular or other topological shapes.

[0038] The first geometric pattern is formed by the junction regions of the series of bicrystal Josephson junctions.

[0039] For example, the computing device can optimize the junction region pattern of the series of bicrystal Josephson junctions through a level set method or a topological derivative method to obtain the first geometric pattern.

[0040] By designing the first geometric pattern through a geometric topology optimization algorithm, based on the principle that the electrical signals of the Josephson junctions do not interfere with each other, and ensuring the uniformity of the parameters of a single junction, the voltage uniformity error of the series of junction regions can be reduced, and the parameter fluctuation problem caused by traditional manual design can be solved.

[0041] In step 102, the computing device tests the signal fidelity of the microwave coupling antenna in the high-frequency radio signal receiving and transmitting scenario based on the junction array region and the antenna region set in the substrate region through simulation software.

[0042] The series of bicrystal Josephson junctions are arranged in the first geometric pattern in the junction array region, and the junction regions of the Josephson junctions in the junction array region are connected in series. The number of series of junction regions can be optimized. For example, the computing device also performs exhaustive optimization to try different combinations of the number of junction regions, the area of the junction regions, and the distance between the junction regions in the junction array region, and tests the related performance through simulation software to determine the combination with the best performance.

[0043] It can be understood that the shape of the bicrystal Josephson junction is pre-set.

[0044] The microwave coupling antenna is arranged in the antenna area, and is used for concentrating radio frequency signals in the junction array area; and the microwave coupling antenna and the double Josephson junction are integrally formed in a photolithography process. Specifically, the antenna area can be arranged near the junction array area, so as to improve the coupling efficiency of high-frequency microwaves and the junction area of the double Josephson junction, and concentrate microwave energy near the junction area.

[0045] Preferably, the antenna area and the junction array area are closely attached.

[0046] Preferably, the antenna area and the junction array area adopt a coplanar integration scheme.

[0047] Preferably, the substrate area further includes an electrode area used for connecting an external circuit; the area of the junction array area accounts for 30% of the area of the substrate area, the area of the electrode area accounts for 50% of the area of the substrate area, and the area of the antenna area accounts for 5% of the area of the substrate area.

[0048] The electrode area is used for connecting an external circuit to meet the four-probe test requirement. Specifically, a direct current signal interface can be reserved in the electrode area according to actual use and test requirements.

[0049] Preferably, the size of the substrate area is 10 mm x 10 mm. For example, refer to Figure 2 In a 10 mm x 10 mm area, the junction array area, the electrode area and the microwave coupling antenna are integrated, the junction array area internally contains a Josephson series junction array, the electrode area internally contains a direct current signal interface (with a spacing of 0.5 mm), and the microwave coupling antenna is based on a logarithmic antenna. In step 103, parameters are adjusted according to simulation conditions.

[0050] The antenna area includes a plurality of microwave coupling antennas, and each microwave coupling antenna is used for a single Josephson junction at the position of the microwave coupling antenna, so that each Josephson junction is equipped with a microwave coupling antenna.

[0051] The computing device can simulate a superconducting thin film superconducting state by using an ideal conductor based on CST Microwave Studio electromagnetic simulation software, and adjust parameters to obtain an optimal microwave coupling antenna design scheme based on parameterized simulation of a logarithmic antenna.

[0052] Preferably, the computing device can divide the substrate area into a plurality of areas by using computer aided design (CAD) software, and the plurality of areas include the junction array area, the antenna area and the electrode area.

[0053] It can be understood that the computing device can divide the substrate region before step 101, and then design the first geometric pattern in the divided junction array region; or first perform step 101 to design the first geometric pattern, and then divide the substrate region and set the first geometric pattern in the junction array region after scaling.

[0054] The functional region of the 10mmx10mm substrate is divided by CAD software to realize the standardization of the design process; the chip preparation cycle is shortened, and the performance difference between batches is less than 2%, which is suitable for large-scale production.

[0055] Step 103, the computing device adjusts the design parameters of the microwave coupling antenna and the series bicrystal Josephson junction based on the signal fidelity, to obtain a second geometric pattern containing the microwave coupling antenna and the series bicrystal Josephson junction.

[0056] Preferably, the computing device can simulate the radio frequency response characteristics of the microwave coupling antenna in the 30-80GHz frequency band based on the junction array region and the antenna region through the simulation software, and obtain the signal fidelity; then adjust the design parameters based on the signal fidelity, and return to the step of simulating the radio frequency response characteristics of the microwave coupling antenna in the 30-80GHz frequency band and obtaining the signal fidelity, until the signal fidelity is greater than or equal to 0.85; based on the design parameters obtained by the last adjustment, generate the second geometric pattern when the signal fidelity is greater than or equal to 0.85.

[0057] Illustratively, the computing device can perform radio frequency band microwave simulation of micron size level planar microwave coupling antenna through CST Microwave Studio software, and combine with the high frequency signal response characteristics of Josephson junction to receive and send high frequency signals, and verify the signal fidelity in the receiving and sending process, to adjust the design parameters of the microwave coupling antenna and the series bicrystal Josephson junction, to obtain a second geometric pattern design scheme that makes high frequency radio frequency signals have high fidelity and concentrate near the bicrystal Josephson junction region.

[0058] Preferably, the computing device can adjust the number of Josephson junctions in the series bicrystal Josephson junction in steps of 40 junctions. Large step adjustment can quickly scan in a wide range of numbers to avoid fine-grained adjustment in irrelevant intervals. For example, when it is necessary to determine the influence of the number of series junctions on the critical current and voltage characteristics, large step can quickly find the key interval of characteristic change (such as critical current mutation point, voltage step range), reducing the debugging time.

[0059] By adjusting the design parameters of the microwave coupling antenna and the series bicrystal Josephson junction through simulation, a second design pattern is obtained, which can expand the upper limit of the high-frequency working frequency of the prepared bicrystal Josephson junction array chip from the traditional 30 GHz to 60 GHz, and the high-frequency signal transmission loss is ≤0.5 dB, which can meet the high-frequency detection needs of quantum computing chips.

[0060] Wherein, the size of each part inside the microwave coupling antenna can also be designed and adjusted based on the signal fidelity, such as how many μm long and wide can achieve the highest signal fidelity in a certain frequency band.

[0061] Step 104, the computing device generates a mask design file based on the second geometric pattern and the substrate area.

[0062] Wherein, the computing device can integrate the design scheme of the bicrystal Josephson junction array chip containing the second geometric pattern in a 10mm x 10mm size substrate area. It can be understood that the design scheme includes the design pattern of the junction array area, the antenna area and the electrode area, and the design pattern of the electrode area includes the position and size of the direct current signal interface.

[0063] The design scheme is suitable for common bicrystal substrates on the market, has high repeatability, is convenient and fast, and can meet the high-frequency design of most Josephson junction array chips.

[0064] Wherein, the mask design file provides a standardized reference for the preparation of the mask, which is convenient for the sustainable development of subsequent photolithography work and the repeated production of the mask.

[0065] Step 105, the computing device draws patterns on the strontium titanate bicrystal on which the Yttrium Barium Copper Oxide (YBCO) high-temperature superconducting film is grown through the mask to obtain a bicrystal Josephson junction array chip.

[0066] Wherein, the mask is produced based on the mask design file, and its material can be glass and chromium metal in the industrial specification, which is compatible with most standard photolithography machines on the market.

[0067] Wherein, the computing device instructs the photolithography equipment to transfer the micro-pattern on the mask to the strontium titanate bicrystal sample on which the YBCO high-temperature superconducting film is grown by using photoresist, which is convenient for subsequent batch preparation and repeated production of bicrystal Josephson junction array chips.

[0068] Wherein, the computing device can transfer the pattern on the mask to the strontium titanate bicrystal by ultraviolet exposure photolithography technology to obtain the bicrystal Josephson junction array chip.

[0069] Specifically, the computing device can select a mercury lamp with a wavelength of 365 nm and a resolution of 0.5 μm as a light source, and use the ultraviolet exposure lithography technology to copy the pattern on the mask to the strontium titanate bicrystal to obtain the bicrystal Josephson junction array chip.

[0070] The mask can assist the ultraviolet exposure lithography machine in performing lithography work and provide a standardized reference for the preparation of the bicrystal Josephson junction array chip, thereby ensuring high repeatability and high efficiency of chip production.

[0071] By using the lithography process suitable for the mainstream bicrystal substrate on the market to prepare the bicrystal Josephson junction array chip, the yield of the bicrystal Josephson junction array chip can be improved, without the need for customized equipment, thereby shortening the process debugging period and reducing production costs, and being compatible with various commercial substrates.

[0072] In the embodiments of the present application, the geometric topology optimization of the pattern design of the series-connected bicrystal Josephson junction solves the problem of geometric parameter fluctuation caused by traditional manual design, thereby improving the consistency of the critical current of the series-connected structure and improving the performance of the chip; the simulation optimization of the parameters of the microwave coupling antenna realizes high signal fidelity of the microwave coupling antenna and the series-connected bicrystal Josephson junction in the scene of transmitting and receiving high-frequency radio frequency signals, improves the upper limit of the working frequency of the bicrystal Josephson junction array chip, reduces signal transmission loss, and meets the high-frequency detection requirements of the quantum computing chip.

[0073] The embodiments of the present application also provide a bicrystal Josephson junction array chip prepared based on the method as Figure 1 described in the embodiments.

[0074] Those skilled in the art can appreciate that the units of the examples described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both, and the constitution of each example has been described in general in the above description in order to clearly illustrate the interchangeability of hardware and software. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0075] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0076] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely illustrative. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0077] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

[0078] In addition, each functional unit in the various embodiments of the present application can be integrated in one processing unit, or each unit can exist physically as a separate unit, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware, or in the form of a software functional unit.

[0079] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that makes a contribution to the prior art, or all or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: a U disk, a read-only memory (ROM, read-only memory), a random access memory (RAM, random access memory), a mobile hard disk, a magnetic disk or an optical disk, and various program codes that can be stored in the medium.

[0080] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some or all of the technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application, and they should be covered in the scope of the claims and the description of the present application.

Claims

1. A method of fabricating a twin Josephson junction array chip, characterized by, include: Using the physical relationship of the bicrystalline Josephson junction as a constraint and aiming at maximizing the critical current, the first geometric pattern of the series bicrystalline Josephson junction is generated through a geometric topology optimization algorithm. Based on the array region and antenna region set in the substrate region, the signal fidelity of the microwave coupled antenna in the scenario of receiving and transmitting high-frequency radio frequency signals is tested by simulation software; wherein, the series dual-crystal Josephson junction is set in the array region in the pattern of the first geometric image, the microwave coupled antenna is set in the antenna region, and the microwave coupled antenna is used to concentrate the radio frequency signal in the array region; Based on the signal fidelity, the design parameters of the microwave coupled antenna and the tandem double-crystal Josephson junction are adjusted to obtain a second geometric pattern including the microwave coupled antenna and the tandem double-crystal Josephson junction; Based on the second geometric pattern and the substrate region, a mask design file is generated; A bicrystalline Josephson junction array chip is obtained by patterning a strontium titanate bicrystalline substrate on which a yttrium barium copper oxide (YBCO) high-temperature superconducting thin film has been grown using a mask. The mask is manufactured based on the mask design file.

2. The method of claim 1, wherein, The junction region of the bicrystalline Josephson junction is rectangular, and the constraints include that the product of the critical current density of the bicrystalline Josephson junction and the junction area is equal to the critical current, and that the spacing between adjacent junction regions of the series Josephson junction is greater than or equal to 100 μm.

3. The method of claim 1, wherein, The array area and antenna area set in the substrate region are used to test the signal fidelity of the microwave coupled antenna in a scenario of transmitting and receiving high-frequency radio frequency signals using simulation software, including: Using the simulation software, based on the array region and the antenna region, the radio frequency response characteristics of the microwave coupled antenna in the 30-80GHz frequency band are simulated, and the signal fidelity is obtained. Based on the test results of the signal fidelity, the design parameters of the microwave coupled antenna and the tandem double-crystal Josephson junction are adjusted to obtain a second geometric pattern including the microwave coupled antenna and the tandem double-crystal Josephson junction, comprising: Based on the signal fidelity, the design parameters are adjusted, and the steps of simulating the radio frequency response characteristics of the microwave coupled antenna in the 30-80GHz band and obtaining the signal fidelity are returned until the signal fidelity is greater than or equal to 0.

85. If the signal fidelity is greater than or equal to 0.85, the second geometric pattern is generated based on the design parameters obtained from the last adjustment.

4. The method of claim 3, wherein, The adjustment of the design parameters based on the signal fidelity includes: The number of bicrystalline Josephson junctions in the tandem bicrystalline Josephson junction is adjusted in increments of 40 junctions.

5. The method according to any one of claims 1-4, characterized in that, The process of patterning a strontium titanate bicrystalline substrate onto a YBCO high-temperature superconducting thin film grown using a mask to obtain a bicrystalline Josephson junction array chip includes: The pattern on the photomask is copied onto the strontium titanate bicrystalline material using ultraviolet lithography to obtain the bicrystalline Josephson junction array chip.

6. The method of claim 5, wherein, The pattern on the mask is copied to the strontium titanate bicrystal by the ultraviolet exposure lithography technology, and the bicrystal Josephson junction array chip is obtained, comprising: A mercury lamp with a wavelength of 365 nm and a resolution of 0.5 μm is used as a light source, and the pattern on the mask is copied to the strontium titanate bicrystal by the ultraviolet exposure lithography technology, and the bicrystal Josephson junction array chip is obtained.

7. The method according to any one of claims 1-4, characterized in that, The substrate region further comprises an electrode region, and the electrode region is used for connecting an external circuit; the area of the junction array region accounts for 30% of the area of the substrate region, the area of the electrode region accounts for 50% of the area of the substrate region, and the area of the antenna region accounts for 5% of the area of the substrate region.

8. The method according to any one of claims 1-4, characterized in that, The size of the substrate region is 10 mm x 10 mm.

9. The method according to any one of claims 1-4, characterized in that, Before testing the signal fidelity of the microwave coupling antenna in the high-frequency radio frequency signal receiving and sending scene by simulation software, the method further comprises: The substrate region is divided into a plurality of regions by CAD software, and the plurality of regions comprise the junction array region, the antenna region and the electrode region.

10. A bicrystal Josephson junction array chip, characterized by, The bicrystal Josephson junction array chip is prepared based on the method of any one of claims 1-9.

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