Full-airspace phased array resource scheduling method, equipment and medium

Abstract

The invention discloses a whole-airspace phased array resource scheduling method, equipment and a medium, and relates to the field of spacecraft measurement and control. According to the method, firstly, a vectorization processing method for the visible arc segment of the satellite is given, so that subsequent optimization modeling is facilitated; secondly, the maximum task satisfaction rate serves as an optimization target, decision variables are defined, and a mathematical expression of a target function is given; thirdly, analyzing constraints corresponding to the optimization problem, including feasibility constraints of time chips, prohibition constraints of the time chips, uniquely allocated constraints of the time chips, full-airspace phased array activation array surface conflict constraints and the like; simulation results show that the algorithm provided by the invention can realize second-level phased array resource scheduling and meet the real-time planning requirements of large-scale constellations in the future. Compared with a traditional heuristic algorithm (a genetic algorithm and a Bayesian optimization algorithm) and a greedy algorithm, the algorithm provided by the invention has the advantage that the task satisfaction rate performance is remarkably improved under the same configuration condition.

Description

Technical Field

[0001] This invention relates to the field of spacecraft telemetry, tracking and command (TT&C), specifically to a method, equipment, and medium for scheduling phased array resources across the entire space domain. Background Technology

[0002] The statements in this section are provided only as background information in relation to this disclosure and may not constitute prior art.

[0003] In recent years, with the large-scale networking of low-Earth orbit satellite constellations (such as OneWeb and Starlink), their low orbit and ultra-dense airspace distribution have posed a severe challenge to the multi-beam scheduling capability of phased array antennas across the entire airspace, requiring support for second-level beam reconfiguration and real-time phased array resource scheduling.

[0004] However, existing technologies face three core bottlenecks: (1) The scheduling granularity is mismatched with the phased array antenna capability. In existing satellite telemetry and control scenarios, phased array resource scheduling generally relies on time window mechanisms. Since traditional satellite telemetry and control mainly relies on parabolic antennas, the preparation time of parabolic antennas (which may be as long as minutes) needs to be taken into account in beam resource allocation, which cannot support the real-time scheduling requirements of large-scale phased array resources. Secondly, in the traditional time window scheduling process, in order to avoid conflicts, each time window can usually only be allocated once. In fact, a visible time window of a satellite (at least 60 seconds) is usually longer than the actual telemetry and control time required by the satellite (10-30 seconds), resulting in a waste of time-domain telemetry and control resources.

[0005] (2) Existing scheduling strategies mostly adopt the greedy algorithm of "first come, first served". Although the computational efficiency is high, it lacks global optimization capability. In multi-task concurrent scenarios, it is difficult to balance the optimality of task planning and computational efficiency, which often leads to fierce resource competition and a sharp drop in the overall throughput of the system.

[0006] (3) Secondly, in large-scale phased array resource scheduling scenarios, traditional heuristic algorithms (such as genetic algorithms, simulated annealing algorithms, particle swarm algorithms, etc.) are difficult to meet the real-time requirements of large-scale phased array beam resource scheduling due to problems such as a large number of iterations and slow convergence speed. In time-sensitive scenarios such as satellite constellation collision avoidance, emergency communication, and disaster monitoring, scheduling delays or failures are likely to occur.

[0007] In summary, it is necessary to design an efficient all-space phased array resource scheduling method to enhance the instantaneous multi-beam capability of existing all-space phased arrays and support the real-time scheduling needs of future large-scale phased array resources. Summary of the Invention

[0008] The purpose of this invention is to address the problems of traditional multi-beam resource scheduling schemes based on parabolic antennas, such as the mismatch between scheduling granularity and actual antenna capabilities, the inability of the "first-come, first-served" strategy to guarantee the optimality of large-scale phased array beam resource scheduling, and the high number of iterations and slow convergence speed of traditional heuristic algorithms in solving large-scale phased array beam resource scheduling problems, which cannot meet the real-time planning requirements of phased array resources. This invention provides a full-space-domain phased array resource scheduling method, device, and medium that can support the real-time scheduling requirements of future large-scale phased array beam resources, thereby solving the aforementioned problems.

[0009] The technical solution of the present invention is as follows: A method for scheduling phased array resources across the entire airspace includes: Step S1: Data preprocessing; scheduling cycle By time interval Divided into Each time slice; converts the visible arc information of each satellite into a length of... binary vectors ; Step S2: Objective function modeling; maximizing the task satisfaction rate is equivalent to maximizing the sum of the elements of the decision variable matrix. ;in This indicates the number of satellites participating in the mission planning, and its value is equal to the number of satellite missions. Indicates satellite Choose in Each time chip executes a task; Step S3: Constraint Modeling; Under the premise of satisfying satellite visibility constraints, the activation conflict of the phased array surface in the entire space domain is modeled as a binary conflict matrix, and the core constraint of the integer programming model is that at most one of the conflicting tasks at the same time can be executed, thereby ensuring that there is no phased array surface resource conflict in any time chip of the scheduling scheme. Step S4: Solve the above objective function as a 0-1 integer programming problem to obtain the optimal scheduling scheme.

[0010] Furthermore, the time interval It is equal to the minimum visible arc length of the satellite.

[0011] Furthermore, in step S2, the task satisfaction rate is defined as the ratio of the number of successfully planned satellite tasks to the total number of tasks.

[0012] Further, step S3 includes: Constraint 1: Ensure that the time chip selected by the satellite is part of its visible arc; Constraint 2: Ensure that the time chip selected by the satellite is not part of its invisible arc segment; Constraint 3: Consider conflict constraints on the active surface of the phased array.

[0013] Furthermore, constraint 1 is expressed as follows: .

[0014] Furthermore, constraint 2 is expressed as follows:

[0015] in: .

[0016] Furthermore, constraint 3 is expressed as follows: For time slices Using the conflict adjacency matrix Record this time slice The conflict situation of array elements between different tasks; activating array surface conflict can be modeled as .

[0017] Furthermore, in step S4, the all-space phased array resource scheduling problem with the objective of maximizing task satisfaction rate can be modeled as the following 0-1 integer programming problem:

[0018] The 0-1 integer programming problem is solved using the branch-and-cut method or by using a commercial solver.

[0019] The present invention also proposes an electronic device, comprising: At least one processor; and a memory communicatively connected to said at least one processor; The memory stores instructions that can be executed by the at least one processor, and the at least one processor executes the instructions stored in the memory to perform the method described above.

[0020] The present invention also proposes a computer-readable storage medium for storing instructions that, when executed, cause the method described above to be implemented.

[0021] Compared with existing technologies, the advantages of this invention are: To meet the real-time scheduling requirements of large-scale phased array beam resources in the future, this invention proposes a full-space-domain phased array resource scheduling method, equipment, and medium. Specifically, this invention first provides a vectorized processing method for the visible arc segment of satellites, facilitating subsequent optimization modeling. Secondly, maximizing the task satisfaction rate is used as the optimization objective, decision variables are defined, and a mathematical expression for the objective function is given. Next, the constraints corresponding to the optimization problem are analyzed, including feasibility constraints for time chips, prohibition constraints for time chips, unique allocation constraints for time chips, and conflict constraints for active array surfaces of the full-space-domain phased array. Simulation results show that the algorithm proposed in this invention can achieve phased array resource scheduling at the second level, meeting the real-time planning requirements of future large-scale constellations. Compared with traditional heuristic algorithms (genetic algorithms, Bayesian optimization algorithms) and greedy algorithms, under the same configuration conditions, the algorithm proposed in this invention significantly improves the task satisfaction rate performance. Attached Figure Description

[0022] Figure 1 A schematic diagram of traditional all-space phased array multibeam resource scheduling based on time windows and a schematic diagram of the proposed all-space phased array multibeam resource scheduling. Figure 2 A comparison of the task satisfaction rate performance between the traditional multi-beam resource scheduling method based on time window and genetic algorithm and the proposed multi-beam resource scheduling method; Figure 3 A comparison of the running time of the traditional beam resource scheduling method based on time window + genetic algorithm and the proposed multi-beam resource scheduling method; Figure 4 A comparison of the task satisfaction rate performance of the "first-come, first-served" greedy algorithm and the proposed multi-beam resource scheduling method under time-slice conditions; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0023] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0024] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0025] Example 1 In recent years, low-Earth orbit satellite constellations (such as OneWeb and Starlink) have entered the stage of large-scale networking. These constellations are characterized by low orbital altitude, a large number of satellites, and dense airspace distribution, which puts forward real-time requirements for the multi-beam scheduling capabilities of ground-based phased array antennas, namely "second-level beam reconstruction and millisecond-level resource reallocation".

[0026] However, existing satellite telemetry and control systems still use the scheduling framework developed during the era of traditional parabolic antennas, leading to the following three bottlenecks: 1. Mismatch in scheduling granularity Existing systems generally use a "time window" as the smallest scheduling unit. Since the mechanical rotation and servo stabilization of parabolic antennas require minutes of preparation time, the time window is typically set to 60 seconds or longer. However, phased array antennas can complete pointing switching in milliseconds. Continuing to use a 60-second window not only fails to leverage the agility of phased arrays but also results in a waste of 30 to 50 seconds of time-domain resources due to the exclusive rule that "one window can only serve once."

[0027] 2. The scheduling strategy lacks global optimization. In engineering sites, a greedy "first-come, first-served" strategy is commonly used: tasks occupy available windows in the order they arrive. This strategy has low computational complexity, but it is prone to local optima in multi-task concurrent scenarios, causing high-priority tasks to be blocked by low-priority tasks, and the overall system throughput to drop sharply as the number of tasks increases.

[0028] 3. Heuristic algorithms lack real-time performance. To alleviate the local optima problem of greedy strategies, some systems introduce heuristic algorithms such as genetic algorithms, simulated annealing, or particle swarm optimization. While these algorithms can improve solution quality to some extent, they require multiple iterations for optimization, and the computation time increases exponentially with the scale of the task. In "second-level response" scenarios such as constellation collision avoidance, emergency communication, and disaster monitoring, they often fail directly because they cannot converge within the time limit.

[0029] Therefore, there is an urgent need for a full-space phased array resource scheduling method that can match the beam agility capability of phased arrays, possess global optimality, and can be solved in seconds, in order to support the real-time measurement and control needs of future large-scale low-Earth orbit constellations.

[0030] Therefore, this embodiment provides a method, device and medium for scheduling phased array resources across the entire airspace, which can support the real-time scheduling needs of large-scale phased array beam resources in the future, thereby solving the above-mentioned problems.

[0031] Please see Figure 1 A method for scheduling phased array resources across the entire airspace, specifically including the following steps: Step S1: Data preprocessing; This stage mainly involves vectorizing the known satellite visible arc information to obtain the time chip occupancy under small time scale conditions, which facilitates subsequent problem modeling and optimization solutions; details are as follows: scheduling period By time interval Divided into Each time slice; converts the visible arc information of each satellite into a length of... binary vectors ; This indicates that the first time chip is for a satellite. A portion of the visible arc; similarly, This indicates that the first, second, and third time chips are all satellites. A portion of the visible arc; it is worth noting that a satellite may have multiple visible arcs within a scheduling period, therefore, the binary array It may contain multiple elements 1; The number of time slices is .

[0032] In this embodiment, specifically, the time interval It is equal to the minimum visible arc length of the satellite (e.g., 1 minute).

[0033] Step S2: Objective function modeling; maximizing the task satisfaction rate is equivalent to maximizing the sum of the elements of the decision variable matrix. ;in This indicates the number of satellites participating in the mission planning, and its value is equal to the number of satellite missions. Indicates satellite Choose in Each time chip executes a task; In this embodiment, it should be noted that the present invention aims to maximize the task satisfaction rate; the task satisfaction rate is defined as the ratio of the number of successfully planned satellite missions to the total number of missions. Based on this, first define Indicates satellite Choose in The task is executed within one time chip; it is worth noting that, based on engineering practice, this invention considers that each satellite task can be completed within one time chip (e.g., less than 1 minute); therefore, maximizing the task satisfaction rate is equivalent to maximizing the decision variable matrix. The sum of the elements, that is ,in This indicates the number of satellites participating in the mission planning, and its value is equal to the number of satellite missions, assuming that each satellite has only one mission to perform.

[0034] Step S3: Constraint Modeling; Under the premise of satisfying satellite visibility constraints, the activation conflict of the phased array surface in the entire space domain is modeled as a binary conflict matrix, and the core constraint of the integer programming model is that at most one of the conflicting tasks at the same time can be executed, thereby ensuring that there is no phased array surface resource conflict in any time chip of the scheduling scheme.

[0035] In this embodiment, specifically, step S3 includes: Constraint 1: Ensure that the time chip selected by the satellite is part of its visible arc; Constraint 2: Ensure that the time chip selected by the satellite is not part of its invisible arc segment; Constraint 3: Consider conflict constraints on the active surface of the phased array.

[0036] In this embodiment, specifically, each satellite's mission can only select one time slice for execution, and it is necessary to ensure that the time slice selected by the satellite is part of its visible arc. The corresponding constraint 1 is:

[0037] It should be noted that when the right side of this constraint is 0, it indicates that the satellite... To avoid conflicts with other missions, the satellite chooses not to participate in resource scheduling. The corresponding task will fail.

[0038] In this embodiment, it is also necessary to ensure that the time chip selected by the satellite does not belong to its invisible arc segment. The corresponding constraint 2 is expressed as follows:

[0039] in: .

[0040] In this embodiment, specifically, finally, conflict constraints on the phased array activation surface are further considered. Specifically, for time slices... Using the conflict adjacency matrix Record this time slice Conflicts between array elements in different tasks. For example... Indicates the first In a time slice, the mission With the task There are conflicts in the activated array surfaces. Correspondingly, the activated array surface conflict can be modeled as follows: .

[0041] Step S4: Solve the above objective function as a 0-1 integer programming problem to obtain the optimal scheduling scheme.

[0042] In this embodiment, specifically, in step S4, the all-space phased array resource scheduling problem with the objective of maximizing task satisfaction rate can be modeled as the following 0-1 integer programming problem:

[0043] The above process enables the modeling of a full-space phased array multi-beam resource scheduling method based on integer programming. This optimization problem is a typical 0-1 integer programming problem, which can be solved efficiently using the branch-and-cut method. Under small- to medium-scale conditions, it can also be solved efficiently using commercial solvers (such as Cplex, Gurobi, and Matlab).

[0044] Based on the same technical concept, embodiments of the present invention also provide an electronic device that can implement the all-space phased array resource scheduling method flow provided in the above embodiments of the present invention. In one embodiment, the electronic device can be a server, a terminal device, or other electronic devices. Figure 5 As shown, the electronic device may include: At least one processor and a memory connected to the at least one processor. In this embodiment of the invention, the specific connection medium between the processor and the memory is not limited. Figure 5 The example used is the connection between the processor and memory via a bus. The bus... Figure 5 The connections between other components are indicated by thick lines and are for illustrative purposes only, not as limiting information. Buses can be divided into address buses, data buses, control buses, etc., but for ease of representation, [the specific bus type is not shown here]. Figure 5 The processor is represented by a single thick line, but this does not imply that there is only one bus or one type of bus. Alternatively, a processor can also be called a controller; there are no restrictions on the name.

[0045] In this embodiment of the invention, the memory stores instructions executable by at least one processor. By executing the instructions stored in the memory, the at least one processor can perform the all-space phased array resource scheduling method described above. The processor can implement... Figure 5 The functions of each module in the device shown.

[0046] The processor is the control center of the device. It can connect to various parts of the control equipment through various interfaces and lines. By running or executing instructions stored in memory and calling data stored in memory, it can monitor the various functions and data processing of the device as a whole.

[0047] In an alternative design, the processor may include one or more processing units. The processor may integrate an application processor and a modem processor, wherein the application processor primarily handles the operating system, user interface, and applications, while the modem processor primarily handles wireless communication. It is understood that the modem processor may also not be integrated into the processor. In some embodiments, the processor and memory may be implemented on the same chip; in some embodiments, they may also be implemented separately on separate chips.

[0048] The processor can be a general-purpose processor, such as a CPU, digital signal processor, application-specific integrated circuit, field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, capable of implementing or executing the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the all-space phased array resource scheduling method disclosed in the embodiments of this invention can be directly manifested as execution by a hardware processor, or execution by a combination of hardware and software modules within the processor.

[0049] Memory, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. Memory can include at least one type of storage medium, such as flash memory, hard disk, multimedia card, card-type memory, random access memory (RAM), static random access memory (SRAM), programmable read-only memory (PROM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), magnetic memory, magnetic disk, optical disk, etc. Memory is any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited thereto. In embodiments of the present invention, memory can also be a circuit or any other device capable of implementing storage functions, used to store program instructions and / or data.

[0050] By designing and programming the processor, the code corresponding to the all-space phased array resource scheduling method described in the foregoing embodiments can be embedded into the chip, enabling the chip to execute the steps of the method described in the foregoing embodiments during runtime. How to design and program the processor is a technique well-known to those skilled in the art and will not be elaborated upon here.

[0051] Based on the same inventive concept, embodiments of the present invention also provide a storage medium storing computer instructions that, when executed on a computer, cause the computer to perform a full-space phased array resource scheduling method described above.

[0052] In some alternative embodiments, the present invention also provides a method for scheduling all-space phased array resources that can be implemented as a program product, which includes program code. When the program product is run on a device, the program code is used to cause the control device to perform the steps in the method for scheduling all-space phased array resources according to various exemplary embodiments of the present invention as described above.

[0053] It should be noted that although several units or sub-units of the apparatus have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of the invention, the features and functions of two or more units described above can be embodied in one unit. Conversely, the features and functions of one unit described above can be further divided and embodied by multiple units. Furthermore, although the operation of the method of the invention is described in a specific order in the drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0054] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0055] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a server, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the process. Figure 1 One or more processes and / or boxes Figure 1A device that provides the functions specified in one or more boxes.

[0056] Program code for performing the operations of this invention can be written using any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0057] In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0058] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0059] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0060] Example 2 To verify the effectiveness of the all-space phased array resource scheduling algorithm proposed in this invention, this invention provides a phased array resource scheduling example under a specific satellite telemetry and control scenario.

[0061] Specifically, the STK software was used to generate GPS satellite orbit information and Starlink low-Earth orbit (LEO) satellite orbit information. Based on the generated satellite information, a set of visible arc segments and a set of satellite missions were created. The visible arc segment set includes information such as: satellite ID, satellite source ID, visible arc segment number, start time, end time, and visible arc segment duration. The mission set includes information such as: mission number, satellite ID, mission execution duration, and mission execution status. The scheduling cycle starts at 23:59:59 on March 3, 2024, and ends at 23:59:59 on March 4, 2024. The telemetry and control station is located at longitude 103° and latitude 31°. The phased array is a spherical and cylindrical array with 26,469 array elements. For the Starlink LEO satellite mission set, the phased array activation angle is set to 20 degrees. For the GPS medium-Earth orbit (MEO) satellites, the phased array activation angle is set to 40 degrees. The low-Earth orbit (LEO) satellite mission set contains 398 satellite missions, and the medium-Earth orbit (MEO) satellite mission set contains 24 satellite missions. During algorithm execution... min, therefore, number of time chips When a phased array is operating with only one channel active, When the phased array has both channels open, .

[0062] A comparison of the task satisfaction rate performance of the traditional multi-beam scheduling method based on time window + genetic algorithm and the proposed multi-beam scheduling method under different system configurations is as follows: Figure 2 As shown, regardless of single-channel or dual-channel conditions, the proposed all-space phased array multi-beam resource scheduling algorithm achieves a 100% mission fulfillment rate under different satellite mission configurations. This is because, compared to traditional phased array multi-beam resource scheduling methods, the proposed method has a smaller scheduling granularity and, by utilizing the beam agility of the all-space phased array, can support more satellite telemetry and control missions. Simulation results also verify the effectiveness of the proposed algorithm.

[0063] This invention also presents the execution time of the proposed algorithm on a low-Earth orbit satellite mission set under different mission numbers, with commonly used genetic algorithms serving as the baseline for comparison. The relevant results are as follows: Figure 3 As shown. To ensure the search quality of the genetic algorithm, the population size of the genetic algorithm is set to... The number of iterations was set to 20. It can be seen that traditional genetic algorithms consume a lot of time when solving large-scale integer programming problems due to their large search space, slow iteration speed, and high iteration speed. In contrast, under similar solution quality conditions, the proposed algorithm achieves a time cost of only 1.3 seconds for 120 tasks, a reduction of over 100 times.

[0064] To verify the optimality of the proposed method, this invention also presents a performance comparison of the task satisfaction rate between the proposed multi-beam resource scheduling algorithm and existing multi-beam resource scheduling algorithms based on a "first-come, first-served" greedy strategy on a single-channel, low-Earth orbit task set. The relevant results are as follows: Figure 4 As shown. To control the problem size, the scheduling cycle started at 23:59:59 on March 3, 2024, and ended at 11:59:59 on March 4, 2024. It can be seen that the task satisfaction rate of the greedy algorithm decreases significantly with the increase in the number of tasks. Specifically, when the number of tasks is 500, the proposed multi-beam scheduling algorithm improves the task satisfaction rate by more than 10% compared to the greedy strategy.

[0065] Example 3 To facilitate understanding, this embodiment also provides a simpler and more intuitive example.

[0066] Assuming a scheduling period of 4 minutes and a number of satellite missions of 6, the vectorized representation of the corresponding visible arc segments is shown in the table below: Table 1. Vectorized representation of the corresponding visible arc segments

[0067] Under single-channel conditions, the optimal solution of the proposed algorithm is:

[0068] There are 4 tasks assigned, with a task satisfaction rate of approximately 66.7%. It is worth noting that the optimal solution is not necessarily unique, but the optimal value is unique.

[0069] Under dual-channel conditions, the optimal solution of the proposed algorithm is:

[0070] The corresponding task satisfaction rate reached 100%.

[0071] The embodiments described above merely illustrate specific implementation methods of this application, and while the descriptions are detailed and specific, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the technical solution of this application, and these modifications and improvements all fall within the scope of protection of this application.

[0072] This background section is provided to generally present the context of the invention. The work of the currently named inventors, the work to the extent described in this background section, and aspects of this section that did not constitute prior art at the time of application are neither expressly nor impliedly acknowledged as prior art to the invention.

Claims

1. A method for scheduling phased array resources across the entire airspace, characterized in that, include: Step S1: Data preprocessing; scheduling period By time interval Divided into Each time slice; converts the visible arc information of each satellite into a length of... binary vectors ; Step S2: Objective function modeling; maximizing the task satisfaction rate is equivalent to maximizing the sum of the elements of the decision variable matrix. ;in This indicates the number of satellites participating in the mission planning, and its value is equal to the number of satellite missions. Indicates satellite Choose in Each time chip executes a task; Step S3: Constraint Modeling; Under the premise of satisfying satellite visibility constraints, the activation conflict of the phased array surface in the entire space domain is modeled as a binary conflict matrix, and the core constraint of the integer programming model is that at most one of the conflicting tasks at the same time can be executed, thereby ensuring that there is no phased array surface resource conflict in any time chip of the scheduling scheme. Step S4: Solve the objective function as a 0-1 integer programming problem to obtain the optimal scheduling scheme.

2. The all-space phased array resource scheduling method according to claim 1, characterized in that, Time interval It is equal to the minimum visible arc length of the satellite.

3. The all-space phased array resource scheduling method according to claim 1, characterized in that, In step S2, the task satisfaction rate is defined as the ratio of the number of successfully planned satellite missions to the total number of missions.

4. The all-space phased array resource scheduling method according to claim 1, characterized in that, Step S3 includes: Constraint 1: Ensure that the time chip selected by the satellite is part of its visible arc; Constraint 2: Ensure that the time chip selected by the satellite is not part of its invisible arc segment; Constraint 3: Consider conflict constraints on the active surface of the phased array.

5. The all-space phased array resource scheduling method according to claim 4, characterized in that, Constraint 1 is expressed as follows: 。 6. The all-space phased array resource scheduling method according to claim 5, characterized in that, Constraint 2 is expressed as follows: in: 。 7. The all-space phased array resource scheduling method according to claim 6, characterized in that, Constraint 3 is expressed as follows: For time slices Using the conflict adjacency matrix Record this time slice The conflict situation of array elements between different tasks; activating array surface conflict can be modeled as .

8. The all-space phased array resource scheduling method according to claim 7, characterized in that, In step S4, the all-space phased array resource scheduling problem with the objective of maximizing the task satisfaction rate can be modeled as the following 0-1 integer programming problem: The 0-1 integer programming problem is solved using the branch-and-cut method or by using a commercial solver.

9. An electronic device, characterized in that, include: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores instructions executable by the at least one processor, which executes the instructions stored in the memory to perform the method as described in any one of claims 1-8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store instructions that, when executed, cause the method as described in any one of claims 1-8 to be implemented.

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