Timing system with tamper function

Abstract

The invention discloses a timing system with an anti-disassembly function, and relates to the field of coach car data collection, and the system comprises an anti-disassembly label which is installed in a coach car; the anti-tamper detection module is installed in close contact with the anti-tamper tag, and the anti-tamper detection module internally comprises an anti-tamper tag read-write circuit so as to obtain state data of the anti-tamper tag; and the timing equipment host is connected with the anti-disassembly module and is used for periodically reading the label state data so as to automatically trigger an anti-disassembly response when the state of the label state data is lost or the communication is interrupted. The tamper detection module is physically attached to the label, label information is continuously read and written, the host polls and verifies the state regularly, once the label leaves, is disconnected or is shielded, abnormity can be detected, response is timely and accurate, and the problem of misinformation caused by physical false triggering is avoided.

Description

Technical Field

[0001] This specification relates to the field of training vehicle data collection, and more specifically, to a timing system with anti-tampering function. Background Technology

[0002] In current training vehicle timing equipment management systems, to prevent cheating or circumventing regulations, regulatory authorities typically require timing equipment to possess a certain level of tamper resistance. Existing tamper resistance technologies mostly rely on methods such as casing opening / closing detection, reed sensors, or photoelectric sensors. Once the detection equipment is illegally disassembled or powered off, an alarm is triggered or abnormal data is uploaded. However, these tamper resistance methods based on physical structural changes or power status monitoring have the following drawbacks: 1. High false alarm rate: The device may falsely trigger anti-tamper events under vibration or environmental interference, affecting normal use.

[0003] 2. High risk of bypassing: Attackers can bypass the anti-tamper detection by replacing the host, blocking sensor signals, or simulating normal state signals.

[0004] 3. High degree of unverifiability: Some solutions lack the ability to identify unique labels, making it impossible to accurately determine whether it is the original equipment or whether hardware replacement has occurred.

[0005] 4. Complex structure and installation: Conventional mechanical anti-tamper structures require molds for the main unit casing or special supporting parts, resulting in high installation and maintenance costs.

[0006] Therefore, there is an urgent need for a more stable, intelligent, and traceable anti-tampering detection method to meet the time-based monitoring requirements of the new generation of training vehicles. Summary of the Invention

[0007] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0008] In a first aspect, the present invention proposes a timing system with tamper-proof function, the method comprising: Tamper-proof tags are installed inside the training vehicle; The tamper detection module is installed in close contact with the aforementioned tamper label. The tamper detection module includes a tamper label reading and writing circuit to obtain the status data of the aforementioned tamper label. The timing device host is connected to the aforementioned anti-tamper module and periodically reads the aforementioned tag status data to automatically trigger an anti-tamper response when the aforementioned tag status data is lost or communication is interrupted.

[0009] In one feasible implementation, it further includes: The host lock module is used to immediately lock the host function based on the above-mentioned anti-tamper response and upload the device serial number and corresponding license plate information to the regulatory backend.

[0010] In one feasible implementation, the aforementioned tamper-evident label is fixed to the inner side of the upper edge of the vehicle's windshield by adhesive.

[0011] In one feasible implementation, the aforementioned tamper-evident tag uses an electronic tag compatible with NFC or F08 chips and has a unique ID number.

[0012] In one feasible implementation, the tamper-evident tag reading and writing circuit includes a radio frequency tuning network composed of inductors and capacitors, which is connected to an external antenna interface for connecting the tamper-evident tag.

[0013] In one feasible implementation, the aforementioned tamper detection module includes a main control chip, and the pins of the main control chip include an RFID transmitter, a receiver, a serial communication terminal, and a crystal oscillator input terminal.

[0014] In one feasible implementation, the main control chip communicates with the timing device host via a TTL level serial communication protocol through a serial communication terminal.

[0015] In one feasible implementation, the aforementioned anti-tamper detection module includes a crystal oscillator circuit, which includes a crystal oscillator and two matching capacitors. The two matching capacitors are respectively connected between the OSCIN and OSCOUT pins and ground to provide a stable clock for the aforementioned main control chip.

[0016] In one feasible implementation, an adjustable capacitor array and a current-limiting resistor are provided between the main control chip and the external antenna to adjust the antenna impedance matching and protect the radio frequency path.

[0017] In one feasible implementation, the aforementioned main control chip is a WS1850S chip.

[0018] In summary, this system uses RFID tags with unique IDs (such as NFC or F08) affixed to the inside of the vehicle's windshield. These tags cannot be copied or replaced, eliminating the possibility of evading supervision by replacing the host unit and achieving a "one vehicle, one tag" binding mechanism. The tamper detection module is physically attached to the tag, continuously reading and writing tag information. The host unit periodically polls to verify the status. If the tag is removed, disconnected, or obscured, an anomaly is detected, with a timely and accurate response, avoiding false alarms caused by physical mis-triggers. The module internally uses a radio frequency tuned network composed of inductors and capacitors, combined with current-limiting resistors and an adjustable capacitor array, effectively improving the impedance matching between the read / write antenna and the main control chip, ensuring stable communication and strong anti-interference capabilities. Communication between the tamper module and the host unit uses the TTL protocol, which is clear, stable, and reliable, facilitating rapid integration by equipment manufacturers into existing timing systems. Once an tamper anomaly is detected, the system immediately locks the host unit's functions and uploads the device serial number and vehicle license plate information to the monitoring backend, achieving a complete tamper prevention closed loop from device to platform, improving monitoring efficiency and traceability.

[0019] The timing system with anti-tamper function proposed in this invention, other advantages, objectives and features of this invention will be partly apparent from the following description, and partly understood by those skilled in the art through study and practice of this invention. Attached Figure Description

[0020] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit this specification. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a structural schematic diagram of a timing system with anti-tamper function provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the circuit structure of an anti-tamper detection module provided in an embodiment of the present invention; Figure 3 A schematic diagram of a crystal oscillator circuit that provides a stable clock signal to a main control chip is provided for an embodiment of the present invention. Figure 4 This is a schematic diagram of an antenna tuning network circuit structure for an anti-tamper tag reading and writing circuit in an anti-tamper detection module, provided as an embodiment of the present invention. Detailed Implementation

[0021] The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. The technical solutions of the embodiments of this invention will now be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them.

[0022] Please see Figure 1 This is a flowchart illustrating a timing system with anti-tamper function provided by an embodiment of the present invention, which may specifically include: Anti-tamper label 10 is installed inside the training vehicle; The tamper detection module 20 is installed in close contact with the tamper label. The tamper detection module includes a tamper label reading and writing circuit to obtain the status data of the tamper label. The timing device host 30 is connected to the anti-tamper module and periodically reads the tag status data so as to automatically trigger the anti-tamper response when the tag status data is lost or communication is interrupted.

[0023] For example, a timing system with tamper protection includes three main components: an tamper protection tag 10, an tamper protection detection module 20, and a timing device host 30. The three components work together to achieve real-time detection and response to abnormal behaviors such as disassembly, disconnection, or replacement of the device.

[0024] Specifically, the tamper-evident tag 10 is an electronic identification tag, which can be an RFID tag compatible with NFC or F08 chips, and has a globally unique ID code. The tag is installed inside the training vehicle by adhesive bonding, preferably on the inner side of the upper edge of the windshield, ensuring relative fixation and signal stability between the tag and the external reading device without affecting the driver's vision.

[0025] The tamper detection module 20 is attached above the tamper-proof tag 10 to ensure continuous reading of tag information. This module integrates an tamper-proof tag reading / writing circuit, including an RF tuning network composed of inductors, capacitors, and other components. This tuning network connects to an external antenna interface, and impedance matching and RF signal protection are achieved through adjusting capacitors and current-limiting resistors. Furthermore, the module incorporates a built-in main control chip (such as the WS1850S), whose pins include an RFID transmitter, receiver, serial communication port, and crystal oscillator input, supporting the TTL serial communication protocol. The module's crystal oscillator circuit includes a 27.12MHz crystal and two 18pF matching capacitors, providing a stable clock source.

[0026] The timing device host 30 is connected to the anti-tamper detection module 20 via a TTL serial port. The host continuously sends tag status reading requests to the anti-tamper module at a preset time period (e.g., once per second), and receives and verifies whether the returned data is normal. If the tag status data is detected to be abnormal (e.g., missing ID number, communication interruption, data verification failure, etc.), the host will immediately trigger the anti-tamper response mechanism, including but not limited to: (1) locking the device function to prevent continued use; (2) recording the current device serial number and vehicle license plate information; (3) uploading the abnormal status to the regulatory backend server in real time for subsequent verification and accountability.

[0027] In summary, this system uses RFID tags with unique IDs (such as NFC or F08) affixed to the inside of the vehicle's windshield. These tags cannot be copied or replaced, eliminating the possibility of evading supervision by replacing the host unit and achieving a "one vehicle, one tag" binding mechanism. The tamper detection module is physically attached to the tag, continuously reading and writing tag information. The host unit periodically polls to verify the status. If the tag is removed, disconnected, or obscured, an anomaly is detected, with a timely and accurate response, avoiding false alarms caused by physical mis-triggers. The module internally uses a radio frequency tuned network composed of inductors and capacitors, combined with current-limiting resistors and an adjustable capacitor array, effectively improving the impedance matching between the read / write antenna and the main control chip, ensuring stable communication and strong anti-interference capabilities. Communication between the tamper module and the host unit uses the TTL protocol, which is clear, stable, and reliable, facilitating rapid integration by equipment manufacturers into existing timing systems. Once an tamper anomaly is detected, the system immediately locks the host unit's functions and uploads the device serial number and vehicle license plate information to the monitoring backend, achieving a complete tamper prevention closed loop from device to platform, improving monitoring efficiency and traceability.

[0028] In one feasible implementation, it further includes: The host lock module is used to immediately lock the host function based on the above-mentioned anti-tamper response and upload the device serial number and corresponding license plate information to the regulatory backend.

[0029] For example, in addition to tamper-proof tags, tamper-proof detection modules, and timing device hosts, a host lock module is further introduced to enhance the system's control capabilities and regulatory loop when a risk of disassembly is detected.

[0030] Specifically, the main lock module is integrated inside the timing device main unit or connected to the main unit as an external control unit. Its main function is to immediately perform the device locking operation after receiving the anti-tamper response signal from the anti-tamper detection module and complete the information synchronization with the background monitoring platform.

[0031] When the anti-tamper detection module detects any of the following situations through the tag reading and writing circuit, such as: tag ID reading failure; tag removal or signal abnormality; data line disconnection; tag data abnormality exceeding the set number, the module will send an "anti-tamper trigger" signal to the timing host.

[0032] At this time, the host lock module will immediately perform the following operations: Lock host function: The host enters a locked state, suspends all core functions (such as timing recording, data uploading, interface operation, etc.), and displays a warning message such as "Device anti-tamper lock, please contact the administrator" on the display screen to prevent continued use for teaching or examinations.

[0033] Generate alarm data packets: The host calls the system information interface to automatically obtain the unique serial number (Device ID) of the current device and the license plate number of the bound vehicle, and packages them to generate alarm data.

[0034] Uploaded to the regulatory backend: The host computer uploads the above data to the platform's regulatory server in real time via a 4G / 5G communication module or a Wi-Fi module. The backend can then quickly perform location tracking, personnel investigation, and fault registration to ensure the compliance of training vehicle management.

[0035] The host lock module introduced in this embodiment enables the system to respond and report immediately in the event of unauthorized removal, tag replacement, or communication interruption, effectively preventing unauthorized use and human interference. This further enhances the stability of the device-vehicle binding relationship and the timeliness of data monitoring. This mechanism offers advantages such as rapid linkage, data traceability, and a compliant closed loop, making it a crucial security measure to ensure the reliable operation of training vehicle timing equipment.

[0036] In one feasible implementation, the aforementioned tamper-evident label is fixed to the inner side of the upper edge of the vehicle's windshield by adhesive.

[0037] In one feasible implementation, the aforementioned tamper-evident tag uses an electronic tag compatible with NFC or F08 chips and has a unique ID number.

[0038] For example, the installation location and label type of the tamper-evident tag are specially designed to ensure that it has good tamper resistance and uniqueness, thereby effectively achieving physical binding between the device and the vehicle.

[0039] Specifically, the tamper-evident label is affixed and fixed to the inside of the upper edge of the vehicle's windshield, a location that offers several advantages: Difficult to reach and with a clear view: The upper edge of the windshield is not easily touched by the driver or passengers, while the label information can be easily read through external or internal devices; Once removed, it is difficult to restore: Once the label is torn off or transferred, the adhesiveness and surface features will be irreversibly damaged, thus achieving physical anti-transfer and anti-counterfeiting characteristics; The fixing method is simple and reliable: labels are attached by means of high-adhesion adhesive or custom card slots, which is convenient for installation and mass deployment, and is suitable for large-scale application of training vehicle timing systems.

[0040] In addition, to achieve unique device identification and security verification, this embodiment uses an electronic tag compatible with NFC or F08 chips as an tamper-proof tag chip: The F08 chip is a contactless IC card chip widely used in access control, transportation, and identity recognition, and it has good stability and versatility. The tag contains a unique ID number that cannot be tampered with, ensuring that each vehicle has a unique ID number and that the tag is associated with a vehicle one by one. It is compatible with the NFC (Near Field Communication) standard and can be quickly identified by standard NFC readers and writers, supporting wireless reading distances of 1 to 5 centimeters; it has passive power supply characteristics, requiring no external power source and is easy to maintain.

[0041] In summary, this embodiment effectively ensures the binding security of the timing device and the vehicle by fixing the tamper-evident tag to the inner side of the upper edge of the windshield and using an NFC / F08 electronic tag with a unique ID number. This prevents the evasion of supervision through tag transfer, counterfeiting, or other means, and strongly supports the reliable operation of the tamper-evident system.

[0042] In one feasible implementation, the tamper-evident tag reading and writing circuit includes a radio frequency tuning network composed of inductors and capacitors, which is connected to an external antenna interface for connecting the tamper-evident tag.

[0043] For example, in order to achieve effective identification and communication of tamper-evident tags, the tamper detection module integrates a set of tamper-evident tag reading and writing circuits. The core structure of this circuit includes a radio frequency tuning network composed of inductors and capacitors, which is used to achieve radio frequency signal matching, modulation and reception in the 13.56MHz band, thereby completing the short-range reading and writing operation of RFID tamper-evident tags.

[0044] Specifically, the radio frequency tuning network includes several inductor (L) and capacitor (C) elements that together form an LC resonant circuit. Through precise selection, its operating frequency is locked at 13.56MHz, the standard frequency for RFID systems, to ensure matching with the operating frequency of tamper-evident tags (such as NFC / F08 chip tags).

[0045] The circuit works as follows: Transmitter section: The main control chip outputs a modulated signal through the transmitter, which is then transmitted to the external antenna interface via a resonant circuit constructed by the transmitting inductor and the parallel matching capacitor in the tuning network. This generates a high-frequency alternating magnetic field to activate the tamper-evident tag.

[0046] Receiving section: After the tamper-evident tag responds to the excitation signal, it will return its ID information in a modulated manner. This signal is coupled to the receiving path in the tuning network through the same antenna, and then after filtering and amplification, the main control chip completes demodulation and data reading.

[0047] External antenna interface: The tuning network is connected to the external RFID antenna (usually a surface-mount coil) via an interface, such as a three-pin connector or PCB soldering interface, to ensure complete signal transmission and good matching performance.

[0048] Current limiting protection and matching adjustment: To enhance system stability, the circuit is also designed with current limiting resistors and adjustable capacitor arrays to adjust impedance matching and suppress harmonic interference, thereby improving the tag reading success rate.

[0049] Through the above structure and working method, the tamper-proof tag reading and writing circuit in this embodiment can achieve efficient, stable, and short-range non-contact reading of tamper-proof tags fixedly installed on the inside of the vehicle windshield. It is simple and compact in structure, and meets the actual needs of fast response, low power consumption and short-range communication in performance. It is the basic support module for the normal operation of the entire tamper-proof system.

[0050] In one feasible implementation, the aforementioned tamper detection module includes a main control chip, and the pins of the main control chip include an RFID transmitter, a receiver, a serial communication terminal, and a crystal oscillator input terminal.

[0051] For example, the tamper detection module integrates a main control chip to control the radio frequency reading and writing of the tamper tags and to communicate with the timing host. The main control chip's pin design includes an RFID transmitter, an RFID receiver, a serial communication port, and a crystal oscillator input. These pins work together to ensure the stable operation of the entire tamper detection process.

[0052] The RFID transmitter and receiver are used to control the transmission and reception of radio frequency signals, respectively. The main control chip excites a high-frequency magnetic field signal (such as 13.56MHz) to an external antenna through the RFID transmitter to activate the tamper-proof electronic tag installed in the training vehicle; the RFID receiver is responsible for receiving the response signal returned by the tag and demodulating it into a recognizable data format to determine whether the tag exists, whether the ID matches, or whether it has been illegally obscured or removed.

[0053] The serial communication ports (typically including TXD and RXD) are used to transmit the above parsing results and status information to the external timing device host via a TTL level serial communication protocol. This communication process is periodic; the main control chip can be set to report the tag status once per second, and the host determines whether the system is in normal working condition based on the received data.

[0054] To ensure stable timing control of the entire system, the main control chip is also connected to an external crystal oscillator circuit via crystal oscillator input terminals (OSCIN and OSCOUT). The crystal oscillator circuit consists of a crystal oscillator and two matching capacitors, providing an accurate and stable clock source. This stable clock signal not only ensures the modulation and demodulation accuracy of the RF communication module but also maintains the logical accuracy of the main control chip during data communication and status judgment.

[0055] In summary, this main control chip, through its integrated RF interface, serial communication interface, and clock interface, enables high-frequency detection of tag presence, status reporting, and disconnection identification within a small embedded module. It serves as the core hardware control unit for implementing the tamper-proof function of the timing device. This design offers advantages such as high integration, fast response speed, and stable communication, making it suitable for training vehicle timing management systems with high requirements for tamper-proof integrity.

[0056] In one feasible implementation, the main control chip communicates with the timing device host via a TTL level serial communication protocol through a serial communication terminal.

[0057] For example, in one feasible implementation, in order to achieve stable data communication between the tamper detection module and the timing device host, the main control chip establishes a communication connection with the timing device host through its serial communication terminal (usually including TXD and RXD pins), and uses the TTL (Transistor-Transistor Logic) level serial communication protocol for data transmission.

[0058] The core idea of ​​this implementation is to leverage the lightweight, low-power, and fast-response characteristics of the TTL serial communication protocol to ensure that the main control chip can quickly and directly complete data interaction with the host without complex intermediate protocol conversion. The TTL level protocol typically uses 0V to represent logic "low" and 5V or 3.3V to represent logic "high," making it very suitable for short-distance point-to-point communication in embedded systems.

[0059] In the specific implementation, the main control chip sends the status data of the tamper-evident tag (such as whether the tag exists, whether the reading was successful, tag ID value, etc.) to the host in real time through the TXD pin; the host receives the data through the RXD pin and performs status parsing. The communication process is a single-wire asynchronous half-duplex or full-duplex mode, and the rate is usually set to 9600 or 115200 bps, configured according to the system response requirements.

[0060] To enhance communication stability and anti-interference capabilities, the serial connection between the main control chip and the host is typically transmitted via shielded cable, with the cable length kept within a reasonable range to prevent signal attenuation or stray interference. Simultaneously, to prevent communication failures caused by level incompatibility, a level matching circuit can be designed into the circuitry, or jumpers can be configured to support both 5V and 3.3V TTL level interface standards.

[0061] This communication mechanism enables the anti-tamper module to report abnormal states (such as tag disconnection, tag removal, or RF reading failure) to the host in a very short time. The host can then quickly trigger the anti-tamper response mechanism (such as locking the system or reporting to the backend), effectively preventing the risk of cheating caused by human disassembly or replacement of devices. This solution has a clear structure, low power consumption, simple implementation, and high stability, making it highly suitable for embedded anti-tamper system design in intelligent timing and monitoring scenarios.

[0062] In one feasible implementation, the aforementioned anti-tamper detection module includes a crystal oscillator circuit, which includes a crystal oscillator and two matching capacitors. The two matching capacitors are respectively connected between the OSCIN and OSCOUT pins and ground to provide a stable clock for the aforementioned main control chip.

[0063] For example, to ensure the timing logic and communication accuracy of the main control chip in the tamper detection module, the tamper detection module integrates a crystal oscillator circuit to provide a stable and accurate operating clock signal for the main control chip.

[0064] The core of this crystal oscillator circuit includes a crystal oscillator and two matching capacitors (typically ranging from a few picofarads to tens of picofarads). One end of the crystal oscillator is connected to the OSCIN (oscillation input) pin of the main control chip, and the other end is connected to the OSCOUT (oscillation output) pin; the two matching capacitors are connected in parallel between OSCIN and ground, and OSCOUT and ground, respectively, forming a typical parallel resonant circuit.

[0065] Specifically, the crystal oscillator begins oscillating after the main control chip is powered on, generating a reference clock signal with a fixed frequency (such as 8MHz, 12MHz, 16MHz, etc.). Two matching capacitors are used to adjust the stability of the oscillation frequency and the startup performance, ensuring that the crystal oscillator can quickly enter the steady-state oscillation mode and maintain low phase noise and low jitter of the clock signal. This circuit configuration is common in microcontroller systems with high timing requirements.

[0066] In this embodiment, a stable clock signal is fundamental for the main control chip to accurately time, precisely send serial port data, and periodically poll the tag status. If the crystal oscillator circuit fails, the main control chip will not function properly, thus affecting the entire tamper detection module's functionality. Therefore, the crystal device used should have high reliability and good temperature stability, and the matching capacitor must be selected according to the chip datasheet's recommended values ​​to avoid excessive frequency deviation or startup failure.

[0067] In one feasible implementation, an adjustable capacitor array and a current-limiting resistor are provided between the main control chip and the external antenna to adjust the antenna impedance matching and protect the radio frequency path.

[0068] For example, to improve the communication reliability and radio frequency path security of tamper-evident tag identification, an adjustable capacitor array and a current-limiting resistor are provided between the main control chip and the external antenna to achieve dynamic matching and adjustment of the antenna impedance and provide circuit protection functions.

[0069] Specifically, as a key component of tamper-evident tag RFID, the external antenna's impedance characteristics must be well matched with the input and output impedance (typically 50Ω) of the RF transceiver module within the main control chip to achieve efficient energy coupling and data transmission. In this embodiment, the adjustable capacitor array located on the antenna path consists of multiple capacitors connected in parallel or series. The combined values ​​are adjusted manually using jumpers or digital switches to achieve fine impedance tuning.

[0070] The adjustment functions of this capacitor array include: compensating for the impact of antenna structure, PCB layout, or external environment on impedance; preventing reflected signal enhancement, reducing standing waves, and improving signal quality; and increasing tag reading distance and response speed.

[0071] Meanwhile, a current-limiting resistor is also set between the main control chip and the antenna. The function of this resistor is to prevent the radio frequency path from being damaged by transient high current surges (such as electrostatic discharge and surges); to limit the current amplitude and protect the radio frequency output port of the main control chip; and to help filter out some high-frequency spurious components and reduce radio frequency interference.

[0072] Through the coordinated configuration of the adjustable capacitor array and current-limiting resistor described above, this embodiment not only effectively improves the stability and identification efficiency of tamper-proof tag communication, but also significantly enhances the system's fault tolerance to abnormal electrical events, providing electrical support and guarantee for the long-term stable operation of the tamper-proof detection module.

[0073] In one feasible implementation, the aforementioned main control chip is a WS1850S chip.

[0074] For example, the main control chip is the WS1850S RFID dedicated chip. This chip integrates a high-performance RFID radio frequency transceiver module, a low-power MCU control unit, and various peripheral interfaces. It is particularly suitable for scenarios involving real-time detection and communication of electronic tags, and has advantages such as low cost, high stability, and high integration.

[0075] The WS1850S chip mainly functions in the following aspects: RF Communication Function: The WS1850S integrates a high-sensitivity RFID read / write module, supporting the reading of NFC tags in the 13.56MHz band and electronic tags compatible with the F08 protocol. It boasts excellent anti-interference capabilities and multi-tag recognition capabilities. Through its RF transmitter (TX) and receiver (RX) pins, it can be connected to an external tuning circuit and antenna to achieve stable tag status reading.

[0076] Main control and logic processing: The chip integrates a low-power microcontroller unit (MCU) that can execute periodic tag status queries, status judgment logic, and serial communication protocol control logic. Through programmable control, the chip can achieve functions such as stable data acquisition, data loss detection, and CRC verification, providing underlying data support for anti-tampering mechanisms.

[0077] Communication Interface: The WS1850S supports TTL level serial communication (UART) to achieve real-time reporting of tag status with the timing device host via the serial communication terminal. After each successful reading of tag information, the chip formats the tag ID and status data and sends it to the host. The host then parses the data to determine whether the device is in a normal installation state.

[0078] Clock stability: To ensure the time accuracy of the system, the WS1850S requires an external crystal oscillator circuit. This circuit includes a crystal oscillator (typically 13.56MHz) and two matching capacitors, which are connected to the chip's OSCIN and OSCOUT pins respectively, providing a highly stable clock source for the internal MCU.

[0079] By using the WS1850S chip as the core controller of the tamper detection module, it is compatible with multiple electronic tag protocols and has strong scalability; modular packaging makes it easy to embed into various timing devices; stable and reliable serial communication facilitates integration with the host system; abundant internal resources reduce the complexity of external circuits; and it supports low-power operation mode, which is conducive to long-term continuous detection.

[0080] In summary, the WS1850S chip, as the main control chip in this embodiment, significantly improves the overall performance of the entire anti-tamper detection module in terms of reading efficiency, response speed, and system stability, forming a key foundation for the hardware design of this solution.

[0081] like Figure 2 As shown, this embodiment provides a circuit design for an anti-tamper detection module based on the WS1850S chip. This module, as a core component of a timing system with anti-tamper functionality, possesses functions such as RFID tag status reading, serial communication, and clock management, effectively enabling real-time monitoring and alarm response of the anti-tamper status inside the training vehicle. The circuit revolves around the main control chip WS1850S, and its main functional modules include: 1. Power Supply Filtering and Power Supply Section: The chip operates at 3.3V. Power supply pins include PVDD, DVDD, AVDD, and VMID. These pins are grounded on both sides via decoupling capacitors (such as C3, C4, C6, and C7) to filter out power supply noise and ensure stable operation of the main control chip. Specifically: C3, C4, and C6 are 100nF ceramic capacitors; C7 is a larger capacitance capacitor (capacity not specified) used to enhance transient current suppression.

[0082] 2. RFID Radio Frequency Interface Configuration: The chip's TX1, TX2, and RX pins correspond to the RF transmitter and receiver, respectively, and are connected to an external tuning network (not shown in this diagram) for signal excitation and response reception of external tamper-evident tags. TX1 and TX2 output differential excitation signals through pins 10 and 11, respectively, while RX (pin 8) receives the response signal reflected back from the antenna. This RF path, consisting of a downstream tuning circuit and an antenna system, is capable of identifying the status of electronic tags attached to the windshield.

[0083] 3. Serial Communication Interface: The chip's TXD and RXD pins (pins 12 and 13) are used for TTL serial communication with the timing device's host. The communication protocol adopts asynchronous serial mode, using a standard 3.3V level to enable the host to periodically poll the tamper-evident tag status. When the tag is removed or the signal is interrupted, the module will send an tamper trigger flag to the host, triggering the host to enter a locked state and report the incident.

[0084] 4. Reset and Control Signals: The chip's reset pin NRSTPD (pin 5) is connected to 3.3V via a pull-up resistor R1 (10kΩ), and can also receive control signals through an external TP8 interface, supporting manual or programmed system reset. MFIN and MFOUT are user-defined interrupt inputs / outputs, which can be expanded for signal input or interrupt control.

[0085] 5. Clock Crystal Interface: OSCIN and OSCOUT (pins 31 and 32) are connected to an external 27.12MHz crystal oscillator (see other attached diagrams), and are connected in series with matching capacitors C9 and C10 to provide a stable main frequency clock to drive the internal logic and communication modules of the chip.

[0086] 6. SPI Interface and Expansion Pins: The SPI2 interface (MISO, MOSI, SCK, NSS) serves as an optional expansion communication bus, interconnecting with the host or upper-level module to facilitate future system expansion with additional functions such as wireless modules and identity verification modules.

[0087] 7. Tag receiving buffer: In the receiving filtering path formed by the RX port, TP5, and C8, C8 (15pF) serves as a bypass filter capacitor, which can suppress high-frequency interference and improve receiving accuracy.

[0088] This circuit integrates RFID, serial communication, and a high-precision clock system to form a stable and reliable tamper detection subsystem. Electronic tags installed inside the windshield of the training vehicle are periodically identified and read by this module. Upon tag removal or interference / obstruction, the system immediately detects the communication anomaly and reports the status to the timing host via serial port. The host then triggers the host lock module to initiate an tamper response. This compact and feature-rich design is suitable for embedding in various vehicle monitoring and training terminals, demonstrating good practicality and promotional value.

[0089] like Figure 3 As shown, this embodiment provides a crystal oscillator circuit design that provides a stable clock signal to the main control chip, forming part of the anti-tamper detection module in a timing system with anti-tamper function, mainly used to drive the high-precision operation of the internal logic and RFID radio frequency communication module.

[0090] like Figure 3As shown, the crystal oscillator circuit includes: a quartz crystal oscillator X2 with an operating frequency of 27.12MHz, a type of industrial band crystal commonly used in RFID systems; two matching capacitors C9 and C10, both 18pF / 50V, connected from the two ends of the crystal to ground (GND), forming the load capacitance of the crystal; pin 4 (input) of the crystal oscillator connected to the OSCIN pin of the main control chip, and pin 2 (output) of the crystal oscillator connected to the OSCOUT pin of the main control chip; capacitor C9 is connected between OSCIN and ground, and capacitor C10 is connected between OSCOUT and ground.

[0091] This tamper detection module can operate independently without an external master clock input, thanks to the crystal oscillator circuit, providing greater clock independence and system stability. The use of an industrial-grade 27.12 MHz crystal ensures frequency consistency between RF modulation and tag communication, thereby improving read / write reliability and anti-interference capabilities, meeting the requirements for electronic tag status monitoring under long-term, high-frequency operation.

[0092] This circuit has a simple structure and strong stability, and is suitable for RFID-based embedded anti-tamper systems. It is one of the key auxiliary circuits in this patented technical solution.

[0093] like Figure 4 As shown, this embodiment provides an antenna tuning network circuit structure for the tamper-proof tag reading and writing circuit in an tamper-proof detection module. It possesses good impedance matching capability and signal coupling characteristics, enabling stable reading and writing of NFC / F08 and other types of electronic tags. The circuit includes: 1. Dual-channel RF signal input: Two RFID transmitter input terminals, RFID_TX1 and RFID_TX2, are connected in series with inductors L1 and L2 (both 1μH) to provide impedance rise and preliminary filtering. The input signal is then connected to two symmetrical parallel capacitor arrays: TX1 channel: C12, C13 (120pF, 36pF); TX2 channel: C11, C14 (120pF, 36pF), together forming the primary resonant tuning circuit.

[0094] 2. Intermediate Resonant Filtering and Matching Unit: After the signal enters the intermediate section through nodes TP1 and TP2, it continues to build a high-frequency bandpass filter through C15, C16 (100pF), C17, and C18 (15pF), and is connected to TP3 and TP4 as debugging probe ports, which can be used for oscilloscope observation or RF power analysis.

[0095] 3. End Antenna Connection and Current Limiting Protection: Capacitors C19 and C20 (15pF, FNC is adjustable) and resistors R6 and R7 (0.33Ω) constitute the last stage impedance adjustment and current limiting module, which is connected to the external antenna connector through connector CN1 (A2501WV-3P). Resistors R13, R14, and R8 are set as 0Ω jumper resistors, used for grounding guidance and loop closure control according to the specific structural location. GND is set at multiple nodes of the signal loop to ensure stable closure of the RF loop.

[0096] This circuit employs a refined capacitor network design, coupled with a small-value inductor, to achieve tuning and impedance matching of the RFID tag's operating frequency band. It can operate in the 13.56MHz band, ensuring that the RF signal output from the main control chip achieves minimum standing wave ratio (SWR) at the antenna end, reducing power reflection and improving tag identification distance and stability. Simultaneously, the design of the current-limiting resistor and debugging port ensures the circuit's maintainability and protection against abnormal voltages.

[0097] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A timing system with anti-tamper function, characterized in that, include: Tamper-proof tags are installed inside the training vehicle; The tamper detection module is installed in close contact with the tamper label. The tamper detection module includes a tamper label reading and writing circuit to obtain the status data of the tamper label. The timing device host is connected to the anti-tamper module and periodically reads the tag status data to automatically trigger an anti-tamper response when the tag status data is lost or communication is interrupted.

2. The timing system with anti-tamper function according to claim 1, characterized in that, Also includes: The host lock module is used to immediately lock the host function based on the anti-tamper response and upload the device serial number and corresponding license plate information to the monitoring backend.

3. The timing system with anti-tamper function according to claim 1, characterized in that, The tamper-evident label is fixed to the inner side of the upper edge of the vehicle's windshield by adhesive.

4. The timing system with anti-tamper function according to claim 1, characterized in that, The tamper-evident tag uses an electronic tag compatible with NFC or F08 chips and has a unique ID number.

5. The timing system with anti-tamper function according to claim 1, characterized in that, The tamper-evident tag reading and writing circuit includes a radio frequency tuning network composed of inductors and capacitors. The network is connected to an external antenna interface for connecting the tamper-evident tag.

6. The timing system with anti-tamper function according to claim 5, characterized in that, The tamper detection module includes a main control chip, and the pins of the main control chip include an RFID transmitter, a receiver, a serial communication port, and a crystal oscillator input.

7. The timing system with anti-tamper function according to claim 6, characterized in that, The main control chip communicates with the timing device host via a TTL level serial communication protocol through a serial communication terminal.

8. The timing system with anti-tamper function according to claim 6, characterized in that, The tamper detection module includes a crystal oscillator circuit, which includes a crystal oscillator and two matching capacitors. The two matching capacitors are respectively connected between the OSCIN and OSCOUT pins and ground to provide a stable clock for the main control chip.

9. The timing system with anti-tamper function according to claim 6, characterized in that, An adjustable capacitor array and a current-limiting resistor are provided between the main control chip and the external antenna to adjust the antenna impedance matching and protect the radio frequency path.

10. The timing system with anti-tamper function according to any one of claims 6 to 9, characterized in that, The main control chip is a WS1850S chip.

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