Intermediary connection board, semiconductor device and electronic apparatus
By introducing base segments and adjustment segments into the wiring layer of the intermediate connection board, the problem of signal quality degradation caused by constant signal line width is solved, and efficient signal transmission and improved stability are achieved.
Patent Information
- Application Number
- CN202511404240.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-28
- Publication Date
- 2025-11-21
AI Technical Summary
The constant width of the signal lines within the interfacing board causes the signal transmission quality to decrease as the length increases. This is especially problematic in areas with congested wiring where the signal line width is difficult to adjust, thus affecting overall performance.
In the routing layer of the intermediate connection board, a base segment and an adjustment segment are introduced. The cross-sectional size of the adjustment segment is larger than that of the base segment. By reasonably setting the width and length of the adjustment segment, the cross-sectional size of the signal line is increased, the current distribution is optimized, and the resistance loss is reduced.
It improves the signal quality of the signal line, reduces resistance loss, enhances signal stability and anti-timing interference capability, and improves the overall signal transmission performance.
Smart Images
Figure CN120998913A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of semiconductor technology, in particular to an interposer, a semiconductor device and an electronic device. BACKGROUND
[0002] An interposer is an intermediate layer structure, mainly used to realize high-density interconnection and heterogeneous integration, which can be used to provide high-speed and low-delay signal transmission paths between memory and processors, and solve the bottleneck of traditional packaging technology in interconnection density and performance.
[0003] In the related art, metal signal lines are arranged in the interposer for interconnection, but in general cases, the width between the input end and the output end of the signal line is constant, so that with the increase of the length of the signal line, the signal transmission quality decreases, thereby affecting the overall performance. SUMMARY
[0004] The purpose of the present disclosure is to provide an interposer, a semiconductor device and an electronic device, which can improve the signal transmission quality to at least partially solve the problems in the related art.
[0005] In order to achieve the above-mentioned purpose, according to a first aspect of the present disclosure, an interposer is provided, comprising: a substrate layer; and a wiring layer formed on the substrate layer, the wiring layer comprising a plurality of signal lines, at least part of the signal lines having a base section and an adjustment section, the cross-sectional size of the adjustment section being greater than the cross-sectional size of the base section.
[0006] Optionally, the width of the adjustment section is greater than the width of the base section.
[0007] Optionally, the ratio of the width of the adjustment section to the width of the base section is K, where 1 < K < 2.
[0008] Optionally, the number of adjustment sections of each signal line is set to one or more.
[0009] Optionally, the widths of the adjustment sections in the same signal line are the same; or the widths of at least two adjustment sections in the same signal line are different.
[0010] Optionally, the wiring layer comprises a first signal line and a second signal line, the length of the first signal line being greater than the length of the second signal line; the length of the adjustment section of the first signal line being greater than the length of the adjustment section of the second signal line.
[0011] Optionally, the signal lines extend along a first direction, and the signal lines are arranged at intervals along a second direction perpendicular to the first direction, and lengths of adjacent two of the signal lines are different along the second direction.
[0012] Optionally, the interposer includes a plurality of wiring layers arranged at intervals along a thickness direction of the substrate layer, and the signal lines of at least one of the wiring layers have the base segment and the adjustment segment.
[0013] According to a second aspect of the present disclosure, a semiconductor device is provided, including a memory, a processor and the above-mentioned interposer, wherein the memory and the processor are arranged on the interposer and are electrically connected through the wiring layers.
[0014] According to a third aspect of the present disclosure, an electronic device is provided, including the above-mentioned semiconductor device.
[0015] Through the above technical solution, i.e. the interposer of the present disclosure, the signal lines of the wiring layers include the base segment and the adjustment segment, wherein the cross-sectional size of the adjustment segment is greater than that of the base segment, and the adjustment segment with a larger carrier surface size is used to improve the signal quality of the signal lines, especially those with a longer length. In the areas where the signal lines are densely distributed, such as routing areas, the base segment can be arranged to meet the signal transmission requirements, and the adjustment segment can be arranged in the range with allowed space to improve the signal quality of the signal lines.
[0016] Other features and advantages of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF DRAWINGS
[0017] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, and are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation of the present disclosure. In the drawings,
[0018] Figure 1 is a structural schematic diagram of a semiconductor device provided in an exemplary embodiment of the present disclosure; Figure 2 is a schematic diagram of one exemplary embodiment of a wiring layer provided by the present disclosure; Figure 3 is a schematic diagram of another exemplary embodiment of a wiring layer provided by the present disclosure; Figure 4 is a schematic diagram of still another exemplary embodiment of a wiring layer provided by the present disclosure; Figure 5a is an eye diagram before the adjustment segment of the signal line is arranged according to the present disclosure; Figure 5b is an eye diagram after the adjustment segment of the signal line is arranged according to the present disclosure.
[0019] Reference Signs List 1000, semiconductor device; 100, package module; 200, substrate structure; 10, interposer; 20, memory; 30, processor; 1, substrate layer; 2, wiring layer; 21, signal line; 211, base section; 212, adjustment section; 21a, first signal line; 21b, second signal line; 3, micro bump; 4, solder ball. DETAILED DESCRIPTION
[0020] The specific embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.
[0021] In the present disclosure, the orientation words such as "upper" and "lower" generally refer to the upper and lower of the corresponding drawings, and "inner" and "outer" refer to the contour of the corresponding components. The terms "first", "second", and the like used in the present disclosure are used to distinguish one element from another element, and do not have sequentiality and importance. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated.
[0022] The inventors have found that the width of the metal signal line in the interposer is constant from the input end to the output end, so that the signal quality decreases as the length of the signal line increases, and in addition, in the routing area where the wiring is crowded, the width of the signal line is not easy to adjust, thus affecting the signal quality.
[0023] To solve the above technical problems, according to a first aspect of the present disclosure, referring to Figures 1 to 4 The present disclosure provides an interposer 10, comprising a substrate layer 1 and a wiring layer 2, wherein the wiring layer 2 is formed on the substrate layer 1, and the wiring layer 2 comprises a plurality of signal lines 21, at least part of the signal lines 21 having a base section 211 and an adjustment section 212, the cross-sectional size of the adjustment section 212 being greater than that of the base section 211.
[0024] Through the above technical solution, i.e. the interposer 10 of the present disclosure, the signal line 21 of the wiring layer 2 comprises a base section 211 and an adjustment section 212, wherein the cross-sectional size of the adjustment section 212 is greater than that of the base section 211, and the adjustment section 212 with a larger cross-sectional size is used to improve the signal quality of the signal line 21, especially the longer one. In areas where the signal lines 21 are distributed more crowded, such as routing areas, the base section 211 can be provided to meet the signal transmission requirements, and the adjustment section 212 can be provided within the range of allowed space to improve the signal quality of the signal line 21.
[0025] It can be understood that increasing the cross-sectional size of the signal line 21 at the adjustment section 212 can reduce the resistance and increase the current distribution space to reduce the current density, thereby reducing the resistance loss and optimizing the current distribution, reducing the probability of electromigration failure, and improving the reliability.
[0026] Reference is made to Figure 5a and Figure 5b , wherein, Figure 5a The eye diagram in Figure 5b is the eye diagram of the signal line 21 provided with the adjustment section 212, and the size of the “eye” opening in the figure can reflect the degree of distortion and the strength of the inter-symbol interference. The present disclosure takes the fixed “eye height” as a reference, and the “eye width” of the right eye diagram is greater than that of the left eye diagram, so that the timing margin of the signal in the time domain is larger, which specifically reflects the stability of the signal transmission and the strong anti-timing interference ability, and the signal quality is improved.
[0027] In some embodiments, reference is made to Figures 2 to 4 , the width of the adjustment section 212 is greater than the width of the base section 211, so as to increase the cross-sectional size of the signal line 21. Exemplarily, the signal line 21 extends along a first direction, and a plurality of signal lines 21 are distributed along a second direction, at this time, the above-mentioned width is the size of the signal line 21 along the second direction, wherein the “X” direction in the figure represents the first direction, and the “Y” direction represents the second direction.
[0028] It can be understood that the layout of the signal line 21 can be realized by etching a groove and electroplating filling, so that the width of the signal line 21 (including the adjustment section 212 and the base section 211) in the above-mentioned is the width of the groove. In this way, the adjustment section 212 can also be formed by deepening the depth of the groove to increase the cross-sectional area of the signal line 21, at this time, the depth direction of the groove is perpendicular to the plane formed by the first direction and the second direction. In addition, the width of the groove can be widened and the depth of the groove can be deepened at the same time. The present disclosure is not limited thereto.
[0029] It can be understood that when the width of the signal line 21 is increased to form the adjustment section 212, the width needs to be reasonably set to balance the adverse factors such as impedance mutation, in some embodiments, reference is made to Figures 2 to 4As shown, the ratio of the width of the adjustment section 212 to the width of the base section 211 is K, where 1 < K < 2. In this way, the width of the adjustment section 212 can be constrained to reduce problems such as impedance discontinuity and signal reflection caused by the adjustment section 212 being too wide, manufacturing process, and uneven current density distribution, so that the width of the adjustment section 212 is within an appropriate range to reduce the impact of the above problems on signal quality, and to ensure that the adjustment section 212 with a larger width is suitable for improving signal quality.
[0030] As an example, the width of the signal line 21 is one of the key factors affecting impedance, and when the signal line 21 suddenly widens from the base section 211 to the adjustment section 212, the impedance at the discontinuity point will decrease significantly. Any discontinuity in impedance will cause signal reflection, and the reflected wave will superimpose on the original signal, causing signal waveform distortion, such as overshoot, undershoot, ringing, and other phenomena. Moreover, the reflection itself represents a loss of signal energy, and the signal quality is reduced.
[0031] Therefore, to reduce the impedance discontinuity caused by the width discontinuity of the signal line 21, the connection between the base section 211 and the adjustment section 212 can be provided as a transition section, where the width of the transition section gradually increases from the base section 211 to the adjustment section 212. In this way, by providing the transition section, the size discontinuity of the base section 211 and the adjustment section 212 can be avoided, the impact of the impedance discontinuity caused by the width discontinuity of the signal line 21 on signal quality can be reduced, and the signal quality can be improved.
[0032] In addition, current tends to choose the path with the smallest resistance, and in the transition region between the base section 211 and the adjustment section 212, the current distribution changes, and the local current density abnormally increases at the entry point of the current from the base section 211 to the adjustment section 212. Over a long period of operation, the metal atoms at these current density hotspots migrate at an accelerated rate, which can cause the wire to be open (form a hole) or short (form a small hill), severely reducing the reliability of the interconnection.
[0033] Therefore, by reasonably setting the width of the adjustment section 212, the above effects can be reduced, and the increase in the width of the adjustment section 212 has more positive effects on improving signal quality, so that the signal quality can be improved.
[0034] In some embodiments, with reference to Figures 2 to 4 As shown, the number of adjustment sections 212 of each signal line 21 can be one or more, so that by providing multiple adjustment sections 212, the cross-sectional size of the signal line 21 can be reasonably increased in the allowed space area, so that the signal quality can be improved.
[0035] It can be understood that the multiple adjustment sections 212 can be arranged adjacently or at intervals. As an example, with reference to Figure 4As shown, the signal line 21 has two adjacent adjustment sections 212, and the widths of the two adjustment sections 212 are different based on the reasonable wiring, so as to further increase the cross-sectional size of the signal line 21 and reasonably utilize the allowed space.
[0036] In some other possible embodiments not shown in the drawings, the signal line 21 can be provided with the base section 211 in the dense wiring area and the adjustment section 212 in the allowed space area, so that the signal line 21 can have a plurality of spaced adjustment sections 212, so as to reasonably utilize the allowed space and improve the signal quality. The present disclosure is not limited thereto.
[0037] In some embodiments, referring to Figures 2 to 4 As shown, the widths of the at least two adjustment sections 212 in the same signal line 21 are different, and the signal line 21 has two adjacent adjustment sections 212 with different widths. It can be understood that in some other embodiments, the two adjustment sections 212 can include three adjustment sections 212, and the widths of the three adjustment sections 212 can sequentially increase along the extension direction of the signal line 21, so as to reduce the width change between the two adjacent adjustment sections 212 and reduce the influence of the above-mentioned, for example, impedance mutation and local increase of current density.
[0038] Alternatively, in some other embodiments, the signal line 21 can be provided with the base section 211 in the dense wiring area and the adjustment section 212 in the allowed space area, so that the signal line 21 can have a plurality of spaced adjustment sections 212, and the widths of the adjustment sections 212 in the same signal line 21 can be the same. It can be understood that the widths of the above-mentioned plurality of adjustment sections 212 can also be different, so as to more reasonably utilize the allowed space and improve the signal quality. The present disclosure is not limited thereto.
[0039] In some embodiments, referring to Figures 2 to 4 As shown, the wiring layer 2 can include a first signal line 21a and a second signal line 21b, wherein the length of the first signal line 21a is greater than the length of the second signal line 21b, and the length of the adjustment section 212 of the first signal line 21a is greater than the length of the adjustment section 212 of the second signal line 21b. In this way, the signal quality of the signal line 21 with a longer length is improved by providing the adjustment section 212 with a longer length.
[0040] It is understood that the lengths of the two signal lines 21 are compared under the premise that the widths of the two signal lines 21 are the same. As can be seen from the foregoing description of the cross-sectional dimensions of the signal lines 21, in some other embodiments, the lengths of the adjustment segments 212 of the two signal lines 21 are the same. The width of the adjustment segment 212 of the first signal line 21a can be greater than the width of the adjustment segment 212 of the second signal line 21b, or the depth of the adjustment segment 212 of the first signal line 21a can be greater than the depth of the adjustment segment 212 of the second signal line 21b. Of course, the width and depth of the adjustment segment 212 of the first signal line 21a can both be greater than the width and depth of the adjustment segment 212 of the second signal line 21b, in order to improve the signal quality. This disclosure does not impose specific limitations on this.
[0041] It is understandable that in order to improve the signal quality of the aforementioned longer signal line 21, it is necessary to adopt at least one of the following methods: increasing the length of the adjustment section 212, widening the width of the adjustment section 212, and deepening the depth of the adjustment section 212. Therefore, it is necessary to reasonably arrange the multiple signal lines 21.
[0042] In some embodiments, reference Figures 2 to 4 As shown, signal lines 21 extend along a first direction, and signal lines 21 are spaced apart along a second direction perpendicular to the first direction. Along the second direction, adjacent signal lines 21 have different lengths. For ease of description, the longer signal line 21 is designated as the first signal line 21a, and the shorter signal line 21 is designated as the second signal line 21b. Therefore, along the first direction, the front end of the second signal line 21b after it stops extending forms an allowable space, allowing the first signal line 21a to form an adjustment section 212 within this allowable space region, thereby increasing the cross-sectional size of the signal line 21.
[0043] For example, refer to Figure 2 As shown, multiple signal lines 21 can be arranged at intervals along the second direction, and along the second direction, the length of the signal lines 21 first increases and then decreases, and then increases and decreases again, so that in two adjacent signal lines 21, the front end of the shorter signal line 21 after it stops extending forms an allowable space, so that the longer signal line 21 forms an adjustment segment 212 in the allowable space area. (Reference) Figure 3 As shown, multiple signal lines 21 can be arranged at intervals along the second direction, and along the second direction, the length of the signal lines 21 first increases and then decreases. (Reference) Figure 4 As shown, multiple signal lines 21 can be arranged at intervals along the second direction, and along the second direction, two adjacent signal lines 21 have different lengths, making the longer signal line 21 suitable for forming an adjustment section 212.
[0044] In addition, in some other possible embodiments not shown in the drawings, the plurality of signal lines 21 can be arranged at intervals in the second direction, and the length of the signal lines 21 can gradually increase or gradually decrease in the second direction. The present disclosure is not limited thereto.
[0045] In some embodiments, referring to Figure 1 As shown, the intermediate connection plate 10 includes a plurality of wiring layers 2 arranged at intervals in the thickness direction of the substrate layer 1, and the signal lines 21 of at least one wiring layer 2 have a base section 211 and an adjustment section 212. In this way, by providing the plurality of wiring layers 2, the wiring density can be significantly improved, the two-dimensional plane limitation can be broken through, signal cross conflicts can be avoided, and layered routing can be achieved. In addition, the plurality of wiring layers 2 pass through the thickness direction of the intermediate connection plate 10 through TSV (through silicon via), and vertically connect the signals of the top chip (such as a CPU) and the bottom substrate (such as a PCB), while each wiring layer 2 is responsible for short-distance interconnection in the horizontal direction, so that the TSV solves the vertical conduction problem, and the plurality of wiring layers 2 solves the high-density wiring in the horizontal direction, forming a three-dimensional interconnection network of “vertical penetration + horizontal layering”, and shortening the signal path.
[0046] According to a second aspect of the present disclosure, referring to Figure 1 As shown, a semiconductor device 1000 is provided, which includes a memory 20, a processor 30, and the above-mentioned intermediate connection plate 10, wherein the memory 20 and the processor 30 are arranged on the intermediate connection plate 10 and are electrically connected through the wiring layer 2. Exemplarily, the intermediate connection plate 10 can include a plurality of micro-bumps 3 for connecting to the memory 20 and the processor 30, and in addition, the intermediate connection plate 10 can also include a plurality of solder balls 4 for connecting to a substrate or a PCB, etc. Wherein, the memory 20 can include, for example, DRAM, SRAM, ROM, etc., and the processor 30 can include, for example, CPU, GPU, IPU, etc. The present disclosure does not make specific limitations thereto.
[0047] According to a third aspect of the present disclosure, an electronic device is provided, which includes the above-mentioned semiconductor device 1000, and has all the beneficial effects of the above-mentioned semiconductor device 1000, and the present disclosure will not be repeated here. In addition, the electronic device can be, for example, a computer, a mobile phone, a tablet, etc. The present disclosure is not limited thereto.
[0048] The preferred embodiments of the present disclosure are described in detail above with reference to the drawings, but the present disclosure is not limited to the specific details in the above-described embodiments, and various simple modifications can be made to the technical solutions of the present disclosure within the technical concept of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.
[0049] It should be further noted that various specific technical features described in the above specific embodiments can be combined in any suitable manner, and the disclosure will not be repeated here for various possible combinations.
[0050] In addition, various different embodiments of the disclosure can also be combined with each other as long as they do not contradict the idea of the disclosure, and they should also be considered as disclosed by the disclosure.
Claims
1. An intermediary connection plate, characterized in that, include: Substrate layer; as well as A wiring layer is formed on the substrate layer, the wiring layer including a plurality of signal lines, at least some of the signal lines having a base segment and an adjustment segment. The cross-sectional dimensions of the adjustment section are larger than those of the base section.
2. The intermediary connecting plate according to claim 1, characterized in that, The width of the adjustment segment is greater than the width of the base segment.
3. The intermediary connecting plate according to claim 2, characterized in that, The ratio of the width of the adjustment segment to the width of the base segment is K, where 1 <K<2。 4. The intermediary connecting plate according to claim 1, characterized in that, The number of adjustment segments for each signal line is set to one or more.
5. The intermediary connecting plate according to claim 4, characterized in that, The widths of the adjustment segments in the same signal line are the same; or At least two of the adjustment segments in the same signal line have different widths.
6. The intermediary connecting plate according to claim 1, characterized in that, The wiring layer includes a first signal line and a second signal line, wherein the length of the first signal line is greater than the length of the second signal line; The length of the adjustment segment of the first signal line is greater than the length of the adjustment segment of the second signal line.
7. The intermediary connecting plate according to claim 1, characterized in that, The signal lines extend along a first direction and are spaced apart along a second direction perpendicular to the first direction. Along the second direction, two adjacent signal lines have different lengths.
8. The intermediary connecting plate according to any one of claims 1-7, characterized in that, The interfacing board includes multiple wiring layers spaced apart along the thickness direction of the substrate layer, and at least one of the wiring layers has a base segment and an adjustment segment for its signal lines.
9. A semiconductor device, characterized in that, Includes a memory, a processor, and an intermediary connection board as described in any one of claims 1-8. The memory and the processor are disposed on the intermediate connection board and electrically connected through the wiring layer.
10. An electronic device, characterized in that, Includes the semiconductor device as described in claim 9.