Equipment communication method and system, terminal equipment and storage medium

Abstract

The invention is suitable for the technical field of power system relay protection, and provides an equipment communication method and system, terminal equipment and a storage medium, and the method comprises the steps: obtaining first message data; the first message data is time sequence data corresponding to the current moment of the first logic device; sending the first message data to a second logic device to indicate the second logic device to perform time sequence calibration according to the first message data to obtain a calibration time sequence, and sending second message data to the first logic device; wherein the second message data is the state data of the slave device acquired by the second logic device based on the calibration time sequence; and after receiving second message data sent by the second logic device, sending the second message data to the master device to indicate the master device to perform differential logic operation according to the second message data to obtain an operation result. According to the method, the communication time efficiency of the equipment can be improved, so that differential protection misjudgment caused by time sequence non-communication is eliminated.

Description

Technical Field

[0001] This application belongs to the field of power system relay protection technology, and in particular relates to a device communication method, system, terminal equipment and storage medium. Background Technology

[0002] Busbar protection systems are the "last line of defense" for the safe operation of power systems. The master-slave architecture is the mainstream technology direction of modern busbar protection systems. Communication between the master and slave units affects the accuracy of differential calculations.

[0003] In related technologies, when a host sends message data to a slave device, it buffers various types of message data, including Ethernet data, and sends them in a specific order. This sequential buffering and sending method may cause some message data to fail to be transmitted to the slave device in a timely manner as required, resulting in transmission delay. If the communication error exceeds 1ms, it may cause differential protection to misjudge. Summary of the Invention

[0004] This application provides a device communication method, system, terminal device, and storage medium, which can improve the communication timeliness of the device and eliminate differential protection misjudgments caused by timing non-communication.

[0005] In a first aspect, embodiments of this application provide a device communication method, applied to a first logic device in a device communication system. The device communication system includes a master device and a slave device. The master device includes the first logic device, and the slave device includes a second logic device.

[0006] Obtain the first message data; the first message data is the timing data corresponding to the first logic device at the current moment;

[0007] The first message data is sent to the second logic device to instruct the second logic device to perform timing calibration based on the first message data, obtain the calibration timing, and send the second message data back to the first logic device; wherein, the second message data is the status data of the slave device collected by the second logic device based on the calibration timing;

[0008] After receiving the second message data sent by the second logic device, the second message data is sent to the master device to instruct the master device to perform differential logic operations based on the second message data and obtain the operation result.

[0009] In this embodiment, logic devices are deployed on the master device and slave devices. The first logic device of the master device obtains its own current timing data as the first message data and sends it to the second logic devices of multiple slave devices at the same time, so that each second logic device can calibrate its own timing accordingly. This method of data transmission and calibration directly through logic devices breaks through the latency problem caused by traditional reliance on CPU software caching and sequential transmission, and improves the synchronization efficiency. This ensures that the status data acquisition time of each slave device is strictly synchronized, so that the master device can perform differential calculation based on the data at the same time, thereby eliminating misjudgment caused by timing asynchrony.

[0010] In one possible implementation of the first aspect, obtaining the first message data includes:

[0011] Get the preset period;

[0012] The first interrupt signal is generated according to a preset period;

[0013] The first message data is obtained based on the first interrupt signal.

[0014] In this embodiment of the application, by generating a first interrupt signal according to a preset period to obtain the first message data, the regularity and timeliness of the acquisition of the first message data can be guaranteed, providing a stable timing reference for subsequent synchronization calibration and improving the accuracy and reliability of synchronization.

[0015] In one possible implementation of the first aspect, obtaining the first message data based on the first interrupt signal includes:

[0016] When the first interrupt signal is detected, the first timing data corresponding to the current moment is obtained;

[0017] The first time sequence data is generated into the first message data according to the preset format.

[0018] In this embodiment of the application, by triggering the acquisition of current timing data through the first interrupt signal and generating the first message data according to the preset format, it can be ensured that the synchronization message is generated based on a precise time reference, providing a reliable basis for slave timing calibration and ensuring the time consistency of data interaction between the master and slave.

[0019] In one possible implementation of the first aspect, the method further includes:

[0020] Receive the first instruction sent by the master device; the first instruction is a control command generated by the master device based on the calculation results.

[0021] The first instruction is sent to the second logic device to instruct the slave device to execute the first instruction.

[0022] In this embodiment, the control command generated by the master device based on the calculation result is sent to the second logic device via the first logic device. The second logic device can drive the slave device to execute the instruction, realize the coordinated response of the master and slave devices, and ensure the accurate execution of the protection action.

[0023] In one possible implementation of the first aspect, after receiving the first instruction, the method further includes:

[0024] If the third message data is obtained, the third message data is sent to the second logic device; wherein, the third message data is the timing data corresponding to the first logic device at the current moment;

[0025] The first instruction is sent to the second logic device.

[0026] In this embodiment, the third message data (synchronization message) is sent first, followed by the first instruction, to ensure that the slave device executes the instruction based on the latest synchronization timing, thereby ensuring that the timing base of the master and slave devices is consistent and improving the accuracy and reliability of the control command execution.

[0027] In one possible implementation of the first aspect, the method further includes:

[0028] If any device in the device communication system is configured to the first mode, the device corresponding to the first mode is identified as the master device; then the device that is not configured to the first mode is identified as the slave device.

[0029] In this embodiment, the master device is determined by configuring the first mode, and the slave device is not configured. This clearly defines the roles of master and slave devices, providing a clear role basis for master-slave program sharing and communication based on programmable logic devices, and facilitating system collaboration.

[0030] Secondly, embodiments of this application provide a device communication system, including a master device and a slave device; the master device includes a first logic device, and the slave device includes a second logic device;

[0031] The first logic device is used to implement the device communication method of any of the first aspects above.

[0032] In one possible implementation of the second aspect, the first logic device and the second logic device are directly connected via optical fiber.

[0033] Thirdly, embodiments of this application provide a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the device communication method as described in any of the first aspects above.

[0034] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the device communication method as described in any of the first aspects above.

[0035] Fifthly, embodiments of this application provide a computer program product that, when run on a terminal device, causes the terminal device to execute any of the device communication methods described in the first aspect above.

[0036] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram of the device communication system provided in the embodiments of this application;

[0039] Figure 2 This is a schematic flowchart of the device communication method provided in the embodiments of this application;

[0040] Figure 3 This is a schematic diagram of the process for obtaining the first message data provided in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of the device data interaction process provided in the embodiments of this application;

[0042] Figure 5 This is a schematic diagram of the multi-message data interaction process provided in the embodiments of this application;

[0043] Figure 6 This is a schematic diagram of the overall structure of the device communication system and method provided in the embodiments of this application;

[0044] Figure 7 This is a schematic diagram of the device communication connection and communication structure provided in the embodiments of this application;

[0045] Figure 8 This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application. Detailed Implementation

[0046] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0047] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0048] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0049] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0050] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0051] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.

[0052] Busbar protection systems are the "last line of defense" for the safe operation of power systems. The master-slave architecture is the mainstream technology direction of modern busbar protection systems. Communication between the master and slave units affects the accuracy of differential calculations.

[0053] In related technologies, when a host sends message data to a slave device, it buffers various types of message data, including Ethernet data, and sends them in a specific order. This sequential buffering and sending method may cause some message data to fail to be transmitted to the slave device in a timely manner as required, resulting in transmission delay. If the synchronization error exceeds 1ms, it may cause differential protection to misjudge.

[0054] To address the problems in the aforementioned related technologies, this application provides a device communication method and system. The host and slave devices use the same hardware boards and underlying programs. The CPU determines the role of the master-slave enable interface. A direct fiber optic connection is used. Synchronization functions (such as a synchronization interrupt counter, with synchronization messages sent once per interrupt) are independently implemented by a Field-Programmable Gate Array (FPGA). Ethernet messages have a lower priority than synchronization messages, which reduces synchronization errors and avoids misjudgments in differential protection. Furthermore, it reduces hardware and software maintenance costs by 50%, making it suitable for the field of power system relay protection.

[0055] See Figure 1 This is a schematic diagram of the device communication system provided in the embodiments of this application, such as... Figure 1 As shown, the device communication system includes a master device (host) and slave devices (slave devices). Both the master and slave devices contain multiple communication interfaces. These interfaces feature independent transmit and receive capabilities and bidirectional transmission and reception. The master device can be configured with multiple interfaces (up to 5) and supports plug-and-play functionality, adapting to architectures such as single master with single slave and single master with multiple slaves. The hardware connection method and physical layout between the master and slave devices are as follows:

[0056] 1) Hardware board consistency

[0057] The host and slave units use the exact same hardware boards with no hardware differences, allowing for flexible role switching.

[0058] 2) Shared underlying programs

[0059] The host and slave machines use the same underlying program, and the roles are defined through the master-slave enable interface within the program.

[0060] 3) Interface Configuration

[0061] Both the host and slave devices are equipped with multiple fiber optic communication interfaces, supporting various architectures such as single host and single slave, and single host and multiple slaves. The interfaces have independent transmit and receive capabilities and bidirectional transmit and receive characteristics, and can be used plug and play as needed.

[0062] 4) Both the host and slave devices are equipped with multiple fiber optic communication interfaces, supporting various architectures such as single host and single slave, and single host and multiple slaves. The interfaces have independent transmission and reception and bidirectional transmission and reception characteristics, and can be plugged and used as needed.

[0063] 5) Synchronous implementation

[0064] The hardware integrates an FPGA (such as the Pango Logos series PG2L100H chip mentioned in the document), which is independently responsible for the synchronization function between the host and the slave, ensuring synchronization accuracy.

[0065] Data synchronization is achieved using the FPGA integrated in the host and slave units of the aforementioned communication system, see [link / reference]. Figure 2 This is a flowchart illustrating a device communication method provided in an embodiment of this application. It is applied to a first logic device in a device communication system. The device communication system includes a master device and a slave device. The master device includes a first logic device, and the slave device includes a second logic device, such as... Figure 2 As shown, and not as a limitation, a method may include the following steps:

[0066] S101, Obtain the first message data; the first message data is the timing data corresponding to the current moment of the first logic device.

[0067] In this embodiment, the first logic device is the host FPGA. A PGA is a programmable logic device that contains a large number of configurable logic units, flip-flops, and interconnect resources. Users can program it using a hardware description language to define specific logic functions and timing logic. The "first message data" is the synchronization message data generated by the host FPGA. Its core content is the timing data recorded by the host FPGA at the current moment, including the interrupt counter, the 64-bit counter, and the complete RTC time (real-time clock time).

[0068] In one embodiment, see Figure 3 This is a schematic diagram of the process for obtaining the first message data provided in an embodiment of this application, such as... Figure 3 As shown, step S101 includes:

[0069] S201, obtain the preset cycle.

[0070] In this embodiment, the host's FPGA (programmable logic device) contains a Timer module, which is set by timing logic. The specific value of this module needs to be determined in conjunction with the hardware design and the actual application scenario.

[0071] S202, generate the first interrupt signal according to the preset period.

[0072] In this embodiment of the application, the Timer module counts according to a preset period. When the count reaches the preset period, it automatically triggers the generation of the first interrupt signal (fpga_sint).

[0073] S203, obtain the first message data according to the first interrupt signal.

[0074] In this embodiment of the application, when the first interrupt signal is generated, the host FPGA collects the relevant timing information at this time and integrates it to form the first message data.

[0075] In the above method, the first message data is obtained by generating a first interrupt signal according to a preset period, which can ensure the regularity and timeliness of the acquisition of the first message data, provide a stable timing reference for subsequent synchronization calibration, and improve the accuracy and reliability of synchronization.

[0076] In one embodiment, step S203 includes:

[0077] When the first interrupt signal is detected, the first timing data corresponding to the current time is obtained; the first timing data is generated into the first message data according to the preset format.

[0078] In this embodiment, the first interrupt signal is the fpga_sint interrupt signal generated by the Timer module within the host FPGA. When this interrupt signal is triggered (specifically, the rising edge of the signal), the host FPGA immediately locks the timing data at the current moment, including the interrupt counter, the 64-bit counter, and the complete RTC time. Subsequently, the SMAC module within the FPGA assembles this locked timing data into a synchronization message, i.e., the first message data.

[0079] The first interrupt signal is the key trigger condition for obtaining the first message data, ensuring that the synchronization message can be generated based on a precise time node, and providing an accurate timing reference for the subsequent synchronization operation between the host and the slave.

[0080] In the above method, the control command generated by the master device based on the calculation result is sent to the second logic device via the first logic device. The second logic device can drive the slave device to execute the instruction, realize the coordinated response of the master and slave devices, and ensure the accurate execution of the protection action.

[0081] S102, the first message data is sent to the second logic device to instruct the second logic device to perform timing calibration based on the first message data, obtain the calibration timing, and send the second message data to the first logic device; wherein, the second message data is the status data of the slave device collected by the second logic device based on the calibration timing.

[0082] In this embodiment, the host FPGA (first logic device) generates a first interrupt signal at a preset period, locks the current timing data (interrupt counter, 64-bit counter, RTC time, etc.), assembles it into first message data (synchronization message), and sends it to the slave FPGA (second logic device) through a direct fiber optic communication interface using the host FPGA's SMAC module. This step is fundamental to achieving master-slave timing synchronization, ensuring that the slave device obtains the host's reference timing.

[0083] After receiving the first message data, the slave FPGA (second logic device) parses the host's timing data through its internal Sync_analysis module. It then aligns its own interrupt counter, 64-bit counter, RTC time, etc., with the host data to complete timing calibration, obtaining a calibration timing sequence consistent with the host. This process is completed independently by the slave FPGA, without relying on the CPU, ensuring calibration accuracy and avoiding differential protection misjudgments due to synchronization errors.

[0084] Based on calibrated timing, the slave FPGA collects slave device status data for its corresponding interval (e.g., line or transformer interval), including CT / PT signals (current / voltage signals) and switch positions. This data is assembled into a second message, such as a GOOSE message, according to a preset format and transmitted back to the host FPGA (first logic device) via optical fiber. Because the data acquisition is based on calibrated timing, it ensures that the status data uploaded by the slave device is consistent with the host's time base, providing an accurate timing basis for subsequent logic operations of the host (e.g., differential current calculation and protection judgment).

[0085] S103 After receiving the second message data sent by the second logic device, the second message data is sent to the master device to instruct the master device to perform differential logic operation based on the second message data and obtain the operation result.

[0086] In this embodiment of the application, after the host FPGA (first logic device) receives the second message data (GOOSE message) sent by the slave FPGA (second logic device), it will pass the data to the host CPU (i.e. the core processing unit of the master device).

[0087] After receiving the second message data, the host CPU performs differential logic operations based on the relevant data it has processed. This operation aims to determine whether a fault exists in the power system (such as determining whether a bus fault has occurred through differential current calculation in differential protection), and finally obtains the calculation result, providing a basis for subsequent decisions such as whether to generate a trip command.

[0088] The above process embodies the core logic of master-slave collaborative operation: the slave unit is responsible for front-end data acquisition and synchronization, while the master unit is responsible for centralized calculation and decision-making, ensuring that the bus protection system can respond quickly and accurately to changes in the power system status.

[0089] In the above method, logic devices are deployed on the master and slave devices. The first logic device of the master device obtains its own current timing data as the first message data and sends it to the second logic devices of multiple slave devices at the same time. This allows each second logic device to calibrate its own timing accordingly. This method of data transmission and calibration directly through logic devices overcomes the latency problem caused by traditional reliance on CPU software caching and sequential transmission, and improves synchronization efficiency. This ensures that the status data acquisition time of each slave device is strictly synchronized, enabling the master device to perform differential calculations based on data at the same time, thereby eliminating misjudgments caused by timing asynchrony.

[0090] In one embodiment, see Figure 4 This is a schematic diagram of the device data interaction process provided in the embodiments of this application, such as... Figure 4 As shown, the method also includes:

[0091] S301, receive the first instruction sent by the master device; the first instruction is a control command generated by the master device based on the calculation result.

[0092] In this embodiment, the CPU of the host device performs differential logic operations on the second message data (GOOSE messages, including CT / PT signals, switch positions, and other status data) uploaded by each slave device. Based on the operation results, it determines whether there is a fault in the power system (such as a bus fault). If it is determined that a protection action (such as disconnecting the faulty circuit) needs to be performed, the host CPU will generate a corresponding control command, namely the first instruction (which may be a trip command).

[0093] The first instruction generated by the host CPU is sent to the slave device via an Ethernet message. After receiving the instruction, the slave device will drive the circuit breaker in the corresponding bay to operate, thereby realizing the protection and control of the power system and completing the closed-loop process from calculation and decision-making to execution.

[0094] S302, the first instruction is sent to the second logic device to instruct the slave device to execute the first instruction.

[0095] In this embodiment, after the host CPU generates the first instruction, it sends it to the slave device via an Ethernet message. After receiving the instruction, the FPGA (second logic device) of the slave device drives the corresponding slave device (such as a circuit breaker) to perform the corresponding operation, thereby realizing the protection and control of the power system.

[0096] In the above method, the control command generated by the master device based on the calculation result is sent to the second logic device via the first logic device. The second logic device can drive the slave device to execute the instruction, realize the coordinated response of the master and slave devices, and ensure the accurate execution of the protection action.

[0097] In one embodiment, see Figure 5This is a schematic diagram of the multi-message data interaction process provided in the embodiments of this application, such as... Figure 5 As shown, after receiving the first instruction, the method further includes:

[0098] S401, if the third message data is obtained, the third message data is sent to the second logic device; wherein the third message data is the timing data corresponding to the current moment of the first logic device.

[0099] In this embodiment, after receiving the first instruction, if the first logic device (host FPGA) obtains the third message data (i.e., the timing data corresponding to the current moment), since the synchronization message has a higher priority than the Ethernet message, the third message data will be sent to the second logic device (daughter FPGA) first. This process reflects the design principle that the synchronization message (containing timing data) has a higher priority than the control instruction (first instruction).

[0100] S402, the first instruction is sent to the second logic device.

[0101] In this embodiment, after the third message data is sent to the slave device, a first instruction is sent to the slave device to ensure that the slave device receives and processes the first instruction only after completing timing synchronization with the master device. After receiving the instruction, the FPGA (second logic device) of the slave device drives the corresponding slave device (such as a circuit breaker) to perform corresponding operations, thereby realizing the protection and control of the power system.

[0102] In the above method, the third message data (synchronization message) is sent first, followed by the first instruction, to ensure that the slave device executes the instruction based on the latest synchronization timing, guaranteeing that the timing base of the master and slave devices is consistent, and improving the accuracy and reliability of the control command execution.

[0103] In one embodiment, the method further includes:

[0104] If any device in the device communication system is configured to the first mode, the device corresponding to the first mode is identified as the master device; then the device that is not configured to the first mode is identified as the slave device.

[0105] In the embodiments of this application, when any device in the device communication system is configured to the first mode (i.e., the master-slave enable of the device is set to 1), the device is determined to be the master device; while the device that is not configured to the first mode (i.e., the master-slave enable is set to 0 or not set) is determined to be the slave device.

[0106] This mechanism is controlled by the CPU through the master-slave enable interface in the underlying program, providing a clear basis for the division of roles between the master and slave machines. This allows the master and slave machines to use the same set of programs and hardware boards, giving them a certain degree of adaptability, while simplifying the development and maintenance process.

[0107] In the above method, the master device is determined by configuring the first mode, and the slave device is not configured. This clearly defines the roles of master and slave devices, providing a clear role basis for master-slave program sharing and communication based on programmable logic devices, and facilitating system collaboration.

[0108] This application provides a device communication system, including a master device and a slave device; the master device includes a first logic device, and the slave device includes a second logic device; the first logic device is used to implement the device communication method described in the above steps.

[0109] In one embodiment, the first logic device and the second logic device are directly connected via optical fiber.

[0110] In this embodiment, the communication interface between the host and the slave is directly connected by optical fiber without going through a switch, ensuring a simple communication path and reducing the impact of relay delay on synchronization accuracy (the synchronization error needs to be controlled within 1ms to avoid differential protection misjudgment).

[0111] See Figure 6 This is a schematic diagram of the overall structure of the device communication system and method provided in the embodiments of this application, as shown below. Figure 6 As shown, it specifically includes:

[0112] 1. Core components and role identifiers of the host and slave machines

[0113] Hardware consistency is reflected in the fact that the hardware structure of the host and slave is completely identical, both including FPGA chip (core processing unit), CPU (master-slave role control), PHY chip (physical layer interface), etc., reflecting the design of "the same set of hardware boards".

[0114] Master-slave enable signal (master_slave_en):

[0115] The master_slave_en of the master machine is marked as "set to 1", while the master_slave_en of the slave machine is marked as "set to 0 or not set". This is the core control signal that distinguishes the master and slave roles (determined by the CPU).

[0116] This signal directly controls the FPGA function: the master can send synchronization messages because master_slave_en=1, while the slave can only receive and parse synchronization messages (cannot actively send them) because master_slave_en=0.

[0117] 2. Core Modules of the Host FPGA and Synchronization Message Data Generation Process

[0118] Timer module:

[0119] It is responsible for generating the interrupt signal fpga_sint (the first interrupt signal in the document), whose rising edge serves as a key trigger point to lock the current interrupt counter, 64-bit counter (cnt64_timer), complete RTC time (rtc...), and other timing data; these data are the core content of the synchronization message, ensuring the accuracy of the synchronization reference.

[0120] SMAC module:

[0121] The timing data locked by the Timer module is received, a synchronization message is constructed according to the preset format, and sent to the slave device via optical fiber through the sending interface (TX1). Since the host master_slave_en=1, the SMAC module has the authority to send synchronization messages.

[0122] 3. Core Modules of the Sub-Unit FPGA and Synchronization Message Data Parsing Process

[0123] Sync_analysis module:

[0124] The slave device receives synchronization messages sent by the host through the receiving interface (RX1), parses out the host timing data (sync_rx_sintcnt corresponds to the interrupt counter, sync_rx_timercnt corresponds to the 64-bit counter, and sync_rx_rtc corresponds to the RTC time), and synchronizes the parsed host data to the slave device's own Timer module, so that the slave device's interrupt counter, 64-bit counter, and RTC time are consistent with the host, thus achieving "timing calibration".

[0125] Timer module (sub-machine):

[0126] Because master_slave_en = 0, the slave timer module does not actively generate a synchronization reference, but instead receives the parsed data from the Sync_analysis module to complete its own timing alignment with the master.

[0127] 4. Priority and direction of data interaction

[0128] The signal flow reflects that "synchronization messages have higher priority than other messages": the transmission path of synchronization messages (master → slave) is marked first. Only after the slave completes synchronization can it upload the collected data (such as CT / PT signals, switch positions) through GOOSE messages. Ethernet messages generated by the master CPU (such as trip commands) also need to be sent after synchronization is completed.

[0129] Two-way interactive channels: TX1 (transmit) and RX1 (receive) clearly define the two-way nature of fiber optic communication, supporting bidirectional data transmission between the host and the slave.

[0130] See Figure 7This is a schematic diagram of the device communication connection and communication structure provided in the embodiments of this application, such as... Figure 7 As shown, it includes:

[0131] Hardware structure:

[0132] The host and slave units are directly connected via fiber optic cable, without intermediate devices such as switches; the hardware modules (such as FPGA, PHY chip, CPU) of the host and slave units have the same structure, intuitively reflecting the design of "the same set of hardware boards".

[0133] Synchronization message path:

[0134] The synchronization message (including interrupt counter, 64-bit counter, and RTC time) generated by the host FPGA is sent to the slave device via optical fiber;

[0135] Business (Status) Data Path:

[0136] The GOOSE messages (including CT / PT signals, switch positions, etc.) collected by the slave unit are transmitted back to the host unit via optical fiber; the Ethernet messages (such as trip commands) generated by the host CPU are sent to the slave unit via optical fiber.

[0137] This application uses the same hardware boards and underlying programs for both the host and slave units. The master-slave enable interface is determined by the CPU. It adopts direct fiber optic connection and independently implements the synchronization function (synchronization interrupt counter, etc., with synchronization messages sent once per interrupt) using a field-programmable gate array (FPGA). Furthermore, the priority of Ethernet messages is lower than that of synchronization messages, which can reduce synchronization errors and avoid differential protection misjudgments. It can also reduce the hardware and software maintenance costs by 50%, making it suitable for the field of power system relay protection.

[0138] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0139] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0140] Figure 8 This is a schematic diagram of the structure of the terminal device provided in the embodiments of this application. For example... Figure 8 As shown, the terminal device 8 of this embodiment includes: at least one processor 80 ( Figure 8 (Only one is shown) a processor, a memory 81, and a computer program 82 stored in the memory 81 and executable on at least one processor 80, wherein the processor 80 executes the computer program 82 to implement the steps in any of the above-described embodiments of the device communication methods.

[0141] The terminal device can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. This terminal device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that... Figure 8 This is merely an example of terminal device 8 and does not constitute a limitation on terminal device 8. It may include more or fewer components than shown in the figure, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0142] The processor 80 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0143] In some embodiments, memory 81 may be an internal storage unit of the terminal device 8, such as a hard disk or memory of the terminal device 8. In other embodiments, memory 81 may be an external storage device of the terminal device 8, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the terminal device 8. Furthermore, memory 81 may include both internal storage units and external storage devices of the terminal device 8. Memory 81 is used to store operating systems, applications, bootloaders, data, and other programs, such as program code of computer programs. Memory 81 can also be used to temporarily store data that has been output or will be output.

[0144] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the steps in the above-described method embodiments.

[0145] This application provides a computer program product that, when run on a terminal device, enables the terminal device to implement the steps described in the various method embodiments above.

[0146] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. A computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / terminal equipment, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0147] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0148] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0149] In the embodiments provided in this application, it should be understood that the disclosed apparatus / terminal devices and methods can be implemented in other ways. For example, the apparatus / terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0150] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0151] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A device communication method, characterized in that, A first logic device applied in a device communication system, the device communication system including a master device and a slave device, the master device including the first logic device, the slave device including a second logic device; the method includes: Obtain the first message data; the first message data is the timing data corresponding to the current moment of the first logic device; The first message data is sent to the second logic device to instruct the second logic device to perform timing calibration based on the first message data, obtain a calibration timing sequence, and send the second message data to the first logic device; wherein, the second message data is the status data of the slave device collected by the second logic device based on the calibration timing sequence; After receiving the second message data sent by the second logic device, the second message data is sent to the master device to instruct the master device to perform differential logic operation based on the second message data and obtain the operation result.

2. The device communication method as described in claim 1, characterized in that, The acquisition of the first message data includes: Get the preset period; A first interrupt signal is generated according to the preset period; The first message data is obtained based on the first interrupt signal.

3. The device communication method as described in claim 2, characterized in that, The step of obtaining the first message data based on the first interrupt signal includes: When the first interrupt signal is detected, the first timing data corresponding to the current moment is obtained; The first time-series data is used to generate the first message data according to a preset format.

4. The device communication method as described in claim 1, characterized in that, The method further includes: Receive a first instruction sent by the master device; the first instruction is a control command generated by the master device based on the calculation result; The first instruction is sent to the second logic device to instruct the slave device to execute the first instruction.

5. The device communication method as described in claim 4, characterized in that, After receiving the first instruction, the method further includes: If the third message data is obtained, the third message data is sent to the second logic device; wherein the third message data is the timing data corresponding to the current moment of the first logic device; The first instruction is sent to the second logic device.

6. The device communication method as described in claim 1, characterized in that, The method further includes: If any device in the device communication system is configured to the first mode, the device corresponding to the first mode is determined to be the master device; then the device that is not configured to the first mode is determined to be the slave device.

7. A device communication system, characterized in that, It includes a master device and a slave device; the master device includes a first logic device, and the slave device includes a second logic device. The first logic device is used to implement the device communication method according to any one of claims 1 to 5.

8. The device communication system as described in claim 7, characterized in that, The first logic device and the second logic device are directly connected via optical fiber.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 5.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 5.

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