LDMOSFET device, manufacturing method and chip

Abstract

The invention relates to the technical field of semiconductors, and provides an LDMOSFET device, a manufacturing method and a chip. The device comprises a substrate, a body region, a drift region, an isolation region, a source region, a drain region and a gate structure, wherein the gate structure comprises a first polycrystalline silicon layer, a second polycrystalline silicon layer and an ONO dielectric layer; the first polycrystalline silicon layer is located above the body region and the drift region, the ONO dielectric layer is located on the surface of the first polycrystalline silicon layer, and the second polycrystalline silicon layer is located on the surface of the ONO dielectric layer; one end of the first polycrystalline silicon layer and one end of the ONO dielectric layer are connected with the isolation region, the first polycrystalline silicon layer serves as a floating gate, the second polycrystalline silicon layer serves as a control gate, and the first polycrystalline silicon layer, the ONO dielectric layer and the isolation region form a field plate structure; according to the invention, the functions of an LDMOS and a memory are integrated, and charges captured by the ONO dielectric layer are easily attracted to enter the floating gate and are stored in the floating gate, so that the starting of the device is controlled, and the breakdown voltage of the device is improved at the same time.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an LDMOSFET device, a method for manufacturing an LDMOSFET device, and a chip. Background Technology

[0002] BCD (Bipolar-CMOS-DMOS) technology is a series of process technologies that integrate bipolar transistors (Bipolar), complementary metal-oxide-semiconductor (CMOS), and double-diffused metal-oxide-semiconductor (DMOS) processes. With technological advancements, various device functions are integrated into the BCD process platform. BCD technology is widely used in the manufacture of power management chips, where LDMOSFETs (Lateral Double-diffused MOSFETs), as high-voltage devices with withstand voltages reaching 800V or even higher, play a crucial role. Existing LDMOSFET devices require an external gate control signal to control their turn-on. Furthermore, a higher breakdown voltage of the LDMOSFET indicates better withstand voltage. Currently, there is a need to research an LDMOSFET device structure and manufacturing method based on BCD technology that can control the device's turn-on without an external gate control signal and improve the device's breakdown voltage. Summary of the Invention

[0003] This invention provides an LDMOSFET device and its manufacturing method. The LDMOSFET device adopts an ONO dielectric layer gate structure, which can control the turn-on of the LDMOSFET without the need for an external gate control signal, while improving the breakdown voltage of the LDMOSFET. Moreover, the manufacturing method of this device is compatible with BCD process.

[0004] The LDMOSFET device provided by the present invention includes: a substrate, a body region, a drift region, an isolation region, a source region, a drain region, and a gate structure. The body region and the drift region are formed in the substrate, the source region is formed on the surface of the body region, and the isolation region and the drain region are formed on the surface of the drift region. The gate structure includes: a first polysilicon layer, a second polysilicon layer, and an ONO dielectric layer. The first polysilicon layer is located above the bulk region and the drift region, the ONO dielectric layer is located on the surface of the first polysilicon layer, and the second polysilicon layer is located on the surface of the ONO dielectric layer. The first polysilicon layer serves as a floating gate, the second polysilicon layer serves as a control gate, one end of the first polysilicon layer and one end of the ONO dielectric layer are connected to the isolation region, and the first polysilicon layer, the ONO dielectric layer and the isolation region constitute a field plate structure. The first polysilicon layer, the second polysilicon layer, and the ONO dielectric layer constitute a capacitor structure. The first polysilicon layer and the ONO dielectric layer can store charge to control the turn-on state of the LDMOSFET device.

[0005] In this embodiment of the invention, the other end of the ONO dielectric layer is connected to the source region or the body region.

[0006] In this embodiment of the invention, the ONO dielectric layer includes: a first oxide layer, a second oxide layer, and a nitride layer located between the first oxide layer and the second oxide layer; The first oxide layer is formed on the surface of the first polysilicon layer, the nitride layer is formed on the surface of the first oxide layer, and the second oxide layer is formed on the surface of the nitride layer.

[0007] In this embodiment of the invention, the first oxide layer and the second oxide layer are made of silicon dioxide, and the nitride layer is made of silicon nitride.

[0008] In this embodiment of the invention, the LDMOSFET device further includes: a well region, a first shallow trench isolation structure, and a second shallow trench isolation structure. The well region is located below the body region and the drift region. The first shallow trench isolation structure is located at the junction of the drift region and the well region. The second shallow trench isolation structure is located at the junction of the well region and the substrate.

[0009] In this embodiment of the invention, the LDMOSFET device further includes: a first contact terminal, a second contact terminal, and a third contact terminal; The first contact end is formed on the surface of the body region and is adjacent to the source region; The second contact end is formed on the surface of the well region and is located between the first shallow trench isolation structure and the second shallow trench isolation structure; The third contact terminal is formed on the surface of the substrate.

[0010] In this embodiment of the invention, the LDMOSFET device further includes: a plurality of mutually isolated metal electrodes, which are respectively connected to the second polysilicon layer, the drain region and the source region.

[0011] The present invention also provides a method for manufacturing the above-described LDMOSFET device, the method comprising: Well regions, bulk regions, and drift regions are formed in the substrate; An isolation zone is formed within the drift zone; A first polysilicon layer serving as a floating gate is formed on the bulk region and the drift region, with one end of the first polysilicon layer connected to the isolation region, and the first polysilicon layer and the isolation region forming a field plate structure. An ONO dielectric layer is formed on the surface of the first polysilicon layer; A second polysilicon layer is formed on the surface of the ONO dielectric layer as a control gate, such that the first polysilicon layer, the ONO dielectric layer and the second polysilicon layer constitute a capacitor structure. The source region is formed on the surface of the solid region, and the drain region is formed on the surface of the drift region.

[0012] In this embodiment of the invention, forming an isolation zone within the drift region includes: Shallow trench isolation technology is used to form shallow trench isolation structures at the junction of the drift region and the well region, as well as at the junction of the well region and the substrate. The LOCOS isolation region is formed on the surface of the drift region using the LOCOS process.

[0013] In this embodiment of the invention, a first polysilicon layer is formed on the body region and the drift region, comprising: A gate oxide layer is formed on the surface of the bulk region and the drift region; N-type doped polysilicon is deposited on the surface of the gate oxide layer, and surface planarization is performed to make the surface of the deposited polysilicon flush with the top surface of the isolation region. The deposited polysilicon is etched to form the first polysilicon layer that is in contact with the isolation region.

[0014] In this embodiment of the invention, an ONO dielectric layer is formed on the surface of the first polysilicon layer, comprising: A thermal oxidation process is performed on the surface of a substrate with a first polycrystalline silicon layer to form silicon dioxide as the first oxide layer. A silicon nitride layer is formed by depositing silicon nitride on the surface of the first oxide layer; A second oxide layer is formed by depositing silicon dioxide on the surface of the nitride layer; The first oxide layer, the nitride layer, and the second oxide layer constitute an ONO dielectric layer.

[0015] In this embodiment of the invention, a second polysilicon layer is formed on the surface of the ONO dielectric layer, comprising: N-type doped polysilicon is deposited on the surface of the ONO dielectric layer to form a second polysilicon layer; The ONO dielectric layer and the second polysilicon layer are etched so that one end of the etched ONO dielectric layer is connected to the isolation region and the other end is connected to the body region.

[0016] In this embodiment of the invention, a source region is formed on the surface of the body region, and a drain region is formed on the surface of the drift region, including: Photolithography is performed on the surfaces of the solid region and the drift region to form regional patterns; N-type ions are injected into the regional patterns of the body region and the drift region, respectively, to form the source region and the drain region.

[0017] In this embodiment of the invention, the method further includes: P-type ions are implanted into the region adjacent to the source region on the surface of the bulk region to form the first contact end; N-type ions are implanted into the surface of the trap region to form a second contact end; P-type ions are implanted into the surface of the substrate to form a third contact terminal.

[0018] The present invention also provides a chip comprising the above-described LDMOSFET device.

[0019] The LDMOSFET device of this invention employs a capacitor structure with a first polysilicon layer, an ONO dielectric layer, and a second polysilicon layer as its gate. In this gate structure, the first polysilicon layer serves as a floating gate, and the second polysilicon layer serves as a control gate. Since the ONO dielectric layer can trap charge, the trapped charge is easily attracted into and stored in the floating gate. Therefore, the floating gate can store more charge, making it easier to control the turn-on of the LDMOSFET device. Furthermore, the first polysilicon layer, acting as the floating gate, together with the ONO dielectric layer and the isolation region, constitutes a field plate structure. Because the ONO dielectric layer (the intermediate silicon nitride layer) can trap charge, it can further reduce the surface electric field of the device and improve its breakdown voltage. The LDMOSFET device of this invention integrates the functions of an LDMOS transistor and a memory, allowing for turn-on control of the LDMOSFET without an external gate control signal, making it suitable for applications without a power supply.

[0020] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description

[0021] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the structure of an LDMOSFET device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of an LDMOSFET device provided in another embodiment of the present invention; Figure 3 This is a flowchart of a method for manufacturing an LDMOSFET device provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of the well region, body region and drift region formed in the manufacturing method provided in the embodiments of the present invention; Figure 5 This is a schematic diagram of the shallow trench isolation structure formed in the manufacturing method provided in the embodiments of the present invention; Figure 6 This is a schematic diagram of the structure of the LOCOS isolation region formed in the manufacturing method provided in the embodiments of the present invention; Figure 7 This is a schematic diagram of the structure of the first polycrystalline silicon layer formed in the manufacturing method provided in the embodiments of the present invention; Figure 8 This is a schematic diagram of the structure of the ONO dielectric layer formed in the manufacturing method provided in the embodiment of the present invention; Figure 9 This is a schematic diagram of the gate structure formed in the manufacturing method provided in the embodiments of the present invention; Figure 10 This is a schematic diagram of the source region, drain region, and contact end formed in the manufacturing method provided in the embodiments of the present invention; Figure 11 This is a schematic diagram of the structure of the metal electrode formed in the manufacturing method provided in the embodiment of the present invention.

[0022] Explanation of reference numerals in the attached figures 1-Substrate, 2-Trap region, 3-Bulk region, 4-Drift region, 5-LOCOS isolation region 6-First shallow trench isolation structure, 7-Second shallow trench isolation structure, 8-First polysilicon layer 9-ONO dielectric layer, 9a-first oxide layer, 9b-nitride layer, 9c-second oxide layer. 10-Second polysilicon layer, 11-Source region, 12-Drain region, 13-First contact terminal, 14-Second contact end, 15-Third contact end, 16-Isolation dielectric layer, 17-Metal electrode. Detailed Implementation

[0023] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0024] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "surface," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0025] In this invention, unless otherwise explicitly specified and limited, the terms "connected," "interlocked," and "linked" should be interpreted broadly. For example, they can refer to mechanical connections, electrical connections, or connections that allow for mutual communication; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0026] Figure 1 This is a schematic diagram of the structure of an LDMOSFET device provided in an embodiment of the present invention. Figure 1As shown, the LDMOSFET device provided in this embodiment includes: a substrate 1, a body region 3, a drift region 4, a LOCOS isolation region 5, a source region 11, a drain region 12, and a gate structure. The body region 3 and the drift region 4 are formed in the substrate 1, the source region 11 is formed on the surface of the body region 3, and the LOCOS isolation region 5 and the drain region 12 are formed on the surface of the drift region 4. The gate structure includes: a first polysilicon layer 8, a second polysilicon layer 10, and an ONO dielectric layer (9a, 9b, 9c). The first polysilicon layer 8 is located above the body region 3 and the drift region 4, the ONO dielectric layer is located on the surface of the first polysilicon layer 8, and the second polysilicon layer 10 is located on the surface of the ONO dielectric layer. One end of the first polysilicon layer 8 and one end of the ONO dielectric layer are connected to the LOCOS isolation region 5, and the other end of the ONO dielectric layer is connected to the source region 11 or the body region 3. The first polysilicon layer 8, the ONO dielectric layer, and the LOCOS isolation region 5 constitute a field plate structure. Since the ONO dielectric layer in this field plate structure can store charge, it can further reduce the surface electric field of the device and improve the breakdown voltage of the device. The first polysilicon layer 8 also serves as a floating gate, and the second polysilicon layer 10 serves as a control gate. The first polysilicon layer 8, the second polysilicon layer 10, and the ONO dielectric layers (9a, 9b, 9c) constitute a capacitor structure. The intermediate layer (9b) between the first polysilicon layer 8 and the ONO dielectric layer can store charge and control the turn-on state of the LDMOSFET device.

[0027] In this embodiment, the ONO dielectric layer includes a first oxide layer 9a, a second oxide layer 9c, and a nitride layer 9b located between the first oxide layer 9a and the second oxide layer 9c. The first oxide layer 9a is formed on the surface of the first polysilicon layer 8, the nitride layer 9b is formed on the surface of the first oxide layer 9a, and the second oxide layer 9c is formed on the surface of the nitride layer 9b. The first oxide layer 9a and the second oxide layer 9c can be made of silicon dioxide, and the nitride layer 9b can be made of silicon nitride.

[0028] Figure 2 This is a schematic diagram of the structure of an LDMOSFET device provided in another embodiment of the present invention. Figure 2As shown, the LDMOSFET device provided in this embodiment includes: a substrate 1, a well region 2, a body region 3, a drift region 4, a LOCOS isolation region 5, a source region 11, a drain region 12, and a gate structure. The well region 2, body region 3, and drift region 4 are formed on the substrate 1. The well region 2 is located below the body region 3 and drift region 4. The source region 11 is formed on the surface of the body region 3. The LOCOS isolation region 5 and drain region 12 are formed on the surface of the drift region 4. The gate structure includes: a first polysilicon layer 8, a second polysilicon layer 10, and an ONO dielectric layer 9. The first polysilicon layer 8 is located above the body region 3 and drift region 4. The ONO dielectric layer 9 is located on the surface of the first polysilicon layer 8, and the second polysilicon layer 10 is located on the surface of the ONO dielectric layer 9. One end of the first polysilicon layer 8 and one end of the ONO dielectric layer 9 are connected to the LOCOS isolation region 5, and the other end of the ONO dielectric layer 9 is connected to the source region 11 or the body region 3. The first polysilicon layer 8, the ONO dielectric layer 9, and the LOCOS isolation region 5 constitute a field plate structure. Since the ONO dielectric layer 9 in this field plate structure can store charge, it can further reduce the surface electric field of the device and improve the breakdown voltage. The first polysilicon layer 8 also serves as a floating gate, and the second polysilicon layer 10 serves as a control gate. The first polysilicon layer 8, the second polysilicon layer 10, and the ONO dielectric layer 9 constitute a capacitor structure. The first polysilicon layer 8 and the ONO dielectric layer 9 can store charge and control the turn-on state of the LDMOSFET device.

[0029] Figure 2 The first oxide layer 9a, nitride layer 9b, and second oxide layer 9c of the ONO dielectric layer 9 are not labeled. Figure 2 For the specific structure of the ONO dielectric layer 9, please refer to Figure 1 To understand.

[0030] In this embodiment, the ONO dielectric layer 9 includes a first oxide layer 9a, a second oxide layer 9c, and a nitride layer 9b located between the first oxide layer 9a and the second oxide layer 9c. The first oxide layer 9a is formed on the surface of the first polysilicon layer 8, the nitride layer 9b is formed on the surface of the first oxide layer 9a, and the second oxide layer 9c is formed on the surface of the nitride layer 9b. The first oxide layer 9a and the second oxide layer 9c can be made of silicon dioxide, and the nitride layer 9b can be made of silicon nitride.

[0031] In this embodiment, the LDMOSFET device further includes a first shallow trench isolation structure 6 and a second shallow trench isolation structure 7. The first shallow trench isolation structure 6 is located at the junction of the drift region 4 and the well region 2, and the second shallow trench isolation structure 7 is located at the junction of the well region 2 and the substrate 1.

[0032] In this embodiment, the LDMOSFET device further includes a first contact terminal 13, a second contact terminal 14, and a third contact terminal 15. The first contact terminal 13 is formed on the surface of the body region 3 and is adjacent to the source region 11; the second contact terminal 14 is formed on the surface of the well region 2 and is located between the first shallow trench isolation structure 6 and the second shallow trench isolation structure 7; the third contact terminal 15 is formed on the surface of the substrate 1. The conductivity type (P-type) of the first contact terminal 13 is different from the conductivity type (N-type) of the second contact terminal 14, while the conductivity type (P-type) of the first contact terminal 13 is the same as the conductivity type (P-type) of the third contact terminal 15.

[0033] In this embodiment, the LDMOSFET device further includes a plurality of mutually isolated metal electrodes 17, which are respectively connected to the second polysilicon layer 10, the source region 11, the drain region 12, the first contact terminal 13, the second contact terminal 14, and the third contact terminal 15. The source region 11 and the first contact terminal 13 are connected to the same metal electrode 17, while the second polysilicon layer 10, the source region 11, the drain region 12, the second contact terminal 14, and the third contact terminal 15 are respectively connected to different metal electrodes 17. An isolation dielectric layer 16 separates adjacent metal electrodes 17, and the different metal electrodes 17 are isolated from each other by the isolation dielectric layer 16.

[0034] In the LDMOSFET device described in the above embodiment, when a high voltage is applied to the control gate relative to the substrate, electrons in the drift region are attracted and tunnel into the floating gate. Since the silicon nitride layer in the middle of the ONO dielectric layer can capture electrons, more electrons are attracted into the floating gate and stored therein. After the applied voltage is stopped, because the floating gate layer is wrapped by an insulating layer, the electrons in the floating gate layer remain stored there. The charge stored in the floating gate layer enables the LDMOSFET device to turn on. For example, when a high voltage is applied to the substrate relative to the gate, the electrons stored in the floating gate layer tunnel back to the substrate (drift region) under the influence of the electric field, at which point the LDMOSFET device is in the turned-on state.

[0035] The LDMOSFET device of this invention employs a capacitor structure with a first polysilicon layer, an ONO dielectric layer, and a second polysilicon layer as its gate. The first polysilicon layer acts as a floating gate, and the second polysilicon layer acts as a control gate. Since the ONO dielectric layer can trap charge, the trapped charge is easily attracted into and stored in the floating gate, allowing it to store more charge and thus control the LDMOSFET device's turn-on. Furthermore, the first polysilicon layer, acting as the floating gate, together with the ONO dielectric layer and the LOCOS isolation region, forms a field plate structure. Because the ONO dielectric layer (the intermediate silicon nitride layer) can trap charge, it further reduces the surface electric field of the device and increases its breakdown voltage. This LDMOSFET device integrates the functions of an LDMOS transistor and a memory, allowing for LDMOSFET turn-on control without an external gate control signal, making it suitable for applications without a power supply.

[0036] This invention also provides a method for manufacturing the LDMOSFET device described above. For example... Figure 3 As shown, the manufacturing method of the LDMOSFET device provided in this embodiment includes the following steps: S310 forms a well region, a bulk region, and a drift region in the substrate; S320 forms an isolation zone within the drift zone; S330, a first polysilicon layer serving as a floating gate is formed on the bulk region and the drift region; S340, an ONO dielectric layer is formed on the surface of the first polysilicon layer; S350, a second polysilicon layer serving as a control gate is formed on the surface of the ONO dielectric layer; S360 forms a source region on the surface of the in-body region and a drain region on the surface of the drift region.

[0037] The LDMOSFET device provided in this embodiment of the invention can be either an N-type LDMOSFET or a P-type LDMOSFET. When the LDMOSFET device is an N-type LDMOSFET, the first doping type is P-type and the second doping type is N-type; when the LDMOSFET device is a P-type LDMOSFET, the first doping type is N-type and the second doping type is P-type. The following describes the manufacturing method steps of the above-mentioned LDMOSFET device in detail, using an N-type LDMOSFET as an example.

[0038] In step S310 above, a substrate 1 is first provided. Substrate 1 is one of a silicon substrate, a silicon-germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate. In this embodiment, substrate 1 is a P-type silicon substrate. Then, a thin oxide layer is grown on the surface of substrate 1 to form a photoresist layer. The photoresist is exposed and developed to form an ion implantation window. N-type ion implantation is performed on the substrate 1 through the ion implantation window to remove the photoresist. Another layer of photoresist is formed on the surface of substrate 1, and the photoresist is exposed and developed to form an ion implantation window. N-type ion implantation is performed on the substrate 1 through the ion implantation window to remove the photoresist. Another layer of photoresist is formed on the surface of substrate 1, and the photoresist is exposed and developed to form an ion implantation window. P-type ion implantation is performed on the substrate 1 through the ion implantation window to remove the photoresist. High-temperature propulsion and wet removal of the oxide layer on the surface of substrate 1 are then performed to form a substrate 1 with a structure resembling a silicon substrate, silicon-germanium substrate, silicon-on-insulator substrate, or germanium-on-insulator substrate. Figure 4 The trap region 2, body region 3, and drift region 4 are shown.

[0039] In step S320 above, a shallow trench isolation (STI) structure is formed at the junction of drift region 4 and well region 2, and at the junction of well region 2 and substrate 1, using a shallow trench isolation process. Specifically, in Figure 4 A thin layer of silicon dioxide (SiO2) is oxidized again on the structure shown, followed by vapor deposition of silicon nitride (Si3N4). Photolithography is then performed, and the silicon nitride and silicon dioxide are dry-etched. The substrate 1 is dry-etched, forming a trench of the first shallow trench isolation structure 6 at the boundary between the drift region 4 and the well region 2, and a trench of the second shallow trench isolation structure 7 at the boundary between the well region 2 and the substrate 1. The trench of the second shallow trench isolation structure 7 is adjacent to the well region 2. Silicon dioxide is deposited within the trenches, followed by high-temperature annealing, chemical mechanical polishing to remove the surface silicon dioxide dielectric, and wet removal of the silicon nitride and silicon dioxide from the surface of the substrate 1, forming the structure shown. Figure 5 The first shallow trench isolation structure 6 and the second shallow trench isolation structure 7 are shown.

[0040] Next, a LOCOS isolation region 5 is fabricated within drift region 4 using a localized silicon oxidation (LOCOS) process, serving as the isolation oxide layer for the field plate. Specifically, in... Figure 5 The structure shown is formed by thermally oxidizing a thin layer of silicon dioxide, depositing a layer of silicon nitride on the silicon dioxide using low-pressure chemical vapor deposition (LPCVD), forming a photoresist layer on the silicon nitride, exposing and developing the photoresist to form etching windows, and sequentially performing dry etching on the silicon nitride and silicon dioxide through these etching windows to expose a portion of the substrate 1. Then, thermal oxidation is performed, followed by wet removal of the silicon nitride to form the structure shown. Figure 6 The LOCOS isolation zone 5 is shown.

[0041] In step S330 above, a gate oxide layer is formed on the surface of the body region 3 and the drift region 4. N-type heavily doped polysilicon is deposited on the surface of the gate oxide layer, and a surface planarization process is performed to make the surface of the deposited polysilicon flush with the top surface of the isolation region 5. Dry etching is then performed on the deposited polysilicon to form a first polysilicon layer 8. One end of the first polysilicon layer 8 is connected to the LOCOS isolation region 5, and the first polysilicon layer 8 and the LOCOS isolation region 5 constitute a field plate structure. Specifically, in... Figure 6 The surface of the structure shown is subjected to thermal oxidation to form a thin oxide layer. The oxide layers on the surfaces of body region 3 and drift region 4 serve as gate oxide layers. Next, a layer of heavily doped N-type polysilicon is deposited using low-pressure chemical vapor deposition (LPCVD), followed by chemical mechanical polishing (CMP) to remove excess polysilicon down to the height of the LOCOS isolation region 5. Finally, the heavily doped N-type polysilicon is dry etched to form the structure shown. Figure 7 The first polycrystalline silicon layer 8 is shown.

[0042] In step S340 above, Figure 7 The surface of the structure shown is subjected to thermal oxidation treatment to form a thin layer of silicon dioxide (SiO2) as the first oxide layer 9a. A thin layer of silicon nitride (Si3N4) is deposited on the surface of the first oxide layer 9a using chemical vapor deposition (CVD) or atomic layer deposition (ALD) to form a nitride layer 9b. A thin layer of silicon dioxide (SiO2) is then deposited on the surface of the nitride layer 9b to form the second oxide layer 9c. The first oxide layer 9a, the nitride layer 9b, and the second oxide layer 9c constitute the ONO dielectric layer 9, forming a structure as shown... Figure 8 The structure shown is as follows. Since the ONO dielectric layer needs to be thin enough to obtain a better capacitive coupling effect, atomic layer deposition (ALD) is used to deposit silicon dioxide (SiO2) and silicon nitride (Si3N4) to obtain a thin ONO dielectric layer with better uniformity.

[0043] In step S350 above, as follows Figure 8 The structure shown is formed by depositing an N-type heavily doped polysilicon layer 10 on the surface of the second oxide layer 9c using low-pressure chemical vapor deposition (LPCVD). Then, the second polysilicon layer 10 and the ONO dielectric layer 9 are dry etched, so that one end of the etched ONO dielectric layer 9 is connected to the LOCOS isolation region 5, and the other end is connected to the body region 3, forming a structure as shown. Figure 9 The gate structure shown.

[0044] In step S360 above, photolithography is performed on the surfaces of the body region 3 and the drift region 4 to form region patterns. N-type ions are then implanted into the region patterns of the body region 3 and the drift region 4 to form the source region 11 and the drain region 12, respectively. During this process, P-type ions can also be implanted simultaneously in the region of the body region 3 adjacent to the source region 11 to form a first contact terminal 13, N-type ions can be implanted on the surface of the well region 2 to form a second contact terminal 14, and P-type ions can be implanted on the surface of the substrate 1 to form a third contact terminal 15, forming a... Figure 10 The structure shown.

[0045] Finally, on the surface of the substrate 1 where the gate structure, source region 11, and drain region 12 are formed ( Figure 10 Silicon dioxide is deposited on the surface of the structure shown to form an isolation dielectric layer 16. The isolation dielectric layer 16 is then dry-etched to form contact holes. Next, physical vapor deposition (PVD) is used to deposit metal inside and on the surface of the contact holes. The metal is then dry-etched and alloyed to form a structure as shown. Figure 11 The metal electrode 17 shown is connected to the same metal electrode 17, with the source region 11 and the first contact terminal 13 connected to the same metal electrode 17. The second polysilicon layer 10, the source region 11, the drain region 12, the second contact terminal 14, and the third contact terminal 15 are connected to different metal electrodes 17, and adjacent metal electrodes 17 are isolated by an isolation dielectric layer 16.

[0046] The present invention also provides a chip comprising the above-described LDMOSFET device.

[0047] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Furthermore, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. As long as such combination does not violate the spirit of the embodiments of the present invention, it should also be considered as the content disclosed in the embodiments of the present invention.

Claims

1. An LDMOSFET device, comprising: A substrate, a body region, a drift region, an isolation region, a source region, a drain region, and a gate structure, wherein the body region and the drift region are formed in the substrate, the source region is formed on the surface of the body region, and the isolation region and the drain region are formed on the surface of the drift region, characterized in that the gate structure comprises: a first polysilicon layer, a second polysilicon layer, and an ONO dielectric layer. The first polysilicon layer is located above the bulk region and the drift region, the ONO dielectric layer is located on the surface of the first polysilicon layer, and the second polysilicon layer is located on the surface of the ONO dielectric layer. The first polysilicon layer serves as a floating gate, the second polysilicon layer serves as a control gate, one end of the first polysilicon layer and one end of the ONO dielectric layer are connected to the isolation region, and the first polysilicon layer, the ONO dielectric layer and the isolation region constitute a field plate structure.

2. The LDMOSFET device according to claim 1, characterized in that, The other end of the ONO dielectric layer is connected to the source region or the body region.

3. The LDMOSFET device according to claim 1, characterized in that, The ONO dielectric layer includes: a first oxide layer, a second oxide layer, and a nitride layer located between the first oxide layer and the second oxide layer; The first oxide layer is formed on the surface of the first polysilicon layer, the nitride layer is formed on the surface of the first oxide layer, and the second oxide layer is formed on the surface of the nitride layer.

4. The LDMOSFET device according to claim 3, characterized in that, The first oxide layer and the second oxide layer are made of silicon dioxide, and the nitride layer is made of silicon nitride.

5. The LDMOSFET device according to claim 1, characterized in that, Also includes: The system comprises a well region, a first shallow trench isolation structure, and a second shallow trench isolation structure. The well region is located below the body region and the drift region. The first shallow trench isolation structure is located at the boundary between the drift region and the well region. The second shallow trench isolation structure is located at the boundary between the well region and the substrate.

6. The LDMOSFET device according to claim 5, characterized in that, Also includes: First contact end, second contact end, and third contact end; The first contact end is formed on the surface of the body region and is adjacent to the source region; The second contact end is formed on the surface of the well region and is located between the first shallow trench isolation structure and the second shallow trench isolation structure; The third contact terminal is formed on the surface of the substrate.

7. The LDMOSFET device according to claim 1, characterized in that, Also includes: Multiple isolated metal electrodes are respectively connected to a second polysilicon layer, a drain region, and a source region.

8. A method for manufacturing an LDMOSFET device, wherein the LDMOSFET device is the LDMOSFET device according to claim 1, characterized in that, The method includes: Well regions, bulk regions, and drift regions are formed in the substrate; An isolation zone is formed within the drift zone; A first polysilicon layer is formed on the bulk region and the drift region, with one end of the first polysilicon layer connected to the isolation region, and the first polysilicon layer and the isolation region forming a field plate structure. An ONO dielectric layer is formed on the surface of the first polysilicon layer; A second polysilicon layer is formed on the surface of the ONO dielectric layer, so that the first polysilicon layer, the ONO dielectric layer and the second polysilicon layer constitute a capacitor structure. The source region is formed on the surface of the solid region, and the drain region is formed on the surface of the drift region.

9. The method for manufacturing an LDMOSFET device according to claim 8, characterized in that, An isolation zone is formed within the drift zone, including: Shallow trench isolation technology is used to form shallow trench isolation structures at the junction of the drift region and the well region, as well as at the junction of the well region and the substrate. The LOCOS isolation region is formed on the surface of the drift region using the LOCOS process.

10. The method for manufacturing an LDMOSFET device according to claim 8, characterized in that, A first polysilicon layer is formed on the bulk region and the drift region, including: A gate oxide layer is formed on the surface of the bulk region and the drift region; N-type doped polysilicon is deposited on the surface of the gate oxide layer, and surface planarization is performed to make the surface of the deposited polysilicon flush with the top surface of the isolation region. The deposited polysilicon is etched to form the first polysilicon layer that is in contact with the isolation region.

11. The method for manufacturing an LDMOSFET device according to claim 8, characterized in that, An ONO dielectric layer is formed on the surface of the first polysilicon layer, including: A thermal oxidation process is performed on the surface of a substrate with a first polycrystalline silicon layer to form silicon dioxide as the first oxide layer. A silicon nitride layer is formed by depositing silicon nitride on the surface of the first oxide layer; A second oxide layer is formed by depositing silicon dioxide on the surface of the nitride layer; The first oxide layer, the nitride layer, and the second oxide layer constitute an ONO dielectric layer.

12. The method for manufacturing an LDMOSFET device according to claim 8, characterized in that, A second polysilicon layer is formed on the surface of the ONO dielectric layer, including: N-type doped polysilicon is deposited on the surface of the ONO dielectric layer to form a second polysilicon layer; The ONO dielectric layer and the second polysilicon layer are etched so that one end of the etched ONO dielectric layer is connected to the isolation region and the other end is connected to the body region.

13. The method for manufacturing an LDMOSFET device according to claim 8, characterized in that, A source region is formed on the surface of the bulk region, and a drain region is formed on the surface of the drift region, including: Photolithography is performed on the surfaces of the solid region and the drift region to form regional patterns; N-type ions are injected into the regional patterns of the body region and the drift region, respectively, to form the source region and the drain region.

14. The method for manufacturing an LDMOSFET device according to claim 13, characterized in that, The method further includes: P-type ions are implanted into the region adjacent to the source region on the surface of the bulk region to form the first contact end; N-type ions are implanted into the surface of the trap region to form a second contact end; P-type ions are implanted into the surface of the substrate to form a third contact terminal.

15. A chip, characterized in that, The chip includes the LDMOSFET device according to any one of claims 1-7.

Images