A method for manufacturing an esd device and an esd device

Abstract

The application provides a preparation method of an ESD device and the ESD device. The preparation method of the ESD device comprises the following steps: providing a substrate, wherein the substrate comprises a substrate, a high-voltage P-well region and a deep N-well region formed on the substrate, and a first oxide layer covering surfaces of the high-voltage P-well region and the deep N-well region, and the high-voltage P-well region and the deep N-well region are arranged along a first direction parallel to the substrate; forming a first trench isolation structure on the substrate, wherein the first trench isolation structure separates the high-voltage P-well region and the deep N-well region; forming a gate-grounded NMOS structure on the high-voltage P-well region, and forming a Schottky barrier diode structure and a voltage regulator diode structure on the deep N-well region, wherein the Schottky barrier diode structure and the voltage regulator diode structure are staggered along a second direction parallel to the substrate, and the second direction is perpendicular to the first direction. The ESD device of the application can form a stepped protection, smooth transition ESD impact, make the current distribution uniform, and improve the reliability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating an ESD device and the ESD device itself. Background Technology

[0002] With the continuous advancement of semiconductor manufacturing processes, the failure of chips and electronic products caused by electrostatic discharge (ESD) has become increasingly prominent, posing a significant challenge for engineers. Currently, the ESD protection devices used in 40HV platforms are primarily based on the gate-grounded N-MOSFET (GGNMOS) principle. Their working mechanism is as follows: when electrostatic discharge current flows in from the anode, the reverse breakdown effect between the low-voltage N-well (LVNW) and high-voltage P-well (HVPW) regions raises the potential of the HVPW, thereby triggering the parasitic bipolar junction transistor (BJT) structure (composed of the anode N-well and the high-voltage P-well). + Drain — LVNW / Cathode P + —LVPW—HVPW / Cathode N + —The LVNW structure is activated to discharge ESD current. The trigger voltage of this structure is typically above 4V, making it suitable for ESD protection in medium to high voltage processes. However, in more advanced processes, such high trigger voltages are insufficient to meet the protection requirements of sensitive circuits and may even cause damage to internal sensitive components due to response lag. Summary of the Invention

[0003] This invention provides a method for fabricating an ESD device and an ESD device, thereby reducing the trigger voltage of the ESD device.

[0004] The present invention provides a method for fabricating an ESD device, comprising the following steps:

[0005] A substrate is provided, the substrate including a substrate and a high-voltage P-well region and a deep N-well region formed on the substrate, and a first oxide layer covering the surfaces of the high-voltage P-well region and the deep N-well region, the high-voltage P-well region and the deep N-well region being arranged along a first direction parallel to the substrate;

[0006] A first trench isolation structure is formed on the substrate, the first trench isolation structure isolating the high-voltage P-well region and the deep N-well region;

[0007] A gate-grounded NMOS structure is formed on the high-voltage P-well region, and a Schottky barrier diode structure and a Zener diode structure are formed on the deep N-well region. The Schottky barrier diode structure and the Zener diode structure are arranged alternately along a second direction parallel to the substrate, and the second direction is perpendicular to the first direction.

[0008] In one embodiment of the present invention, there are multiple first trench isolation structures, which are spaced apart along the first direction. Along the direction from the high-voltage P-well region to the deep N-well region, the high-voltage P-well region is sequentially isolated into a P-ion implantation region, an N-ion implantation region, a gate formation region, and an N-ion implantation region. The deep N-well region is sequentially isolated to form a first region and an N-ion implantation region. Simultaneously with forming multiple first trench isolation structures on the substrate, the method for fabricating the ESD device further includes forming multiple second trench isolation structures on the substrate. These multiple second trench isolation structures are located in the middle of the first region and are spaced apart along the second direction. N-ion implantation regions are formed within the gaps between the second trench isolation structures, and P-ion implantation regions extending along the second direction are formed within the first regions on both sides of the second trench isolation structures within the first region.

[0009] In one embodiment of the present invention, a gate-grounded NMOS structure is formed on the high-voltage P-well region, and a Schottky barrier diode structure and a Zener diode structure are formed on the deep N-well region. The Schottky barrier diode structure and the Zener diode structure are arranged alternately along a second direction parallel to the substrate, comprising the following steps:

[0010] The P-ion implantation region is subjected to a first P-ion implantation to form a low-pressure P-well region, and the N-ion implantation region is subjected to a first N-ion implantation to form a low-pressure N-well region.

[0011] A gate structure is formed on the surface of the gate forming region;

[0012] A second P-ion implantation is performed on the P-ion implantation region to form a P+ doped region, and a second N-ion implantation is performed on the N-ion implantation region outside the first region to form an N+ doped region.

[0013] In one embodiment of the present invention, while forming a plurality of first trench isolation structures on the substrate, the method for fabricating the ESD device further includes forming a plurality of second trench isolation structures on the substrate, comprising the following steps:

[0014] A patterned third photoresist layer is formed on the surface of the first oxide layer, and the third photoresist layer exposes the first trench region and the second trench region;

[0015] The first oxide layer and the substrate are etched sequentially to form a plurality of first trenches and a plurality of second trenches on the substrate;

[0016] An insulating medium is deposited in a plurality of first trenches and a plurality of second trenches until the insulating medium covers the surface of the first oxide layer;

[0017] The insulating medium is planarized until it is flush with the first oxide layer, forming a plurality of first trench isolation structures and a plurality of second trench isolation structures.

[0018] In one embodiment of the present invention, the ion concentration in the high-pressure P-trap region is 5E11~1E13 / cm³. 3 The ion concentration in the deep N-well region is 5E11~1E13 / cm³. 3 .

[0019] In one embodiment of the present invention, the ion concentration in the low-pressure P-trap region is 1E12~5E14 / cm³. 3 The ion concentration in the low-pressure N-trap region is 1E12~5E14 / cm³. 3 The ion concentration of the P+ doped region is 5E13~1E16 / cm³. 3 The ion concentration of the N+ doped region is 5E13~1E16 / cm³. 3 .

[0020] In one embodiment of the present invention, forming a gate structure on the surface of the gate forming region includes the following steps:

[0021] Remove the first oxide layer and form a nitride layer on the surface of the substrate;

[0022] The nitride layer is etched using a patterned photoresist as a mask layer, and the nitride layer exposes the gate formation region;

[0023] A gate oxide layer is formed on the surface of the gate forming region;

[0024] A gate material layer is formed on the surface of the gate oxide layer.

[0025] In one embodiment of the present invention, after forming the P+ doped region and the N+ doped region, the fabrication method of the ESD device further includes forming a self-aligned silicide layer on the surface of the P-ion implantation region, the N-ion implantation region and the gate structure, comprising the following steps:

[0026] A self-aligned silicide barrier layer is deposited on the surface of the substrate, the self-aligned silicide barrier layer exposing the surfaces of the P-ion implantation region, the N-ion implantation region and the gate structure;

[0027] A first contact material layer is deposited on the surfaces of the P-ion implantation region, the N-ion implantation region, and the gate structure;

[0028] The first annealing process and the second annealing process are performed sequentially.

[0029] In one embodiment of the present invention, the method for preparing the substrate includes the following steps:

[0030] Provide the substrate;

[0031] The first oxide layer is deposited on the substrate;

[0032] A high-voltage P-well region is formed by implanting P-ions into the substrate using a patterned first photoresist layer as a mask layer.

[0033] A patterned second photoresist layer is used as a mask layer to perform N-ion implantation on the substrate to form a deep N-well region.

[0034] The present invention also provides an ESD device, the ESD device comprising a substrate, a gate-grounded NMOS structure, a Schottky barrier diode structure, and a Zener diode structure; the substrate comprises a substrate and a high-voltage P-well region and a deep N-well region formed on the substrate, the high-voltage P-well region and the deep N-well region being isolated by a trench isolation structure and arranged along a first direction parallel to the substrate; the gate-grounded NMOS structure is formed on the high-voltage P-well region; the Schottky barrier diode structure is disposed on the deep N-well region; the Zener diode structure is disposed on the deep N-well region and is staggered with the Schottky barrier diode structure along a second direction parallel to the substrate, the second direction being perpendicular to the first direction.

[0035] The beneficial effects of this invention are as follows: The proposed method for fabricating an ESD device involves a high-voltage P-well region and a deep N-well region isolated by a first trench isolation structure and arranged along a first direction parallel to the substrate. A gate-grounded NMOS structure is formed on the high-voltage P-well region, and a Schottky barrier diode structure and a Zener diode structure are formed on the deep N-well region. The Schottky barrier diode structure and the Zener diode structure are staggered along a second direction parallel to the substrate, perpendicular to the first direction. An unexpected effect of this invention is that when a low-energy pulse arrives, the extremely low forward voltage drop and picosecond-level response speed of the Schottky barrier diode structure can quickly clamp the ESD voltage. When a high-energy pulse arrives, multiple Schottky barrier diode structures connected in parallel can absorb the initial ESD spike. Subsequently, the Zener diode structure and the gate-grounded NMOS structure turn on to become the main discharge path, maintaining high current discharge capability. When the gate-grounded NMOS structure is connected in parallel with multiple Schottky barrier diode structures and Zener diode structures, multi-level voltage clamping can be formed to provide stepped protection at key potentials in the low and medium voltage ranges. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0037] In the attached diagram:

[0038] Figure 1 This is a flowchart illustrating the fabrication process of an ESD device according to an embodiment of the present invention.

[0039] Figure 2 This is a schematic diagram of forming a first oxide layer on a substrate according to an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the formation of a high-pressure P-well region provided in one embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of forming a deep N-well region according to an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of removing the second photoresist layer according to one embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of the formation of a third photoresist layer provided in one embodiment of the present invention;

[0044] Figure 7 This is a schematic diagram illustrating the formation of a first trench and a second trench according to one embodiment of the present invention;

[0045] Figure 8 This is a schematic diagram of the formation of a first trench isolation structure and a second trench isolation structure provided in one embodiment of the present invention;

[0046] Figure 9 This is a top view schematic diagram of the formation of the first trench isolation structure and the second trench isolation structure provided in one embodiment of the present invention;

[0047] Figure 10 This is a schematic diagram of the first P-ion implantation in a P-ion implantation region provided in one embodiment of the present invention;

[0048] Figure 11 This is a schematic diagram of the first N-ion implantation in an N-ion implantation region provided in one embodiment of the present invention;

[0049] Figure 12 This is a schematic diagram of the formation of a nitride layer provided in one embodiment of the present invention;

[0050] Figure 13 This is a schematic diagram of an etched nitride layer provided in one embodiment of the present invention;

[0051] Figure 14 This is a schematic diagram of the formation of a gate oxide layer provided in one embodiment of the present invention;

[0052] Figure 15 This is a schematic diagram of forming a polycrystalline silicon layer according to an embodiment of the present invention;

[0053] Figure 16 This is a schematic diagram of the formation of a gate material layer provided in one embodiment of the present invention;

[0054] Figure 17 This is a schematic diagram of a second P-ion implantation in a P-ion implantation region provided in one embodiment of the present invention;

[0055] Figure 18 This is a schematic diagram of a second N-ion implantation in an N-ion implantation region provided in one embodiment of the present invention;

[0056] Figure 19 for Figure 18 Corresponding top view diagram;

[0057] Figure 20 for Figure 19 Schematic diagram of the cross section along the BB direction;

[0058] Figure 21 This is a schematic diagram of the formation of a second oxide layer provided in one embodiment of the present invention;

[0059] Figure 22 This is a schematic diagram of the formation of a self-aligned silicide barrier layer provided in one embodiment of the present invention;

[0060] Figure 23 This is a schematic diagram of the formation of a first contact material layer provided in one embodiment of the present invention;

[0061] Figure 24 This is a schematic diagram of the formation of an initial self-aligned silicide layer provided in one embodiment of the present invention;

[0062] Figure 25 This is a schematic diagram of the formation of a self-aligned silicide layer provided in one embodiment of the present invention;

[0063] Figure 26 This is another schematic diagram of the formation of a self-aligned silicide layer provided in one embodiment of the present invention;

[0064] Figure 27 This is a schematic diagram of the electrode connections of an ESD device provided in one embodiment of the present invention;

[0065] Figure 28 This is a schematic diagram of the connection of another electrode of the ESD device provided in one embodiment of the present invention;

[0066] Figure 29 This is a current-voltage relationship diagram of an ESD device provided in one embodiment of the present invention and an existing ESD device.

[0067] The attached figures are labeled as follows:

[0068] 10. Substrate; 100. Substrate; 110. High-voltage P-well region; 120. Deep N-well region; 130. First trench isolation structure; 140. Second trench isolation structure; 150. P-ion implantation region; 151. Low-voltage P-well region; 152. P+ doped region; 160. N-ion implantation region; 161. Low-voltage N-well region; 162. N+ doped region; 170. Gate formation region; 171. Gate structure; 1711. Gate oxide layer; 1712. Gate material layer; 180. First region; 200. First Oxide layer; 300, First photoresist layer; 310, Second photoresist layer; 320, Third photoresist layer; 330, Fourth photoresist layer; 340, Fifth photoresist layer; 400, Nitride layer; 500, Polysilicon layer; 600, Second oxide layer; 610, Self-aligned silicide barrier layer; 700, First contact material layer; 710, Initial self-aligned silicide layer; 720, Self-aligned silicide layer; 20, Gate-grounded NMOS structure; 30, Schottky barrier diode structure; 40, Zener diode structure. Detailed Implementation

[0069] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0070] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0071] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0072] Please see Figures 1 to 20 This application provides a method for fabricating an ESD device, comprising the following steps:

[0073] S1, providing such Figure 5 The substrate 10 shown includes a substrate 100 and a high-voltage P-well region 110 and a deep N-well region 120 formed on the substrate 100, and a first oxide layer 200 covering the surfaces of the high-voltage P-well region 110 and the deep N-well region 120. The high-voltage P-well region 110 and the deep N-well region 120 are arranged along a first direction parallel to the substrate 100 (i.e., Figure 5 Arranged in the X direction.

[0074] S2, such as Figures 6 to 9 As shown, a first trench isolation structure 130 is formed on the substrate 10, which isolates the high-voltage P-well region 110 and the deep N-well region 120.

[0075] S3, such as Figures 10 to 20 As shown, a gate-grounded NMOS structure 20 is formed on the high-voltage P-well region 110, and a Schottky barrier diode structure 30 and a Zener diode structure 40 are formed on the deep N-well region 120. The Schottky barrier diode structure 30 and the Zener diode structure 40 are arranged along a second direction parallel to the substrate 100 (i.e., Figure 9 The Y-direction in the middle is arranged in an alternating pattern, and the second direction is perpendicular to the first direction.

[0076] The substrate 10 can be a commercially available semi-finished product or it can be prepared in-house. In one embodiment, the substrate 10 is prepared in-house based on the substrate 100. Please refer to [link to relevant documentation]. Figures 2 to 5 As shown, the preparation method of substrate 10 is as follows:

[0077] Please see Figure 2As shown, in step S1 of this invention, the substrate 100 can be any material suitable for forming a semiconductor structure, such as undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). This invention does not limit the specific material and thickness of the substrate 100, and the substrate 100 can be a p-doped semiconductor substrate 100 or an n-doped semiconductor substrate 100. The doping type of the impurities can be flexibly set according to the desired semiconductor structure. In this embodiment, the substrate 100 is, for example, a p-doped semiconductor substrate.

[0078] Please see Figure 2 As shown, in one embodiment of the present invention, a first oxide layer 200 is formed on the surface of the substrate 100. The first oxide layer 200 can serve as a protective layer for the substrate 100, protecting the substrate 100 it covers in subsequent processes and preventing unnecessary damage to the substrate 100. The material of the first oxide layer 200 can be silicon dioxide or similar materials, and the first oxide layer 200 can be formed by any one of the following methods: dry oxygen oxidation, wet oxygen oxidation, or in-situ steam generation (ISSG). In this embodiment, for example, the first oxide layer 200 is formed by dry oxygen oxidation. Exemplarily, the substrate 100 is placed in a furnace tube, oxygen is introduced, and the surface of the substrate 100 reacts with oxygen at a high temperature to form a dense first oxide layer 200. The preparation process of the substrate 10 may also include cleaning the substrate 100 before forming the first oxide layer 200 to remove impurities present on the surface of the substrate 100, preventing impurities from affecting subsequent processes and thus ensuring the performance of the device. For example, the substrate 100 can be cleaned by using a cleaning solution or by using a gas such as nitrogen to purge the substrate 100.

[0079] Please see Figures 3 to 5As shown, in one embodiment of the present invention, after forming a first oxide layer 200, a patterned first photoresist layer 300 is formed on the surface of the first oxide layer 200. Using the first photoresist layer 300 as a mask layer, P-type ion implantation is performed on the substrate 100 to form a high-voltage P-well region 110. The P-type ions are, for example, boron (B) or gallium (Ga). After removing the first photoresist layer 300, a patterned second photoresist layer 310 is formed on the surface of the first oxide layer 200. Using the second photoresist layer 310 as a mask layer, N-type ion implantation is performed on the substrate 100 to form a deep N-well region 120. The N-type ions are, for example, phosphorus (P) or arsenic (As). After forming the deep N-well region 120, the second photoresist layer 310 is removed. The high-voltage P-well region 110 and the deep N-well region 120 are arranged along a first direction parallel to the substrate 100. The type of photoresist material for the first photoresist layer 300 and the second photoresist layer 310 is not limited here; it can be a common positive photoresist material or a negative photoresist material. For example, the first photoresist layer 300 and the second photoresist layer 310 can be removed by wet cleaning or ashing. Exemplarily, the ion concentration in the high-voltage P-well region 110 can be 5E11~1E13 / cm³. 3 For example, 5E11 / cm 3 1E12 / cm 3 1E13 / cm 3 5E11~1E13 / cm 3 Any value in the range. The ion concentration in the deep N-well region 120 can be 5E11~1E13 / cm³. 3 For example, 5E11 / cm 3 1E12 / cm 3 1E13 / cm 3 5E11~1E13 / cm 3 Any value in the range.

[0080] In step S2 of this invention, the number of first trench isolation structures 130 is multiple. While forming multiple first trench isolation structures 130 on the substrate 10, the ESD device fabrication method also includes forming multiple second trench isolation structures 140 on the substrate 10. Please refer to... Figures 6 to 9 As shown, forming a plurality of first trench isolation structures 130 and a plurality of second trench isolation structures 140 on the substrate 10 includes the following steps:

[0081] Please see Figure 6 and Figure 7 As shown, in one embodiment of the present invention, a patterned third photoresist layer 320 is formed on the surface of the first oxide layer 200, and the third photoresist layer 320 exposes the first trench region and the second trench region. Figure 6In the area not covered by the third photoresist layer 320, the first oxide layer 200 and the substrate 100 are sequentially etched using the third photoresist layer 320 as a mask to form multiple first trenches and multiple second trenches. The number, location, depth, and width of the first and second trenches are set according to actual needs and are not limited here. In this embodiment, the first and second trenches extend from the first oxide layer 200 into the substrate 100, and the shapes of the first and second trenches are rectangular. The first oxide layer 200 and part of the substrate 100 can be removed sequentially by dry etching to form the first and second trenches. The etching gas includes, for example, one or a mixture of several of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or hydrogen bromide (HBr), or a combination of them and oxygen (O2). After the first and second trenches are formed, the third photoresist layer 320 is removed, for example, by wet cleaning or ashing.

[0082] Please see Figure 8 and Figure 9 As shown, in one embodiment of the present invention, after forming the first trench and the second trench, an insulating medium is deposited in the plurality of first trenches and the plurality of second trenches until the insulating medium covers the surface of the first oxide layer 200. The present invention does not limit the deposition method of the insulating medium; for example, it can be deposited by high-density plasma chemical vapor deposition (HDP). CVD or High Aspect Ratio Process CVD (HARP) The insulating medium is deposited using methods such as CVD (chemical vapor deposition). The insulating medium is, for example, a highly abrasive insulating material such as silicon oxide or fluorosilicone glass. After deposition, a high-temperature tempering process is performed to increase the density and stress characteristics of the insulating medium. After deposition, the insulating medium is planarized, for example, by chemical mechanical polishing, to obtain multiple first trench isolation structures 130 and multiple second trench isolation structures 140. The first trench isolation structures 130 and the second trench isolation structures 140 are at least partially exposed on the substrate 100. This invention does not limit the planarization of the insulating medium to a specific location; it can be placed at any location according to the semiconductor device design requirements. For example, the insulating medium in the first and second trenches can be planarized to be flush with the first oxide layer 200. In this embodiment, a plurality of first trench isolation structures 130 are spaced apart along a first direction to isolate the high-voltage P-well region 110 and the deep N-well region 120. Along the direction from the high-voltage P-well region 110 to the deep N-well region 120, a P-ion implantation region 150, an N-ion implantation region 160, a gate formation region 170, and an N-ion implantation region 160 are sequentially isolated on the high-voltage P-well region 110. A first region 180 and an N-ion implantation region 160 are sequentially isolated on the deep N-well region 120. A plurality of second trench isolation structures 140 are located in the middle of the first region 180 and are spaced apart along a second direction parallel to the substrate 100 and perpendicular to the first direction. An N-ion implantation region 160 is formed within the gaps between the second trench isolation structures 140. A P-ion implantation region 150 extending along the second direction is formed within the first region 180 on both sides of the second trench isolation structure 140 along the first direction.

[0083] Please see Figure 10 As shown, in one embodiment of the present invention, after forming the first trench isolation structure 130 and the second trench isolation structure 140, a patterned fourth photoresist layer 330 is formed on the surface of the first oxide layer 200, and the fourth photoresist layer 330 exposes the first oxide layer 200 above the P-ion implantation region 150. Figure 10 In the area not covered by the fourth photoresist layer 330, a first P-ion implantation is performed on the P-ion implantation region 150 to form a low-pressure P-well region 151. P-type ions are, for example, boron (B) or gallium (Ga). After forming the low-pressure P-well region 151, the fourth photoresist layer 330 is removed, for example, by wet cleaning or ashing. The ion concentration of the low-pressure P-well region 151 can be 1E12~5E14 / cm³. 3 For example, 1E12 / cm 3 5E13 / cm 3 5E14 / cm 3 1E12~5E14 / cm 3 Any value in the range.

[0084] Please see Figure 11As shown, in one embodiment of the present invention, after removing the fourth photoresist layer 330, a patterned fifth photoresist layer 340 is formed on the surface of the first oxide layer 200, and the fifth photoresist layer 340 exposes the first oxide layer 200 above the N ion implantation region 160. Figure 11 The area not covered by the fifth photoresist layer 340 is used to perform a first N-ion implantation on the N-ion implantation region 160 to form a low-pressure N-well region 161. N-type ions are, for example, phosphorus (P) or arsenic (As). After forming the low-pressure N-well region 161, the fifth photoresist layer 340 is removed, for example, by wet cleaning or ashing. The ion concentration of the low-pressure N-well region 161 can be 1E12~5E14 / cm³. 3 For example, 1E12 / cm 3 5E13 / cm 3 5E14 / cm 3 1E12~5E14 / cm 3 Any value in the range. This application does not restrict the formation order of the low-pressure P-well region 151 and the low-pressure N-well region 161. In some embodiments, the low-pressure N-well region 161 may be formed first and then the low-pressure P-well region 151 may be formed.

[0085] Please see Figure 12 As shown, in one embodiment of the present invention, after removing the fifth photoresist layer 340, the first oxide layer 200 is removed, and a nitride layer 400 is formed on the surface of the substrate 100. The material of the nitride layer 400 can be silicon nitride or oxynitride. In this embodiment, the nitride layer 400 is, for example, a silicon nitride (SiN) layer. The nitride layer 400 can be prepared by any one of the following processes: low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, ion-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition. Exemplarily, when preparing the nitride layer 400 using a low-pressure chemical vapor deposition process, silicon nitride can be formed by reacting ammonia and dichlorosilane. Exemplarily, after removing the first oxide layer 200 and before forming the nitride layer 400, etching of the insulating medium may be performed to adjust the height of the first trench isolation structure 130 and the second trench isolation structure 140, such that the first trench isolation structure 130 and the second trench isolation structure 140 are flush with the substrate 100.

[0086] Please see Figures 13 to 16As shown, in one embodiment of the present invention, after forming the nitride layer 400, the nitride layer 400 is etched using a patterned photoresist layer as a mask layer, exposing the gate formation region 170, and a gate structure 171 is formed on the gate formation region 170. Exemplarily, a gate oxide layer 1711 is first formed on the surface of the substrate 100, and then a gate material layer 1712 is formed on the surface of the gate oxide layer 1711. The material of the gate material layer 1712 is, for example, polysilicon. Specifically, the gate formation region 170 is oxidized, and a gate oxide layer 1711 is formed on the surface of the gate formation region 170. Exemplarily, the substrate 10 is placed in a furnace tube, oxygen is introduced, and the surface of the substrate 100 exposed by the gate formation region 170 reacts with oxygen at high temperature to form the gate oxide layer 1711. After forming the gate oxide layer 1711, the nitride layer 400 is removed, and a polysilicon layer 500 is deposited on the surface of the substrate 10. A patterned photoresist layer is used as a mask layer to etch the polysilicon layer 500, forming a gate material layer 1712 on the surface of the gate oxide layer 1711. This invention does not limit the method for removing the nitride layer 400; for example, the nitride layer 400 can be removed by dry etching, wet etching, or a combination of both. For example, the polysilicon layer 500 can be etched using a dry etching process, a wet etching process, or a combination of both.

[0087] Please see Figure 17 and Figure 18 As shown, in one embodiment of the present invention, after forming the gate material layer 1712, a patterned photoresist layer is used as a mask layer to perform a second P-ion implantation on the P-ion implantation region 150 to form a P+ doped region 152, and a second N-ion implantation is performed on the N-ion implantation region 160 outside the first region 180 to form an N+ doped region 162. The P-ions are, for example, boron (B) or gallium (Ga), and the N-ions are, for example, phosphorus (P) or arsenic (As). Exemplarily, the ion concentration of the P+ doped region 152 can be 5E13~1E16 / cm³. 3 For example, 5E13 / cm 3 1E15 / cm 3 1E16 / cm 3 5E13~1E16 / cm 3 Any value in the range. The ion concentration of the N+ doped region 162 can be 5E13~1E16 / cm³. 3 For example, 5E13 / cm 3 1E15 / cm 3 1E16 / cm 3 5E13~1E16 / cm 3 Any value in the range.

[0088] Please see Figure 19As shown, after forming the P+ doped region 152 and the N+ doped region 162, a gate-grounded NMOS structure 20 is formed on the high-voltage P-well region 110, and a Schottky barrier diode structure 30 and a Zener diode structure 40 are formed on the deep N-well region 120. The Schottky barrier diode structure 30 and the Zener diode structure 40 are arranged alternately along a second direction parallel to the substrate 100, and the second direction is perpendicular to the first direction. Figure 18 A schematic cross-sectional view of the Schottky barrier diode structure 30 formed after the second N-ion implantation of the N-ion implantation region 160. Figure 19 A schematic diagram of the cross-section along the AA direction. Figure 20 for Figure 19 A cross-sectional schematic diagram along the BB direction, corresponding to the cross-sectional schematic diagram of the Zener diode structure 40 formed after the second N-ion implantation in the N-ion implantation region 160.

[0089] In one embodiment of the present invention, to ensure the connection between the fabricated ESD device and the external circuit, the fabrication of the ESD device further includes forming a self-aligned silicide layer 720 on the surfaces of the P-ion implantation region 150, the N-ion implantation region 160, and the gate structure 171. Please refer to [link to previous document]. Figures 21 to 25 As shown, the formation of the self-aligned silicide layer 720 includes the following steps:

[0090] Please see Figures 21 to 23 As shown, in one embodiment of the present invention, with Figure 18 Taking the cross-section of the Schottky barrier diode structure 30 as an example, after forming the P+ doped region 152 and the N+ doped region 162, a second oxide layer 600 is deposited on the surface of the substrate 10. A patterned photoresist layer is used as a mask layer to etch the second oxide layer 600, forming a self-aligned silicide barrier layer 610 on the surface of the substrate 10. The self-aligned silicide barrier layer 610 exposes the surfaces of the P-ion implantation region 150, the N-ion implantation region 160, and the gate structure 171. A first contact material layer 700 is deposited on the surface of the substrate 10. The first contact material layer 700 can be formed by any process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer epitaxy. In this embodiment, the first contact material layer 700 is formed on the substrate 10 by physical vapor deposition, and the first contact material layer 700 is, for example, a NiPt layer. For example, the thickness of NiPt is 100 to 150 Å, such as any value in the range of 100 Å, 120 Å, or 150 Å.

[0091] Please see Figure 24As shown, in one embodiment of the present invention, after depositing the first contact material layer 700, a first annealing treatment is performed. The temperature of the first annealing treatment can be 200~400°C, and the time of the first annealing treatment is, for example, 20~40s. For example, the temperature of the first annealing treatment can be any value among 200~400°C, such as 200°C, 300°C, or 400°C, and the time of the first annealing treatment can be any value among 20~40s, such as 20s, 30s, or 40s. The first annealing treatment allows the NiPt layer to react with the surface Si of the P-ion implantation region 150, the N-ion implantation region 160, and the gate structure 171 to form an initial self-aligned silicide layer 710 with a high resistance. The initial self-aligned silicide layer 710 is a Ni2PtSi layer. Exemplarily, before performing the first annealing treatment, the preparation of the self-aligned silicide layer 720 also includes depositing a second contact material layer (not shown in the figure) on the surface of the first contact material layer 700. The second contact material layer can be formed using any process, such as physical vapor deposition, chemical vapor deposition, or atomic layer epitaxy. The second contact material layer is, for example, a TiN layer with a thickness of 50-100 Å, such as any value within this range (e.g., 50 Å, 80 Å, or 100 Å). During the first annealing process, the TiN second contact material layer can reduce the fluidity of Ni in NiPt, allowing the initial self-aligned silicide layer 710 to form within a specific area without haphazard drilling. Furthermore, Ti in the TiN layer has a stronger oxygen absorption capacity than Ni, enabling it to absorb naturally oxidized O from the surfaces of the P-ion implantation region 150, N-ion implantation region 160, and gate structure 171. In some embodiments, a mixture of nitrogen and helium can be introduced during the first annealing process. Nitrogen is added because oxygen affects the reaction, and adding nitrogen removes oxygen. Helium is added because the temperature of the first annealing process is relatively low, and adding helium ensures uniform heating throughout the wafer. After forming the initial self-aligned silicide layer 710, the second contact material layer, the unconverted first contact material layer 700, and the self-aligned silicide barrier layer 610 are removed. This invention does not limit the method of removing the second contact material layer, the unconverted first contact material layer 700, and the self-aligned silicide barrier layer 610, such as by dry etching or wet etching. In some embodiments, before depositing the first contact material layer 700 on the substrate 10, a SiCoNi pre-cleaning treatment is performed on the surface of the substrate 10. The SiCoNi pre-cleaning treatment can selectively remove SiO2 from the surface of the substrate 10 to form a clean, atomically flat surface. For example, after the SiCoNi pre-cleaning treatment of the substrate 10, the thickness of the substrate 10 surface is reduced by 60 Å.

[0092] Please see Figure 25As shown, in one embodiment of the present invention, after removing the second contact material layer, the unconverted first contact material layer 700, and the self-aligned silicide barrier layer 610, a second annealing process is performed to form a self-aligned silicide layer 720, which is a NiPtSi2 layer. The second annealing process can be, for example, a rapid annealing process, and the temperature of the second annealing process can be 600~900℃, for example, any value among 600℃, 700℃, 800℃, or 900℃. During the second annealing process, nitrogen gas can be introduced into a high-temperature environment to convert the high-resistivity Ni2PtSi into a low-resistivity NiPtSi2, thereby reducing the contact resistance of subsequent circuits and improving the electrical performance of the subsequently fabricated semiconductor device. In one embodiment of the present invention, Figure 19 A schematic diagram of the cross-section containing the Zener diode structure 40 after the formation of the self-aligned silicide layer 720 is shown below. Figure 26 As shown. In the fabrication process of the ESD device in this invention, the standard complementary metal-oxide-semiconductor (CMOS) process is used, which eliminates the need for an additional photomask and saves costs.

[0093] Please see Figure 27 and Figure 28 As shown, along the first direction of the substrate 10, the P+ doped region 152 of the gate-grounded NMOS structure 20 is sequentially used as the base, the N+ doped region 162 as the emitter, and the N+ doped region 162 as the collector, according to... Figure 27 and Figure 28 The electrodes were connected in a specific manner, and the breakdown voltage of the ESD device was tested. An ESD device with only a gate-grounded NMOS structure was used as a comparison, and the results are as follows: Figure 29As shown, the trigger voltage of existing ESD devices is 4V, while the trigger voltage Vt1 of the ESD device in this application is reduced to 1V. The trigger voltage of the ESD device in this application is four times lower than that of existing ESD devices, significantly improving device sensitivity. Furthermore, when a low-energy pulse arrives, the ESD device of this application can quickly clamp the ESD voltage due to the extremely low forward voltage drop and picosecond-level response speed of the Schottky barrier diode structure 30. When a high-energy pulse arrives, multiple Schottky barrier diode structures 30 connected in parallel can absorb the initial ESD spike. Subsequently, the Zener diode structure 40 and the gate-grounded NMOS structure 20 turn on, becoming the main discharge path and maintaining high current discharge capability. In other words, the ESD device of this application forms a stepped protection system with the Schottky barrier diode structure 30, Zener diode structure 40, and gate-grounded NMOS structure 20 in that order, smoothly transitioning through ESD impacts, resulting in uniform current distribution, reduced thermal stress, and improved device reliability. Therefore, when the gate-grounded NMOS structure 20 is connected in parallel with multiple Schottky barrier diode structures 30 and Zener diode structures 40, it can form a multi-level voltage clamp, providing stepped protection at each critical potential in the medium and low voltage range, so that the secondary breakdown current It2 remains at a high level. In advanced process sensitive circuits or high-speed interface circuits, multi-level protection in the medium and low voltage range is realized.

[0094] The present invention also provides, for example Figure 19 The ESD device shown includes a substrate 10, a gate-grounded NMOS structure 20, a Schottky barrier diode structure 30, and a Zener diode structure 40. The substrate 10 includes a base 100 and a high-voltage P-well region 110 and a deep N-well region 120 formed on the substrate 100. The high-voltage P-well region 110 and the deep N-well region 120 are isolated by a trench isolation structure and are arranged along a first direction parallel to the substrate 100. The gate-grounded NMOS structure 20 is formed on the high-voltage P-well region 110. The Schottky barrier diode structure 30 is disposed in the deep N-well region 120. The Zener diode structure 40 is disposed on the deep N-well region 120 and is staggered with the Schottky barrier diode structure 30 along a second direction parallel to the substrate 100. The second direction is perpendicular to the first direction. The ESD device of this application features a Schottky barrier diode structure 30 and a Zener diode structure 40 interleaved on the same deep N-well region 120, which reduces the device layout and saves 20-30% of area compared to a structure with a series-connected Schottky barrier diode structure 30 and a Zener diode structure 40. Furthermore, the number of Schottky barrier diode structures 30 and Zener diode structures 40 can be adjusted according to actual needs, allowing for different combinations of numbers to be used for different technology nodes and voltages.

[0095] In summary, this invention provides a method for fabricating an ESD device. A high-voltage P-well region and a deep N-well region are isolated by a first trench isolation structure and arranged along a first direction parallel to the substrate. A gate-grounded NMOS structure is formed on the high-voltage P-well region, and a Schottky barrier diode structure and a Zener diode structure are formed on the deep N-well region. The Schottky barrier diode structure and the Zener diode structure are arranged alternately along a second direction parallel to the substrate, which is perpendicular to the first direction. An unexpected benefit of this application is that when the gate-grounded NMOS structure is connected in parallel with multiple Schottky barrier diode structures and Zener diode structures, multi-level voltage clamping can be formed, providing stepped protection at critical potentials in the low and medium voltage ranges. This allows for a smooth transition from ESD impacts, resulting in uniform current distribution, reduced thermal stress, and improved device reliability.

[0096] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating an ESD device, characterized in that, Includes the following steps: A substrate is provided, the substrate including a substrate and a high-voltage P-well region and a deep N-well region formed on the substrate, and a first oxide layer covering the surfaces of the high-voltage P-well region and the deep N-well region, the high-voltage P-well region and the deep N-well region being arranged along a first direction parallel to the substrate; A first trench isolation structure is formed on the substrate, the first trench isolation structure isolating the high-voltage P-well region and the deep N-well region; A gate-grounded NMOS structure is formed on the high-voltage P-well region, and a Schottky barrier diode structure and a Zener diode structure are formed on the deep N-well region. The Schottky barrier diode structure and the Zener diode structure are arranged alternately along a second direction parallel to the substrate, and the second direction is perpendicular to the first direction. The number of the first trench isolation structures is multiple, and the multiple first trench isolation structures are spaced apart along the first direction. Along the direction from the high-voltage P-well region to the deep N-well region, the high-voltage P-well region is sequentially isolated into a P-ion implantation region, an N-ion implantation region, a gate formation region, and an N-ion implantation region, and the deep N-well region is sequentially isolated to form a first region and an N-ion implantation region. While forming a plurality of first trench isolation structures on the substrate, the method for fabricating the ESD device further includes forming a plurality of second trench isolation structures on the substrate. The plurality of second trench isolation structures are located in the middle of the first region and are spaced apart along the second direction. N-ion implantation regions are formed in the gaps between the second trench isolation structures. P-ion implantation regions that extend continuously along the second direction are formed in the first regions on both sides of the second trench isolation structures along the first direction and in the first regions on both sides of the N-ion implantation regions along the first direction.

2. The preparation method according to claim 1, characterized in that, A gate-grounded NMOS structure is formed on the high-voltage P-well region, and a Schottky barrier diode structure and a Zener diode structure are formed on the deep N-well region. The Schottky barrier diode structure and the Zener diode structure are arranged alternately along a second direction parallel to the substrate, comprising the following steps: The P-ion implantation region is subjected to a first P-ion implantation to form a low-pressure P-well region, and the N-ion implantation region is subjected to a first N-ion implantation to form a low-pressure N-well region. A gate structure is formed on the surface of the gate forming region; A second P-ion implantation is performed on the P-ion implantation region to form a P+ doped region, and a second N-ion implantation is performed on the N-ion implantation region outside the first region to form an N+ doped region.

3. The preparation method according to claim 1, characterized in that, While forming multiple first trench isolation structures on the substrate, the method for fabricating the ESD device also includes forming multiple second trench isolation structures on the substrate, comprising the following steps: A patterned third photoresist layer is formed on the surface of the first oxide layer, and the third photoresist layer exposes the first trench region and the second trench region; The first oxide layer and the substrate are etched sequentially to form a plurality of first trenches and a plurality of second trenches on the substrate; An insulating medium is deposited in a plurality of first trenches and a plurality of second trenches until the insulating medium covers the surface of the first oxide layer; The insulating medium is planarized until it is flush with the first oxide layer, forming a plurality of first trench isolation structures and a plurality of second trench isolation structures.

4. The preparation method according to claim 1, characterized in that, The ion concentration in the high-pressure P-trap region is 5E11~1E13 / cm³ 3 The ion concentration in the deep N-well region is 5E11~1E13 / cm³. 3 .

5. The preparation method according to claim 2, characterized in that, The ion concentration in the low-pressure P-trap region is 1E12~5E14 / cm³. 3 The ion concentration in the low-pressure N-trap region is 1E12~5E14 / cm³. 3 The ion concentration of the P+ doped region is 5E13~1E16 / cm³. 3 The ion concentration of the N+ doped region is 5E13~1E16 / cm³. 3 .

6. The preparation method according to claim 2, characterized in that, Forming a gate structure on the surface of the gate forming region includes the following steps: Remove the first oxide layer and form a nitride layer on the surface of the substrate; The nitride layer is etched using a patterned photoresist as a mask layer, and the nitride layer exposes the gate formation region; A gate oxide layer is formed on the surface of the gate forming region; A gate material layer is formed on the surface of the gate oxide layer.

7. The preparation method according to claim 2, characterized in that, After forming the P+ doped region and the N+ doped region, the fabrication method of the ESD device further includes forming a self-aligned silicide layer on the surface of the P-ion implantation region, the N-ion implantation region, and the gate structure, including the following steps: A self-aligned silicide barrier layer is deposited on the surface of the substrate, the self-aligned silicide barrier layer exposing the surfaces of the P-ion implantation region, the N-ion implantation region and the gate structure; A first contact material layer is deposited on the surfaces of the P-ion implantation region, the N-ion implantation region, and the gate structure; The first annealing process and the second annealing process are performed sequentially.

8. The preparation method according to claim 1, characterized in that, The method for preparing the substrate includes the following steps: Provide the substrate; The first oxide layer is deposited on the substrate; A high-voltage P-well region is formed by implanting P-ions into the substrate using a patterned first photoresist layer as a mask layer. A patterned second photoresist layer is used as a mask layer to perform N-ion implantation on the substrate to form a deep N-well region.

9. An ESD device, characterized in that, include: The substrate includes a substrate and a high-voltage P-well region and a deep N-well region formed on the substrate, the high-voltage P-well region and the deep N-well region being isolated by a trench isolation structure and arranged along a first direction parallel to the substrate; A gate-grounded NMOS structure is formed on the high-voltage P-well region; A Schottky barrier diode structure is disposed on the deep N-well region; A Zener diode structure is disposed on the deep N-well region and is staggered with the Schottky barrier diode structure along a second direction parallel to the substrate, the second direction being perpendicular to the first direction.

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