FT6678 multi-core DSP redundancy starting system

Abstract

The invention discloses an FT6678 multi-core DSP (Digital Signal Processor) redundant starting system, which relates to the technical field of electronics, is simple and practical, and can quickly complete multi-core DSP redundant starting. A redundant starting mode is adopted, the problem of system starting abnormity is solved, it is guaranteed that the program can be successfully loaded, and the system reliability is improved.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a redundant startup system for an FT6678 multi-core DSP. Background Technology

[0002] The FT6678 core board is based on an 8-core DSP processor from the National University of Defense Technology. The board is 100% domestically produced in its chip design, and its quality is classified into two levels: Domestic Grade I and Domestic Grade J. It possesses powerful computing capabilities and is suitable for high-speed real-time signal processing fields such as radar, communication, imaging, and electronic warfare.

[0003] The existing FT6678 multi-core DSP startup method typically involves storing the code and data of each core in different locations. This method is slow to start and cannot guarantee reliability.

[0004] In addition, existing technologies cannot solve the problem of abnormal program startup when the storage medium is disturbed by external factors and the program reads abnormally, and cannot provide multiple guarantees for the smooth startup of the program. Summary of the Invention

[0005] In view of the above problems, the present invention provides an FT6678 multi-core DSP redundant boot system for overcoming or at least partially solving the above problems.

[0006] This invention provides the following solution:

[0007] A redundant boot system for an FT6678 multi-core DSP, comprising:

[0008] An EEPROM storage medium is connected to the FT6678 processor via an I2C interface; the EEPROM storage medium is used to store the boot program.

[0009] The NOR Flash storage medium is connected to the FT6678 processor via an SPI interface; the NOR Flash storage medium is used to store the boot program.

[0010] The NAND Flash storage medium is connected to the FT6678 processor via an EMIF interface; the NAND Flash storage medium is used to store backup programs.

[0011] The system startup method includes:

[0012] The boot program is loaded and run from address 0x00 of the EEPROM storage medium;

[0013] The program segment of the NOR Flash storage medium is read to calculate and generate the first calculation verification data;

[0014] First read verification data is obtained from the verification segment of the NOR Flash storage medium, and the first read verification data and the first calculated verification data are parsed and verified.

[0015] If the verification is successful, the parser application will be executed, and the process will jump to the application's running state.

[0016] If the verification fails, the program is read from the program segment of the NAND Flash storage medium to calculate and generate second verification data;

[0017] The second read verification data is obtained from the verification segment of the NAND Flash storage medium, and the second read verification data and the second calculated verification data are parsed and verified.

[0018] If the verification is successful, the parser application will be executed, and the process will jump to the application's running state.

[0019] If the verification fails, the startup process will terminate.

[0020] Preferably, the boot program is loaded and run from address 0x00 of EEPROM through the ROM Boot Loader program embedded in the BOOT ROM module.

[0021] Preferably, the bootloader parsing uses preset rules to parse the upgrade program and copies the parsed data to the target storage location.

[0022] Preferably, when generating multi-core bin files, global addresses are used when using L2SRAM space.

[0023] Preferably, when generating a multi-core bin file, core 0 includes a boot function, which writes the entry addresses of the programs in cores 1-7 into the BOOT_MAGIC_ADDRESS register.

[0024] Preferably, core 0 causes cores 1-7 to begin executing their respective programs via interrupts of core 4.

[0025] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0026] This application provides an FT6678 multi-core DSP redundant boot system, which is simple and practical, and can quickly complete the redundant boot of multi-core DSPs. By employing redundant boot, it solves the problem of system boot anomalies, ensures successful program loading, and improves system reliability.

[0027] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0029] Figure 1 This is a framework diagram of an FT6678 multi-core DSP redundant boot system provided in an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram illustrating the storage of the program in Nor Flash and Nand Flash according to an embodiment of the present invention;

[0031] Figure 3 This is a flowchart of the DSP redundant startup process provided in an embodiment of the present invention;

[0032] Figure 4 This is a command parsing rule diagram provided in an embodiment of the present invention;

[0033] Figure 5 This is a diagram illustrating the definition of BOOT_MAGIC_ADDRESS provided in an embodiment of the present invention. Detailed Implementation

[0034] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0035] See Figure 1 This invention provides an FT6678 multi-core DSP redundant boot system, such as... Figure 1 As shown, the system may include:

[0036] An EEPROM storage medium is connected to the FT6678 processor via an I2C interface; the EEPROM storage medium is used to store the boot program.

[0037] The NOR Flash storage medium is connected to the FT6678 processor via an SPI interface; the NOR Flash storage medium is used to store the boot program.

[0038] The NAND Flash storage medium is connected to the FT6678 processor via an EMIF interface; the NAND Flash storage medium is used to store backup programs.

[0039] The system startup method includes:

[0040] The boot program is loaded and run from address 0x00 of the EEPROM storage medium;

[0041] The program segment of the NOR Flash storage medium is read to calculate and generate the first calculation verification data;

[0042] First read verification data is obtained from the verification segment of the NOR Flash storage medium, and the first read verification data and the first calculated verification data are parsed and verified.

[0043] If the verification is successful, the parser application will be executed, and the process will jump to the application's running state.

[0044] If the verification fails, the program is read from the program segment of the NAND Flash storage medium to calculate and generate second verification data;

[0045] The second read verification data is obtained from the verification segment of the NAND Flash storage medium, and the second read verification data and the second calculated verification data are parsed and verified.

[0046] If the verification is successful, the parser application will be executed, and the process will jump to the application's running state.

[0047] If the verification fails, the startup process will terminate.

[0048] In a specific implementation, embodiments of this application can provide a program ROM BootLoader embedded in the BOOT ROM module to load and run the boot program from address 0x00 of the EEPROM.

[0049] The bootloader parsing uses preset rules to parse the upgrade program and copies the parsed data to the target storage location.

[0050] When generating multi-core bin files, use global addresses when using L2SRAM space.

[0051] When generating the multi-core bin file, core 0 includes a boot function that writes the entry addresses of the core 1-7 programs into the BOOT_MAGIC_ADDRESS register.

[0052] Core 0 causes cores 1-7 to begin executing their respective programs via interrupts of core 4.

[0053] The FT6678 multi-core DSP redundant boot system provided in this application adopts a redundant boot method to ensure successful program loading and improve system stability. It also enables fast boot.

[0054] The system provided in this application will be described in detail below.

[0055] The FT6678 provided in this application has 8 C66x cores (hereinafter referred to as cores 0 to 7), each core has an independent arithmetic unit, 12kB of internal L2 SRAM, multiple cores share 4kB of RAM, and off-chip DDR3 memory.

[0056] The structure of this system is as follows: Figure 1 As shown, the FT6678 processor is configured for I2C boot mode. The EEPROM storage medium is connected to the FT6678 processor via the I2C interface. The NOR Flash storage medium is connected to the FT6678 processor via the SPI interface. The NAND Flash storage medium is connected to the FT6678 processor via the EMIF interface. Three different receive and store programs are as follows:

[0057] EEPROM storage medium: fixed boot program, no subsequent upgrades.

[0058] NOR Flash storage medium: stores the boot program. In normal mode, the system obtains the program from the NOR Flash to complete the system boot.

[0059] NAND Flash storage medium: Stores backup programs. When the NOR Flash program encounters an error, the program is retrieved from the NAND Flash to start the system.

[0060] The program is stored on Nor Flash storage medium h and Nand Flash storage medium as follows: Figure 2 As shown. NorFlash and Nand Flash storage media require a stored program and a program checksum.

[0061] System redundant startup process, the redundant startup process is as follows Figure 3 As shown.

[0062] a. The program embedded in the on-chip BOOT ROM module of the FT6678 multi-core DSP is the ROM Boot Loader (RBL), which loads the boot program from the EEPROM address 0x00 and runs it.

[0063] b. After the boot program runs, it first reads the program segment from the Nor Flash storage medium to calculate and generate the first calculation verification data.

[0064] c. Read the first verification data and the first calculated verification data from the verification segment of the Nor Flash storage medium and parse them; if the verification fails, start the program from the NAND Flash. Otherwise, execute the parsing program.

[0065] d. After Nor Flash boot fails, read the program from the NAND Flash program segment to generate the second calculation verification data.

[0066] e. Read the second verification data and the second calculated verification data from the NAND Flash verification segment and parse them; if the verification fails, stop the startup; otherwise, execute the parsing program.

[0067] f. Bootloader parsing requires reference. Figure 4 The rules are upgraded by parsing the program and copying the parsed data to a suitable storage location.

[0068] When generating multi-core bin files, the memory allocation and usage of each core need to be considered. When using L2SRAM space, global addresses should be used to avoid incorrect address resolution in the generated bin files.

[0069] When generating the multi-core bin file, a boot function is added to core 0, writing the entry addresses of the programs for cores 1-7 into the BOOT_MAGIC_ADDRESS register; core 0 then uses interrupt number 4 of each core to start the execution of their respective programs for cores 1-7. This completes the startup of multiple core programs. The BOOT_MAGIC_ADDRESS definition is as follows: Figure 5 As shown.

[0070] g. After the program is parsed, the program will be executed.

[0071] In summary, the FT6678 multi-core DSP redundant boot system provided in this application is simple and practical, and can quickly complete the redundant boot of multi-core DSPs. By employing redundant boot, it solves the system boot failure problem, ensures successful program loading, and improves system reliability.

[0072] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0073] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0074] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for system or system embodiments, since they are basically similar to method embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions in the method embodiments. The systems and system embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A redundant boot system for an FT6678 multi-core DSP, characterized in that, include: EEPROM storage medium, wherein the EEPROM storage medium is connected to the FT6678 processor via an I2C interface; The EEPROM storage medium is used to store the boot program; The NOR Flash storage medium is connected to the FT6678 processor via an SPI interface; the NOR Flash storage medium is used to store the boot program. NAND Flash storage medium, wherein the NAND Flash storage medium is connected to the FT6678 processor via an EMIF interface; The NAND Flash storage medium is used to store backup programs; The system startup method includes: The boot program is loaded and run from address 0x00 of the EEPROM storage medium; The program segment of the NOR Flash storage medium is read to calculate and generate the first calculation verification data; First read verification data is obtained from the verification segment of the NOR Flash storage medium, and the first read verification data and the first calculated verification data are parsed and verified. If the verification is successful, the parser application will be executed, and the process will jump to the application's running state. If the verification fails, the program is read from the program segment of the NAND Flash storage medium to calculate and generate second verification data; The second read verification data is obtained from the verification segment of the NAND Flash storage medium, and the second read verification data and the second calculated verification data are parsed and verified. If the verification is successful, the parser application will be executed, and the process will jump to the application's running state. If the verification fails, the startup process will terminate.

2. The FT6678 multi-core DSP redundant boot system according to claim 1, characterized in that, The bootloader is loaded from address 0x00 of EEPROM and run by using the ROM Boot Loader program embedded in the BOOT ROM module.

3. The FT6678 multi-core DSP redundant boot system according to claim 1, characterized in that, The bootloader parsing uses preset rules to parse the upgrade program and copies the parsed data to the target storage location.

4. The FT6678 multi-core DSP redundant boot system according to claim 1, characterized in that, When generating multi-core bin files, use global addresses when using L2SRAM space.

5. The FT6678 multi-core DSP redundant boot system according to claim 1, characterized in that, When generating the multi-core bin file, core 0 includes a boot function that writes the entry addresses of the core 1-7 programs into the BOOT_MAGIC_ADDRESS register.

6. The FT6678 multi-core DSP redundant boot system according to claim 5, characterized in that, Core 0 causes cores 1-7 to begin executing their respective programs via interrupts of core 4.

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