Address mapping method and device, electronic equipment and chip

Abstract

The invention provides an address mapping method and device, electronic equipment and a chip, and relates to the technical field of memory management, the method comprises the following steps: obtaining a plurality of original memory addresses, at least two original memory addresses in the plurality of original memory addresses including the same memory bank address; based on an original address bit of each original memory address, determining a target address bit of each original memory address, the number of bits of the target address bits being a first preset number, and the first preset number being smaller than the number of bits of the original address bits; determining a mapping result of each original memory address based on the target address bit and a preset mapping relation; target memory addresses corresponding to the original memory addresses are determined based on the mapping result and the memory bank addresses in the original memory addresses, and the memory bank addresses included in the target memory addresses corresponding to different original memory addresses are different.

Description

Technical Field

[0001] This disclosure relates to the field of memory management technology, and in particular to an address mapping method, apparatus, electronic device and chip. Background Technology

[0002] In related memory address mapping schemes, the original memory address is usually mapped by performing targeted bank address mapping based on the access address of the Intellectual Property (IP) core. However, when there are many IP cores and the access space size of each IP core varies greatly, different mapping strategies need to be designed for the specific access mode of each IP core. Therefore, when there are many IP cores, this targeted bank address mapping method cannot effectively improve the system bandwidth utilization. In some schemes, designing a statistics module in the chip to implement bank address mapping requires additional logic circuits and is not easy to implement. Summary of the Invention

[0003] This disclosure provides an address mapping method, apparatus, electronic device, and chip to solve the problems that targeted bank address mapping methods in related technologies cannot effectively improve system bandwidth utilization and are difficult to implement.

[0004] A first aspect of this disclosure provides an address mapping method, comprising: acquiring a plurality of original memory addresses, wherein at least two of the original memory addresses include the same memory bank address; determining a target address bit for each original memory address based on the original address bits of each original memory address, wherein the number of bits of the target address bit is a first preset number, the first preset number being less than the number of bits of the original address bit; determining a mapping result for each original memory address based on the target address bit and a preset mapping relationship; and determining a target memory address corresponding to each original memory address based on the mapping result and the memory bank address in each original memory address, wherein the target memory addresses corresponding to different original memory addresses include different memory bank addresses.

[0005] In some embodiments of this disclosure, determining the target address bit of each original memory address based on the original address bits of each original memory address includes: determining multiple address bits with different bit values ​​at the same bit position from the original address bits of at least two original memory addresses; and determining a first preset number of address bits from the multiple address bits as target address bits.

[0006] In some embodiments of this disclosure, determining a first preset number of address bits from a plurality of address bits as target address bits includes: determining the number of address bits n of the bank address in at least two original memory addresses; and determining n groups of target address bits from the plurality of address bits based on the number of address bits n, wherein each group of target address bits includes the first preset number of address bits.

[0007] In some embodiments of this disclosure, the mapping result of each original memory address is determined based on the target address bits and a preset mapping relationship, including: using the preset mapping relationship, determining the mapping result of the target address bits m times, and obtaining m mapping results of the target address bits, where the value of m is the same as the value of the number of address bits n of the memory address.

[0008] In some embodiments of this disclosure, determining the target memory address corresponding to each original memory address based on the mapping result and the storage address in each original memory address includes: obtaining the original memory address configuration instruction; determining the location of each original memory address based on the original memory address configuration instruction; and determining the target memory address based on the location, the mapping result, and the storage address.

[0009] In some embodiments of this disclosure, determining a target memory address based on location, mapping results, and memory bank address includes: in response to the location being in the memory controller, obtaining a preset replacement address bit in the memory bank address; and replacing the preset replacement address bit with m mapping results to obtain the target memory address.

[0010] In some embodiments of this disclosure, determining a target memory address based on location, mapping results, and memory bank address includes: in response to the location being between the bus and the memory controller, replacing the memory bank address with m mapping results to obtain the target memory address.

[0011] A second aspect of this disclosure provides an address mapping apparatus, comprising: an acquisition unit for acquiring a plurality of original memory addresses, wherein at least two of the original memory addresses include the same memory bank address; a first determination unit for determining a target address bit for each original memory address based on the original address bits of each original memory address, wherein the number of bits of the target address bit is a first preset number, the first preset number being less than the number of bits of the original address bits; a second determination unit for determining a mapping result for each original memory address based on the target address bit and a preset mapping relationship; and a third determination unit for determining a target memory address corresponding to each original memory address based on the mapping result and the memory bank address in each original memory address, wherein the target memory addresses corresponding to different original memory addresses include different memory bank addresses.

[0012] In some embodiments of this disclosure, the first determining unit is configured to: determine a plurality of address bits with different bit values ​​at the same bit position from the original address bits of at least two original memory addresses; and determine a first preset number of address bits from the plurality of address bits as target address bits.

[0013] In some embodiments of this disclosure, the first determining unit is configured to: determine the number of address bits n of the storage address in at least two original memory addresses; and, based on the number of address bits n, determine n groups of target address bits from a plurality of address bits, each group of target address bits including a first preset number of address bits.

[0014] In some embodiments of this disclosure, the second determining unit is used to: determine the mapping result of the target address bits m times using a preset mapping relationship, and obtain m mapping results of the target address bits, wherein the value of m is the same as the value of the number of address bits n of the storage address.

[0015] In some embodiments of this disclosure, the third determining unit is used to: obtain the original memory address configuration instruction; determine the location of each original memory address based on the original memory address configuration instruction; and determine the target memory address based on the location, the mapping result, and the storage address.

[0016] In some embodiments of this disclosure, the third determining unit is configured to: in response to the location being in the memory controller, obtain a preset replacement address bit in the memory address; and replace the preset replacement address bit with m mapping results to obtain the target memory address.

[0017] In some embodiments of this disclosure, the third determining unit is configured to: in response to the location being between the bus and the memory controller, replace the memory bank address with m mapping results to obtain the target memory address.

[0018] A third aspect of this disclosure provides an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the first aspect of this disclosure.

[0019] A fourth aspect of this disclosure provides a chip including one or more interface circuits and one or more processors; the interface circuits are configured to receive signals and send signals to the processors, the signals including computer instructions stored in a memory, which, when executed by the processors, cause the chip to perform the methods described in the first aspect of this disclosure.

[0020] In summary, according to the address mapping method proposed in this disclosure, multiple original memory addresses are obtained, with at least two of them containing the same memory bank address. Based on the original address bits of each original memory address, a target address bit is determined for each original memory address, the number of bits in the target address bit being a first preset number, which is less than the number of bits in the original address bit. Based on the target address bit and a preset mapping relationship, a mapping result for each original memory address is determined. Based on the mapping result and the memory bank address in each original memory address, a target memory address corresponding to each original memory address is determined. The target memory addresses corresponding to different original memory addresses contain different memory bank addresses, thereby mapping multiple original memory addresses to different memory banks. Since read and write instructions on different memory banks can be implemented in parallel, system bandwidth utilization can be improved. Because this application uses a mapping relationship to obtain the target memory address, no additional logic circuitry is required, making it easy to implement.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure, and are not intended to unduly limit this disclosure.

[0023] Figure 1 A flowchart of an address mapping method provided in this embodiment of the disclosure;

[0024] Figure 2 A flowchart illustrating a method for determining a target memory address provided in this disclosure embodiment;

[0025] Figure 3 This is a schematic diagram of the structure of an address mapping device provided in an embodiment of the present disclosure;

[0026] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure;

[0027] Figure 5 This is a schematic diagram of the chip structure provided in an embodiment of this disclosure. Detailed Implementation

[0028] The embodiments of this disclosure are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0029] When the IP cores in a System on a Chip (SOC) access memory, the read / write commands they issue are routed via bus arbitration and eventually reach the memory controller. If two adjacent read / write commands received by the memory controller access the same bank and the same row, the memory controller can continuously send read / write commands to the DRAM chip without needing additional activation, act, precharge, or precharge commands, and without waiting for the corresponding delays.

[0030] If accessing different rows within the same bank, a pre command and an act command need to be added between the read / write commands of the two DRAMs. These two commands will increase the tRP+tRCD latency.

[0031] If accessing different banks, the two banks can execute the pre and act commands in parallel, which can hide some of the latency and reduce the memory access latency of the IP core.

[0032] In real-world SOC applications, the probability of different IP cores accessing the same bank or row simultaneously is very small. However, by optimizing address mapping, the probability of accessing different banks can be increased, thereby improving the parallelism of DRAM chip access and the balance of bank tasks, ultimately improving system bandwidth utilization.

[0033] In a computer system, memory address mapping refers to the process of translating logical addresses into physical addresses. The logical address is the address of the read / write command issued by the IP core. This process is typically performed by the memory controller and ultimately mapped to the bank, row, and column addresses of the Dynamic Random Access Memory (DRAM) particles.

[0034] In existing memory address mapping schemes, targeted bank address mapping is typically performed directly based on the IP access address. However, when there are many IP cores and the access space size of each IP core varies significantly, different mapping strategies need to be designed for the specific access patterns of each IP core. This targeted bank address mapping is not easy to implement. Some solutions incorporate a statistical module within the chip to count the number of consecutive flips (the number of 0 and 1 flips) of each memory address bit, then select the address bit corresponding to the maximum number of flips as the bank address. While this method provides relatively accurate bank address bits, it requires additional logic circuitry, increasing the chip area.

[0035] To address the problems existing in related technologies, this disclosure proposes an address mapping method. This method involves obtaining multiple raw memory addresses, where at least two of these raw memory addresses include the same memory bank address. Based on the raw address bits of each raw memory address, a target address bit is determined for each raw memory address. The number of bits in the target address bit is a first preset number, which is less than the number of bits in the raw address bit. Based on the target address bit and a preset mapping relationship, a mapping result for each raw memory address is determined. Based on the mapping result and the memory bank address in each raw memory address, a target memory address corresponding to each raw memory address is determined. The target memory addresses corresponding to different raw memory addresses include different memory bank addresses, thereby mapping multiple raw memory addresses to different memory banks. Since read and write instructions on different memory banks can be implemented in parallel, system bandwidth utilization can be improved. Because this application uses a mapping relationship to obtain the target memory address, no additional logic circuitry is required, making it easy to implement.

[0036] The address mapping method proposed in this disclosure can be applied to chip designs that access external DDR, specifically in fields such as high-performance computing, graphics processing units, and network processors. However, the specific application scenarios are not limited in the embodiments of this disclosure.

[0037] The address mapping method provided in this application will be described in detail below with reference to the accompanying drawings.

[0038] Figure 1 This is a flowchart illustrating an address mapping method provided in an embodiment of this disclosure. Figure 1 As shown, the address mapping method includes steps 101-104.

[0039] Step 101: Obtain multiple raw memory addresses, where at least two of the raw memory addresses contain the same memory bank address.

[0040] In the embodiments of this disclosure, the method shown in this disclosure can be executed by a memory controller, a bus interface unit, and a hardware accelerator, etc.

[0041] In this embodiment of the disclosure, the original memory address can be obtained from the read and write commands issued by the IP core, which can be a CPU, GPU, or other dedicated accelerators. During the simulation phase, virtual read and write instructions can also be generated by simulation tools (such as Verilog simulators, SystemC, etc.), and the original memory address can be obtained from the virtual read and write instructions.

[0042] In this embodiment, the original memory address includes a bank address, a row address, and a column address. The bank address is generally located in the high-order bits of the original memory address and is used to identify a specific bank. DRAM chips typically contain multiple banks, each of which can be operated independently. The number of bits in the bank address depends on the DRAM chip design; for example, if a DRAM chip has 8 banks, 3 bits are needed to represent different banks. The row address identifies a specific row within a bank. Within a bank, data is organized in rows, and the number of bits in the row address depends on the number of rows in the DRAM chip. For example, if a bank has 16,384 rows, 14 bits are needed to represent the row address. The column address identifies a specific column within a bank. Within the same row, data is organized in columns, and the number of bits in the column address depends on the number of columns in the DRAM chip. For example, if a row has 1024 columns, 10 bits are needed to represent the column address.

[0043] Step 102: Based on the original address bits of each original memory address, determine the target address bits of each original memory address. The number of bits in the target address bits is a first preset number, which is less than the number of bits in the original address bits.

[0044] In this embodiment of the disclosure, the original address bits of the original memory address can be 32 bits or 64 bits, depending on the system architecture.

[0045] In the embodiments disclosed herein, the target address bits can be consecutive bits in the original memory address or discrete bits in the original memory address, and this application does not limit them.

[0046] In this embodiment of the disclosure, the first preset quantity can be any value among the number of bits less than the original address bits, and this application does not limit the specific value of the first preset quantity.

[0047] Step 103: Based on the target address bits and the preset mapping relationship, determine the mapping result for each original memory address.

[0048] In the embodiments of this disclosure, the preset mapping relationship can be a hash mapping relationship or a direct mapping relationship. The hash mapping relationship can map the target address bits to any position, while the direct mapping relationship maps the target address bits to a specified position. In order to cope with the scenario of a large number of IP cores, the hash mapping relationship is selected in this application to meet the mapping of the original memory addresses issued by a large number of IP cores.

[0049] In the embodiments of this disclosure, for each original memory address, a different number of address bits can be selected as the target address bits, or address bits at different positions can be selected as the target address bits.

[0050] Step 104: Based on the mapping result and the memory bank address in each original memory address, determine the target memory address corresponding to each original memory address. The memory bank addresses included in the target memory addresses corresponding to different original memory addresses are different.

[0051] In this embodiment of the disclosure, the mapping result can be used to directly replace the storage address in the original memory address to obtain a new storage address corresponding to the original memory address. Alternatively, the mapping result can be used to update the storage address in the original memory address according to a preset rule to obtain a new storage address corresponding to the original memory address.

[0052] In this embodiment of the disclosure, by determining the target memory address corresponding to each original memory address based on the mapping result and the memory bank address in each original memory address, the probability of the original memory address being mapped to different memory banks can be increased, thereby improving memory access efficiency and system bandwidth utilization.

[0053] In summary, according to the address mapping method proposed in this disclosure, multiple original memory addresses are obtained, with at least two of them containing the same memory bank address. Based on the original address bits of each original memory address, a target address bit is determined for each original memory address, the number of bits in the target address bit being a first preset number, which is less than the number of bits in the original address bit. Based on the target address bit and a preset mapping relationship, a mapping result for each original memory address is determined. Based on the mapping result and the memory bank address in each original memory address, a target memory address corresponding to each original memory address is determined. The target memory addresses corresponding to different original memory addresses contain different memory bank addresses, thereby mapping multiple original memory addresses to different memory banks. Since read and write instructions on different memory banks can be implemented in parallel, system bandwidth utilization can be improved. Because this application uses a mapping relationship to obtain the target memory address, no additional logic circuitry is required, making it easy to implement.

[0054] In this embodiment of the disclosure, determining the target address bits of each original memory address based on the original address bits of each original memory address includes:

[0055] From the original address bits of at least two original memory addresses, determine multiple address bits with different bit values ​​at the same bit position;

[0056] In this embodiment of the disclosure, multiple address bits with different bit values ​​at the same bit position are used to determine the differing bits in at least two original memory bits.

[0057] In this embodiment of the disclosure, by determining multiple address bits with different bit values ​​at the same bit position from the original address bits of at least two original memory addresses, it is convenient to perform more refined address mapping and optimization in the future. This can avoid frequent access to the same memory bank, reduce the number of pre and act commands, reduce system latency, and improve system bandwidth utilization.

[0058] From a plurality of address bits, a first preset number of address bits are determined as the target address bits.

[0059] In this embodiment of the disclosure, for different original memory addresses, a different number of address bits can be determined from multiple address bits as target address bits. For example, for original memory address A, 4 bits are selected from multiple address bits as target address bits, and for original memory address B, 6 bits are selected from multiple address bits as target address bits.

[0060] In this embodiment of the disclosure, the position of the selected address bits is not limited for two original memory addresses. For example, if the original memory address A and the original memory address B select the same number of address bits as the target address bits, they can both select address bits at positions 4, 5, 6, and 7, or they can select address bits at different positions.

[0061] In this embodiment of the disclosure, determining a first preset number of address bits from a plurality of address bits as target address bits includes:

[0062] Determine the number of address bits n in the memory bank address from at least two raw memory addresses;

[0063] In the embodiments of this disclosure, the number of address bits n of the storage bank address in the original memory address is usually determined by the DRAM chip design and system architecture, and the address bits of the storage bank address can be directly extracted from the original memory address.

[0064] Based on the number of address bits n, n groups of target address bits are determined from multiple address bits, and each group of target address bits includes a first preset number of address bits.

[0065] In this embodiment of the disclosure, if only one bit in the storage address needs to be replaced, a set of target address bits can be directly obtained from multiple address bits. The target address bits are used for the aforementioned hash mapping to obtain the mapping result.

[0066] In this embodiment of the disclosure, if the memory address includes three address bits, then three sets of target address bits need to be determined from multiple address bits. The three sets of target address bits can be any combination of bits from the multiple address bits, and the number of bits in each set of address bits is not limited here.

[0067] In this embodiment of the disclosure, the mapping result of each original memory address is determined based on the target address bits and a preset mapping relationship, including:

[0068] Using a preset mapping relationship, determine the mapping result of the target address bits m times, and obtain m mapping results of the target address bits. The value of m is the same as the value of the number of address bits n of the memory address.

[0069] In the embodiments disclosed herein, the hash mapping relationship can be a simple Exclusive OR (XOR) algorithm or a more complex Cyclic Redundancy Check (CRC) algorithm. This application does not limit the specific hash mapping algorithm.

[0070] In this embodiment of the disclosure, the mathematical expression for the hash mapping relationship is as follows:

[0071] hash_bit[0]=hash(addr[a],addr[b],addr[c],addr[d]);

[0072] Where hash_bit[0] represents the mapping result, and addr[a], addr[b], addr[c], addr[d] represent the four bits a, b, c, and d in the multiple address bits respectively.

[0073] In this embodiment of the disclosure, if the memory address has 3 bits, then the values ​​of 3 mapping results need to be obtained to replace the address bits in the memory address.

[0074] based on Figure 1 The embodiment shown, Figure 2 A flowchart of a method for determining a target memory address as presented in this disclosure is further shown. Figure 2 based on Figure 1 The illustrated embodiment further defines step 104. For example... Figure 2 As shown, the method includes the following steps:

[0075] Step 201: Obtain the original memory address configuration instruction;

[0076] In this embodiment of the disclosure, the raw memory address configuration instructions can be obtained through the operating system interface, or by consulting the datasheets of the motherboard, CPU, and memory module.

[0077] Step 202: Determine the location of each original memory address based on the original memory address configuration instructions;

[0078] In this embodiment of the disclosure, the original memory address configuration instructions are parsed to obtain the location of each original memory address.

[0079] Step 203: Determine the target memory address based on the location, mapping result, and storage address.

[0080] In this embodiment of the disclosure, determining the target memory address based on the location, mapping result, and memory address includes:

[0081] In response to the location in the memory controller, the preset replacement address bits in the memory address are retrieved;

[0082] In this embodiment of the disclosure, the preset replacement address bits are determined by the memory controller. For example, the memory controller can determine the 10th and 11th bits in the original memory address as the preset replacement address bits.

[0083] In the embodiments disclosed herein, the number and position of the preset replacement address bits are not limited.

[0084] The target memory address is obtained by replacing the preset replacement address bits with m mapping results.

[0085] In this embodiment of the disclosure, a new memory address is obtained by replacing the preset replacement address bits with m mapping results, and then the final target memory address is generated based on the new memory address and other address parts (such as row address and column address).

[0086] In this embodiment of the disclosure, determining the target memory address based on the location, mapping result, and memory address includes:

[0087] In response to the location between the bus and the memory controller, the target memory address is obtained by replacing the memory bank address with m mapping results.

[0088] In this embodiment of the disclosure, if the original memory address is located between the bus and the memory controller, the address of the memory bank is directly replaced by the obtained mapping result to obtain a new memory bank address, and then the target memory address is obtained based on the new memory bank address, row address, and column address.

[0089] In summary, the method provided in this disclosure involves obtaining multiple raw memory addresses, where at least two of these raw memory addresses include the same memory bank address; determining the target address bits for each raw memory address based on the raw address bits of each raw memory address, wherein the number of bits in the target address bits is a first preset number, which is less than the number of bits in the raw address bits; determining the mapping result for each raw memory address based on the target address bits and a preset mapping relationship; and determining the target memory address corresponding to each raw memory address based on the mapping result and the memory bank address in each raw memory address. The target memory addresses corresponding to different raw memory addresses include different memory bank addresses, thereby mapping multiple raw memory addresses to different memory banks. Since read and write instructions on different memory banks can be implemented in parallel, system bandwidth utilization can be improved. Because this application uses a mapping relationship to obtain the target memory address, no additional logic circuitry is required, making it easy to implement.

[0090] Figure 3 This is a schematic diagram of the structure of an address mapping device 300 provided in an embodiment of this disclosure. Figure 3 As shown, the address mapping device includes:

[0091] The acquisition unit 310 is used to acquire multiple raw memory addresses, wherein at least two of the multiple raw memory addresses include the same memory bank address;

[0092] The first determining unit 320 is used to determine the target address bits of each original memory address based on the original address bits of each original memory address. The number of bits of the target address bits is a first preset number, which is less than the number of bits of the original address bits.

[0093] The second determining unit 330 is used to determine the mapping result of each original memory address based on the target address bits and the preset mapping relationship;

[0094] The third determining unit 340 is used to determine the target memory address corresponding to each original memory address based on the mapping result and the memory bank address in each original memory address, wherein the memory bank address included in the target memory address corresponding to different original memory addresses is different.

[0095] In some embodiments of this disclosure, the first determining unit 320 is configured to: determine a plurality of address bits with different bit values ​​at the same bit position from the original address bits of at least two original memory addresses; and determine a first preset number of address bits from the plurality of address bits as target address bits.

[0096] In some embodiments of this disclosure, the first determining unit 320 is configured to: determine the number of address bits n of the storage address in at least two original memory addresses; and, based on the number of address bits n, determine n groups of target address bits from a plurality of address bits, each group of target address bits including a first preset number of address bits.

[0097] In some embodiments of this disclosure, the second determining unit 330 is used to: determine the mapping result of the target address bits m times using a preset mapping relationship, and obtain m mapping results of the target address bits, wherein the value of m is the same as the value of the number of address bits n of the storage address.

[0098] In some embodiments of this disclosure, the third determining unit 330 is configured to: obtain original memory address configuration instructions; determine the location of each original memory address based on the original memory address configuration instructions; and determine the target memory address based on the location, mapping result, and storage address.

[0099] In some embodiments of this disclosure, the third determining unit 340 is configured to: in response to the location being in the memory controller, obtain a preset replacement address bit in the memory address; and replace the preset replacement address bit with m mapping results to obtain the target memory address.

[0100] In some embodiments of this disclosure, the third determining unit 340 is configured to: in response to the location being between the bus and the memory controller, replace the memory bank address with m mapping results to obtain the target memory address.

[0101] In summary, the address mapping device obtains multiple raw memory addresses, where at least two of these raw memory addresses contain the same memory bank address. Based on the raw address bits of each raw memory address, a target address bit is determined for each raw memory address. The number of bits in the target address bit is a first preset number, which is less than the number of bits in the raw address bit. Based on the target address bit and a preset mapping relationship, the mapping result for each raw memory address is determined. Based on the mapping result and the memory bank address in each raw memory address, the target memory address corresponding to each raw memory address is determined. Different raw memory addresses contain different memory bank addresses in their corresponding target memory addresses, thus mapping multiple raw memory addresses to different memory banks. Since read and write instructions on different memory banks can be implemented in parallel, system bandwidth utilization can be improved. Because this application uses a mapping relationship to obtain the target memory address, no additional logic circuitry is required, making it easy to implement.

[0102] Corresponding to the methods provided in the above embodiments, this disclosure also provides an address mapping device. Since the device provided in this disclosure corresponds to the methods provided in the above embodiments, the implementation of the methods is also applicable to the device provided in this embodiment, and will not be described in detail in this embodiment.

[0103] The methods and apparatus provided in the embodiments of this application have been described above. To implement the functions of the methods provided in the embodiments of this application, the electronic device may include a hardware structure and software modules, and may implement the above functions in the form of a hardware structure, software modules, or a hardware structure plus software modules. One of the above functions may be executed in the form of a hardware structure, software modules, or a hardware structure plus software modules.

[0104] Figure 4 This is a block diagram illustrating an electronic device 400 for implementing the above-described address mapping method according to an exemplary embodiment. For example, the electronic device 400 may be a mobile phone, computer, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc. The electronic device 400 may also be an artificial intelligence (AI) computing server, server cluster, AI edge computing device, etc.

[0105] Reference Figure 4 The electronic device 400 may include one or more of the following components: processing component 402, memory 404, power supply component 406, multimedia component 408, audio component 410, input / output (I / O) interface 412, sensor component 414, and communication component 416.

[0106] Processing component 402 typically controls the overall operation of electronic device 400, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 402 may include one or more processors 420 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 402 may include one or more modules to facilitate interaction between processing component 402 and other components. For example, processing component 402 may include a multimedia module to facilitate interaction between multimedia component 408 and processing component 402.

[0107] Memory 404 is configured to store various types of data to support the operation of electronic device 400. Examples of this data include instructions for any application or method operating on electronic device 400, contact data, phonebook data, messages, pictures, videos, etc. Memory 404 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0108] Power supply component 406 provides power to various components of electronic device 400. Power supply component 406 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 400.

[0109] Multimedia component 408 includes a screen that provides an output interface between electronic device 400 and a user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of touch or swipe actions but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 408 includes a front-facing camera and / or a rear-facing camera. When electronic device 400 is in an operating mode, such as a shooting mode or video mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0110] Audio component 410 is configured to output and / or input audio signals. For example, audio component 410 includes a microphone (MIC) configured to receive external audio signals when electronic device 400 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 404 or transmitted via communication component 416. In some embodiments, audio component 410 also includes a speaker for outputting audio signals.

[0111] I / O interface 412 provides an interface between processing component 402 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0112] Sensor assembly 414 includes one or more sensors for providing state assessments of various aspects of electronic device 400. For example, sensor assembly 414 may detect the on / off state of electronic device 400, the relative positioning of components such as the display and keypad of electronic device 400, changes in position of electronic device 400 or a component of electronic device 400, the presence or absence of user contact with electronic device 400, orientation or acceleration / deceleration of electronic device 400, and temperature changes of electronic device 400. Sensor assembly 414 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 414 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 414 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0113] Communication component 416 is configured to facilitate wired or wireless communication between electronic device 400 and other devices. Electronic device 400 can access wireless networks based on communication standards, such as WiFi, 2G or 3G, 4G LTE, 5G NR (NewRadio), or combinations thereof. In one exemplary embodiment, communication component 416 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 416 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0114] In an exemplary embodiment, the electronic device 400 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0115] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 404 including instructions, which can be executed by a processor 420 of an electronic device 400 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0116] Embodiments of this disclosure also propose a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the address mapping method described in the above embodiments of this disclosure.

[0117] Embodiments of this disclosure also provide a computer program product, including a computer program that is executed by a processor using the address mapping method described in the above embodiments of this disclosure.

[0118] Embodiments of this disclosure also propose a chip, such as Figure 5 As shown, the chip includes one or more interface circuits 501 and one or more processors 502; the interface circuits are used to receive signals and send signals to the processors, the signals including computer instructions stored in the memory, and when the processor executes the computer instructions, the chip executes the address mapping method described in the above embodiments of this disclosure.

[0119] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0120] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0121] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0122] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processing module, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (control method), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or otherwise processing as necessary, and then stored in computer memory.

[0123] It should be understood that various parts of the embodiments of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0124] Those skilled in the art will understand that all or part of the steps of the methods described in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0125] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc.

[0126] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. An address mapping method, characterized in that, include: Obtain multiple raw memory addresses, wherein at least two of the multiple raw memory addresses include the same memory bank address; Based on the original address bits of each original memory address, the target address bits of each original memory address are determined, wherein the number of bits of the target address bits is the first preset number, and the first preset number is less than the number of bits of the original address bits; Based on the target address bits and the preset mapping relationship, determine the mapping result for each original memory address; Based on the mapping result and the memory bank address in each original memory address, the target memory address corresponding to each original memory address is determined, wherein the memory bank address included in the target memory address corresponding to different original memory addresses is different.

2. The method according to claim 1, characterized in that, The process of determining the target address bits for each original memory address based on the original address bits of each original memory address includes: From the original address bits of the at least two original memory addresses, determine multiple address bits with different bit values ​​at the same bit position; From the plurality of address bits, a first preset number of address bits are determined as the target address bits.

3. The method according to claim 2, characterized in that, The step of determining the first preset number of address bits from the plurality of address bits as the target address bits includes: Determine the number of address bits n in the bank address of the at least two original memory addresses; Based on the number of address bits n, n groups of target address bits are determined from the plurality of address bits, and each group of target address bits includes the first preset number of address bits.

4. The method according to any one of claims 1 to 3, characterized in that, The step of determining the mapping result for each original memory address based on the target address bits and the preset mapping relationship includes: Using the preset mapping relationship, the mapping results of the target address bits are determined m times, resulting in m mapping results of the target address bits, where the value of m is the same as the value of the number of address bits n of the memory address.

5. The method according to claim 4, characterized in that, The step of determining the target memory address corresponding to each original memory address based on the mapping result and the memory bank address in each original memory address includes: Commands to obtain the raw memory address configuration; Based on the original memory address configuration instructions, the location of each original memory address is determined; The target memory address is determined based on the location, the mapping result, and the storage address.

6. The method according to claim 5, characterized in that, Determining the target memory address based on the location, the mapping result, and the memory address includes: In response to the location being in the memory controller, a preset replacement address bit is obtained from the memory address; The target memory address is obtained by replacing the preset replacement address bits with the m mapping results.

7. The method according to claim 5, characterized in that, Determining the target memory address based on the location, the mapping result, and the memory address includes: In response to the location being between the bus and the memory controller, the memory bank address is replaced with the m mapping results to obtain the target memory address.

8. An address mapping device, characterized in that, include: An acquisition unit is used to acquire multiple raw memory addresses, wherein at least two of the multiple raw memory addresses include the same storage bank address; The first determining unit is configured to determine the target address bits of each original memory address based on the original address bits of each original memory address, wherein the number of bits of the target address bits is a first preset number, and the first preset number is less than the number of bits of the original address bits; The second determining unit is used to determine the mapping result of each original memory address based on the target address bits and the preset mapping relationship; The third determining unit is used to determine the target memory address corresponding to each original memory address based on the mapping result and the memory bank address in each original memory address, wherein the memory bank address included in the target memory address corresponding to different original memory addresses is different.

9. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-7.

10. A chip, characterized in that, The device includes one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from the memory of the electronic device and send the signals to the processors, the signals including computer instructions stored in the memory, which, when executed by the processors, cause the electronic device to perform the method of any one of claims 1-7.

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