Implementation method of SpMV (Space Model Value) on CPU-DCU (Central Processing Unit-Data Communication Unit) heterogeneous platform based on adaptive strategy

Abstract

The invention belongs to the field of high-performance parallel computing, particularly relates to an implementation method of a SpMV on a CPU-DCU heterogeneous platform based on a self-adaptive strategy, and aims to improve the SpMV operation efficiency. The method comprises the following steps: acquiring sparse matrix data at a CPU end, and converting the sparse matrix data into a CSR format to obtain a CSR format array; based on the CSR format array, performing adaptive decomposition on a sparse matrix represented by the CSR format array to obtain a dense block and a sparse block, and constructing an RDCSR format array based on the CSR format array; the RDCSR format array comprises a CSR format array, an array for recording a dense block row index and an array for recording a sparse block row index. And transmitting the RDCSR format array to the DCU, performing adaptive thread allocation on the dense blocks and the sparse blocks at the DCU end, and then executing SpMV calculation in parallel to obtain a merged calculation result. And the merged calculation result is transmitted from the DCU to the CPU, and the calculation performance of the SpMV is evaluated.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of high-performance parallel computing, in particular to a method for implementing SpMV on a CPU-DCU heterogeneous platform based on an adaptive strategy. BACKGROUND

[0002] Sparse matrix-vector multiplication (SpMV) is a core operation in scientific computing, numerical analysis, engineering simulation, etc., and its computational efficiency directly affects the overall performance of large-scale data processing and complex problem solving. With the explosive growth of data size and the continuous improvement of computing demand, a single processor has been difficult to meet the efficient computing demand. CPU-DCU heterogeneous platforms, with the logical control ability of CPU and the parallel computing advantage of DCU, have become an important hardware architecture to support high-performance SpMV operation.

[0003] Traditional SpMV implementation methods generally use a unified matrix storage format (such as CSR format) and a static thread scheduling strategy. However, existing methods cannot effectively distinguish the density and sparsity differences in local regions of the matrix, resulting in unreasonable allocation of storage and computing resources, and difficulty in adapting to different computing needs of dense blocks and sparse blocks, which easily causes thread idling or uneven load, seriously restricting the computing potential of CPU-DCU heterogeneous platforms. SUMMARY

[0004] The purpose of the present application is to provide a method for implementing SpMV on a CPU-DCU heterogeneous platform based on an adaptive strategy, aiming to improve the efficiency of SpMV operation and solve the problem of limited computing performance caused by insufficient matrix structure adaptation and inflexible thread resource allocation in traditional methods.

[0005] To achieve the above purpose, the technical scheme adopted by the present application is as follows: The present application provides a method for implementing SpMV on a CPU-DCU heterogeneous platform based on an adaptive strategy, comprising: S1: obtaining sparse matrix data at the CPU end, converting the sparse matrix data to CSR format, and obtaining a CSR format array; S2: based on the CSR format array, adaptively decomposing the sparse matrix represented by the CSR format array to obtain dense blocks and sparse blocks, and constructing an RDCSR format array based on the CSR format array; the RDCSR format array includes the CSR format array, an array recording the row index of the dense blocks, and an array recording the row index of the sparse blocks; S3: transmitting the RDCSR format array to the DCU, and after adaptively allocating threads to the dense blocks and sparse blocks at the DCU end, performing SpMV calculation in parallel to obtain the merged calculation result; S4: transmitting the merged calculation result from the DCU to the CPU, and evaluating the computing performance of SpMV.

[0006] In step S1, the sparse matrix data stored in the mtx file format is received at the CPU end; basic information such as the number of rows, the number of columns and the total number of non-zero elements of the sparse matrix is extracted, the sparse matrix is converted into the CSR format, and the CSR format array containing the non-zero value array, the column position array and the row offset array is obtained.

[0007] In step S2, the adaptive decomposition of the sparse matrix specifically includes: moving the non-zero elements of each row of the sparse matrix to the left, and counting the number of non-zero elements of each row; taking the number of threads contained in the DCU thread bundle as the division threshold, and dividing the non-zero elements in each row whose number is an integer multiple of the threshold into dense blocks, and dividing the remaining non-zero elements into sparse blocks.

[0008] In step S2, the dense block row index array and the sparse block row index array are constructed to record the row indexes corresponding to the dense blocks and the sparse blocks respectively; the CSR format array is combined with the dense block row index array and the sparse block row index array to form the RDCSR format array.

[0009] In step S3, based on the dense block row index array, a thread bundle is allocated for each row of the dense block, and the threads in the thread bundle correspond to the non-zero elements of the dense block one by one.

[0010] In step S3, the adaptive thread allocation for the sparse block specifically includes: based on the sparse block row index array and the total number of non-zero elements of the sparse block, the number of threads to be allocated for each row of the sparse block is calculated; and according to the calculated number of threads, a corresponding number of threads are allocated for each row of the sparse block.

[0011] In step S3, the SpMV calculation specifically includes: the threads in the thread bundle perform multiplication and addition operations on the non-zero elements of the dense block in parallel to obtain the calculation result of the dense block; the threads allocated to the sparse block perform multiplication and addition operations on the non-zero elements of the sparse block in parallel to obtain the calculation result of the sparse block; and the calculation result of the dense block and the calculation result of the sparse block are combined and written into the DCU global memory.

[0012] In step S4, the combined calculation result in the DCU global memory is transmitted to the CPU end to complete the SpMV calculation process.

[0013] The performance evaluation in step S4 specifically includes: taking the running time as the evaluation index, and comparing and evaluating the calculation performance of the SpMV with the traditional CSR format implementation method.

[0014] The determination method of the division threshold is: taking the number of threads contained in a thread bundle in the DCU as the division threshold, which is used to distinguish the number limit of the non-zero elements of the dense block and the sparse block.

[0015] Compared with the prior art, the present application has the beneficial effects that: 1. The implementation method of SpMV based on adaptive strategy on a CPU-DCU heterogeneous platform provided by the embodiment of the application, through adaptive decomposition of a sparse matrix, the sparse matrix is divided into dense blocks and sparse blocks, which can accurately adapt to the local structure characteristics of the matrix. This decomposition mode breaks through the limitation of the traditional uniform processing mode, so that the subsequent calculation can adopt differentiated strategies according to the difference in sparsity of the two types of blocks, avoiding the waste of resources caused by overall uniform processing. The RDCSR format constructed based on the CSR format extension realizes the explicit recording and rapid positioning of the data of the two types of blocks by adding dense block and sparse block row index arrays. This format not only retains the compact storage advantage of the CSR format for sparse data, but also can directly provide structured data basis for the calculation scheduling of the DCU end, reducing the additional overhead of data analysis and improving the data access efficiency.

[0016] 2. One thread bundle is allocated for each row of the dense block to realize one-to-one mapping of threads and non-zero elements, fully exerting the parallel processing capability of the DCU thread bundle and ensuring saturated utilization of the computing resources in the dense area; and threads are dynamically allocated according to the number of non-zero elements for the sparse block to avoid the problem of idle threads caused by fixed thread allocation and realize balanced scheduling of the computing load in the sparse area. The thread allocation strategies for the two types of blocks work together to significantly improve the utilization rate of the computing resources of the DCU. Through the cooperative design of matrix adaptive decomposition, RDCSR format optimization and thread adaptive allocation, the efficiency bottleneck caused by insufficient structure adaptation and inflexible resource allocation of the traditional SpMV method on the heterogeneous platform is effectively solved. Experimental verification shows that, compared with traditional implementations such as hipSPARSE and CSR_scalar, the method can significantly shorten the running time of SpMV calculation, fully release the computing potential of the CPU-DCU heterogeneous platform and provide an efficient solution for large-scale sparse matrix operation. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a flowchart of the implementation method of SpMV based on adaptive strategy on a CPU-DCU heterogeneous platform provided by the embodiment of the application; Figure 2 is a strategy diagram of adaptive matrix decomposition provided by the embodiment of the application; Figure 3 is a schematic diagram of the RDCSR storage format provided by the embodiment of the application; Figure 4 is a schematic diagram of the SpMV calculation process provided by the embodiment of the application; Figure 5 is a schematic diagram of the parallel algorithm of dense block SpMV provided by the embodiment of the application; Figure 6 is a schematic diagram of the parallel algorithm of sparse block SpMV provided by the embodiment of the application; Figure 7 is a basic information schematic diagram of a SuiteSparse matrix library provided by an embodiment of the present application. Figure 8 is a performance evaluation experimental result diagram provided by an embodiment of the present application. DETAILED DESCRIPTION

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0019] Before describing the implementation method of SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform provided by an embodiment of the present application, the English mentioned in the present application is explained: SpMV: Sparse Matrix-Vector Multiplication (Sparse Matrix-Vector Multiplication), is a core operation in the field of scientific computing, which refers to the multiplication operation of a sparse matrix and a vector.

[0020] CPU: Central Processing Unit (Central Processing Unit), is the core component of a computer, responsible for data processing and logic control, in the present application, as part of a heterogeneous platform, responsible for preprocessing and receiving calculation results.

[0021] DPU: Data Processing Unit (Data Processing Unit), in the present application, as a core component of a heterogeneous platform for performing parallel computing, has strong parallel computing capability.

[0022] CSR: Compressed Sparse Row (Compressed Sparse Row), is a commonly used sparse matrix storage format, which compresses and stores a sparse matrix through a non-zero value array, a column position array and a row offset array.

[0023] RDCSR: Row Decomposition Compressed Spare Row (Row Decomposition Compressed Spare Row), is an extended format constructed in the present application, which adds a dense block and a sparse block row index array based on CSR.

[0024] The embodiment of the present application provides an implementation method of SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform, for example, as shown in Figure 1 The method comprises the following steps: S1: Obtain sparse matrix data at the CPU end, convert the sparse matrix data into a CSR format, and obtain a CSR format array.

[0025] More specifically, in step S1, sparse matrix data stored in an mtx file format is received at the CPU end; basic information such as the number of rows m, the number of columns n, and the total number of non-zero elements nnz of the sparse matrix is extracted, the sparse matrix is converted into a CSR format, and a CSR format array containing a non-zero value array data array, a column position array col index array, and a row offset array row pointer array is obtained.

[0026] S2: Based on the CSR format array, the sparse matrix represented thereby is adaptively decomposed to obtain dense blocks and sparse blocks, and an RDCSR format array is constructed based on the CSR format array. The RDCSR format array contains the CSR format array, an array recording the row indexes of the dense blocks, and an array recording the row indexes of the sparse blocks.

[0027] For example, referring to Figure 2 In step S2, the adaptive decomposition of the sparse matrix specifically includes: S21: Shift the non-zero elements of each row of the sparse matrix to the left, and count the number of non-zero elements in each row.

[0028] First, the non-zero elements of each row of the matrix are shifted to the left, the row pointer array of the sparse matrix is traversed, and the difference between adjacent elements is used to calculate the number of non-zero elements in each row of the sparse matrix . The specific calculation formula is as follows: wherein, is the row offset array of the sparse matrix.

[0029] S22: Take the number of threads contained in a DCU thread bundle as the division threshold, divide the non-zero elements in each row whose number is an integer multiple of the threshold into dense blocks, and divide the remaining non-zero elements into sparse blocks.

[0030] As a possible implementation manner, the determination manner of the division threshold is as follows: take the number of threads contained in a thread bundle in a DCU as the division threshold, which is used to distinguish the number boundary of the non-zero elements of the dense blocks and the sparse blocks.

[0031] For example, take the number of threads contained in a DCU thread bundle as the division threshold , that is, . According to the number of non-zero elements in a row and the division threshold Adaptive decomposition is performed on each row of the matrix. For each row, the first non-zero elements (multiples of k) are placed into a dense block, and the remaining non-zero elements (the remainder after subtracting multiples of k from the total number of non-zero elements) are placed into a sparse block. If the number of non-zero elements in the current row is... for Integer multiples of, i.e. If the number of non-zero elements in the current row satisfies the condition, then the entire row is divided into dense blocks. If the number of non-zero elements in the current row is [value missing], then the entire row is divided into sparse blocks. And not for Integer multiples of, i.e. Then the line before Each element is divided into a dense block, and the remaining elements are... Each element is assigned to a sparse block.

[0032] In step S2, a dense block row index array and a sparse block row index array are constructed, and the row indices corresponding to the dense blocks and sparse blocks are recorded respectively. The CSR format array is merged with the dense block row index array and the sparse block row index array to form an RDCSR format array.

[0033] For example, after completing the matrix decomposition, construct a dense block row index array and a sparse block row index array, respectively recording the row indices corresponding to the dense block and the sparse block, and simultaneously calculate the lengths of the two arrays, with the length of the dense block row index array being L1 and the length of the sparse block row index array being L2.

[0034] For example, such as Figure 3 As shown, the RDCSR format array is composed of the original CSR format array, the dense block row index array dense_indices, and the sparse block row index array sparse_indices.

[0035] S3: Transmit the RDCSR format array to the DCU. After adaptive thread allocation for dense and sparse blocks at the DCU, perform SpMV calculation in parallel to obtain the merged calculation result.

[0036] Specifically, transferring the RDCSR format array to the DCU includes transferring the row offset array, column index array, non-zero value array, dense block row index array, and sparse block row index array constructed in step S3 to the DCU.

[0037] In step S3, based on the dense block row index array, a thread bundle is allocated to each row of the dense block, and the threads in the thread bundle correspond one-to-one with the non-zero elements of the dense block.

[0038] For example, in a DCU, a thread bundle contains 64 threads. For dense blocks where the number of non-zero elements is a multiple of 64, one thread bundle is allocated to each row, implementing a one-to-one mapping between threads and non-zero elements, thereby enabling full-load parallel processing of that row and avoiding thread idleness. This depends on the thread block size. Calculate the number of thread blocks in the dense block section. , The specific calculation formula is as follows: in Indicates the thread bundle size. The number of rows in the dense block. The number of threads that can be accommodated in each thread block.

[0039] In step S3, adaptive thread allocation for sparse blocks specifically includes: calculating the number of threads required for each row of the sparse block based on the row index array of the sparse block and the total number of non-zero elements in the sparse block; and allocating the corresponding number of threads to each row of the sparse block according to the calculated number of threads.

[0040] For sparse blocks, the adaptive thread count is calculated according to the formula. Assign each row of the sparse block There are 10 threads, each performing the multiplication and addition operation in parallel at its corresponding position. (Number of threads per line) The calculation formula is as follows: in, The number of rows in the dense block. The number of rows in the sparse block. The total number of non-zero elements in the matrix.

[0041] in accordance with and The size of the sparse block is used to calculate the number of thread blocks in the sparse block portion. , The calculation formula is as follows: ; in The number of threads allocated to each line of the sparse block. The number of rows in the sparse block.

[0042] For example, such as Figure 4In step S3, the SpMV calculation specifically includes: threads within a thread bundle performing multiplication and addition operations on the non-zero elements of the dense block in parallel, and reducing to obtain the dense block calculation result; threads allocated to the sparse block performing multiplication and addition operations on the non-zero elements of the sparse block in parallel, and reducing to obtain the sparse block calculation result; merging the dense block calculation result and the sparse block calculation result and writing them into the DCU global memory.

[0043] For the computation of dense block SpMV, each thread obtains the row number to be processed from the dense block row index array dense_indices. Then, obtain the row start from the row_pointer_array array, based on the number of non-zero elements in the current row. Adjust the ending position This is to ensure that the number of elements is a multiple of 64. The calculation formula is as follows: in The row index calculated for the current thread. It is a row offset array. The number of non-zero elements in the current row.

[0044] Within a thread bundle, 64 threads read data in parallel and execute corresponding multiply-accumulate operations with a step size of 64. After calculation, the intermediate product results are reduced using a shuffle instruction and integrated into the sum of products for that row of dense blocks. The parallel algorithm for dense block SpMV is as follows: Figure 5 As shown.

[0045] For the computation of sparse block SpMV, the global thread ID is calculated using blockIdx and threadIdx, and then mapped to sparse_indices to obtain the row index. Get the starting position of the current row from the row_pointer_array array. And based on the number of non-zero elements in that row Adjust the starting position This ensures that the remaining elements are processed. The adjustment calculation formula is as follows: in The row index calculated for the current thread. It is a row offset array. The number of non-zero elements in the current row. TpR threads read data in parallel and perform corresponding multiply-accumulate operations with a step size of TpR. After the calculation is completed, the intermediate product results of each thread are reduced by the shuffle instruction and integrated into the sum of the products of the sparse blocks in the row.

[0046] For example, the sparse block SpMV parallel algorithm is shown in Figure 6 The merging is completed by the first thread of each row writing the two-part result into the DCU global memory by atomic operation.

[0047] S4: transmitting the merged calculation result from the DCU to the CPU, and evaluating the calculation performance of the SpMV.

[0048] The performance evaluation in step S4 specifically includes: taking the running time as an evaluation index, and comparing and evaluating the calculation performance of the SpMV with the traditional CSR format implementation method.

[0049] To verify the actual effect of the method provided by the embodiments of the application, the application is compared with the traditional CSR format method such as hipSPARSE, CSR_scalar, CSR_vector and light_spmv, and the performance is evaluated by taking the running time as an index. The test is performed on the Supercomputing Platform of HUANGXI, the operating system of which is Linux 3.1.0, the version of rocm heterogeneous programming is 4.0, the CPU compiler is gcc / g++ 7.3.1, and the DCU accelerator compiler is hipcc-24.04.0. The system is equipped with HUANGXI 7185 CPU processor and HUANGXI DC1000 accelerator. The HUANGXI 7185 CPU adopts X86 architecture, has 32 cores, and has high calculation capacity, memory performance and I / O expansion capacity.

[0050] To comprehensively evaluate the performance of the method of the application, multiple typical sparse matrices from the SuiteSparse matrix library are selected as test objects, and the basic information of the test objects is shown in Figure 7 The performance evaluation result obtained by the experiment is shown in Figure 8 The running efficiency of the SpMV implementation method based on the adaptive strategy provided by the application is better than that of the existing method on multiple sparse matrices. Compared with the traditional CSR format implementation methods such as hipSPARSE, CSR_scalar, CSR_vector and light_spmv, the method significantly shortens the execution time of the sparse matrix-vector multiplication, and verifies the high efficiency of the method on the CPU-DCU heterogeneous platform.

[0051] The method provided by the application mainly comprises two stages: a CPU preprocessing stage and a DCU parallel computing stage. In the CPU preprocessing stage, an adaptive matrix decomposition strategy is adopted to split a sparse matrix into dense blocks and sparse blocks, and an RDCSR storage structure is established to clearly record the data of the dense blocks and the sparse blocks; in the DCU parallel computing stage, an adaptive thread allocation strategy is adopted, the dense blocks adopt a parallel scheduling mode of the thread bundle level, the sparse blocks adopt a parallel scheduling mode of the thread level, and thread resources are adaptively allocated according to the number of non-zero elements. By allowing the dense blocks and the sparse blocks to perform SpMV calculation in parallel, the calculation efficiency of SpMV is improved.

[0052] In the description of the present specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0053] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform, characterized in that, include: S1: Obtain sparse matrix data on the CPU, convert the sparse matrix data into CSR format, and obtain a CSR format array; S2: Based on the CSR format array, adaptively decompose the sparse matrix represented by it to obtain dense blocks and sparse blocks, and construct an RDCSR format array based on the CSR format array; the RDCSR format array includes the CSR format array, an array recording the row indices of dense blocks, and an array recording the row indices of sparse blocks; S3: Transmit the RDCSR format array to the DCU, and after adaptively allocating threads for dense blocks and sparse blocks at the DCU, execute SpMV calculation in parallel to obtain the merged calculation result; S4: Transmit the merged calculation result from the DCU to the CPU, and evaluate the calculation performance of SpMV.

2. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 1, characterized in that: In step S1, sparse matrix data stored in mtx file format is received at the CPU. Extract basic information such as the number of rows, columns, and total number of non-zero elements from the sparse matrix, and convert the sparse matrix into the CSR format to obtain a CSR format array containing an array of non-zero values, an array of column positions, and an array of row offsets.

3. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 1, characterized in that: In step S2, the adaptive decomposition of the sparse matrix specifically includes: shifting the non-zero elements of each row of the sparse matrix to the left and counting the number of non-zero elements in each row; using the number of threads contained in the DCU thread bundle as the partitioning threshold, dividing the non-zero elements in each row that are integer multiples of the threshold into dense blocks, and dividing the remaining non-zero elements into sparse blocks.

4. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 1, characterized in that, In step S2, a dense block row index array and a sparse block row index array are constructed to record the row indices corresponding to the dense blocks and sparse blocks, respectively; the CSR format array is merged with the dense block row index array and the sparse block row index array to form the RDCSR format array.

5. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 1, characterized in that: In step S3, based on the dense block row index array, a thread bundle is allocated to each row of the dense block, and the threads in the thread bundle correspond one-to-one with the non-zero elements of the dense block.

6. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 1, characterized in that: In step S3, adaptive thread allocation for sparse blocks specifically includes: calculating the number of threads required for each row of the sparse block based on the row index array of the sparse block and the total number of non-zero elements in the sparse block; and allocating a corresponding number of threads to each row of the sparse block according to the calculated number of threads.

7. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 1, characterized in that: In step S3, performing SpMV calculation specifically includes: threads within the thread bundle performing multiply-add operations on the non-zero elements of the dense block in parallel, reducing to obtain the dense block calculation result; threads allocated to the sparse block performing multiply-add operations on the non-zero elements of the sparse block in parallel, reducing to obtain the sparse block calculation result; merging the dense block calculation result and the sparse block calculation result and writing them into the DCU global memory.

8. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 1, characterized in that, In step S4, the merged calculation results in the DCU global memory are transferred to the CPU to complete the calculation process of SpMV.

9. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 1, characterized in that, The performance evaluation in step S4 specifically includes: using runtime as the evaluation metric, comparing and evaluating the computational performance of the SpMV with that of the traditional CSR format implementation method.

10. The method for implementing SpMV based on an adaptive strategy on a CPU-DCU heterogeneous platform according to claim 3, characterized in that, The partitioning threshold is determined by using the number of threads contained in a thread bundle in the DCU as the partitioning threshold, which is used to distinguish the non-zero element limit between dense blocks and sparse blocks.

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