Method and device for generating excitation file of large-scale integrated circuit
By automatically generating stimulus sequences using a reinforcement learning framework, the inefficiency of traditional methods is solved, enabling efficient integrated circuit verification and reducing the cost of manual intervention.
Patent Information
- Application Number
- CN202510988134.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-17
- Publication Date
- 2025-11-25
AI Technical Summary
Traditional methods for generating incentive files are inefficient, fail to meet the design and verification requirements of modern large-scale integrated circuits, and are costly to require manual intervention.
A reinforcement learning-based verification framework is adopted, which forms a closed-loop feedback through coverage collection, dynamic reward mechanism and incremental learning, automatically generates incentive sequences with high coverage and optimizes incentive generation strategy.
It improves the efficiency of incentive file generation, reduces the verification cycle, lowers the cost of manual intervention, and avoids verification vulnerabilities.
Smart Images
Figure CN121009949A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit design and verification technology, and more specifically, to a method and apparatus for generating stimulus files for large-scale integrated circuits. Background Technology
[0002] With the development of emerging technologies such as artificial intelligence and the Internet of Things, the integration and complexity of large-scale integrated circuits are constantly increasing, which poses a huge challenge to the design verification of integrated circuits. Among them, the generation of stimulus files is a key step in the design verification process, which directly affects the efficiency and quality of verification.
[0003] Traditional stimulus file generation methods primarily employ constrained random verification and coverage-driven verification approaches. In specific verification scenarios, random stimuli are subject to limitations in achieving coverage targets, a process that often consumes significant time and effort, resulting in low efficiency. With the increasing complexity of large-scale integrated circuits, traditional chip verification methods are struggling to meet the demands of modern large-scale chip development. Therefore, a new stimulus file generation method is urgently needed to improve the efficiency of large-scale integrated circuit design verification. Summary of the Invention
[0004] This invention provides a method and apparatus for generating stimulus files for large-scale integrated circuits. Based on a reinforcement learning-based verification framework, it employs an intelligent stimulus generation method that forms a closed-loop feedback loop through coverage collection, a dynamic reward mechanism, and incremental learning. By optimizing the closed-loop loop iteratively, it effectively solves the problems of inaccurate stimulus generation and high cost of manual intervention in traditional methods, thereby automatically generating stimulus sequences with high coverage and shortening the verification cycle of large-scale integrated circuits.
[0005] In a first aspect, the present invention provides a method for generating a large-scale integrated circuit stimulus file, the method comprising:
[0006] Obtain the technical information of the target integrated circuit, and determine the target standard specifications based on the technical information;
[0007] A verification environment platform was built based on the aforementioned target standard specifications;
[0008] Simulations were performed using the aforementioned verification environment platform to collect code coverage data.
[0009] Configure the original reinforcement learning environment, and determine the reward / penalty value based on the original reinforcement learning environment and the code coverage;
[0010] The original reinforcement learning environment is iteratively updated based on the reward and penalty values to determine the target reinforcement learning environment;
[0011] The target incentive file is determined based on the target reinforcement learning environment.
[0012] Preferably, the step of acquiring the technical information of the target integrated circuit and determining the target standard specification based on the technical information includes:
[0013] The technical information includes the requirements specification and RTL code of the target integrated circuit;
[0014] The target standard specification is determined by parsing the requirements specification and the RTL code.
[0015] Preferably, the step of performing simulation based on the verification environment platform to collect code coverage includes:
[0016] Based on the verification environment platform, data interaction between the Python environment and the verification environment platform is realized through the DPI interface, and simulation is performed to collect the code coverage.
[0017] Preferably, the configuration of the original reinforcement learning environment includes:
[0018] Specify the design module to be verified in the target integrated circuit;
[0019] Specify the target ports that contribute to the coverage of the design module;
[0020] Define the action space based on all possible combinations of values for the target port;
[0021] A reinforcement learning algorithm is determined based on the action space; the reinforcement learning algorithm is selected as the learning strategy.
[0022] Determine the coverage type used to calculate rewards;
[0023] Establish a reward and punishment scheme.
[0024] Preferably, determining the reward / penalty value based on the original reinforcement learning environment and the code coverage includes:
[0025] The reward / penalty value is determined dynamically based on the comparison between the current code coverage and the code coverage described in the previous step, and the reward / penalty scheme.
[0026] Preferably, the reward and punishment scheme includes:
[0027] The reward and punishment scheme includes a reward scheme and a punishment scheme;
[0028] The reward scheme is as follows: if the current code coverage rate improves compared to the code coverage rate in the previous step, a positive reward or penalty value is given.
[0029] The penalty scheme is as follows: if the current code coverage rate decreases or does not improve compared to the code coverage rate in the previous step, a reverse reward or penalty value is given.
[0030] Preferably, the step of iteratively updating the original reinforcement learning environment based on the reward / penalty value to determine the target reinforcement learning environment includes:
[0031] The validity of the current round of simulation is determined based on the reward and penalty values;
[0032] The learning strategy is updated and optimized based on its effectiveness.
[0033] The target reinforcement learning environment is determined when the code coverage reaches a preset target.
[0034] In a second aspect, the present invention provides an apparatus for generating large-scale integrated circuit stimulus files, comprising:
[0035] The target standard specification determination module is used to acquire technical information of the target integrated circuit and determine the target standard specification based on the technical information.
[0036] The verification environment platform construction module is used to build a verification environment platform based on the target standard specifications.
[0037] The code coverage collection module is used to perform simulation based on the verification environment platform to collect code coverage.
[0038] The reward / penalty value determination module is used to configure the original reinforcement learning environment and determine the reward / penalty value based on the original reinforcement learning environment and the code coverage.
[0039] The target reinforcement learning environment determination module is used to iteratively update the original reinforcement learning environment based on the reward and penalty value to determine the target reinforcement learning environment.
[0040] The target incentive file determination module is used to determine the target incentive file based on the target reinforcement learning environment.
[0041] Thirdly, the present invention provides a readable medium including executable instructions, which, when executed by a processor of an electronic device, cause the electronic device to perform any of the methods described in the first aspect.
[0042] Fourthly, the present invention provides an electronic device including a processor and a memory storing execution instructions, wherein when the processor executes the execution instructions stored in the memory, the processor performs the method as described in any of the first aspects.
[0043] This invention provides a method and apparatus for generating stimulus files for large-scale integrated circuits. Based on a reinforcement learning-based verification framework, it employs an intelligent stimulus generation method that uses a closed-loop feedback mechanism—coverage collection, dynamic reward mechanism, and incremental learning—to effectively address the problems of inaccurate stimulus generation and high manual intervention costs associated with traditional methods. This achieves automatic generation of high-coverage stimulus sequences, shortening the verification cycle of large-scale integrated circuits. This invention includes at least the following beneficial results:
[0044] 1. Improved stimulus file generation efficiency. By enhancing the interaction between the learning environment and the simulation environment, the stimulus generation strategy can be automatically optimized, significantly reducing the number of stimuli required to achieve the coverage target and effectively shortening the verification cycle;
[0045] 2. Flexible configuration to adapt to different needs. The reinforcement learning environment is highly configurable in terms of learning strategies, reward schemes, and coverage types. Users can flexibly adjust these parameters according to specific large-scale integrated circuit design and verification needs to obtain the best incentive file generation results;
[0046] 3. Reduced the cost of manual intervention. It reduced the reliance on manually writing targeted test cases, decreased the workload of engineers, and avoided verification vulnerabilities caused by insufficient human experience.
[0047] The further effects of the aforementioned non-conventional preferred method will be explained below in conjunction with specific embodiments. Attached Figure Description
[0048] To more clearly illustrate the embodiments of the present invention or the existing technical solutions, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0049] Figure 1 This is a schematic diagram of a method for generating a large-scale integrated circuit stimulus file according to an embodiment of the present invention;
[0050] Figure 2 This is a schematic diagram of the architecture for generating incentive files in a reinforcement learning environment according to one embodiment of the present invention;
[0051] Figure 3 This is a schematic diagram of another method for generating stimulus files for large-scale integrated circuits according to an embodiment of the present invention;
[0052] Figure 4 This is a schematic diagram of a device for generating stimulus files for large-scale integrated circuits according to an embodiment of the present invention;
[0053] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation
[0054] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.
[0055] With the development of emerging technologies such as artificial intelligence and the Internet of Things, the integration and complexity of large-scale integrated circuits are constantly increasing, which poses a huge challenge to the design verification of integrated circuits. Among them, the generation of stimulus files is a key step in the design verification process, which directly affects the efficiency and quality of verification.
[0056] Traditional stimulus file generation methods primarily employ constrained random verification and coverage-driven verification approaches. In specific verification scenarios, random stimuli are subject to limitations in achieving coverage targets, a process that often consumes significant time and effort, resulting in low efficiency. With the increasing complexity of large-scale integrated circuits, traditional chip verification methods are struggling to meet the demands of modern large-scale chip development. Therefore, a new stimulus file generation method is urgently needed to improve the efficiency of large-scale integrated circuit design verification.
[0057] In view of this, the present invention provides a method for generating stimulus files for large-scale integrated circuits. See also Figure 1 The image shows a specific embodiment of a method for generating stimulus files for large-scale integrated circuits provided by the present invention. The method includes:
[0058] Step 101: Obtain the technical information of the target integrated circuit and determine the target standard specifications based on the technical information;
[0059] In this embodiment, the target integrated circuit refers to a large-scale integrated circuit that requires design verification using stimulus documents. Technical information includes the target integrated circuit's requirements specification and RTL code. The requirements specification is a document that details the software system requirements of the target integrated circuit, focusing on standardizing the requirements from a technical perspective. It includes detailed descriptions of the software system's functional requirements, performance requirements, interface requirements, data requirements, and security requirements, typically containing detailed technical descriptions such as use case diagrams, flowcharts, and data dictionaries to accurately define what the software system should do and what technical specifications it should achieve. Its purpose is to provide detailed technical guidance for software developers, serving as an important basis in the software development process, helping developers accurately understand customer needs, ensuring the developed software system meets expected functional and performance requirements, and also serving as an important reference document for software testers designing test cases. RTL code, or Register Transfer Level code, is an encoding method used to describe Hardware Description Language (HDL) codes for digital circuits. In the target integrated circuit design, RTL code is mainly used to describe the key characteristics of synchronous digital circuits, including combinational logic, registers, and clock control.
[0060] Furthermore, the target standard specification is determined by parsing the requirements specification and RTL code. Specifically, the document structure of the requirements specification is first analyzed to clarify the description location and boundaries of each functional module. For example, for a large-scale integrated circuit with data processing and communication functions, the requirements descriptions of different functional areas such as data processing modules and communication interface modules are distinguished, and port-related information is extracted. For example, if a port is used for data input, its corresponding data processing module and its role in the communication protocol are identified. The requirements specification and RTL code of the given target integrated circuit are parsed to extract the parameters of the main ports, including port name, type, size, and orientation. Then, this extracted information is used to create the target standard specification in Extensible Markup Language (XML) format. During the construction process, a specific XML architecture design is followed to ensure that all port nodes contain the correct attributes, and that attribute values conform to the predetermined format and value range, ensuring the accuracy and reliability of the target standard specification and providing a solid foundation for subsequent processes. This step provides standardized basic data for the subsequent generation of the verification environment platform and the entire stimulus file generation process.
[0061] Step 102: Build a verification environment platform based on the target standard specifications;
[0062] Based on the target standard specifications compiled in step 101, the verification environment platform can be built. SystemVerilog can be chosen as the construction language, leveraging its powerful verification capabilities and rich class libraries. During the construction process, open-source verification platform templates can be referenced and customized according to the specific target integrated circuit design requirements. For example, for complex chip designs containing multiple sub-modules, each sub-module needs to be correctly instantiated in the verification environment platform, and the signals between modules need to be properly connected. The verification environment platform can be used to simulate the input stimulus files to output the corresponding code coverage.
[0063] For functional modules such as stimulus-driven and response-monitoring in the verification environment platform, customized generation is performed according to target standard specifications. For example, based on the direction and function of the ports, corresponding signal driving logic is generated in the stimulus-driven module. For input ports, code logic is generated to drive signal changes according to certain timing and rules; for output ports, code logic is generated in the response-monitoring module to monitor signal changes and perform corresponding processing, ensuring that the verification environment platform can accurately verify the target integrated circuit.
[0064] Step 103: Perform simulation based on the verification environment platform to collect code coverage;
[0065] Code coverage is a metric in integrated circuit testing that describes the proportion and extent to which the source code of an application is tested. It is calculated by dividing the execution results of test cases by the number of lines of code. Code coverage is a crucial indicator of the adequacy and completeness of software testing. This embodiment uses code coverage as a benchmark to evaluate the quality of stimulus file generation. Based on a verification environment platform, data interaction between the Python environment and the verification environment platform is achieved through the DPI (Direct Programming Interface) interface, and simulation is performed to collect code coverage data. Specifically, since the stimulus file generation environment is implemented in Python, while the verification environment platform is based on SystemVerilog, their data structures differ. To address this issue, DPI technology is used to build a data interaction bridge, enabling data communication with the Python environment and interaction with the verification environment platform. On the Python side, specific function calls send data (such as generated stimulus signal values) to the verification environment platform to the intermediate interface program. In the intermediate interface program, the received data is formatted and processed to conform to SystemVerilog data type requirements. Then, the processed data is passed to the corresponding variables in the verification environment platform through the DPI interface. Data returned from the verification environment platform (such as simulation results and coverage information) is also passed to the intermediate interface program via the DPI interface. The intermediate interface program converts the data into a format that Python can recognize before passing it to the corresponding processing module in the Python environment, thus achieving efficient and accurate data interaction between the Python environment and the verification environment platform.
[0066] After completing the verification environment platform setup in step 102, use professional hardware simulation tools (such as ModelSim, VCS, etc.) for simulation. In the simulation tool settings, enable the coverage collection function and select the coverage type to be collected, such as line coverage, branch coverage, conditional coverage, etc., according to the specific verification requirements. During simulation, the verification environment platform drives the target integrated circuit to operate according to preset stimulus signals. The simulation tool monitors the circuit's operating status in real time and analyzes and statistically analyzes the code execution based on pre-set coverage calculation rules. For example, for each line of code, it records whether it has been executed; for each branch condition, it determines whether it is satisfied and executes the corresponding branch, etc.
[0067] After the simulation, the simulation tool generates a detailed coverage report. The report lists the coverage details for various coverage types, including covered and uncovered code sections. Analysis of the coverage report clarifies the extent to which the current stimulus signals cover the target integrated circuit's functional verification, providing crucial information for subsequent optimization of the reinforcement learning environment and the generation of stimulus files.
[0068] Step 104: Configure the original reinforcement learning environment and determine the reward / penalty value based on the original reinforcement learning environment and code coverage;
[0069] In this embodiment, the original reinforcement learning (RL) environment can be configured based on OpenAI's Gym, and the following information needs to be configured:
[0070] Design Module: Specifies the large-scale integrated circuit design module to be verified; Coverage Type: Determines the data type of coverage used to calculate the reward, such as row coverage, finite state machine coverage, flip coverage, conditional coverage, and branch coverage; Learning Policy: Selects the algorithm to guide the learning process of the reinforcement learning agent, such as the Proximal Policy Optimization (PPO) algorithm or the Deep Q-Network (DQN) algorithm; Target Port: Specifies the port that contributes to the increase in coverage; Reward / Penalty Scheme: Selects either a reward scheme or a penalty scheme.
[0071] The reinforcement learning (RL) described in this embodiment is a machine learning method in which a reinforcement learning agent learns how to take actions to maximize a certain cumulative reward by interacting with the reinforcement learning environment. The core idea of reinforcement learning is to allow the reinforcement learning agent to continuously adjust its learning strategy through trial and error, eventually learning the optimal strategy.
[0072] Furthermore, the reward / penalty value is dynamically calculated and determined based on the comparison between the current code coverage and the code coverage of the previous step, and the reward / penalty scheme. After each simulation cycle, the original reinforcement learning environment needs to automatically read the code coverage data output by the simulator. Different simulators may output code coverage data in different formats, therefore, an adapted parsing program needs to be written. Taking the VCS simulator as an example, its code coverage data is stored in a specific text format. A parsing script can be written in Python, using regular expressions to extract key code coverage information. The specific rules for reward / penalty values are applied as follows:
[0073] After each new code coverage data is read, the current code coverage of the current step is compared with the code coverage of the previous step. If the current code coverage exceeds the code coverage of the previous step, it indicates that the incentive signal generated by the reinforcement learning agent has played a positive role in improving code coverage, and according to the reward and punishment scheme, the reward or punishment value is assigned to 1.
[0074] If code coverage decreases, and the selected reward / penalty scheme is a penalty scheme, the reward / penalty value is set to -1 according to the rules to punish the reinforcement learning agent for ineffective action selection, prompting it to adjust its strategy. When the selected reward / penalty scheme is a reward scheme, the reward / penalty value is set to 0, meaning that no positive reward is given for the decrease in code coverage, but no penalty is imposed either, encouraging the reinforcement learning agent to continue exploring other actions that may improve code coverage.
[0075] If the code coverage remains constant, rewards and penalties are assigned according to the selected reward and penalty scheme. Under the penalty scheme, the value is -1; under the reward scheme, the value is 0. By strictly adhering to these rules, clear feedback signals are provided to the reinforcement learning agent, guiding it to continuously optimize its incentive signal generation strategy to improve the verification coverage of the target integrated circuit.
[0076] Step 105: Iteratively update the original reinforcement learning environment based on the reward and penalty values to determine the target reinforcement learning environment;
[0077] Specifically, such as Figure 2 As shown, the effectiveness of the current simulation round is determined based on the reward and penalty values. The learning strategy is then updated and optimized based on this effectiveness until the code coverage reaches the preset target, thus determining the target reinforcement learning environment. The original reinforcement learning environment refers to the initially configured reinforcement learning environment, where the learning strategy is in the early stages of iteration. The reinforcement learning agent selects actions from the action space based on the selected learning strategy. Different algorithms have different selection mechanisms when choosing actions. For example, the DQN algorithm selects the action with the largest Q-value based on the action value function Q-value; the PPO algorithm samples and selects actions based on the action probability distribution output by the policy network. The reinforcement learning agent packages the generated incentive signals (incentive sequences) and corresponding port names into a message packet, which is the incentive file. The format of the message packet needs to be defined in advance to ensure accurate transmission between the Python environment and the verification environment platform.
[0078] When the verification environment platform issues a request, the reinforcement learning agent sends a message packet to the platform through a pre-established data transmission channel, driving the simulation to run. During the simulation, the simulation's running status needs to be monitored to ensure it proceeds normally. After the simulation ends, the reinforcement learning agent receives the reward / penalty value corresponding to the action and evaluates the effectiveness of the action based on the reward. The evaluation process considers not only the magnitude of the reward / penalty value but also a comprehensive analysis of factors such as the action's contribution to improving code coverage and the frequency of action execution.
[0079] Reinforcement learning agents update their policies based on the learned strategy to select the next better action. The policy update process involves the core computations of the algorithm. For example, the DQN algorithm updates network parameters through the target network and experience replay mechanism, while the PPO algorithm updates the policy network by optimizing the objective function. This process is repeated until the code coverage reaches a predetermined target (e.g., 100%) or a pre-set maximum number of steps is reached. The original reinforcement learning environment with the iteratively learned policy at this point is the target reinforcement learning environment.
[0080] Step 106: Determine the target incentive file based on the target reinforcement learning environment.
[0081] Each iteration in the above steps is accompanied by a corresponding incentive file. After the final update, the incentive file generated by the reinforcement learning agent in the target reinforcement learning environment is the target incentive file. The code coverage corresponding to this target incentive file reaches the predetermined target and meets the generation requirements.
[0082] As can be seen from the above technical solution, the beneficial effects of this embodiment are: improved stimulus file generation efficiency. Through the interaction between the reinforcement learning environment and the simulation environment, the stimulus generation strategy can be automatically optimized, significantly reducing the number of stimuli required to achieve the coverage target and effectively shortening the verification cycle. It also reduces the cost of manual intervention, decreases the reliance on manually writing targeted test cases, reduces the workload of engineers, and avoids verification vulnerabilities caused by insufficient human experience.
[0083] Figure 1 The embodiments shown are merely basic examples of the method of the present invention. Other preferred embodiments of the method can be obtained by making certain optimizations and extensions based on them.
[0084] like Figure 3 The illustration shows another specific embodiment of a method for generating stimulus files for large-scale integrated circuits according to the present invention. This embodiment further describes the method based on the foregoing embodiments, and includes the following steps:
[0085] Step 301: Specify the design module to be verified in the target integrated circuit;
[0086] This embodiment describes the configuration process of the original reinforcement learning environment. To adapt to the design and verification requirements of the target integrated circuit, the original reinforcement learning environment is configured accordingly. Specifically, when configuring the original reinforcement learning environment under OpenAI's Gym framework, the design module of the target integrated circuit to be verified must be explicitly specified. Taking the verification of the storage control module in a large-scale integrated circuit as an example, the configuration interface of the Gym environment can be opened or configured by writing a configuration file. In the configuration file, a specific identifier is used to specify the module, such as "design_module:"storage_control_module"". After the configuration is complete, a module recognition test is required. A simple query command can be sent to the original reinforcement learning environment to check whether the original reinforcement learning environment has correctly identified and loaded the specified design module, ensuring that the subsequent reinforcement learning process focuses on the verification requirements of this design module.
[0087] Step 302: Specify the target ports that contribute to the coverage of the design modules;
[0088] In the port configuration section, explicitly specify a list of port names that contribute to increased coverage. By analyzing the functions of the large-scale integrated circuit, determine which port signal changes can effectively affect the circuit's functionality and coverage improvement. Accurately enter these port names in the configuration file; these ports are the target ports.
[0089] Step 303: Define the action space based on all possible combinations of values for the target port;
[0090] For a given target port, a thorough analysis is performed on all possible values that each target port can present, thereby accurately determining the action space. Taking an 8-bit control port in a digital signal processing module as an example, its theoretical value range is 0 to 2. 8 -1, which represents values from 0 to 255. However, in practical applications, some values may be invalid due to design constraints, and these invalid values need to be excluded according to the target standard specifications. After determining the action space, a completeness check needs to be performed on the action space to ensure that it covers all possible valid actions. This can be done by writing a simple script to traverse each value in the action space and check whether it meets the design requirements. Simultaneously, to facilitate the reinforcement learning agent's understanding and use of the action space, actions can be encoded, such as using one-hot encoding, mapping each action to a unique encoded vector, providing the reinforcement learning agent with a clear range of action choices.
[0091] Step 304: Determine the reinforcement learning algorithm based on the action space; select the reinforcement learning algorithm as the learning strategy.
[0092] Depending on the complexity of the integrated circuit design and verification requirements, a suitable learning strategy can be carefully selected from algorithms such as Proximal Policy Optimization (PPO) and Deep Q-Network (DQN). If the action space of the design module is continuous, such as parameter adjustment of an analog signal, where parameter values can change continuously within a certain range, the PPO algorithm can be given priority due to its ability to effectively handle continuous action spaces. If the action space is discrete, such as the selection of an instruction opcode, where the opcode has a finite number of discrete values, the DQN algorithm, which selects the optimal action by learning an action value function, may be more suitable. After selecting an algorithm, it is also necessary to configure corresponding hyperparameters, such as the learning rate and discount factor, according to the characteristics of the algorithm, and adjust and optimize them through small-scale pre-experiments. In the learning strategy configuration section, the algorithm that guides the learning process of the reinforcement learning agent can generally be selected from common reinforcement learning algorithms as the learning strategy.
[0093] Step 305: Determine the coverage type used to calculate the reward;
[0094] Based on the functional characteristics and verification priorities of large-scale integrated circuits, selecting appropriate coverage data types (coverage types) as the basis for reward calculation can generate corresponding reward and penalty values more effectively. For modules with complex logical operations, such as the arithmetic logic unit (ALU) of a CPU, condition coverage and branch coverage types can effectively detect the correctness of logical judgments, and therefore can be used as the primary coverage types. For modules involving state transitions, such as finite state machine (FSM) controllers, finite state machine coverage types can comprehensively verify the correctness and completeness of state transitions and should be given priority. When selecting coverage types, industry standards and project experience should also be consulted to ensure that the selected coverage type can fully meet the verification requirements and guide reinforcement learning towards key verification objectives.
[0095] Step 306: Set up a reward and punishment scheme.
[0096] The reward and penalty scheme in this embodiment includes a reward scheme and a penalty scheme. The reward scheme can be: if the current code coverage improves compared to the previous code coverage, a positive reward or penalty value is given; the penalty scheme can be: if the current code coverage decreases or does not improve compared to the previous code coverage, a negative reward or penalty value is given.
[0097] Specifically, a suitable reward and penalty scheme can be selected based on verification needs and past experience. If project timelines are tight and a rapid increase in code coverage is desired, a proactive reward scheme can be adopted, where rewards are given for any improvement in code coverage. The reward and penalty values can also take into account the magnitude of the code coverage improvement; for example, a reward or penalty value of 10 can be given for every 1% increase in code coverage. To prevent the reinforcement learning agent from getting stuck in local optima and to pursue a more comprehensive verification effect, a penalty scheme can be combined, imposing penalties when code coverage does not improve or even decreases. The reward and penalty values should be set reasonably to avoid being too harsh, which could slow down the learning of the reinforcement learning agent. For example, a reward or penalty value of -5 can be given when code coverage remains unchanged or decreases. After determining the reward and penalty scheme, its rationality needs to be verified. This can be done by simulating some typical verification scenarios to check whether the reward and penalty scheme can effectively guide the learning direction of the reinforcement learning agent.
[0098] As can be seen from the above technical solution, the beneficial effects of this embodiment are: flexible configuration to adapt to different needs. The reinforcement learning environment has a high degree of configurability in terms of learning strategies, reward and punishment schemes, and coverage types. Users can flexibly adjust these parameters according to specific large-scale integrated circuit design and verification requirements to obtain the best stimulus file generation effect.
[0099] like Figure 4 The image shows a specific embodiment of a device for generating stimulus files for large-scale integrated circuits according to the present invention. This embodiment's device is used to execute... Figures 1-3 The physical apparatus of the method. Its technical solution is essentially the same as the above embodiments, and the corresponding descriptions in the above embodiments also apply to this embodiment. The apparatus in this embodiment includes:
[0100] The target standard specification determination module 401 is configured to acquire technical information of the target integrated circuit and determine the target standard specification based on the technical information.
[0101] The verification environment platform construction module 402 is configured to build a verification environment platform based on the target standard specification.
[0102] The code coverage collection module 403 is configured to perform simulation based on the verification environment platform to collect code coverage.
[0103] The reward / penalty value determination module 404 is configured to configure the original reinforcement learning environment and determine the reward / penalty value based on the original reinforcement learning environment and the code coverage.
[0104] The target reinforcement learning environment determination module 405 is configured to iteratively update the original reinforcement learning environment based on the reward / penalty value to determine the target reinforcement learning environment.
[0105] The target incentive file determination module 406 is configured to determine the target incentive file based on the target reinforcement learning environment.
[0106] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. At the hardware level, the electronic device includes a processor, and optionally also includes an internal bus, a network interface, and a memory. The memory may include main memory, such as high-speed random-access memory (RAM), or it may also include non-volatile memory, such as at least one disk storage device. Of course, the electronic device may also include other hardware required for other services.
[0107] The processor, network interface, and memory can be interconnected via an internal bus, which can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.
[0108] Memory is used to store instructions for execution. Specifically, instructions for execution are computer programs that can be executed. Memory can include main memory and non-volatile memory, and it provides the processor with execution instructions and data.
[0109] In one possible implementation, the processor reads the corresponding execution instructions from non-volatile memory into memory and then executes them. Alternatively, it may obtain the corresponding execution instructions from other devices to form a large-scale integrated circuit stimulus file generation device at the logical level. The processor executes the execution instructions stored in memory to implement the large-scale integrated circuit stimulus file generation method provided in any embodiment of the present invention through the executed execution instructions.
[0110] The above is as described in the present invention. Figure 4The method executed by the apparatus for generating large-scale integrated circuit stimulus files provided in the illustrated embodiment can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor.
[0111] The steps of the method disclosed in the embodiments of this invention can be directly manifested as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.
[0112] This invention also proposes a readable medium storing executable instructions. When these instructions are executed by a processor of an electronic device, the electronic device can perform a method for generating a large-scale integrated circuit stimulus file provided in any embodiment of this invention, and specifically execute, for example... Figure 1 , Figure 3 The method shown.
[0113] The electronic devices in the foregoing embodiments may be computers.
[0114] Those skilled in the art will understand that embodiments of the present invention can be provided as methods or computer program products. Therefore, the present invention can be implemented in a completely hardware embodiment, a completely software embodiment, or a combination of software and hardware.
[0115] The various embodiments in this invention are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.
[0116] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0117] The above are merely embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of the claims of the present invention.
Claims
1. A method for generating stimulus files for large-scale integrated circuits, characterized in that, The method includes: Obtain the technical information of the target integrated circuit, and determine the target standard specifications based on the technical information; A verification environment platform was built based on the aforementioned target standard specifications; Simulations were performed using the aforementioned verification environment platform to collect code coverage data. Configure the original reinforcement learning environment, and determine the reward / penalty value based on the original reinforcement learning environment and the code coverage; The original reinforcement learning environment is iteratively updated based on the reward and penalty values to determine the target reinforcement learning environment; The target incentive file is determined based on the target reinforcement learning environment.
2. The method according to claim 1, characterized in that, The process of acquiring the technical information of the target integrated circuit and determining the target standard specifications based on the technical information includes: The technical information includes the requirements specification and RTL code of the target integrated circuit; The target standard specification is determined by parsing the requirements specification and the RTL code.
3. The method according to claim 1, characterized in that, The step of performing simulation based on the verification environment platform to collect code coverage includes: Based on the verification environment platform, data interaction between the Python environment and the verification environment platform is realized through the DPI interface, and simulation is performed to collect the code coverage.
4. The method according to claim 1, characterized in that, The original reinforcement learning environment configuration includes: Specify the design module to be verified in the target integrated circuit; Specify the target ports that contribute to the coverage of the design module; Define the action space based on all possible combinations of values for the target port; A reinforcement learning algorithm is determined based on the action space; the reinforcement learning algorithm is selected as the learning strategy. Determine the coverage type used to calculate rewards; Establish a reward and punishment scheme.
5. The method according to claim 4, characterized in that, The determination of reward / penalty values based on the original reinforcement learning environment and the code coverage includes: The reward / penalty value is determined dynamically based on the comparison between the current code coverage and the code coverage described in the previous step, and the reward / penalty scheme.
6. The method according to claim 5, characterized in that, The established reward and punishment scheme includes: The reward and punishment scheme includes a reward scheme and a punishment scheme; The reward scheme is as follows: if the current code coverage rate improves compared to the code coverage rate in the previous step, a positive reward or penalty value is given. The penalty scheme is as follows: if the current code coverage rate decreases or does not increase compared to the code coverage rate in the previous step, a reverse reward or penalty value is given.
7. The method according to claim 4, characterized in that, The step of iteratively updating the original reinforcement learning environment based on the reward / penalty value to determine the target reinforcement learning environment includes: The validity of the current round of simulation is determined based on the reward and penalty values; The learning strategy is updated and optimized based on its effectiveness. The target reinforcement learning environment is determined when the code coverage reaches a preset target.
8. An apparatus for generating stimulus files for large-scale integrated circuits, characterized in that, include: The target standard specification determination module is used to acquire technical information of the target integrated circuit and determine the target standard specification based on the technical information. The verification environment platform construction module is used to build a verification environment platform based on the target standard specifications. The code coverage collection module is used to perform simulation based on the verification environment platform to collect code coverage. The reward / penalty value determination module is used to configure the original reinforcement learning environment and determine the reward / penalty value based on the original reinforcement learning environment and the code coverage. The target reinforcement learning environment determination module is used to iteratively update the original reinforcement learning environment based on the reward and penalty value to determine the target reinforcement learning environment. The target incentive file determination module is used to determine the target incentive file based on the target reinforcement learning environment.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored program, wherein the program, when executed, performs the method of any one of claims 1 to 7.
10. An electronic device, characterized in that, The electronic device includes: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method described in any one of claims 1 to 7.