Massive three-dimensional grid model automatic simplification and lightweight processing system

Abstract

The application discloses a mass three-dimensional grid model automatic simplification and lightening processing system and relates to the technical field of mineral screening. The application discloses a mass three-dimensional grid model automatic simplification and lightening processing system and relates to the technical field of mineral screening. The time sequence dependent index construction module acquires a time sequence baseline and a memory access mapping released by multi-thread caching, constructs a dynamic dependent index table according to a thread scheduling sequence, identifies a release path triggered in advance under the constraint of the dynamic dependent index table, extracts corresponding cache node information, and generates an initial mapping of memory fragment distribution. The application realizes accurate alignment of multi-thread memory release through a time sequence baseline and a dynamic dependent index, improves the consistency and stability of memory management, realizes adaptive correction and error-proof control of memory through a closed-loop mechanism of remapping, playback and regulation, and ensures efficient and reliable operation of the batch three-dimensional grid simplification process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of mineral screening, in particular to a massive three-dimensional grid model automatic simplification and lightweight processing system. BACKGROUND

[0002] The massive three-dimensional grid model automatic simplification and lightweight processing system is an intelligent three-dimensional data optimization platform for multi-field three-dimensional technical application scenarios. The system takes three-dimensional wireframe rendering as the core, integrates the bidirectional algorithm mechanism of polygon simplification and refinement, and can dynamically adjust the precision and data volume of the model according to different application requirements. In the simplification mode, the system performs structural compression and geometric downsampling on the model through redundant face identification, topology reconstruction and error control algorithm, thereby significantly reducing the file size and improving the transmission and loading speed; in the refinement mode, the boundary preservation, normal correction and texture reconstruction technology is used to strengthen the local detail performance of the model, and the high-fidelity rendering effect is realized. The system can be widely applied to fields such as architectural design, urban digital twin, game development and special effects production, and can efficiently deal with the performance bottleneck of massive three-dimensional data in storage, transmission and real-time rendering, providing efficient and reliable technical support for the digital upgrading and intelligent visualization development of the three-dimensional industry.

[0003] The prior art has the following disadvantages:

[0004] In the batch three-dimensional grid model simplification processing process, since the system needs to perform multi-thread cache release operations in parallel, when the thread scheduling sequence appears slight timing drift under high load conditions, the release instructions of part of the intermediate cache blocks will be triggered in advance without completing the dependency cleaning, causing the memory fragments to present nonlinear aggregation in spatial distribution. Such abnormal fragment distribution will destroy the original memory continuity and pointer mapping relationship, causing the stack pointer to jump out of place, resulting in address reverse reflux of the cache management unit in subsequent access. If the abnormality is not detected in time, data out-of-bound writing and access conflicts will occur when the system performs memory recycling or reallocation operations, thereby causing process-level crashes and irreversible damage to batch model data and task interruption.

[0005] The above information disclosed in the background section is only used to enhance the understanding of the background of the present disclosure, and therefore it can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present application is to provide a massive three-dimensional grid model automatic simplification and lightweight processing system to solve the problems in the background art.

[0007] In order to achieve the above object, the present application provides the following technical scheme: the mass three-dimensional grid model automatic simplification and lightweight processing system, including time sequence dependent index construction module, nonlinear aggregation detection module, memory remapping correction module, time sequence playback adaptive control module and phase conjugate self-correction fault prevention module;

[0008] The time sequence dependent index construction module acquires the time sequence baseline and memory access mapping of the multi-thread cache release, constructs a dynamic dependent index table according to the thread scheduling sequence, identifies the release path triggered in advance under the constraint of the dynamic dependent index table, extracts the corresponding cache node information, and generates an initial mapping of memory fragment distribution, thereby providing a benchmark reference for subsequent nonlinear detection;

[0009] The nonlinear aggregation detection module constructs a nonlinear aggregation detection matrix according to the initial mapping of memory fragment distribution, performs hierarchical analysis on the cache node information, extracts the drift gradient of the stack pointer, establishes a pointer correlation path tracking model, locates the stack misplacement trigger point under the constraint of the nonlinear aggregation detection matrix, and generates a spatial anchor point for remapping operation;

[0010] The memory remapping correction module generates a memory remapping sequence according to the stack misplacement trigger point and the spatial anchor point, performs bidirectional adjustment on the pointer reference path and the allocation window boundary by using a time synchronization mechanism and a phase correction mechanism, restores the heap area continuity under the constraint of the remapping sequence, and ensures the consistency of the cache release sequence and the access sequence in time sequence;

[0011] The time sequence playback adaptive control module constructs a time sequence playback chain under the condition of restoring the heap area continuity, dynamically replays the entire cache release process, generates a false release judgment threshold according to the time sequence residual error obtained by the replay, and realizes adaptive control of the release behavior through the false release judgment threshold, thereby forming a memory stability control field with self-healing characteristics;

[0012] The phase conjugate self-correction fault prevention module constructs a phase conjugate regulation instruction set according to the memory stability control field, performs address reverse flow suppression and access path amplitude limiting calibration, realizes inter-thread synchronization correction based on residual density feedback under the constraint of the phase conjugate regulation instruction set, and thereby constructs a stack pointer fault prevention mechanism with dynamic self-correction capability, so as to ensure the continuous and stable operation of the batch three-dimensional grid model simplification process.

[0013] Preferably, the process of acquiring the time sequence baseline and memory access mapping of the multi-thread cache release includes the following steps:

[0014] The time characteristics of the multi-thread cache release are captured to establish the time sequence baseline, the time start point and duration interval of the cache allocation, reference and release of each thread are recorded, the thread behavior characteristics are extracted to determine the time boundary and dependent order of the cache release;

[0015] After the time sequence baseline is established, a memory access mapping is constructed according to a thread scheduling sequence, a read-write behavior of each thread to a cache unit during execution is spatially associated and mapped, and the time sequence baseline is combined with the memory access mapping to form a multi-dimensional relationship network with time continuity and spatial dependence;

[0016] A dynamic dependence index table is constructed according to the memory access mapping, and an early triggered release path is identified under the constraint of the index table. The release path is cross-compared to find a potential dependence breaking point.

[0017] After the early triggered release path is identified, corresponding cache node information is extracted, and an initial memory fragmentation distribution mapping is generated according to the spatial position, release time and reference level of the cache node, thereby providing a benchmark reference for nonlinear aggregation detection.

[0018] Preferably, in the step of generating the initial memory fragmentation distribution mapping, the logical position of the cache node involved in the early triggered release path in the memory space, the release time point and the access state of the adjacent cache unit are spatially reorganized and logically mapped, so that the initial memory fragmentation distribution mapping is measured by spatial continuity, thereby characterizing the structural integrity and fragmentation aggregation trend of the memory space after the cache is released.

[0019] Preferably, the process of constructing a nonlinear aggregation detection matrix and generating a spatial anchor point according to the initial memory fragmentation distribution mapping includes the following steps:

[0020] According to the initial memory fragmentation distribution mapping, the cache node is subjected to hierarchical structured analysis, and a hierarchical structure is established according to spatial continuity, time release order and dependence relationship, thereby providing a hierarchical basis for the construction of the nonlinear aggregation detection matrix.

[0021] After obtaining the hierarchical cache node structure, a nonlinear aggregation detection matrix is constructed according to the spatial contact strength between levels, the dependence overlap degree and the release order residual, thereby reflecting the nonlinear degree and local abnormal trend of the fragmentation aggregation.

[0022] According to the spatial comparison relationship of the nonlinear aggregation detection matrix, the cache node information is subjected to hierarchical analysis, the drift gradient of the stack pointer is extracted, and a pointer association path tracking model is established, thereby describing the drift trajectory of the pointer in the memory space.

[0023] The drift gradient change characteristics of the pointer association path tracking model are comprehensively compared by using the constraint condition of the nonlinear aggregation detection matrix, the stack misalignment trigger point is located, and a spatial anchor point for memory remapping operation is generated at the location.

[0024] Preferably, in the process of generating the spatial anchor point, the drift node recorded in the pointer association path tracking model is compared with the abnormal distribution area in the nonlinear aggregation detection matrix, and when the drift gradient discontinuously jumps in the local space, the stack misalignment trigger point is determined, and the consistency of the cache nodes in the trigger point neighborhood is verified to ensure the accuracy of the spatial anchor point positioning and the reliability of the memory remapping.

[0025] Preferably, the process of generating the memory remapping sequence and restoring the heap area continuity according to the stack misalignment trigger point and the spatial anchor point includes the following steps:

[0026] According to the determined stack misalignment trigger point and the spatial anchor point, a memory remapping sequence is generated, and the physical location, time release order and association degree of the dependent path of the adjacent cache units in the heap area are sequentially arranged to establish an order framework for the heap area space adjustment;

[0027] According to the remapping sequence, the time synchronization adjustment is performed on the pointer reference path, so that the cache release process and the reference path execution order are time consistent, thereby eliminating the time misalignment caused by thread scheduling drift;

[0028] After completing the time synchronization adjustment, a phase correction mechanism is used to perform bidirectional adjustment on the allocation window boundary, so that the space allocation change and the time synchronization process are mutually compensated, thereby maintaining the phase consistency of the heap area space;

[0029] Under the joint action of the time synchronization mechanism and the phase correction mechanism, the heap area is continuously restored according to the constraint relationship of the remapping sequence, so that the cache release sequence and the access sequence are time consistent, thereby restoring the overall continuous structure of the heap area.

[0030] Preferably, in the bidirectional adjustment of the allocation window boundary, the spatial anchor point is taken as a reference, the boundary offset direction and amplitude are determined by comparing the space occupation relationship of the cache unit before and after remapping, and the heap area space layout is compensated and adjusted under the cooperation of the time synchronization mechanism, so as to prevent local structure misalignment and avoid the generation of secondary fragmentation.

[0031] Preferably, the process of realizing adaptive control of release behavior through the false release judgment threshold includes the following steps:

[0032] Under the condition of restoring the continuity of the heap area, a time sequence playback chain is constructed, the time identifier, access dependency relationship and space corresponding information of each cache unit are integrated into a playback structure with time sequence logic, and the whole process from cache allocation to release is traced back;

[0033] On the basis of the time sequence playback chain, the whole process of buffer release is dynamically replayed, and time sequence residual data is generated according to the change track of the release and access actions, so as to reflect the time offset characteristics of the heap area stability.

[0034] The misrelease judgment threshold is established according to the time sequence residual data, the normal release behavior and the abnormal release behavior are distinguished according to the residual distribution and the amplitude change, and the quantitative identification of the release behavior is realized.

[0035] The release process is adaptively constrained and corrected according to the misrelease judgment threshold, so that the release rhythm automatically returns to the safe interval, thereby forming a memory stability control field with the time residual as the feedback factor, and realizing the self-detection and self-healing maintenance of the heap area state.

[0036] Preferably, the misrelease judgment threshold is updated in real time according to the time sequence residual recorded in the time sequence playback chain, and is dynamically corrected in combination with the heap area continuity recovery state and the pointer path mapping relationship, so that the release rhythm and the access rhythm are kept synchronized under the condition of multi-thread parallel execution, thereby improving the adaptive accuracy of the memory stability control field and the self-healing response speed of the heap area.

[0037] Preferably, the process of realizing the inter-thread synchronous correction based on the residual density feedback under the constraint of the phase conjugate control instruction set comprises the following steps:

[0038] According to the formed memory stability control field, a phase conjugate control instruction set is constructed, the thread execution residual, the release time sequence offset and the spatial layout change information are integrated, so as to establish a unified control reference of the space-time coupling between threads;

[0039] Under the action of the phase conjugate control instruction set, address reverse flow suppression is performed, the reverse access trend is suppressed and reoriented by comparing the access path direction and the time sequence relationship, so as to maintain the one-way continuity of the heap area access;

[0040] After completing the address reverse flow suppression, the access path amplitude limiting calibration is performed according to the phase conjugate control instruction set, the thread access amplitude and the boundary position are constrained, so that the heap area space reaches a dynamic balance state;

[0041] Under the continuous constraint of the phase conjugate control instruction set, the inter-thread execution offset is synchronously corrected based on the residual density feedback, so that the stack pointer maintains a stable mapping relationship, thereby constructing a stack pointer fault-tolerant mechanism with dynamic self-correction ability.

[0042] In the above technical solution, the technical effects and advantages provided by the present application are as follows:

[0043] The application introduces a cooperative constraint mechanism of time sequence baseline and dynamic dependency index in the multi-thread cache release process, so that the cache release and memory access are accurately aligned in the time dimension, thereby effectively avoiding the premature release of the cache and the abnormal aggregation of the space fragments caused by the dependency drift. By constructing the initial mapping of the memory fragment distribution and the nonlinear aggregation detection matrix, the potential misalignment points can be predicted and located before the release behavior occurs, thereby significantly improving the time sequence consistency and the space continuity of the memory management, so that the heap area can still maintain stable logical structure and recoverability under high-load parallel processing, and the occurrence of data misalignment and memory overflow is fundamentally reduced.

[0044] The application realizes adaptive correction and continuous calibration of the memory state through the dynamic linkage of the memory remapping sequence, the time sequence playback chain and the phase conjugate control instruction set, so that the cache release behavior has self-healing ability and real-time error prevention characteristics. Through the closed-loop feedback mechanism formed in the three stages of remapping, playback and control, the synchronization rhythm between threads can be automatically adjusted according to the residual density change, the dynamic balance of the heap space and the access path is maintained, thereby significantly improving the running stability and the task completion rate of the batch three-dimensional grid simplification process, effectively preventing process-level collapse and data damage, and ensuring the long-term reliability of the overall processing flow. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0046] Figure 1 The module schematic diagram of the mass three-dimensional grid model automatic simplification and lightweight processing system of the present application. DETAILED DESCRIPTION

[0047] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations, however, can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these example implementations are provided so that this disclosure will be thorough and complete, and will fully convey the inventive aspects to those skilled in the art.

[0048] The present application provides a mass three-dimensional grid model automatic simplification and lightweight processing system as shown in Figure 1 The present application provides a mass three-dimensional grid model automatic simplification and lightweight processing system as shown in

[0049] The time sequence dependent index construction module obtains a time sequence baseline of multi-thread cache release and a memory access mapping, constructs a dynamic dependent index table according to a thread scheduling sequence, identifies an early triggered release path under the constraint of the dynamic dependent index table, extracts corresponding cache node information, and generates an initial memory fragment distribution mapping, thereby providing a benchmark reference for subsequent nonlinear detection.

[0050] The initial memory fragment distribution mapping is generated in the following specific steps:

[0051] The time characteristics of multi-thread cache release are captured to establish a time sequence baseline. In a specific operation, for the simplification process of a batch of three-dimensional grid models, the time starting point and duration interval of cache allocation, reference and release of each thread are recorded synchronously at the multi-thread task starting stage. By sampling and analyzing the time span of multi-thread running, time sequence baseline data representing thread behavior characteristics are extracted. The time sequence baseline reflects the relative execution rhythm and cache release order structure of different threads in the same processing period, and is used to describe the time relationship of resource occupation and release of each thread. By establishing the time sequence baseline, the time boundary and dependent order of the cache release action of each thread can be determined, so that the subsequent dependent index construction has an alignable time reference. The time sequence baseline is not only used to measure the stability of thread scheduling, but also used to identify potential early triggered release trends, thereby ensuring the accuracy of subsequent dependent analysis.

[0052] After the time sequence baseline is established, a memory access mapping is constructed according to the thread scheduling sequence. In this stage, according to the captured time sequence baseline information, the read-write behavior of each thread to the cache unit during execution is spatially correlated and mapped. By logically sorting the access order of the cache unit, a complete memory access mapping structure is formed, in which each cache unit and its corresponding access thread, access time and dependent state establish a traceable corresponding relationship. The mapping is used to reveal the sharing, covering and cross access of threads in the memory space, and can accurately reflect the life cycle connection relationship of cache data between different threads. By combining the time sequence baseline and the memory access mapping, a multi-dimensional relationship network reflecting both time continuity and spatial dependency can be obtained, thereby providing a data basis for the construction of a dynamic dependent index table. It is worth noting that the memory access mapping is synchronized with the time sequence baseline when generated, thereby avoiding the record misalignment phenomenon caused by time drift of different threads under high load conditions.

[0053] After obtaining the memory access mapping, a dynamic dependency index table is constructed according to the thread scheduling sequence, and an early triggered release path is identified under the constraint of the index table. In this stage, the timing baseline and the memory access mapping are taken as input references, and the dynamic dependency index table is established through the thread scheduling sequence. The index table takes the thread execution order as the main axis, and the cache dependency relationship between threads is hierarchically associated according to the access timing, thereby forming a multi-dimensional dependency index network. Under the constraint of the index network, those cache release paths that are triggered in advance in the time dimension can be identified, that is, the cache nodes that are marked as release state before the dependency relationship is completely released. By cross-comparing the release paths in the dependency index table, potential dependency breaking points and early release behaviors can be found. This process not only reveals the micro timing drift of threads in resource release, but also provides a key dependency control basis for the generation of subsequent fragment distribution mapping. Through the construction of the dynamic dependency index table, the entire cache release process can have dynamic constraint capability, thereby avoiding the accumulation of structural fragments caused by timing imbalance between threads.

[0054] After the early triggered release path is identified, the corresponding cache node information is extracted, and an initial memory fragment distribution mapping is generated, providing a reference for subsequent nonlinear detection. Specifically, under the constraint of the dynamic dependency index table, the cache nodes involved in the identified early release path are information extracted. The information includes the logical position of the cache node in the memory space, the release time point, the reference level, and the access state of the adjacent cache unit. By spatially reorganizing and logically mapping the above information, an initial memory fragment distribution mapping is generated. The mapping takes spatial continuity as the core measurement index, and is used to represent the structural integrity and fragmentation trend of the memory space after the cache is released. By analyzing the spatial interval and time residual of each cache node in the initial mapping, the distribution characteristics and potential focusing areas of nonlinear aggregation can be intuitively revealed. The initial memory fragment distribution mapping not only provides a reference for subsequent nonlinear aggregation detection, but also provides a structural reference for subsequent heap area continuity recovery. Through this step, a unified mapping from the time dimension to the space dimension is realized, and the dependency relationship, time sequence and memory structure state of the entire cache release process form a complete corresponding system, thereby laying a foundation for subsequent stack misalignment detection and memory stability control.

[0055] Through the above steps, the organic integration between the timing baseline, the memory access mapping, the dynamic dependency index table and the initial memory fragment distribution mapping is realized in the multi-thread cache release process. The method can accurately depict the spatial and temporal characteristics of cache release without interfering with the efficiency of thread scheduling, thereby providing high-precision, low-delay reference basis for subsequent nonlinear aggregation detection and heap area continuity reconstruction.

[0056] The nonlinear aggregation detection module constructs a nonlinear aggregation detection matrix according to the initial memory fragment distribution mapping, performs hierarchical analysis on the cache node information, extracts the drift gradient of the stack pointer, establishes a pointer correlation path tracking model, locates the stack misplacement trigger point under the constraint of the nonlinear aggregation detection matrix, and generates a spatial anchor point for remapping operation.

[0057] The nonlinear aggregation detection matrix is constructed under the constraint of the nonlinear aggregation detection matrix, and a spatial anchor point for remapping operation is generated. The specific steps are as follows:

[0058] According to the initial memory fragment distribution mapping generated in the previous stage, the cache nodes are analyzed in a hierarchical structure to establish the basic structure of the nonlinear aggregation detection matrix. In specific implementation, first, the cache node information contained in the initial memory fragment distribution mapping is classified and sorted according to the spatial continuity, time release order and mutual correlation degree of dependency relationship. Through this hierarchical method, cache nodes in the same memory fragment region or sharing similar release dependency features can be divided into the same level to form comparable spatial units in the analysis. Each level not only contains the spatial coordinate range and time attribute of the cache node, but also records the connection relationship of adjacent levels to represent the dependency migration characteristics across layers. Through this hierarchical structured processing method, the fragment state of the memory space is transformed from discrete distribution to a hierarchical logical mapping system, providing structural support for the establishment of the nonlinear aggregation detection matrix. The core of this step is to abstract the complex fragment distribution in layers, so that the subsequent spatial relationship analysis can be carried out in a unified reference framework.

[0059] After obtaining the hierarchical cache node structure, a nonlinear aggregation detection matrix is constructed to describe the spatial coupling degree and dependency offset relationship between levels. In specific implementation, the hierarchical structured cache node set is taken as the input basis, and a detection matrix is established according to the spatial contact strength, dependency overlap and release order residual between levels. The detection matrix can be logically understood as a set of spatial comparison relationships that quantify the relationship between levels, which is used to reflect the nonlinear degree of fragment aggregation and local abnormal focusing trend. Through the establishment of the detection matrix, the coupling phenomenon between different levels is clearly presented. When the cache nodes of a certain level appear aggregation offset in space, the corresponding relationship in the matrix will be manifested as obvious asymmetry or discontinuity. The introduction of the nonlinear aggregation detection matrix makes it possible to describe the fragment aggregation characteristics in a hierarchical relationship, thereby forming a set of spatial dependency monitoring structure that can be dynamically updated. Through the establishment of the matrix, not only the overall distribution state of the fragments can be observed macroscopically, but also the local area that may cause stack drift can be identified microscopically.

[0060] According to the spatial correspondence relationship of the nonlinear aggregation detection matrix, the cache node information is hierarchically analyzed, the drift gradient of the stack pointer is extracted, and a pointer associated path tracking model is established. In this step, the hierarchical coupling characteristics embodied in the detection matrix are combined with the spatial displacement data of the cache nodes, and by differentiating the spatial offset between the cache nodes in different levels, the drift gradient of the stack pointer in the multi-level structure is obtained. The drift gradient reflects the offset trend of the pointer reference path between different levels, and can reveal the continuous offset relationship of the pointer in the memory space due to the fragmentation aggregation. On the basis of extracting the drift gradient, the drift trend is further combined with the specific cache node dependency path by means of associated path tracking, forming a complete pointer associated path tracking model. The model can be used to track the migration trajectory of the stack pointer in the memory space, and reveal the jump relationship and mapping dependency between the pointers in different stages. By combining the drift gradient with the path tracking model, the whole process of the abnormal drift of the pointer can be described, and reliable basis is provided for the accurate positioning of the subsequent stack misplacement trigger point.

[0061] After obtaining the pointer associated path tracking model, the change characteristics of the drift gradient are compared by using the constraint condition of the nonlinear aggregation detection matrix, the trigger point of the stack misplacement is located, and the spatial anchor point for the remapping operation is generated. In the specific implementation process, the drift node recorded in the pointer associated path tracking model is compared with the abnormal distribution area in the nonlinear aggregation detection matrix, and when it is detected that the drift gradient of a pointer path presents discontinuous jump characteristics in the local space, it is judged that the position is a potential trigger point of the stack misplacement. In order to ensure the accuracy of the positioning, the cache nodes around the trigger point are further analyzed for neighborhood consistency in combination with the initial mapping of the memory fragmentation distribution in the previous stage, and whether the position is the actual source of the stack misplacement is verified. After confirmation, a spatial anchor point is generated at the position, which is used to identify the physical area boundary of the stack misplacement. The spatial anchor point is not only used to record the spatial coordinates and time identifier of the trigger point, but also serves as a reference benchmark for the subsequent memory remapping process. Through the establishment of the anchor point, the abnormal offset position in the stack area can be accurately locked, so that the subsequent remapping operation can restore the memory continuity with the anchor point as the center, thereby effectively eliminating the structural misplacement influence caused by the fragmentation aggregation.

[0062] Through the above steps, on the basis of the initial mapping of the memory fragmentation distribution, the construction of the nonlinear aggregation detection matrix, the extraction of the stack pointer drift gradient, the establishment of the pointer path tracking model and the generation of the spatial anchor point are successfully realized. Through this method, the trigger source of the stack misplacement can be accurately identified and located on the basis of the spatial hierarchical structure after the multi-thread cache is released, which provides data support for the subsequent memory remapping and time sequence playback.

[0063] The memory remapping correction module generates a memory remapping sequence according to the stack misplacement trigger point and the space anchor point, adjusts the pointer reference path and the allocation window boundary in both directions by using a time synchronization mechanism and a phase correction mechanism, restores the heap area continuity under the constraint of the remapping sequence, and ensures the consistency of the cache release sequence and the access sequence in time sequence.

[0064] The memory remapping sequence is generated according to the stack misplacement trigger point and the space anchor point, and the heap area continuity is restored under the constraint of the remapping sequence. The specific steps are as follows:

[0065] First, the memory remapping sequence is generated according to the determined stack misplacement trigger point and the space anchor point to establish the sequence framework of the heap area space adjustment. In the specific operation, the spatial position of the stack misplacement trigger point and the corresponding space anchor point information have been determined in the previous stage. Based on the anchor point, the physical position of the adjacent cache units in the heap area, the time release sequence, and the correlation degree of the dependent path are sequentially sorted to form a set of remapping sequences with spatial extension. The remapping sequence is used to represent the spatial mapping path of the heap area memory from the current distribution state to the target continuous state, and can reflect the recombination order and reference relationship that each cache unit should follow in the adjustment process. By establishing the sequence, the restoration of the memory structure has an executable timeline and spatial direction, which provides a clear constraint basis for subsequent synchronization and correction. The generation of the remapping sequence not only considers the overall spatial layout of the heap area, but also takes the misplacement trigger point as the core reference to ensure the coordination between the local area and the overall structure in the adjustment process.

[0066] After generating the memory remapping sequence, the time synchronization adjustment of the pointer reference path is performed according to the sequence, so that the reference chain and the spatial distribution form a unified execution rhythm in time. In this process, the cache units in the memory remapping sequence are rearranged according to the release time sequence, so that the starting point and the ending point of each reference path are continuously associated in time. By analyzing the time difference between each cache node in the release and remapping, the adjustment window of time synchronization is determined. The adjustment window is used to dynamically coordinate the calling order of the pointer reference path, so that the pointer can be executed in the spatial order of the remapping sequence in the access process, avoiding the situation of crossing the anchor point or out-of-bound reference. Through this time synchronization mechanism, the execution order of the cache release process and the reference path is realigned, thereby eliminating the time misplacement phenomenon caused by thread scheduling drift. This synchronization process not only ensures the logical continuity of the reference path, but also provides a stable time basis for subsequent spatial phase correction.

[0067] After the time synchronization adjustment is completed, a phase correction mechanism is used to adjust the allocation window boundary in both directions, so that the spatial allocation and the time execution form a coordinated response relationship. In specific implementation, the spatial anchor points in the remapping sequence are taken as boundary references, and the allocation window is regarded as an adjustable area of the heap space. By comparing the spatial occupation relationship of each cache unit before and after remapping, the offset direction and amplitude of the boundary area are determined. The phase correction mechanism is used to coordinate the interaction state of space and time, so that the boundary change of the allocation window can be consistent with the time synchronization adjustment process. Through this two-way correction method, when the release order on the time axis changes, the spatial layout can be adjusted in the opposite or corresponding direction to maintain the phase consistency of the overall structure. The introduction of the mechanism makes the heap space no longer present nonlinear misalignment caused by fragment aggregation, while ensuring that the arrangement order of the cache unit after redistribution conforms to the timing rules. The two-way action of the phase correction mechanism effectively avoids the secondary fragmentation problem caused by local adjustment in the traditional linear memory recycling, and improves the stability and predictability of the heap space.

[0068] Finally, under the joint action of the time synchronization mechanism and the phase correction mechanism, the heap is continuously recovered according to the constraint relationship of the remapping sequence, to ensure the consistency of the cache release sequence and the access sequence in time sequence. In specific operation, the remapping sequence that has completed correction is taken as the execution path to sequentially recover the cache units that exist discontinuity or misalignment in the heap, so as to re-form a complete continuous structure in space. This recovery process follows the principle of first anchoring, then connecting, and then unifying, that is, first taking the spatial anchor point as the starting reference, gradually connecting the spatial positions of the surrounding cache nodes, and finally recovering the entire heap into a continuous memory structure that can be accessed. With the progress of the recovery process, the cache release sequence and the access sequence are re-synchronized in time, so that they maintain a one-to-one correspondence in execution logic. In this way, when multiple threads perform cache access or data writing again, the system can access according to the new memory mapping relationship, thereby avoiding conflicts between the access path and the release path. Finally, through this continuity recovery process, the integrity of the heap space is re-established, the logical order and the time order of the memory structure are unified, and the cache release behavior and the access behavior remain completely consistent in the dynamic execution process, providing a stable memory basis for subsequent timing playback and misrelease detection.

[0069] Through the above steps, a memory remapping and continuity recovery method based on stack misalignment trigger points and spatial anchor points is constructed. This method realizes the whole-process closed-loop control from spatial anchoring to time synchronization, then to phase correction and finally to continuity recovery, so that the spatial and time structure of the multi-thread cache release is re-matched, and the stability and access consistency of the heap memory layout are significantly improved.

[0070] The time sequence playback adaptive control module constructs a time sequence playback chain under the condition of heap area continuity recovery, dynamically replays the whole process of cache release, generates a false release judgment threshold according to the time sequence residual obtained by the replay, and realizes adaptive control of the release behavior through the false release judgment threshold, thereby forming a memory stability control field with self-healing characteristics;

[0071] The adaptive control of the release behavior is realized through the false release judgment threshold, and the specific steps are as follows:

[0072] The time sequence playback chain is constructed under the condition of heap area continuity recovery, and is used to reconstruct the time structure and dependency order of the cache release process. In the specific implementation process, the time identifier, access dependency relationship and space corresponding information of each cache unit in the release phase are re-integrated into a playback chain with time sequence logic on the basis of the previously restored heap area continuity state. Through the comparison of the memory states before and after the restoration, the time mapping relationship of the release behavior is established, so that the system can completely trace back the whole process from cache allocation to release. Through the construction of the time sequence playback chain, not only the release order and mutual dependency of each thread can be recorded, but also the influence of the heap area continuity adjustment on the release rhythm in the restoration process can be accurately reflected. The key of this step is to convert the static heap area state into a time sequence structure that can be dynamically replayed, providing accurate time reference for the subsequent behavior replay and false release analysis.

[0073] On the basis of the constructed time sequence playback chain, the whole process of cache release is dynamically replayed to reproduce the change trajectory of the memory state in the actual execution process. In the specific operation, the release and access actions of the cache unit in each time period are simulated in sequence according to the time sequence and dependency path in the time sequence playback chain. Through the replay process, the cooperative release behavior of the threads under high load state can be dynamically restored, and the time sequence drift and release anomaly that may occur in the real execution environment can be revealed. This replay process not only reproduces the release order of the cache unit, but also synchronously tracks the dynamic changes of the heap area structure, thereby reflecting the influence of the release behavior on the memory continuity and space balance. In the process of dynamic replay, the system can gradually accumulate the time sequence offset and access delay at each time, thereby forming a set of time sequence residual data for evaluating the stability of the heap area. This process makes the heap area be logically re-verified, ensuring that the space structure after continuity recovery remains coherent and correct in the time dimension. Through dynamic replay, the small release deviation caused by thread scheduling changes or dependency chain delay can be accurately identified, providing a reliable data foundation for subsequent false release judgment.

[0074] The time sequence residual error generated according to the dynamic replay is used to generate a false release judgment threshold, so as to realize the quantitative identification and dynamic evaluation of the cache release behavior. In this stage, the time sequence residual error data recorded in the replay process is comprehensively analyzed, and a false release judgment threshold is established according to the time distribution and amplitude change of the residual error. The threshold is used to describe the boundary condition between the normal release behavior and the abnormal release behavior. When the release behavior of a thread or cache unit corresponds to a time sequence residual error that exceeds the judgment threshold, it is determined that the release action has a potential risk of early triggering or dependence destruction. By setting the threshold, the system can have adaptive judgment ability in subsequent execution process, and can automatically distinguish between normal release delay and abnormal time sequence drift. The generation process of the threshold considers the continuity recovery state of the heap area, the stability of the pointer association path, and the access frequency of the cache unit, so as to ensure the dynamic adaptability and universal applicability of the judgment standard. Through this step, a dynamic feedback mechanism of time sequence residual error is introduced on the basis of traditional static verification, so that the judgment of memory release behavior has real-time and intelligent characteristics.

[0075] The adaptive control of release behavior is realized through the false release judgment threshold, and a memory stability control field with self-healing characteristics is formed. In this implementation step, the aforementioned judgment threshold is used as the basis for dynamic regulation to real-time constrain and correct the behavior in the cache release process. When the time sequence residual error of a release action exceeds the judgment threshold, the system automatically adjusts the release rhythm according to the current continuity state of the heap area and the pointer path mapping relationship, so that it returns to the safe interval within the threshold range. Through this adaptive regulation process, the cache release behavior can realize self-detection, self-correction and self-recovery during execution, so as to effectively avoid the instability or collapse phenomenon of the heap area structure caused by continuous false release. With the continuous adaptive control, a stable control field is further formed, which is physically based on the heap area space and feedback factor of time residual error. The control field can continuously monitor the state change of the heap area under the condition of multi-thread parallel execution, automatically balance the dynamic difference between the release rhythm and the access rhythm, and make the system maintain stable memory structure and efficient resource utilization in long-time running. Through the establishment of the self-healing mechanism, the stability of the heap area is no longer dependent on external intervention, but is maintained by internal feedback, thereby significantly improving the reliability and continuity of the batch simplification process of the three-dimensional mesh model.

[0076] Through the above steps, a set of time sequence playback and adaptive control mechanism under the condition of heap area continuity recovery is constructed. The mechanism realizes the whole process closed loop from time replay, residual extraction to dynamic judgment and self-healing control, so that the cache release process is accurately reproduced and corrected in time and space dimensions. Through this method, the system can actively identify potential release abnormalities and repair in real time in a high-load parallel processing environment, preventing data disorder and process crashes and achieving high-reliability memory stable operation.

[0077] The phase conjugate self-correcting error prevention module constructs a phase conjugate control instruction set based on the memory stability control field, performs address reverse flow suppression and access path amplitude limiting calibration, and realizes inter-thread synchronous correction based on residual density feedback under the constraint of the phase conjugate control instruction set, thereby constructing a stack pointer error prevention mechanism with dynamic self-correcting capability to ensure continuous and stable operation of the batch three-dimensional mesh model simplification process.

[0078] Under the constraint of the phase conjugate control instruction set, inter-thread synchronous correction is realized based on residual density feedback, and the specific steps are as follows:

[0079] A phase conjugate control instruction set is constructed based on the formed memory stability control field to establish a unified control reference for the space-time coupling between threads. In specific implementation, the memory stability control field formed in the previous stage is taken as the input basis, and the control field contains dynamic feedback information such as thread execution residual, release timing offset, and spatial layout change. By integrating and summarizing these information, a set of phase conjugate control instruction set is constructed at the logical level. The instruction set takes the conjugate concept as the core, emphasizes the mutual mapping and opposite correction relationship between time sequence and spatial structure, so that each thread can realize synchronous compensation in the opposite phase during execution. The establishment of the phase conjugate control instruction set makes the execution behavior of each thread dynamically coupled with its adjacent threads in time and space, thereby ensuring that the system has self-balancing capability during overall operation. Through the construction of the instruction set, the memory stability control field is transformed from a passive state to an active control state, providing a unified behavior constraint basis for subsequent access path calibration and synchronous correction.

[0080] Under the action of the phase conjugation regulation instruction set, address reverse flow suppression is performed to prevent the stack pointer from generating incorrect access due to address mapping reversal. In specific operation, the phase conjugation regulation instruction set is applied to the monitoring and constraint process of the memory access path. When the thread is executing cache access or release operation, the system performs real-time comparison and analysis on the address mapping relationship. If it is found that there is a reverse flow trend in a certain access path, i.e. the access direction is inconsistent with the time sequence, the reverse constraint mechanism in the phase conjugation regulation instruction set is triggered immediately to suppress and reorient the access behavior. The suppression process is not a simple interruption, but under the action of the memory stable control field, the space access direction and time rhythm are synchronized and corrected to make the access path consistent with the normal time sequence. In this way, reverse jump or cross coverage of the stack pointer in multi-thread parallel access can be effectively avoided, thereby preventing abnormal phenomena such as out-of-bound writing, pointer misplacement and stack structure damage. The implementation of address reverse flow suppression makes the heap space access maintain one-way continuity, creating a stable structure environment for subsequent fine calibration of the access path.

[0081] After completing the address reverse flow suppression, the amplitude limiting calibration of the access path is performed according to the phase conjugation regulation instruction set to further stabilize the access boundary between threads and the effective range of the heap pointer. In this phase, the access path of each thread is compared and analyzed with the residual density recorded in the memory stable control field to determine the access amplitude and boundary position of each thread in the heap space. When it is detected that the access behavior of a certain thread exceeds the normal amplitude range or has an invasion trend on the access space of adjacent threads, the amplitude limiting calibration mechanism is triggered immediately to compress the amplitude and call back the space of the access path of the thread. The calibration process takes the phase conjugation regulation instruction set as the constraint basis, so that the calibration direction and the previous reverse suppression behavior form a complementary relationship, thereby maintaining the symmetry and balance of the space access as a whole. Through this amplitude limiting calibration method, the access boundary of each thread in the heap can be accurately constrained without affecting the execution efficiency of the thread, thereby preventing stack diffusion and memory imbalance caused by excessive access. The execution of this step makes the heap space reach a dynamic balance state in structure, and the access path maintains coordination and consistency in both time and space dimensions.

[0082] Under the constraint of the phase conjugation regulation instruction set, the residual density feedback is used to realize the inter-thread synchronization correction, thereby constructing a stack pointer error-proof mechanism with dynamic self-correcting capability. In this implementation step, the residual density generated in real time in the memory stability control field is used as a dynamic feedback signal to continuously monitor the deviation degree of each thread during execution. When the residual density presents a concentration or mutation feature in a certain region, the system performs synchronization correction on the corresponding thread according to the phase inversion principle of the phase conjugation regulation instruction set, so that the execution rhythm, access delay and spatial positioning of the thread return to the unified control reference. Through this synchronization correction mechanism based on residual feedback, the execution difference between threads can be offset in real time, and the stack pointer maintains a relatively stable mapping relationship in the global range, thereby forming an adaptive error-proof system. The error-proof mechanism can automatically identify abnormal features such as pointer deviation, access drift and release delay during continuous operation, and realize immediate repair through phase conjugation regulation, so that the system can maintain the consistency of the heap space and time logic without external intervention. Finally, under the continuous action of the error-proof mechanism, the batch simplification process of the entire three-dimensional mesh model can be stably operated under high concurrency conditions, avoiding task interruption and data damage caused by memory drift or access misplacement, and significantly improving the reliability and efficiency of the system.

[0083] Through the above steps, a complete closed-loop control process from the memory stability control field to the phase conjugation regulation, and then to the access path limiting and thread synchronization correction is realized. This method changes the management of the heap space from passive monitoring to active self-correcting state, ensuring the logical consistency and spatial stability of memory access in a complex multi-thread environment. By constructing the phase conjugation regulation instruction set and introducing the residual density feedback mechanism, dynamic adaptive error-proof control of the stack pointer is effectively realized, providing technical support for high-reliability operation of batch simplification processing of three-dimensional mesh models.

[0084] The present application introduces a cooperative constraint mechanism of timing baseline and dynamic dependency index in the multi-thread cache release process, so that the cache release and memory access are accurately aligned in the time dimension, thereby effectively avoiding the premature release of cache and abnormal aggregation of space fragments caused by dependency drift. By constructing the initial mapping of memory fragment distribution and the nonlinear aggregation detection matrix, potential misplacement points can be predicted and located before the release behavior occurs, significantly improving the timing consistency and spatial continuity of memory management, so that the heap area can still maintain a stable logical structure and recoverability under high-load parallel processing, fundamentally reducing the occurrence of data misplacement and memory overflow.

[0085] The application realizes adaptive correction and continuous calibration of memory state through dynamic linkage of memory remapping sequence, timing playback chain and phase conjugate control instruction set, so that the cache release behavior has self-healing ability and real-time error prevention characteristics. Through the closed-loop feedback mechanism formed in the three stages of remapping, playback and control, the synchronization rhythm between threads can be automatically adjusted according to the residual density change, the dynamic balance of heap space and access path is maintained, so that the running stability and task completion rate of the batch three-dimensional grid simplification process are significantly improved, the process-level collapse and data damage are effectively prevented, and the long-term reliability of the overall processing flow is ensured.

[0086] The above only describes certain exemplary embodiments of the application by way of illustration, and it is needless to say that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the application. Therefore, the above drawings and descriptions are illustrative in nature and should not be understood as limiting the scope of protection of the claims of the application.

Claims

1. A system for automatic simplification and lightweight processing of massive three-dimensional mesh models, characterized in that, The timing-dependent index construction module, the nonlinear aggregation detection module, the memory remapping correction module, the timing playback adaptive control module, and the phase conjugate self-correction fault-tolerant module; The timing-dependent index construction module obtains a timing baseline of a multi-thread cache release and a memory access mapping, constructs a dynamic dependency index table according to a thread scheduling sequence, identifies an early triggered release path under the constraint of the dynamic dependency index table, extracts corresponding cache node information, and generates an initial memory fragment distribution mapping; The nonlinear aggregation detection module constructs a nonlinear aggregation detection matrix according to the initial memory fragment distribution mapping, performs hierarchical analysis on the cache node information, extracts a drift gradient of a stack pointer, establishes a pointer correlation path tracking model, locates a stack misplacement trigger point under the constraint of the nonlinear aggregation detection matrix, and generates a spatial anchor point for a remapping operation; The memory remapping correction module generates a memory remapping sequence according to the stack misplacement trigger point and the spatial anchor point, performs bidirectional adjustment on a pointer reference path and an allocation window boundary by using a time synchronization mechanism and a phase correction mechanism, and restores heap continuity under the constraint of the remapping sequence; The timing playback adaptive control module constructs a timing playback chain under the condition of heap continuity restoration, dynamically replays a whole process of cache release, generates a false release judgment threshold according to a timing residual error obtained by the replay, realizes adaptive control of a release behavior by using the false release judgment threshold, and forms a memory stability control field with self-healing characteristics; The phase conjugate self-correction fault-tolerant module constructs a phase conjugate regulation instruction set according to the memory stability control field, performs address reverse flow suppression and access path amplitude limiting calibration, realizes inter-thread synchronization correction based on residual density feedback under the constraint of the phase conjugate regulation instruction set, and constructs a stack pointer fault-tolerant mechanism with dynamic self-correction capability; In the step of generating the initial memory fragment distribution mapping, the logical position of a cache node involved in an early triggered release path in a memory space, a release time point, and an adjacent cache unit access state are spatially reorganized and logically mapped, so that the initial memory fragment distribution mapping is measured by spatial continuity; The process of constructing the nonlinear aggregation detection matrix according to the initial memory fragment distribution mapping and generating the spatial anchor point includes the following steps: According to the initial memory fragment distribution mapping, the cache nodes are hierarchically and structurally analyzed, and a hierarchical structure is established according to spatial continuity, time release order, and correlation degree of dependency; After obtaining the hierarchical cache node structure, a nonlinear aggregation detection matrix is constructed according to spatial contact intensity between levels, dependency overlap degree, and release order residual error; According to the spatial comparison relationship of the nonlinear aggregation detection matrix, the cache node information is hierarchically analyzed, the drift gradient of the stack pointer is extracted, and a pointer correlation path tracking model is established; The drift gradient change characteristics of the pointer correlation path tracking model are comprehensively compared by using the constraint condition of the nonlinear aggregation detection matrix, the stack misplacement trigger point is located, and the spatial anchor point for the memory remapping operation is generated at the position; In the generation process of the spatial anchor point, the drift node recorded in the pointer association path tracking model is compared with the abnormal distribution area in the nonlinear cluster detection matrix, and when the drift gradient discontinuously jumps in the local space, the stack misplacement trigger point is determined, and the consistency of the cache node in the trigger point neighborhood is verified in combination with the initial mapping of the memory fragment distribution.

2. The automatic simplification and lightweight processing system of a massive three-dimensional mesh model according to claim 1, characterized in that, The process of obtaining the timing baseline of the multi-thread cache release and the memory access mapping includes the following steps: Baseline capture is performed on the time characteristics of the multi-thread cache release to establish the timing baseline, the time start point and duration interval of the cache allocation, reference and release of each thread are recorded, the thread behavior characteristics are extracted to determine the time boundary and dependency order of the cache release; After the timing baseline is established, the memory access mapping is constructed according to the thread scheduling sequence, the read-write behavior of each thread to the cache unit during execution is spatially associated and mapped, and the timing baseline and the memory access mapping are combined to form a multi-dimensional relationship network with time continuity and spatial dependence; A dynamic dependency index table is constructed according to the memory access mapping, and the release path triggered in advance is identified under the constraint of the index table, the release path is cross-compared to find potential dependency breaking points; After the release path triggered in advance is identified, the corresponding cache node information is extracted, and the initial mapping of the memory fragment distribution is generated according to the spatial position, release time and reference level of the cache node.

3. The system according to claim 1, wherein The process of generating a memory remapping sequence and restoring the continuity of the heap area according to the stack misplacement trigger point and the spatial anchor point includes the following steps: A memory remapping sequence is generated according to the determined stack misplacement trigger point and spatial anchor point, the physical location, time release order and correlation degree of the adjacent cache units in the heap area are sequentially arranged, and the sequential framework of the heap area space adjustment is established; According to the remapping sequence, the time synchronization adjustment of the pointer reference path is performed, so that the cache release process and the reference path execution order are time consistent, and the time misplacement caused by thread scheduling drift is eliminated; After completing the time synchronization adjustment, the phase correction mechanism is used to perform bidirectional adjustment on the allocation window boundary, so that the space allocation change and the time synchronization process are mutually compensated, and the phase consistency of the heap area space is maintained; Under the joint action of the time synchronization mechanism and the phase correction mechanism, the continuity of the heap area is restored according to the constraint relationship of the remapping sequence, so that the cache release sequence and the access sequence are time consistent, and the overall continuous structure of the heap area is restored.

4. The automatic simplification and lightweight processing system of a massive three-dimensional mesh model according to claim 3, characterized in that, When the phase correction mechanism performs bidirectional adjustment on the allocation window boundary, the spatial anchor point is taken as a reference, the boundary offset direction and amplitude are determined by comparing the space occupation relationship of the cache unit before and after remapping, and the heap area space layout is compensated and adjusted under the cooperation of the time synchronization mechanism.

5. The automatic simplification and lightweight processing system of a massive three-dimensional mesh model according to claim 1, characterized in that, The process of realizing adaptive control of release behavior through the false release judgment threshold includes the following steps: Under the condition of restoring the continuity of the heap area, a timing playback chain is constructed, the time identifier, access dependency relationship and spatial corresponding information of each cache unit are integrated into a playback structure with timing logic, which is used to trace the whole process from cache allocation to release; On the basis of the time sequence playback chain, the whole process of buffer release is dynamically replayed, and time sequence residual data is generated according to the change track of release and access actions, which is used to reflect the time offset characteristics of heap area stability; According to the time sequence residual data, the misrelease judgment threshold is established, and the residual distribution and amplitude change are used to distinguish normal release behavior and abnormal release behavior, so as to realize the quantitative identification of release behavior; Taking the misrelease judgment threshold as the control basis, the release process is adaptively constrained and corrected, so that the release rhythm automatically returns to the safe interval, forming a memory stability control field with time residual as feedback factor, and realizing self-detection and self-healing maintenance of heap area state.

6. The automatic simplification and lightweighting system of massive three-dimensional mesh models according to claim 5, characterized in that, The misrelease judgment threshold is updated in real time according to the time sequence residual recorded in the time sequence playback chain, and is dynamically corrected combined with the heap area continuity recovery state and pointer path mapping relationship, so that the release rhythm and access rhythm are kept synchronized under the condition of multi-thread parallel execution.

7. The automatic simplification and lightweighting system of massive three-dimensional mesh models according to claim 5, characterized in that, The process of realizing inter-thread synchronous correction based on residual density feedback under the constraint of phase conjugate control instruction set includes the following steps: According to the memory stability control field formed, the phase conjugate control instruction set is constructed, the thread execution residual, release time sequence offset and spatial layout change information are integrated, so as to establish a unified control benchmark of space-time coupling between threads; Under the action of the phase conjugate control instruction set, address reverse flow suppression is performed, the reverse access trend is suppressed and reoriented by comparing the access path direction and time sequence relationship, and the one-way continuity of heap area access is maintained; After completing the address reverse flow suppression, the access path amplitude limiting calibration is performed according to the phase conjugate control instruction set, and the thread access amplitude and boundary position are constrained, so that the heap area space reaches a dynamic balance state; Under the continuous constraint of the phase conjugate control instruction set, the inter-thread execution offset is corrected based on the residual density feedback, so that the stack pointer maintains a stable mapping relationship, and a stack pointer fault-tolerant mechanism with dynamic self-correction ability is constructed.

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