Power-on reset circuit with Schmitt trigger
By using a power-on reset circuit with a Schmitt trigger, the problems of insufficient reset pulse amplitude, weak anti-interference ability and high power consumption of traditional POR circuits are solved, achieving stable reset delay and low power consumption, which is suitable for integrated circuit systems such as phase-locked loop chips.
Patent Information
- Application Number
- CN202511113426.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-08
- Publication Date
- 2025-11-25
AI Technical Summary
Traditional power-on reset circuits have problems such as insufficient reset pulse amplitude, weak anti-interference ability and high power consumption, which affect the stability and reliability of the circuit. In particular, they are prone to reset failure in unstable power supply or noisy environments, and do not meet the high energy efficiency requirements of modern integrated circuits.
The power-on reset circuit with Schmitt trigger includes a current bias circuit, a low-voltage cascode current mirror, node capacitors, an inverter, and a discharge branch. It achieves stable reset and low power consumption by distributing current through the current mirror, increasing output impedance through the cascode structure, filtering noise through the Schmitt trigger, and providing reset delay in combination with the equivalent capacitance of the NMOS transistor.
It provides stable reset delay, enhances anti-interference capability, significantly reduces power consumption, and ensures stable circuit reset after power-on. It is suitable for integrated circuit systems that require high power stability and low power consumption operation.
Smart Images
Figure CN121012484A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a power-on reset circuit with a Schmitt trigger. Background Technology
[0002] In integrated circuit design, the power-on reset circuit is a critical component that ensures the circuit starts working from a known initial state. Traditional POR circuits mainly rely on the charging and discharging principle of resistors and capacitors to generate a reset pulse, including a delay generation section and a pulse generation section. The capacitor charging causes the node potential to rise, triggering the inverter T to flip, which in turn generates a reset pulse signal through the delay unit and XOR gate.
[0003] In traditional POR circuits, when the power supply voltage rise time is long, the capacitor may not charge sufficiently, resulting in a significantly reduced amplitude of the generated reset pulse. This low-amplitude reset pulse may not reach the threshold voltage required for successful circuit reset, leading to reset failure. This problem is particularly prominent in applications requiring high reliability, severely impacting the stability and reliability of the circuit.
[0004] Traditional POR circuits are extremely sensitive to power supply fluctuations; even minor changes in the power supply can interfere with the normal operation of the circuit. Especially in environments with unstable power supplies or noise, the circuit is prone to false resets, leading to system instability. This low immunity to interference limits the application of traditional POR circuits in complex electromagnetic environments.
[0005] Traditional POR circuits exhibit quiescent current during operation, which continuously consumes electrical energy, increasing the overall power consumption of the circuit. In today's trend towards low-power design, this unnecessary power consumption is particularly prominent and fails to meet the high energy efficiency requirements of modern integrated circuits. Especially in portable devices and embedded systems, high power consumption significantly shortens battery life and degrades the user experience. Summary of the Invention
[0006] The purpose of this invention is to provide a power-on reset circuit with a Schmitt trigger, which solves the problems of traditional POR circuits in terms of reset pulse amplitude, anti-interference capability and power consumption.
[0007] To achieve the above objectives, the present invention provides a power-on reset circuit with a Schmitt trigger, comprising:
[0008] The current bias circuit, composed of components M1, M2, M5, M6, M7, and M8, distributes current through a basic current mirror to provide a stable bias current for subsequent circuits.
[0009] The low-voltage common-source cascode current mirror, composed of components M2, M3, M6, and M9, improves the output impedance and reduces the impact of output voltage changes on the current.
[0010] The node capacitor, composed of component M10, provides a reset delay;
[0011] Inverters and Schmitt triggers: Inverters perform level shifting, and Schmitt triggers filter noise and jitter.
[0012] The discharge branch, composed of component M7, controls the rate of output voltage decrease through discharge and works in conjunction with the charging process to achieve a reset delay.
[0013] Preferably, in the current bias circuit, M1 and M2 constitute the first basic current mirror, M5 and M6 constitute the second basic current mirror, and M7 and M8 constitute the third basic current mirror. M1 and M2 have the same width-to-length ratio, M5 and M6 have a width-to-length ratio that is one-tenth that of M1, and M8 has a width-to-length ratio that is one-eighth that of M7.
[0014] Preferably, in the low-voltage common-source common-gate current mirror, M2 and M6 constitute a current mirror, with M6 mirroring the current of M2; M3 and M9 constitute a common-gate transistor, which increases the output impedance of the current mirror.
[0015] Preferably, the inverter is composed of PMOS and NMOS, the input terminal of the inverter is provided with a V0 node, the output terminal of the inverter is provided with a V1 node, and the Schmitt trigger is connected to the output terminal of the inverter.
[0016] Preferably, the source of M10 is shorted, the gate of M10 is connected to the V1 node, and the back gate of M10 is grounded.
[0017] Preferably, the V0 node is connected to the drain of M6 and the output terminal of the cascode structure.
[0018] Therefore, the present invention employs the above-described power-on reset circuit with a Schmitt trigger, and the technical effects are as follows:
[0019] 1. Provides stable reset delay: The POR circuit of this invention provides the necessary reset delay, ensuring that the circuit can stably complete the reset process after the power is turned on, avoiding system instability caused by too fast or too slow reset.
[0020] 2. Enhanced anti-interference capability: By incorporating a Schmitt trigger and utilizing its hysteresis characteristics, the POR circuit of this invention exhibits stronger anti-interference capability when facing power fluctuations and noise.
[0021] 3. Achieving a balance between low power consumption and high stability: While ensuring fast response and high stability, the power consumption of the circuit is significantly reduced, meeting the dual requirements of modern integrated circuits for energy efficiency and reliability. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of a traditional POR circuit structure;
[0023] Figure 2 This is a schematic diagram of the POR circuit structure of the present invention;
[0024] Figure 3 This is a schematic diagram of the output voltage waveforms at various points when OEN=0 in this invention;
[0025] Figure 4 This is a schematic diagram of the output voltage waveforms at various points when OEN=1 according to the present invention. Detailed Implementation
[0026] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.
[0027] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention pertains.
[0028] Example 1
[0029] This invention provides a power-on reset circuit with a Schmitt trigger, applied in a phase-locked loop (PLL) chip to reset the frequency divider. This ensures the PLL chip is initialized each time power is connected. Simultaneously, it works in conjunction with the frequency divider input to ensure the PLL chip enters normal operating mode and low-power mode, i.e., the frequency divider's reset state, normal operating state, and off state. Compared to traditional POR circuits, it avoids the situation where the reset pulse amplitude is too low to reset the circuit, achieving low-power and high-stability power-on reset functionality.
[0030] like Figure 1 As shown, a traditional POR circuit typically uses the charging and discharging principle of resistors and capacitors to generate a reset pulse. It consists of a delay generation section and a pulse generation section. The capacitor C, resistor R, and inverter T form the delay module, while the delay circuit and XOR gate constitute the pulse generation module.
[0031] When the power supply is turned on, capacitor C is charged, and the potential at node A begins to rise. When the potential at node A rises to the flip-flop threshold voltage of inverter T, the potential at node B flips and becomes high. After being delayed by a delay unit, the signals before and after the delay are passed through an XOR gate to obtain a reset pulse signal, thus completing the circuit reset. However, in this circuit, when the voltage rise time is greater than the capacitor charging time constant, the amplitude of the generated reset pulse will be very low, which may not be sufficient to reset the circuit. Moreover, power supply fluctuations have a significant impact on the stability of the circuit, and more importantly, there is quiescent current.
[0032] The POR circuit designed in this invention is used in a phase-locked loop (PLL) chip to reset the frequency divider, ensuring that the PLL chip is initialized each time it is powered on. It also works in conjunction with the frequency divider input to ensure the PLL chip enters normal operating mode and low-power mode, i.e., the frequency divider's reset state, normal operating state, and off state. Compared to traditional POR circuits, it avoids the situation where the reset pulse amplitude is too low to reset the circuit, achieving a low-power and highly stable power-on reset function.
[0033] like Figure 2 As shown, the POR circuit of the present invention includes
[0034] The current bias circuit consists of components M1, M2, M5, M6, M7, and M8. It distributes current through a basic current mirror and achieves precise current control by setting different width-to-length ratios to realize current distribution and mirroring.
[0035] The low-voltage cascode current mirror, composed of components M2, M3, M6, and M9, suppresses channel length modulation effects and improves the performance of the current mirror. M2 and M6 form the current mirror, while M3 and M9 act as common-gate transistors, together forming a low-voltage cascode structure. This increases the output impedance, making the output current less affected by changes in output voltage, thus ensuring the stability of the output voltage V0 during power supply rise.
[0036] The node capacitor, composed of component M10, provides a large capacitance value at node V1. Since an NMOS transistor can be equivalent to a capacitor under certain connection conditions, the required capacitance value can be obtained by properly designing its size. This capacitor, in conjunction with the small charging current flowing through M6, slows down the rise of the voltage at node V1, thereby providing the necessary reset delay.
[0037] Inverters and Schmitt triggers: Inverters are used for signal inversion and level conversion, while Schmitt triggers utilize their hysteresis characteristics to increase signal delay, making them insensitive to noise and jitter during the slow voltage rise process, preventing noise from causing voltage fluctuations near the flip threshold, thereby producing a clean, steep reset signal transition.
[0038] The discharge branch, composed of component M7, controls the rate of output voltage decrease through discharge and works in conjunction with the charging process to achieve a reset delay.
[0039] In the current biasing circuit, M1 and M2 form the first basic current mirror, M5 and M6 form the second basic current mirror, and M7 and M8 form the third basic current mirror. The width-to-length ratio of M5 and M6 is 1 / 10 of that of M1, and the width-to-length ratio of M8 is 1 / 8 of that of M7. Assuming the current flowing through M1 is I0, based on the mirror principle and the width-to-length ratio, the current flowing through M5 and M6 is I0 / 10. Since M5 and M8 are in the same branch, the current flowing through M8 is I0 / 10. Therefore, the current flowing through M7 is 8I0 / 10.
[0040] In a low-voltage cascode current mirror, M2 and M6 form a current mirror. When the circuit is powered on, M6 mirrors the current of M2, meaning M6 also begins to conduct and generates a current approximately equal to one-tenth of the current of M2. M3 and M9, as common-gate transistors, suppress channel length modulation effects and improve the performance of the current mirror. When M6 conducts, M9 will also conduct under appropriate gate-source voltage conditions, thus demonstrating that M2, M3, M6, and M9 constitute a low-voltage cascode current mirror structure. The increased output impedance of the cascode structure means that the output current is less affected by changes in the output voltage, V0. Therefore, during the power-up process, even if the voltage of V0 changes, it ensures that V0 can stably follow VDD. For very slow power-up processes, V0 can be approximately one V lower than VDD. od That is, V0 rises with the power supply and eventually approaches VDD.
[0041] The inverter consists of PMOS and NMOS transistors. The inverter input has a V0 node, and the output has a V1 node. A Schmitt trigger is connected to the inverter output. Since the discharge current at V0 is the current flowing through M7 (8I0 / 10), and the charging current is the current flowing through M6 (I0 / 10), it can be seen that the discharge current is greater than the charging current. Therefore, after power-on, V0 discharges through the M7 branch, gradually decreasing from a value approximately equal to VDD. Because the P and N transistors in inverter A0 have a very small size ratio, the switching threshold is close to 0V. Therefore, when V0 drops to near 0V, V1 begins to gradually increase from 0V after passing through the inverter. POR Subsequently, VDD gradually decreases through the inverter.
[0042] M10 is used as the capacitor at node V1. The capacitance at node V1 is relatively large, and the current flowing through M6 (i.e., the charging current) is small, resulting in a slow voltage rise. It takes time t to reach the switching threshold of the subsequent inverter. Within time period t, V... POR Maintaining a high level (VDD), the frequency divider is in a reset state. After time t, the inverter after V1 toggles, and V... PORThe Schmitt trigger flips to a low level (0V) and maintains this state, allowing the frequency divider to enter normal operation. The reset action is then complete, where t is the reset time. Because Schmitt triggers have different positive and negative threshold voltages, the input signal requires a certain amount of time to rise from low to VT+ and from high to VT-. This increases signal delay to some extent, thus exhibiting hysteresis. To prevent insensitivity to noise and jitter during the slow voltage rise process—that is, to prevent noise-induced voltage fluctuations near the flip threshold and thus V... POR By repeatedly toggling between 0V and VDD, this circuit incorporates a Schmitt trigger, which generates a clean, steep reset signal transition.
[0043] In addition to the power-on reset function, when the input of the divider control terminal is in a specific state, this circuit can also enable the entire phase-locked loop chip to enter a low-power state. At this time, OEN is set to 1 (other inputs and enable OEN are all 0), the power-on reset signal becomes high level, continuously resetting the internal D flip-flop of the chip, thereby turning off the entire divider.
[0044] Simulation of the output voltage of the power-on reset circuit is as follows: Figures 3-4 As shown, when OEN = 0, the circuit outputs a reset signal, i.e., V, immediately upon power-on. POR When V0 is high, V1 gradually rises as V0 drops to 0. When V1 reaches 1.92V, the VPOR output flips, meaning the output becomes 0 (low potential) after t = 770ns, the reset ends, and the circuit operates normally. When OEN = 1, the power-on reset circuit output voltage is always 1 (high level), shutting down the frequency divider module, and the chip is in a low-power state.
[0045] When the power supply is turned on, the current bias circuit of this invention starts working, providing a stable bias current for the active devices. The voltage at point V0 rises with the power supply voltage, but due to the cascode structure, V0 can stably follow VDD's rise. Even if the power supply rises slowly, V0 discharges through branch M7, and the voltage gradually decreases. When the voltage at node V1 rises to the inverter A0's toggling threshold, V... POR The signal toggles, completing the reset action. The Schmitt trigger adds signal hysteresis to prevent noise-induced voltage fluctuations near the toggle threshold, ensuring V... POR The signal is clean and steep.
[0046] Therefore, this invention employs the aforementioned power-on reset circuit with a Schmitt trigger. Through an innovative current bias circuit and a low-voltage common-source common-gate current mirror structure, combined with NMOS transistor equivalent capacitance technology, it achieves a low-power, high-stability power-on reset function. This effectively solves the reset instability problem of traditional POR circuits during power fluctuations and slow power-on processes. At the same time, it utilizes the hysteresis characteristics of the Schmitt trigger to enhance noise immunity, significantly improving the overall performance and reliability of the circuit. It is suitable for integrated circuit systems that require high power stability and low-power operation.
[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the technical solutions of the present invention, and these modifications or equivalent substitutions cannot cause the modified technical solutions to deviate from the spirit and scope of the technical solutions of the present invention.
Claims
1. A power-on reset circuit with a Schmitt trigger, characterized in that, include The current bias circuit, composed of components M1, M2, M5, M6, M7, and M8, distributes current through a basic current mirror to provide a stable bias current for subsequent circuits. The low-voltage common-source cascode current mirror, composed of components M2, M3, M6, and M9, improves the output impedance and reduces the impact of output voltage changes on the current. The node capacitor, composed of component M10, provides a reset delay; Inverters and Schmitt triggers: Inverters perform level shifting, and Schmitt triggers filter noise and jitter. The discharge branch, composed of component M7, controls the rate of output voltage decrease through discharge and works in conjunction with the charging process to achieve a reset delay.
2. The power-on reset circuit with a Schmitt trigger according to claim 1, characterized in that, In the current bias circuit, M1 and M2 constitute the first basic current mirror, M5 and M6 constitute the second basic current mirror, and M7 and M8 constitute the third basic current mirror. M1 and M2 have the same width-to-length ratio, M5 and M6 have a width-to-length ratio that is one-tenth that of M1, and M8 has a width-to-length ratio that is one-eighth that of M7.
3. The power-on reset circuit with a Schmitt trigger according to claim 1, characterized in that, In the low-voltage common-source common-gate current mirror, M2 and M6 form a current mirror, with M6 mirroring the current of M2; M3 and M9 form a common-gate transistor, which increases the output impedance of the current mirror.
4. The power-on reset circuit with a Schmitt trigger according to claim 1, characterized in that, The inverter is composed of PMOS and NMOS, the input terminal of the inverter has a V0 node, the output terminal of the inverter has a V1 node, and the Schmitt trigger is connected to the output terminal of the inverter.
5. A power-on reset circuit with a Schmitt trigger according to claim 4, characterized in that, The source of M10 is shorted, the gate of M10 is connected to node V1, and the back gate of M10 is grounded.
6. The power-on reset circuit with a Schmitt trigger according to claim 4, characterized in that, The V0 node is connected to the drain of M6 and the output terminal of the cascode structure.