Semiconductor device and method of manufacturing the same

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The device comprises a substrate, an active region and an isolation structure formed in the substrate, a gate and a barrier layer on the active region, the gate extending to the isolation structure in a second direction, the barrier layer covering a side wall of the gate and extending to cover a part of a top of the gate, a field plate on the barrier layer, a dummy gate on the isolation structure at both ends of the field plate, a gap between the dummy gate and the gate, and the barrier layer covering at least a part of the dummy gate, a side wall on a side wall of the gate and the dummy gate, and the side wall material filling the gap between the gate and the dummy gate. The application sets the dummy gate on the isolation structure at a side of the gate covered by the barrier layer, fills the side wall material in the gap between the dummy gate and the gate, thereby blocking the hollow channel below the gate side wall, avoiding the communication between the field plate and the hollow, avoiding the device damage caused by the short circuit, increasing the process window, and improving the product reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a semiconductor device and its fabrication method. Background Technology

[0002] BCD (Bipolar-CMOS-DMOS) is a monolithic integration process technology that enables the fabrication of bipolar transistors, CMOS devices, and DMOS devices on a single chip. It combines the high transconductance and strong load drive capability of bipolar devices with the high integration density and low power consumption of CMOS devices. More importantly, it integrates DMOS power devices, which can operate in switching mode with extremely low power consumption.

[0003] In BCD process chips, DMOS devices typically use a field plate to increase breakdown voltage (BV). However, due to the process characteristics of forming the gate sidewall, a void is formed under the sidewall. When the self-aligned silicide barrier (SAB) layer does not completely fill the void, the etching solution during subsequent etching of the barrier layer can enter the active region (AA) through the void channel, causing the void in the AA region to enlarge. The void connects with the field plate, causing the metal of the field plate to enter the void, resulting in a short circuit between the field plate and the drain, and the device burns out.

[0004] Current processes typically avoid creating void channels by reducing the process window, thereby solving the short circuit problem between the field plate and the drain. For example, the silicon oxide layer in the sidewalls needs to have excellent corrosion resistance, the barrier layer needs to have strong filling ability, and the etching ability of the sidewalls and barrier layer needs to be very stable. However, this places very stringent requirements on the entire process, which is not conducive to mass production. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and its manufacturing method, which can block the void channel below the gate sidewall, prevent the field plate from communicating with the void, and thus avoid device damage caused by short circuit.

[0006] To address the aforementioned technical problems, according to a first aspect of the present invention, a semiconductor device is provided, comprising:

[0007] A substrate, wherein an active region extending along a first direction and an isolation structure surrounding the active region are formed therein;

[0008] A gate is located on the active region, the gate extends along a second direction and extends to the isolation structure, wherein the first direction is perpendicular to the second direction;

[0009] a barrier layer on the active region, the barrier layer extending along the second direction and extending onto the isolation structure, the barrier layer covering a sidewall of the gate and extending to cover a portion of the top of the gate;

[0010] a field plate on the barrier layer, the field plate extending along the second direction and extending onto the isolation structure;

[0011] a dummy gate on the isolation structure at both ends of the field plate and on the side of the gate covered by the barrier layer, the dummy gate having a gap with the gate, and the barrier layer covering at least a portion of the dummy gate; and

[0012] a sidewall on sidewalls of the gate and the dummy gate, the sidewall material filling the gap between the gate and the dummy gate.

[0013] Optionally, the gap between the dummy gate and the gate is less than or equal to the thickness of the sidewall.

[0014] Optionally, the gap between the dummy gate and the gate is less than the gap between the field plate and the gate.

[0015] Optionally, further comprising an interlayer dielectric layer covering the substrate, the gate, the dummy gate, the sidewall, and the barrier layer, the interlayer dielectric layer having a field plate contact hole exposing the barrier layer, the field plate being in the field plate contact hole.

[0016] To solve the above technical problems, according to a second aspect of the present application, a method for manufacturing a semiconductor device is also provided, comprising the following steps:

[0017] providing a substrate, forming an active region extending along a first direction and an isolation structure surrounding the active region in the substrate;

[0018] forming a gate and a dummy gate on the substrate, the gate being on the active region extending along a second direction and extending onto the isolation structure, the dummy gate being on the isolation structure at both sides of the active region in the second direction, the dummy gate having a gap with the gate, wherein the first direction is perpendicular to the second direction;

[0019] forming a sidewall on sidewalls of the gate and the dummy gate, the sidewall material filling the gap between the dummy gate and the gate;

[0020] A barrier layer is formed on the substrate, the barrier layer being located on the active region and extending along the second direction to the isolation structure, the barrier layer covering one sidewall of the gate and extending to cover a portion of the top of the gate, the dummy gate being located on the side of the gate covered by the barrier layer, and the barrier layer at least partially covering the dummy gate; and,

[0021] A field plate is formed on the substrate, the field plate being located on the barrier layer and extending along the second direction and extending to the isolation structure.

[0022] Optionally, the gate and the dummy gate are formed in the same process step.

[0023] Optionally, the method for forming the gate and the dummy gate includes:

[0024] A gate material layer is formed on the substrate;

[0025] A patterned mask layer is formed on the gate material layer, and the gate material layer is etched using the patterned mask layer as a mask to form the gate and the virtual gate.

[0026] Optionally, the method of forming the field plate includes:

[0027] An interlayer dielectric layer is formed, which covers the substrate, the gate, the dummy gate, the sidewall, and the barrier layer;

[0028] Etching the interlayer dielectric layer to form field plate contact holes exposing the barrier layer; and...

[0029] A field plate is formed within the contact hole of the field plate.

[0030] Optionally, the barrier layer comprises a silicon-rich silicon oxide layer and a silicon nitride layer stacked sequentially, and the field plate contact hole penetrates the silicon nitride layer to expose the silicon-rich silicon oxide layer.

[0031] Optionally, while forming the field plate contact hole that exposes the barrier layer, a contact hole that exposes the gate or the active region is also formed; while forming the field plate in the field plate contact hole, a conductive plug is formed in the contact hole.

[0032] The semiconductor device and its fabrication method provided by the present invention include: a substrate, wherein an active region extending along a first direction and an isolation structure surrounding the active region are formed therein; a gate, located on the active region, extending along a second direction and extending to the isolation structure, wherein the first direction is perpendicular to the second direction; a barrier layer, located on the active region, extending along the second direction and extending to the isolation structure, the barrier layer covering one sidewall of the gate and extending to cover a portion of the top of the gate; a field plate, located on the barrier layer, extending along the second direction and extending to the isolation structure; a dummy gate, located on the isolation structure at both ends of the field plate and located on the side of the gate covered by the barrier layer, wherein there is a gap between the dummy gate and the gate, and the barrier layer at least covers a portion of the dummy gate; and a sidewall, located on the sidewall between the gate and the dummy gate, wherein the sidewall material fills the gap between the gate and the dummy gate. This invention provides a virtual gate on the isolation structure on the side of the gate covered by the barrier layer. The gap between the virtual gate and the gate is filled with sidewall material, thereby blocking the void channel below the gate sidewall and preventing the field plate from communicating with the void. This avoids device damage caused by short circuits, increases the process window, and improves product reliability. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the layout structure of semiconductor devices in related technologies.

[0034] Figure 2 It is based on Figure 1 A schematic diagram of the cross-section of a semiconductor device fabricated from the layout of AA'.

[0035] Figure 3 It is based on Figure 1 A schematic diagram of the cross-section of a semiconductor device fabricated from the layout of BB'.

[0036] Figure 4 It is based on Figure 1 A schematic diagram of the cross-section of a semiconductor device fabricated from the layout of CC'.

[0037] Figure 5 It is based on Figure 1 A schematic diagram of a cross-section of a semiconductor device fabricated from the layout of AA' using a scanning electron microscope.

[0038] Figure 6 It is based on Figure 1 A schematic diagram of a cross-section of a semiconductor device fabricated from the layout of CC' using a scanning electron microscope.

[0039] Figure 7This is a schematic diagram of the layout structure of a semiconductor device provided in an embodiment of the present invention.

[0040] Figure 8 It is based on Figure 7 A schematic diagram of the cross-section of a semiconductor device fabricated from the layout of AA'.

[0041] Figure 9 It is based on Figure 7 A schematic diagram of the cross-section of a semiconductor device fabricated from the layout of BB'.

[0042] Figure 10 It is based on Figure 7 A schematic diagram of the cross-section of a semiconductor device fabricated from the layout of CC'.

[0043] Figure 11 This is a schematic diagram of the layout structure of a semiconductor device provided in another embodiment of the present invention.

[0044] Figure 12 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0045] Figures 13 to 15 This is a schematic diagram of the steps of a semiconductor structure fabrication method provided in an embodiment of the present invention, shown in AA'.

[0046] Figures 16 to 19 This is a schematic diagram of the steps in the semiconductor structure fabrication method provided in an embodiment of the present invention, shown in BB'.

[0047] Explanation of reference numerals in the attached figures:

[0048] 10-Substrate; 11-Isolation structure; 12-Active region; 20-Gate; 21-Gate oxide layer; 22-Sidewall; 30-Barrier layer; 31-Silicon-rich silicon oxide layer; 32-Silicon nitride layer; 40-Field plate; 50-Contact hole; 60-Interlayer dielectric layer; 70-Void; 71-Void channel; 80-Dummy gate. Detailed Implementation

[0049] Figure 1 This is a schematic diagram of the layout structure of a semiconductor device in related technologies. Please refer to it. Figure 1As shown, the layout structure of a semiconductor device generally includes: a substrate 10, in which an active region 12 extending along a first direction X and an isolation structure 11 surrounding the active region 12 are formed; a gate 20, located on the active region 12, extending along a second direction Y and onto the isolation structure 11, wherein the first direction X is perpendicular to the second direction Y; a barrier layer 30, located on the active region 12, extending along the second direction Y and onto the isolation structure 11, the barrier layer 30 covering one sidewall of the gate 20 and extending to cover a portion of the top of the gate 20; and a field plate 40, located on the barrier layer 30, extending along the second direction Y and onto the isolation structure 11, with a gap between the projection of the field plate 40 on the substrate 10 and the projection of the gate 20 on the substrate 10. It also includes contact holes 50 located on the gate 20 and on the source / drain regions on both sides of the gate, for connecting the gate 20 to an external circuit, and connecting the source / drain regions to an external circuit.

[0050] Figure 2 It is based on Figure 1 A schematic cross-section of AA' showing a semiconductor device fabricated from the layout. Figure 3 It is based on Figure 1 A schematic diagram of the cross-section of a semiconductor device fabricated from the layout of BB'. Figure 4 It is based on Figure 1 A schematic cross-sectional view of the semiconductor device fabricated from the layout at CC'. Please refer to... Figures 2 to 4 As shown, according to Figure 1 The method for fabricating a semiconductor device based on the layout shown generally includes: first, providing a substrate 10, forming an active region 12 extending along a first direction X and an isolation structure 11 surrounding the active region 12 within the substrate 10; then forming a gate 20 on the substrate 10, the gate 20 being located on the active region 12 and extending along a second direction Y, and extending to the isolation structure 11; next, forming a sidewall material layer on the substrate 10 and the gate 20, and etching the sidewall material layer to form a sidewall located on the sidewall of the gate 20; Then, a barrier material layer is formed, which covers the gate 20, the sidewall, and the substrate 10. The barrier material layer is wet-etched to form a barrier layer 30. Next, an interlayer dielectric layer 60 is formed, which covers the substrate 10, the gate 20, the sidewall, and the barrier layer 30. The interlayer dielectric layer 60 is etched to form field plate contact holes that expose the barrier layer 30. A field plate 40 is formed in the field plate contact holes. The field plate 40 extends along the second direction Y and extends to the isolation structure 11.

[0051] Please continue to refer to this. Figures 2 to 4As shown, during the wet etching process of the sidewall material layer, a void 70 may be formed at the bottom of the sidewall 22, and a void channel 71 may be formed between the sidewall 22, the isolation structure 11, and the substrate 10. When the barrier material layer is formed, the barrier material layer cannot completely fill the void 70 and void channel 71 below the sidewall 22. The etching solution during the wet etching of the barrier material layer can easily enter the active region 12 from the void channel 71, making the void in the sidewall 22 of the active region 12 larger. The void penetrates the field plate 40, causing the metal of the field plate 40 to enter the void, thereby causing a short circuit between the field plate and the active region 12 (e.g., the drain terminal), and the device burns out.

[0052] Figure 5 It is based on Figure 1 A schematic diagram of a cross-section of a semiconductor device fabricated from the layout of AA' using a scanning electron microscope. Figure 6 It is based on Figure 1 A cross-sectional view of a semiconductor device fabricated from the layout shown in a scanning electron microscope at CC'. Please refer to... Figure 5 and Figure 6 As shown, a void channel 71 is formed between the bottom of the sidewall 22 and the substrate 10. The metal of the field plate 40 fills the void 70, thereby causing a short circuit in the device.

[0053] To address the aforementioned issues, the present invention provides a virtual gate on the isolation structure 11 on the side of the gate 20 covered by the barrier layer 30. The gap between the virtual gate and the gate 20 is filled with sidewall material, thereby blocking the void channel below the gate sidewall and preventing the field plate 40 from communicating with the void 70. This avoids device damage caused by short circuits, increases the process window, and improves product reliability.

[0054] Further research reveals that the present invention provides a semiconductor device comprising: a substrate having an active region extending along a first direction and an isolation structure surrounding the active region therein; a gate located on the active region, the gate extending along a second direction and extending to the isolation structure, wherein the first direction is perpendicular to the second direction; a barrier layer located on the active region, the barrier layer extending along the second direction and extending to the isolation structure, the barrier layer covering one sidewall of the gate and extending to cover a portion of the top of the gate; a field plate located on the barrier layer, the field plate extending along the second direction and extending to the isolation structure; a dummy gate located on the isolation structure at both ends of the field plate, and located on the side of the gate covered by the barrier layer, the dummy gate having a gap with the gate, and the barrier layer at least partially covering the dummy gate; and a sidewall located on the sidewalls of the gate and the dummy gate, the sidewall material filling the gap between the gate and the dummy gate.

[0055] Accordingly, the present invention also provides a method for fabricating a semiconductor device, comprising the following steps: providing a substrate, forming an active region extending along a first direction and an isolation structure surrounding the active region within the substrate; forming a gate and a dummy gate on the substrate, the gate being located on the active region and extending along a second direction to the isolation structure, the dummy gate being located on the isolation structure on both sides of the active region in the second direction, a gap being present between the dummy gate and the gate, wherein the first direction is perpendicular to the second direction; forming sidewalls on the sidewalls of the gate and the dummy gate, the sidewall material filling the gap between the dummy gate and the gate; forming a barrier layer on the substrate, the barrier layer being located on the active region and extending along the second direction to the isolation structure, the barrier layer covering one sidewall of the gate and extending to cover a portion of the top of the gate, the dummy gate being located on the side of the gate covered by the barrier layer, and the barrier layer at least covering a portion of the dummy gate; forming a field plate on the substrate, the field plate being located on the barrier layer and extending along the second direction to the isolation structure.

[0056] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0057] As used herein, the singular forms “a,” “an,” and “the” include plural objects unless otherwise expressly indicated. As used herein, the term “or” is generally used to mean “and / or” unless otherwise expressly indicated. As used herein, the term “a number” is generally used to mean “at least one” unless otherwise expressly indicated. As used herein, the term “at least two” is generally used to mean “two or more” unless otherwise expressly indicated. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0058] Figure 7 This is a schematic diagram of the layout structure of a semiconductor device provided in an embodiment of the present invention. Figure 8 It is based onFigure 7 A schematic cross-section of AA' showing a semiconductor device fabricated from the layout. Figure 9 It is based on Figure 7 A schematic diagram of the cross-section of a semiconductor device fabricated from the layout of BB'. Figure 10 It is based on Figure 7 A schematic cross-sectional view of the semiconductor device fabricated from the layout at CC'. Please refer to... Figures 7 to 10 As shown, the semiconductor device provided in this embodiment of the invention includes:

[0059] Substrate 10, wherein an active region 12 extending along a first direction X and an isolation structure 11 surrounding the active region 12 are formed therein;

[0060] A gate 20 is located on the active region 12, and the gate 20 extends along the second direction Y and extends to the isolation structure 11, wherein the first direction X is perpendicular to the second direction Y;

[0061] A barrier layer 30 is located on the active region 12. The barrier layer 30 extends along the second direction Y and extends to the isolation structure 11. The barrier layer 30 covers one sidewall of the gate 20 and extends to cover a portion of the top of the gate 20.

[0062] Field plate 40 is located on the barrier layer 30, and the field plate 40 extends along the second direction Y and extends to the isolation structure 11;

[0063] A virtual gate 80 is located on the isolation structures 11 at both ends of the field plate 40, and on the side of the gate 20 covered by the barrier layer 30. A gap exists between the virtual gate 80 and the gate 20, and the barrier layer 30 at least partially covers the virtual gate 80. In this embodiment, the barrier layer 30 completely covers the virtual gate 80.

[0064] Sidewall 22 is located on the sidewall of the gate 20 and the virtual gate 80, and the sidewall material fills the gap between the gate 20 and the virtual gate 80.

[0065] Please refer to Figure 8 As shown, a cavity 70 is also formed below the sidewall 22. This is determined by the forming process of the sidewall 22. Please refer to [reference needed]. Figure 9 and Figure 10 As shown, due to the arrangement of the dummy gate 80, and the gap between the gate 20 and the dummy gate 80 being filled with sidewall material, the void channel 71 below the sidewall 22 is blocked, therefore... Figure 8 The cavity 70 shown in the figure was not enlarged by etching, nor was it connected to the field plate 40. The cavity 70 was not filled with field plate material, thereby avoiding the occurrence of short circuits.

[0066] In the semiconductor device provided by this invention, a virtual gate 80 is provided on the isolation structure 11 on the side of the gate 20 covered by the barrier layer 30. The gap between the virtual gate 80 and the gate 20 is filled with sidewall material, thereby blocking the void channel below the sidewall 22 and avoiding the problem of communication between the field plate 40 and the void 70, thus avoiding device damage caused by short circuit. Furthermore, since the virtual gate 80 can achieve the purpose of avoiding short circuit, it is not necessary to require the silicon oxide layer in the sidewall to have good corrosion resistance, the barrier layer to have strong filling ability, and the etching ability of the sidewall and barrier layer to be very stable, as required by the prior art. This increases the process window and improves product reliability.

[0067] In one embodiment of the present invention, the distance between the virtual gate 80 and the gate 20 is less than or equal to the thickness of the sidewall 22, such that the gap between the virtual gate 80 and the gate 20 is filled with the sidewall material to block the void channel 71.

[0068] In one embodiment of the present invention, the distance between the virtual gate 80 and the gate 20 is smaller than the distance between the field plate 40 and the gate 20, that is, the virtual gate 80 is closer to the gate 20 than the field plate 40.

[0069] In one embodiment of the present invention, please refer to Figure 7 As shown, the semiconductor device also includes contact holes 50 located on the gate 20 and the active regions 12 on both sides of the gate 20. Please refer to... Figure 8 As shown in Figure 9, an interlayer dielectric layer 60 is formed on the substrate 10, the gate 20, the sidewall 22, and the barrier layer 30. Field plate contact holes exposing the barrier layer 30 are formed within the interlayer dielectric layer 60, and a field plate 40 is located within these field plate contact holes. Contact holes exposing the gate 20 and the source / drain regions on both sides of the gate 20 are also formed within the interlayer dielectric layer 60. These contact holes are filled with a conductive material to connect the gate 20 and the source / drain regions to an external circuit.

[0070] In one embodiment of the present invention, please refer to Figure 8 As shown, a gate oxide layer 21 is also formed between the gate 20 and the substrate 10. The material of the gate oxide layer 21 includes, but is not limited to, silicon oxide, silicon oxynitride, or a high-k dielectric material. The material of the gate 20 includes, but is not limited to, polysilicon.

[0071] In one embodiment of the present invention, please refer to Figure 8 As shown, the sidewall 22 can be a single-layer, double-layer, or multi-layer structure, and the sidewall material can be silicon oxide, silicon nitride, etc. Please refer to [reference needed]. Figure 8As shown, the sidewall 22 is a three-layer stacked structure comprising silicon oxide, silicon nitride and silicon oxide.

[0072] In one embodiment of the present invention, please refer to Figure 8 and Figure 9 As shown, the barrier layer 30 includes a silicon-rich silicon oxide (SRO) layer 31 and a silicon nitride layer 32 stacked sequentially. The field plate 40 penetrates the interlayer dielectric layer 60 and the silicon nitride layer 32 and is in contact with the silicon-rich silicon oxide layer 31. The material of the field plate 40 includes, but is not limited to, tungsten.

[0073] In one embodiment of the present invention, please refer to Figure 7 As shown, the blocking layer 30 completely covers the virtual gate 80. In another embodiment of the present invention, please refer to... Figure 11 As shown, the barrier layer 30 covers a portion of the virtual gate 80. Whether it fully or partially covers the virtual gate can be chosen based on the size of the barrier layer 30. Of course, the size of the virtual gate 80 can also be determined by the actual manufacturing process and the dimensions of components such as the gate 20 and the barrier layer 30; this invention does not impose any limitations on this.

[0074] The semiconductor device provided by the present invention includes: a substrate 10, wherein an active region 12 extending along a first direction X and an isolation structure 11 surrounding the active region 12 are formed therein; a gate 20 located on the active region 12, the gate 20 extending along a second direction Y and extending to the isolation structure 11, wherein the first direction X is perpendicular to the second direction Y; and a barrier layer 30 located on the active region 12, the barrier layer 30 extending along the second direction Y and extending to the isolation structure 11, the barrier layer 30 covering one sidewall of the gate 20 and extending to cover the gate. A portion of the top of electrode 20; a field plate 40 located on the barrier layer 30, the field plate 40 extending along the second direction Y and extending to the isolation structure 11; a dummy gate 80 located on the isolation structure 11 at both ends of the field plate 40, and located on the side of the gate 20 covered by the barrier layer 30, the dummy gate 80 having a gap with the gate 20, and the barrier layer 30 at least partially covering the dummy gate 80; and a sidewall 22 located on the sidewalls of the gate 20 and the dummy gate 80, the sidewall material filling the gap between the gate 20 and the dummy gate 80.

[0075] The present invention provides a virtual gate 80 on the isolation structure 11 on the side of the gate 20 covered by the barrier layer 30, and fills the gap between the virtual gate 80 and the gate 20 with sidewall material, thereby blocking the void channel 71 below the gate sidewall 22, preventing the field plate 40 from communicating with the void 70, thus avoiding device damage caused by short circuit, increasing the process window, and improving product reliability.

[0076] Accordingly, the present invention also provides a method for fabricating a semiconductor device, for forming the semiconductor device as described above.

[0077] Figure 12 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention. Figure 12 As shown, the method for fabricating a semiconductor device provided in this embodiment includes the following steps:

[0078] S1: Provide a substrate, in which an active region extending in a first direction and an isolation structure surrounding the active region are formed;

[0079] S2: A gate and a dummy gate are formed on the substrate. The gate is located on the active region and extends along a second direction to the isolation structure. The dummy gate is located on the isolation structure on both sides of the active region in the second direction. There is a gap between the dummy gate and the gate. The first direction is perpendicular to the second direction.

[0080] S3: A sidewall is formed on the sidewall of the gate and the virtual gate, and the sidewall material fills the gap between the virtual gate and the gate;

[0081] S4: A barrier layer is formed on the substrate, the barrier layer being located on the active region and extending along the second direction to the isolation structure, the barrier layer covering one sidewall of the gate and extending to cover a portion of the top of the gate, the dummy gate being located on the side of the gate covered by the barrier layer, and the barrier layer at least partially covering the dummy gate; and,

[0082] S5: A field plate is formed on the substrate, the field plate being located on the barrier layer and extending along the second direction and extending to the isolation structure.

[0083] Figures 13 to 15 This is a schematic diagram of the steps in the semiconductor structure fabrication method provided by an embodiment of the present invention, shown in AA'. Figures 16 to 19 This is a schematic diagram of the steps in the fabrication method of a semiconductor structure provided by an embodiment of the present invention, shown in BB'. Next, we will combine... Figures 7 to 10 , Figure 12 , Figures 13 to 15 and Figures 16 to 19 The method for fabricating the semiconductor device provided in the embodiments of the present invention will be described in detail.

[0084] In step S1, please refer to Figure 7 and Figure 16As shown, a substrate 10 is provided, in which an active region 12 extending along a first direction X and an isolation structure 11 surrounding the active region 12 are formed.

[0085] The substrate 10 can be made of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, or it can be silicon-on-insulator or germanium-on-insulator; or it can be other materials, such as gallium arsenide or other III-V compounds. In this embodiment, the substrate 10 is a silicon substrate.

[0086] An isolation structure 11 is formed within the substrate 10 to isolate the active region 12. For example, a patterned mask layer is formed on the substrate 10, and the substrate 10 is etched using the patterned mask layer as a mask to form isolation trenches. Isolation material is filled into the isolation trenches to form the isolation structure 11, and then the patterned mask layer is removed. The area isolated by the isolation structure 11 within the substrate 10 is the active region 12. Subsequently, regions required for semiconductor devices, such as well regions and drift regions, can be formed within the active region 12. The isolation structure 11 includes a shallow trench isolation structure.

[0087] In step S2, please refer to Figure 7 , Figure 13 and Figure 17 As shown, a gate 20 and a dummy gate 80 are formed on the substrate 10. The gate 20 is located on the active region 12 and extends along the second direction Y to the isolation structure 11. The dummy gate 80 is located on the isolation structure 11 on both sides of the active region 12 in the second direction Y. There is a gap between the dummy gate 80 and the gate 20, wherein the first direction X is perpendicular to the second direction Y.

[0088] In one embodiment of the present invention, the gate 20 and the dummy gate 80 are formed in the same process step. Exemplarily, a gate material layer is formed on the substrate 10, a patterned mask layer is formed on the gate material layer, the gate material layer is etched using the patterned mask layer as a mask to form the gate 20 and the dummy gate 80; and the patterned mask layer is removed.

[0089] The virtual gate 80 is spaced apart from the field plate 40, with a gap between them.

[0090] The spacing between the gate 20 and the virtual gate 80 is less than or equal to the thickness of the subsequently formed sidewall 22, so that the sidewall material fills the gap between the gate 20 and the virtual gate 80. The sidewall material can be silicon oxide, silicon nitride, etc.

[0091] In one embodiment of the present invention, before forming a gate material layer on the substrate 10, a gate oxide material layer is formed on the substrate, a gate material layer is formed on the gate oxide material layer, and the gate material layer and the gate oxide material layer are sequentially etched to form a gate 20, a dummy gate 80, and a gate oxide layer 21 located below the gate 20 and the dummy gate 80. The gate oxide layer 21 can be formed using any suitable process known to those skilled in the art, such as thermal oxidation, in-situ steam generation (ISSG), chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Similarly, the gate 20 and the dummy gate 80 can be formed using any suitable process known to those skilled in the art, such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition.

[0092] In step S3, please refer to Figure 7 , Figure 14 and Figure 18 As shown, a sidewall 22 is formed on the sidewalls of the gate 20 and the virtual gate 80, and the sidewall material fills the gap between the virtual gate 80 and the gate 20.

[0093] For example, firstly, a sidewall material is formed that covers the gate 20, the dummy gate 80, the substrate 10, and the gap between the gate 20 and the dummy gate 80. Then, the sidewall material is etched to retain only the sidewall material between the sidewalls of the gate 20 and the dummy gate 80 as sidewall 22, and the sidewall material in the gap between the dummy gate 80 and the gate 20 is retained to block the void channel.

[0094] In one embodiment of the present invention, the sidewall 22 is a stacked structure comprising silicon oxide, silicon nitride, and silicon oxide. First, a first silicon oxide layer is formed, conformally covering the gate 20 and the dummy gate 80, i.e., the first silicon oxide layer covers the sidewalls and top of the gate 20, the sidewalls and top of the dummy gate 80, and the substrate 10. Then, a silicon nitride layer is formed, conformally covering the gate 20 and the dummy gate 80 and filling the gap between them. Next, a second silicon oxide layer is formed, conformally covering the gate 20 and the dummy gate 80. Then, the second silicon oxide layer, the silicon nitride layer, and the first silicon oxide layer are etched to form... Figure 14 and Figure 18 The structure shown.

[0095] In this embodiment, a void is formed at the bottom of the sidewall 22, specifically at the bottom of the silicon nitride layer (of course, it is not yet a complete void; it is only formed on the sidewall of the gate 20 or the dummy gate 80, where the silicon nitride layer extends away from the first silicon oxide layer relative to the sidewall, forming the area where the void is located at the bottom of the silicon nitride layer, and the void is formed after the barrier layer 30 is subsequently formed). Furthermore, since the gap between the gate 20 and the dummy gate 80 is filled with sidewall material, there is no void at the bottom of the structure between the gate 20 and the dummy gate 80, thus blocking the void channel.

[0096] In step S4, please refer to Figure 7 , Figure 15 and Figure 19 As shown, a barrier layer 30 is formed on the substrate 10. The barrier layer 30 is located on the active region 12 and extends along the second direction Y to the isolation structure 11. The barrier layer 30 covers one sidewall of the gate 20 and extends to cover a portion of the top of the gate 20. The dummy gate 80 is located on the side of the gate 20 covered by the barrier layer 30, and the barrier layer 30 covers at least a portion of the dummy gate 80.

[0097] For example, a barrier material layer is first formed, which covers the gate 20, the dummy gate 80, the sidewall 22 and the substrate 10. Then, the barrier material layer is etched to remove a portion of the top and sidewall of the gate 20 and the barrier material layer on the substrate 10 away from the dummy gate 80. The remaining barrier material layer constitutes the barrier layer 30.

[0098] During the etching process of the barrier material layer, since the cavity channel 71 is blocked, the etching liquid will not enter the cavity 70 under the side wall 22 of the active region 12 through the cavity channel 71, thereby avoiding etching the cavity 70 under the side wall 22 of the active region 12 and preventing the field plate 40 formed subsequently from communicating with the cavity 70 under the side wall 22 of the active region 12.

[0099] In one embodiment of the present invention, the barrier layer 30 includes a silicon-rich silicon oxide layer 31 and a silicon nitride layer 32 stacked sequentially, but is not limited to this.

[0100] In one embodiment of the present invention, please refer to Figure 7 As shown, the barrier layer 30 completely covers the virtual gate 80. In another embodiment of the present invention, please refer to... Figure 11 As shown, the barrier layer 30 partially covers the virtual gate 80. The size of the barrier layer 30 can be used to select whether it provides full or partial coverage.

[0101] In step S4, please refer toFigure 7 and Figure 8 As shown, a field plate 40 is formed on the substrate 10, the field plate 40 is located on the barrier layer 30 and extends along the second direction Y and extends to the isolation structure 11.

[0102] In one embodiment of the present invention, an interlayer dielectric layer 60 is first formed, which covers the substrate 10, the gate 20, the dummy gate 80, the sidewall 22, and the barrier layer 30; then the interlayer dielectric layer 60 is etched to form a field plate contact hole that exposes the barrier layer 30; and then a field plate 40 is formed in the field plate contact hole.

[0103] When the barrier layer 30 comprises a silicon-rich silicon oxide layer 31 and a silicon nitride layer 32 stacked sequentially, the interlayer dielectric layer 60 and the silicon nitride layer 32 are etched to form field plate contact holes exposing the silicon-rich silicon oxide layer 31, and a field plate 40 is formed within the field plate contact holes. The material of the field plate 40 includes, but is not limited to, tungsten.

[0104] In one embodiment of the present invention, while forming the field plate contact hole that exposes the barrier layer 30, a contact hole that exposes the gate 20 or the source / drain region is also formed; while forming the field plate 40 in the field plate contact hole, a conductive plug is made in the contact hole of the gate 20 or the source / drain region to connect the gate 20 or the source / drain region to an external circuit.

[0105] In the method for fabricating a semiconductor device provided by the present invention, a substrate 10 is first provided, and an active region 12 extending along a first direction X and an isolation structure 11 surrounding the active region 12 are formed within the substrate 10. Next, a gate 20 and a dummy gate 80 are formed on the substrate 10. The gate 20 is located on the active region 12 and extends along a second direction Y, reaching the isolation structure 11. The dummy gate 80 is located on the isolation structure 11 on both sides of the active region 12 in the second direction Y and is located on one side of the gate 20. A gap exists between the dummy gate 80 and the gate 20, wherein the first direction X is perpendicular to the second direction Y. A gap is formed between the gate 20 and the dummy gate 80. A sidewall 22 is formed, and the sidewall material fills the gap between the dummy gate 80 and the gate 20; then a barrier layer 30 is formed on the substrate 10, the barrier layer 30 is located on the active region 12 and extends along the second direction Y and extends to the isolation structure 11, the barrier layer 30 covers one sidewall of the gate 20 and extends to cover a portion of the top of the gate 20, the dummy gate 80 is located on the side of the gate 20 covered by the barrier layer 30, and the barrier layer 30 at least covers a portion of the dummy gate 80; and a field plate 40 is formed on the substrate 10, the field plate 40 is located on the barrier layer 30 and extends along the second direction Y and extends to the isolation structure 11. The present invention provides a virtual gate 80 on the isolation structure 11 on the side of the gate 20 covered by the barrier layer 30, and fills the gap between the virtual gate 80 and the gate 20 with sidewall material, thereby blocking the void channel below the gate sidewall 22, preventing the field plate 40 from communicating with the void 70 below the active region gate sidewall 22, thus avoiding device damage caused by short circuit, increasing the process window, and improving product reliability.

[0106] In summary, the semiconductor device and its fabrication method provided by the present invention include: a substrate, wherein an active region extending along a first direction and an isolation structure surrounding the active region are formed therein; a gate, located on the active region, extending along a second direction and extending to the isolation structure, wherein the first direction is perpendicular to the second direction; a barrier layer, located on the active region, extending along the second direction and extending to the isolation structure, the barrier layer covering one sidewall of the gate and extending to cover a portion of the top of the gate; a field plate, located on the barrier layer, extending along the second direction and extending to the isolation structure; a dummy gate, located on the isolation structure at both ends of the field plate and located on the side of the gate covered by the barrier layer, wherein there is a gap between the dummy gate and the gate, and the barrier layer at least covers a portion of the dummy gate; and a sidewall, located on the sidewall between the gate and the dummy gate, wherein the sidewall material fills the gap between the gate and the dummy gate. This invention provides a virtual gate on the isolation structure on the side of the gate covered by the barrier layer. The gap between the virtual gate and the gate is filled with sidewall material, thereby blocking the void channel below the gate sidewall and preventing the field plate from communicating with the void. This avoids device damage caused by short circuits, increases the process window, and improves product reliability.

[0107] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A substrate, wherein an active region extending along a first direction and an isolation structure surrounding the active region are formed therein; A gate is located on the active region, the gate extends along a second direction and extends to the isolation structure, wherein the first direction is perpendicular to the second direction; A barrier layer is located on the active region, the barrier layer extends along the second direction and extends to the isolation structure, the barrier layer covers one sidewall of the gate and extends to cover a portion of the top of the gate; A field plate is located on the barrier layer, the field plate extending along the second direction and extending onto the isolation structure; A virtual gate is located on the isolation structure at both ends of the field plate and on the side of the gate covered by the barrier layer. There is a gap between the virtual gate and the gate, and the barrier layer covers at least part of the virtual gate. as well as, A sidewall is located on the sidewall between the gate and the virtual gate, and the sidewall material fills the gap between the gate and the virtual gate; the distance between the virtual gate and the gate is less than or equal to the thickness of the sidewall.

2. The semiconductor device according to claim 1, characterized in that, The spacing between the virtual gate and the gate is smaller than the spacing between the field plate and the gate.

3. The semiconductor device according to claim 1, characterized in that, It also includes an interlayer dielectric layer that covers the substrate, the gate, the dummy gate, the sidewall, and the barrier layer. A field plate contact hole is formed in the interlayer dielectric layer to expose the barrier layer, and the field plate is located in the field plate contact hole.

4. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided in which an active region extending in a first direction and an isolation structure surrounding the active region are formed; A gate and a dummy gate are formed on the substrate. The gate is located on the active region and extends along a second direction to the isolation structure. The dummy gate is located on the isolation structure on both sides of the active region in the second direction. There is a gap between the dummy gate and the gate. The first direction is perpendicular to the second direction. A sidewall is formed on the sidewall of the gate and the dummy gate, and the sidewall material fills the gap between the dummy gate and the gate; the distance between the dummy gate and the gate is less than or equal to the thickness of the sidewall; A barrier layer is formed on the substrate, the barrier layer is located on the active region and extends along the second direction and extends to the isolation structure, the barrier layer covers one sidewall of the gate and extends to cover a portion of the top of the gate, the dummy gate is located on the side of the gate covered by the barrier layer, and the barrier layer covers at least a portion of the dummy gate; as well as, A field plate is formed on the substrate, the field plate being located on the barrier layer and extending along the second direction and extending to the isolation structure.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, The gate and the dummy gate are formed in the same process step.

6. The method for fabricating a semiconductor device according to claim 5, characterized in that, The method of forming the gate and the dummy gate includes: A gate material layer is formed on the substrate; A patterned mask layer is formed on the gate material layer, and the gate material layer is etched using the patterned mask layer as a mask to form the gate and the virtual gate.

7. The method for fabricating a semiconductor device according to claim 4, characterized in that, The method of forming the field plate includes: An interlayer dielectric layer is formed, which covers the substrate, the gate, the dummy gate, the sidewall, and the barrier layer; Etching the interlayer dielectric layer to form field plate contact holes exposing the barrier layer; and... A field plate is formed within the contact hole of the field plate.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The barrier layer comprises a silicon-rich silicon oxide layer and a silicon nitride layer stacked sequentially, and the field plate contact hole penetrates the silicon nitride layer to expose the silicon-rich silicon oxide layer.

9. The method for fabricating a semiconductor device according to claim 7, characterized in that, While forming the field plate contact hole that exposes the barrier layer, a contact hole that exposes the gate or the active region is also formed; while forming the field plate in the field plate contact hole, a conductive plug is formed in the contact hole.

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