Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. A first well region in the substrate; the second well region is located in the substrate at the side part of the first well region, and the doping type of the second well region is different from that of the first well region; the buffer layer is located in the second well region, the doping type of the buffer layer is the same as that of the second well region, and the concentration of doped ions in the buffer layer is higher than that of the doped ions in the second well region; the source region is located in the first well region, and the concentration of doped ions in the source region is higher than that of doped ions in the first well region; the drain region is located in the second well region, the doping type of the drain region is the same as that of the second well region, and the concentration of doped ions in the drain region is higher than that of the doped ions in the second well region; and the gate structure is located at the top of the substrate at the junction of the first well region and the second well region. And the risk of breakdown of the semiconductor structure due to overlarge electric field intensity is reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and particularly to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] LDMOS (Lateral Double-diffused Metal Oxide Semiconductor) is a kind of power semiconductor device, which is widely used in high-voltage and high-current occasions, such as power management, motor drive, automotive electronics and industrial control system, etc. LDMOS combines the characteristics of bipolar transistor (Bipolar) and metal oxide semiconductor field effect transistor (MOSFET), and provides high-voltage, high-current processing capability and good switching performance.

[0003] LDMOS device is valued for its excellent performance in high-voltage applications, but with the development of semiconductor technology, methods for improving its switching speed and reducing on-resistance are also being sought to meet more extensive application requirements. SUMMARY

[0004] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which optimizes the performance of the semiconductor device.

[0005] To solve the above problems, embodiments of the present application provide a semiconductor structure, comprising: a substrate; a first well region located in the substrate, the substrate exposing a top surface of the first well region; a second well region located in the substrate on a side of the first well region, the substrate exposing a top surface of the second well region, the doping type of the second well region being different from the doping type of the first well region; one or more buffer layers located in the second well region and stacked in a longitudinal direction, the doping type of the buffer layer being the same as the doping type of the second well region, and the concentration of the doping ions in the buffer layer being higher than the concentration of the doping ions in the second well region; a source region located in the first well region, the doping type of the source region being the same as the doping type of the first well region, and the concentration of the doping ions in the source region being higher than the concentration of the doping ions in the first well region, the first well region exposing a top surface of the source region; a drain region located in the second well region, the doping type of the drain region being the same as the doping type of the second well region, and the concentration of the doping ions in the drain region being higher than the concentration of the doping ions in the second well region, the second well region exposing a top surface of the drain region; and a gate structure located on the top of the substrate at the junction of the first well region and the second well region.

[0006] Optionally, when the number of buffer layers is multiple, the concentration of the doping ions in the buffer layer gradually increases in the direction close to the top surface of the second well region.

[0007] Optionally, the thickness of the buffer layer is 300 angstroms to 2000 angstroms along the normal direction of the substrate surface.

[0008] Optionally, the concentration of doped ions in the buffer layer is in the range of 5.0 E12 atom / cm³. 3 Up to 1.0E15 atom / cm 3 .

[0009] Optionally, the semiconductor structure further includes: an isolation structure located in the first well region and the second well region, the first well region and the second well region exposing the top surface of the isolation structure; a buffer layer located in the second well region between adjacent isolation structures; a source region located in the first well region between adjacent isolation structures; and a drain region located in the second well region between adjacent isolation structures.

[0010] Optionally, the semiconductor structure further includes a gate oxide layer located on top of the substrate at the junction of the first well region and the second well region, and the gate structure covers the top surface of the gate oxide layer.

[0011] Optionally, the thickness of the gate oxide layer along the normal direction of the substrate surface is 100 angstroms to 280 angstroms.

[0012] Optionally, the first well region is doped with P-type doping, and the second well region is doped with N-type doping.

[0013] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a first well region is formed in the substrate, the top surface of the first well region is exposed in the substrate, and a second well region is further formed in the substrate on the side of the first well region, the top surface of the second well region is exposed in the substrate, and the doping type of the second well region is different from that of the first well region; forming one or more buffer layers stacked in the vertical direction in the second well region, wherein the doping type of the buffer layer is the same as that of the second well region, and the concentration of doped ions in the buffer layer is higher than that in the second well region; and after forming the buffer layer... A source region is formed in the first well region, the doping type of the source region is the same as that of the first well region, and the concentration of doped ions in the source region is higher than that in the first well region. The top surface of the first well region is exposed. After forming the buffer layer, a drain region is formed in the second well region above the buffer layer, the doping type of the drain region is the same as that of the second well region, and the concentration of doped ions in the drain region is higher than that in the second well region. The top surface of the second well region is exposed. After forming the source region and the drain region, a gate structure is formed on the top of the substrate at the junction of the first well region and the second well region.

[0014] Optionally, in the step of forming the buffer layer, when the number of layers of the buffer layer is multi-layered, the concentration of doped ions in the buffer layer gradually increases in the direction close to the top surface of the second well region.

[0015] Optionally, the step of forming the buffer layer includes: doping a portion of the thickness of the second well region to form an ion-doped layer in the second well region, and using the ion-doped layer as the buffer layer.

[0016] Optionally, the process for doping a portion of the second well region includes ion implantation.

[0017] Optionally, the thickness of the buffer layer is 300 angstroms to 2000 angstroms along the normal direction of the substrate surface.

[0018] Optionally, in the step of forming the buffer layer, the concentration of doped ions in the buffer layer is in the range of 5.0 E12 atom / cm³. 3 Up to 1.0E15 atom / cm 3 .

[0019] Optionally, in the step of providing the substrate, an isolation structure is further formed in the first well region and the second well region, with the top surface of the isolation structure exposed in the first well region and the second well region; in the step of forming the buffer layer, the buffer layer is located in the second well region between adjacent isolation structures; in the step of forming the source region, the source region is located in the first well region between adjacent isolation structures; and in the step of forming the drain region, the drain region is located in the second well region between adjacent isolation structures.

[0020] Optionally, after forming the source region and drain region and before forming the gate structure, the method further includes: forming a gate oxide layer on top of a substrate at the junction of the first well region and the second well region; in the step of forming the gate structure, the gate structure covers the top surface of the gate oxide layer.

[0021] Optionally, the thickness of the gate oxide layer along the normal direction of the substrate surface is 100 angstroms to 280 angstroms.

[0022] Optionally, the first well region is doped with P-type doping, and the second well region is doped with N-type doping.

[0023] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0024] In the semiconductor structure formation method provided by the embodiments of the present invention, one or more buffer layers are formed in the second well region in a vertically stacked manner. The doping type of the buffer layer is the same as that of the second well region, and the concentration of doped ions in the buffer layer is higher than that in the second well region. After the drain region is subsequently formed, it means that a buffer layer is provided between the drain region and the second well region. When the semiconductor structure is in a high-voltage operating state, since the concentration of doped ions in the buffer layer is higher than that in the second well region, a depletion region will be formed between the second well region and the buffer layer. The buffer layer can slow down the rate at which the boundary of the depletion region gradually approaches the drain, thereby slowing down the rate at which the depletion region expands in depth. Correspondingly, the rate at which the electric field strength increases at the edge position of the depletion region near the drain region is also slowed down, reducing the risk of semiconductor structure breakdown due to excessive electric field strength, and thus improving the robustness of the semiconductor structure. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of a semiconductor structure.

[0026] Figure 2 This is a schematic diagram of the corresponding structure in one embodiment of the semiconductor structure of the present invention;

[0027] Figures 3 to 8 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0028] As the background technology shows, the performance of semiconductor devices still needs improvement. This paper analyzes the reasons why the performance of semiconductor devices still needs improvement, using a specific semiconductor structure as an example.

[0029] Figure 1 This is a schematic diagram of a semiconductor structure.

[0030] The semiconductor structure includes: a substrate 10; a first well region 14 located in the substrate 10, with the top surface of the first well region 14 exposed; a second well region 12 located in the substrate 10 on the side of the first well region 14, with the top surface of the second well region 12 exposed, the doping type of the second well region 12 being different from that of the first well region 14; and a source region 13 located in the first well region 14, the doping type of the source region 13 being the same as that of the first well region 14, and the source region 13 being doped with... The concentration of impurity ions is higher than the concentration of doped ions in the first well region 14, and the first well region 14 exposes the top surface of the source region 13; the drain region 11 is located in the second well region 12, the doping type of the drain region 11 is the same as the doping type of the second well region 12, and the concentration of doped ions in the drain region 11 is higher than the concentration of doped ions in the second well region 12, and the second well region 12 exposes the top surface of the drain region 11; the gate structure 18 is located on top of the substrate 10 at the junction of the first well region 14 and the second well region 12.

[0031] Research has revealed that when the semiconductor structure is in operation, a depletion region is formed between the second well region 12 and the drain region 11 because the concentration of doped ions in the second well region 12 is lower than that in the drain region 11. When the semiconductor structure is in a high-voltage operating state, the depletion region between the second well region 12 and the drain region 11 moves towards the drain region 11, making the distance between the boundary of the depletion region and the drain electrode smaller and smaller. At the same time, the high-voltage semiconductor structure causes the electric field strength at the edge of the depletion region near the drain region 11 to gradually increase. Since the distance between the boundary of the depletion region and the drain electrode is getting smaller and smaller, and the electric field strength at the edge of the depletion region near the drain region 11 is gradually increasing, the risk of the semiconductor structure being broken down is increased, which in turn affects the robustness of the semiconductor structure.

[0032] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a first well region is formed in the substrate, the top surface of the first well region is exposed in the substrate, and a second well region is further formed in the substrate on the side of the first well region, the top surface of the second well region is exposed in the substrate, and the doping type of the second well region is different from that of the first well region; forming one or more buffer layers stacked in the second well region in a vertical direction, wherein the doping type of the buffer layer is the same as that of the second well region, and the concentration of doped ions in the buffer layer is higher than that in the second well region; forming the buffer layer... After the buffer layer is formed, a source region is formed in the first well region. The doping type of the source region is the same as that of the first well region, and the concentration of doped ions in the source region is higher than that in the first well region. The top surface of the first well region is exposed. After the buffer layer is formed, a drain region is formed in the second well region above the buffer layer. The doping type of the drain region is the same as that of the second well region, and the concentration of doped ions in the drain region is higher than that in the second well region. The top surface of the second well region is exposed. After the source region and the drain region are formed, a gate structure is formed on the top of the substrate at the junction of the first well region and the second well region.

[0033] In the semiconductor structure formation method provided by the embodiments of the present invention, one or more buffer layers are formed in the second well region in a vertically stacked manner. The doping type of the buffer layer is the same as that of the second well region, and the concentration of doped ions in the buffer layer is higher than that in the second well region. After the drain region is subsequently formed, it means that a buffer layer is provided between the drain region and the second well region. When the semiconductor structure is in a high-voltage operating state, since the concentration of doped ions in the buffer layer is higher than that in the second well region, a depletion region will be formed between the second well region and the buffer layer. The buffer layer can slow down the rate at which the boundary of the depletion region gradually approaches the drain, thereby slowing down the rate at which the depletion region expands in depth. Correspondingly, the rate at which the electric field strength increases at the edge position of the depletion region near the drain region is also slowed down, reducing the risk of semiconductor structure breakdown due to excessive electric field strength, and thus improving the robustness of the semiconductor structure.

[0034] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figure 2 This is a schematic diagram of the semiconductor structure corresponding to the first embodiment of the present invention.

[0036] The semiconductor structure includes: a substrate 200; a first well region 201 located in the substrate 200, with the top surface of the first well region 201 exposed; a second well region 202 located in the substrate 200 to the side of the first well region 201, with the top surface of the second well region 202 exposed, the doping type of the second well region 202 being different from that of the first well region 201; one or more buffer layers 206 located in the second well region 202 and stacked in the longitudinal direction, the doping type of the buffer layers 206 being the same as that of the second well region 202, and the concentration of doped ions in the buffer layers 206 being higher than that in the second well region 202. A source region is located in the first well region 201. The doping type of the source region is the same as that of the first well region 201, and the concentration of doped ions in the source region is higher than that in the first well region 201. The top surface of the first well region 201 is exposed. A drain region 210 is located in the second well region 202. The doping type of the drain region 210 is the same as that of the second well region 202, and the concentration of doped ions in the drain region 210 is higher than that in the second well region 202. The top surface of the drain region 210 is exposed. A gate structure 218 is located on top of the substrate 200 at the junction of the first well region 201 and the second well region 202.

[0037] It should be noted that one or more buffer layers 206 stacked in the longitudinal direction are disposed in the second well region 202. The doping type of the buffer layer 206 is the same as that of the second well region 202, and the concentration of doped ions in the buffer layer 206 is higher than that in the second well region 202. After the drain region 210 is subsequently formed, it means that a buffer layer 206 is disposed between the drain region 210 and the second well region 202. When the semiconductor structure is in a high voltage operating state, since the concentration of doped ions in the buffer layer 206 is higher than that in the second well region 202, a depletion region will be formed between the second well region 202 and the buffer layer 206. The buffer layer 206 can slow down the rate at which the boundary of the depletion region gradually approaches the drain, thereby slowing down the rate at which the depletion region expands in depth. Correspondingly, the rate at which the electric field strength increases at the edge of the depletion region near the drain region 210 is also slowed down, reducing the risk of semiconductor structure breakdown due to excessive electric field strength, and thus improving the robustness of the semiconductor structure.

[0038] Specifically, the substrate 200 provides a platform for the formation process of semiconductor structures.

[0039] As an example, the semiconductor structure is LDMOS (Laterally Diffused Metal-Oxide Semiconductor).

[0040] In this embodiment, taking the formed LDMOS as a planar transistor as an example, the substrate 200 is a planar substrate.

[0041] In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the substrate may also be a substrate of other materials such as germanium substrate, silicon germanide substrate, silicon carbide substrate, gallium arsenide substrate, or indium gallium bismuth substrate, and the substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0042] It should be noted that by setting the first well region 201, the breakdown resistance of LDMOS can be improved. Specifically, when LDMOS is in the working state, a depletion region is formed between the first well region 201 and the subsequently formed source region. This depletion region can disperse the electric field, reduce the risk of electric field concentration in LDMOS, and thus improve the breakdown resistance of LDMOS.

[0043] As an example, the first well region 201 is doped with P-type ions. That is, the first well region 201 is doped with P-type ions.

[0044] Specifically, the first well region 201 is doped with P-type ions. As the operating voltage of the LDMOS gradually increases, the depletion region between the first well region 201 and the subsequently formed source region can move away from the source region, thereby reducing the probability of the accumulated electric field strength damaging the source region.

[0045] As an example, P-type ions include B ions, Ga ions, or In ions.

[0046] It should be noted that by setting the second well region 202, the breakdown resistance of LDMOS can be improved. Specifically, when LDMOS is in the working state, a depletion region is formed between the second well region 202 and the subsequently formed buffer layer 206. This depletion region can disperse the electric field, reduce the risk of electric field concentration in LDMOS, and thus improve the breakdown resistance of LDMOS.

[0047] As an example, the second well region 202 is doped with N-type ions. That is, the second well region 202 is doped with N-type ions.

[0048] In this embodiment, the doping type of the second well region 202 is different from the doping type of the first well region 201.

[0049] Specifically, the doping type of the second well region 202 is different from that of the first well region 201, which enables the formation of a PN junction between the second well region 202 and the first well region 201. This helps to improve the breakdown capability of the LDMOS. At the same time, it can also reduce the probability of leakage current between the subsequently formed source and drain regions 210, and play an electrical isolation role between the source and drain regions 210.

[0050] As an example, N-type ions include P ions, As ions, or Sb ions.

[0051] In this embodiment, the semiconductor structure further includes an isolation structure 204 located in the first well region 201 and the second well region 202, with the top surface of the isolation structure 204 exposed in the first well region 201 and the second well region 202.

[0052] Specifically, the isolation structure 204 provides electrical isolation for the subsequently formed buffer layer 206, source region, and drain region 210, further reducing the probability of leakage current in the semiconductor structure and thus improving the performance of the semiconductor structure.

[0053] As an example, the material of the isolation structure 204 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0054] It should be noted that one or more buffer layers 206 are formed in the second well region 202 in the longitudinal direction. The doping type of the buffer layer 206 is the same as that of the second well region 202, and the concentration of doped ions in the buffer layer 206 is higher than that in the second well region 202. After the drain region 210 is formed, it means that a buffer layer 206 is provided between the drain region 210 and the second well region 202. When the semiconductor structure is in a high voltage operating state, since the concentration of doped ions in the buffer layer 206 is higher than that in the second well region 202, a depletion region will be formed between the second well region 202 and the buffer layer 206. The buffer layer 206 can slow down the rate at which the boundary of the depletion region gradually approaches the drain, thereby slowing down the rate at which the depletion region expands in depth. Correspondingly, the rate at which the electric field strength increases at the edge of the depletion region near the drain region 210 is also slowed down, reducing the risk of the semiconductor structure breaking down due to excessive electric field strength, and thus improving the robustness of the semiconductor structure.

[0055] It should also be noted that in the process of forming the buffer layer 206, the buffer layer 206 is formed by doping a portion of the thickness of the second well region 202. At the same time, in the process of forming multiple buffer layers 206, the concentration of doped ions in each buffer layer 206 can be made different by continuously adjusting the doping dosage.

[0056] In this embodiment, when the buffer layer 206 has multiple layers, the concentration of doped ions in the buffer layer 206 gradually increases in the direction close to the top surface of the second well region 202.

[0057] Specifically, when the buffer layer 206 has multiple layers, the concentration of doped ions in the buffer layer 206 gradually increases in the direction near the top surface of the second well region 202. This allows for the formation of multiple buffer layers 206 with a gradient distribution of doped ion concentration between the drain region 210 and the second well region 202 below the drain region 210. Since the concentration of doped ions in the buffer layer 206 is higher than that in the second well region 202, meaning that the closer to the drain region 210, the higher the concentration of doped ions in the buffer layer 206, the slower the rate at which the depletion region formed between the buffer layer 206 and the second well region 202 approaches the drain region 210. Consequently, the rate at which the electric field strength increases at the edge of the depletion region near the drain region 210 is further reduced, thereby reducing the risk of semiconductor structure breakdown due to excessive electric field strength and improving the robustness of the semiconductor structure.

[0058] As an example, such as Figure 2 As shown, a buffer layer 206 is illustrated.

[0059] It should be noted that the concentration of doped ions in the buffer layer 206 should not be too high or too low. If the concentration of doped ions in the buffer layer 206 is too high, the advance rate of the depletion region may approach 0, causing the device to fail to turn on; if the concentration of doped ions in the buffer layer 206 is too low, it will not be able to slow down the advance rate of the depletion region. Therefore, in this embodiment, the concentration range of doped ions in the buffer layer 206 is 5.0 E12 atom / cm³. 3 Up to 1.0E15 atom / cm 3 .

[0060] It should also be noted that the thickness of the buffer layer 206 along the normal direction of the substrate 200 surface should not be too large or too small. If the thickness of the buffer layer 206 is too large, given a fixed thickness of the second well region 202, the thickness of the second well region 202 below the buffer layer 206 may be too small. Since the thickness of the second well region 202 is positively correlated with the breakdown voltage capability of the LDMOS, a small thickness of the second well region 202 below the buffer layer 206 will result in a smaller voltage value that the LDMOS can withstand, thus affecting the performance of the LDMOS. If the thickness of the buffer layer 206 is too small, the rate at which the depletion region formed between the buffer layer 206 and the second well region 202 approaches the drain region 210 may not be slowed down, thereby increasing the risk of LDMOS breakdown due to excessive electric field strength, and thus affecting the robustness of the semiconductor structure. Therefore, in this embodiment, the thickness of the buffer layer 206 along the normal direction of the substrate 200 surface is 300 angstroms to 2000 angstroms.

[0061] In this embodiment, the buffer layer 206 is located in the second well region 202 between adjacent isolation structures 204.

[0062] Specifically, the buffer layer 206 is located in the second well region 202 between adjacent isolation structures 204, so that the isolation structure 204 can reduce the probability of doped ions in the buffer layer 206 diffusing in the lateral direction, thereby generating leakage current between the subsequently formed source region and drain region 210.

[0063] Specifically, the source region is used to electrically connect with the external circuit structure, so that the source region serves as the electrode input terminal.

[0064] It should be noted that the concentration of doped ions in the source region is higher than that in the first well region 201, which helps to reduce the contact resistance between the source region and the external circuit structure, and at the same time, it can also improve the current driving capability of the semiconductor structure.

[0065] In this embodiment, the source region is located in the first well region 201 between adjacent isolation structures 204.

[0066] Specifically, the source region is located in the first well region 201 between adjacent isolation structures 204, so that the isolation structure 204 provides electrical isolation to the source region, reducing the probability of leakage current between the source region and the subsequently formed drain region 210.

[0067] Specifically, the drain region 210 is used to electrically connect with the external circuit structure, so that the drain region 210 serves as an electrode output terminal.

[0068] It should be noted that the concentration of doped ions in the drain region 210 is higher than that in the second well region 202, which helps to reduce the contact resistance between the drain region 210 and the external circuit structure, and at the same time, it can also improve the current driving capability of the semiconductor structure.

[0069] In this embodiment, the drain region 210 is located in the second well region 202 between adjacent isolation structures 204.

[0070] Specifically, the drain region 210 is located in the second well region 202 between adjacent isolation structures 204, so that the isolation structure 204 provides electrical isolation to the drain region 210, reducing the probability of leakage current between the drain region 210 and the source region.

[0071] The semiconductor structure further includes a gate oxide layer 216 located on top of the substrate 200 at the junction of the first well region 201 and the second well region 202, and the gate structure 218 covering the top surface of the gate oxide layer 216.

[0072] Specifically, the gate oxide layer 216 can filter out most of the weak mixed flow and reduce the parameters of the device, thereby enhancing the performance and reliability of the semiconductor structure.

[0073] In this embodiment, the gate oxide layer 216 is formed by a local oxidation of silicon (LOCOS) process. During the local oxidation process, O2 diffuses in all directions and reacts with the substrate 200 to form silicon oxide.

[0074] As an example, the material of the gate oxide layer 216 includes silicon oxide.

[0075] It should be noted that the thickness of the gate oxide layer 216 along the normal direction of the substrate 200 surface should not be too large or too small. If the thickness of the gate oxide layer 216 is too large, it can easily lead to an increase in the device turn-on voltage of the semiconductor structure; if the thickness of the gate oxide layer 216 is too small, it can easily affect the electrical isolation between the gate structure and the substrate 200. Therefore, the thickness of the gate oxide layer 216 along the normal direction of the substrate 200 surface is 100 angstroms to 280 angstroms.

[0076] The gate structure 218 is used to control the opening and closing of the conductive channel of the semiconductor junction.

[0077] In the semiconductor structure formation process, after the source region and drain region 210 are formed, the gate structure 218 is formed, which can reduce the risk of the gate structure 218 being implanted with doped ions and improve the electrical performance of the gate structure 218.

[0078] In this embodiment, the gate structure 218 is made of polycrystalline silicon.

[0079] Figures 3 to 6 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention.

[0080] refer to Figures 3 to 4 A substrate 100 is provided, in which a first well region 101 is formed, the top surface of the first well region 101 is exposed, and a second well region 102 is also formed in the substrate 100 on the side of the first well region 101, the top surface of the second well region 102 is exposed, and the doping type of the second well region 102 is different from that of the first well region 101.

[0081] Specifically, the substrate 100 provides a platform for the formation process of semiconductor structures.

[0082] As an example, the semiconductor structure is LDMOS (Laterally Diffused Metal-Oxide Semiconductor).

[0083] In this embodiment, taking the formed LDMOS as a planar transistor as an example, the substrate 100 is a planar substrate.

[0084] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be a substrate of other materials such as germanium substrate, silicon germanide substrate, silicon carbide substrate, gallium arsenide substrate, or indium gallium bismuth substrate, and the substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0085] It should be noted that forming the first well region 101 can improve the breakdown resistance of LDMOS. Specifically, when LDMOS is in the working state, a depletion region is formed between the first well region 101 and the subsequently formed source region. This depletion region can disperse the electric field, reduce the risk of electric field concentration in LDMOS, and thus improve the breakdown resistance of LDMOS.

[0086] As an example, the first well region 101 is doped with P-type ions. That is, the first well region 101 is doped with P-type ions.

[0087] Specifically, the first well region 101 is doped with P-type ions. As the operating voltage of the LDMOS gradually increases, the depletion region between the first well region 101 and the subsequently formed source region can move away from the source region, thereby reducing the probability of the accumulated electric field strength damaging the source region.

[0088] As an example, P-type ions include B ions, Ga ions, or In ions.

[0089] It should be noted that forming the second well region 102 can improve the breakdown resistance of LDMOS. Specifically, when LDMOS is in the working state, a depletion region is formed between the second well region 102 and the subsequently formed buffer layer. This depletion region can disperse the electric field, reduce the risk of electric field concentration in LDMOS, and thus improve the breakdown resistance of LDMOS.

[0090] As an example, the second well region 102 is doped with N-type ions. That is, the second well region 102 is doped with N-type ions.

[0091] In this embodiment, the doping type of the second well region 102 is different from the doping type of the first well region 101.

[0092] Specifically, the doping type of the second well region 102 is different from that of the first well region 101, which enables the formation of a PN junction between the second well region 102 and the first well region 101. This helps to improve the breakdown capability of the LDMOS. At the same time, it can also reduce the probability of leakage current between the subsequently formed source and drain regions, and play an electrical isolation role between the source and drain regions.

[0093] As an example, N-type ions include P ions, As ions, or Sb ions.

[0094] In this embodiment, during the step of providing the substrate 100, an isolation structure 104 is also formed in the first well region 101 and the second well region 102, and the top surface of the isolation structure 104 is exposed in the first well region 101 and the second well region 102.

[0095] Specifically, the isolation structure 104 is used to electrically isolate the subsequently formed buffer layer, source region and drain region, which can further reduce the probability of leakage current in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0096] In this embodiment, the step of forming the isolation structure 104 includes: forming an opening in the first well region 101 and the second well region 102; forming an isolation material layer in the opening and on the top of the substrate 100; removing the isolation material layer on the top of the substrate 100, and using the remaining isolation material layer in the opening as the isolation structure 104.

[0097] As an example, the material of the isolation structure 104 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0098] refer to Figure 5One or more buffer layers 106 are formed in the second well region 102 in the longitudinal direction. The doping type of the buffer layer 106 is the same as that of the second well region 102, and the concentration of doped ions in the buffer layer 106 is higher than that in the second well region 102.

[0099] It should be noted that one or more buffer layers 106 are formed in the second well region 102 in the longitudinal direction. The doping type of the buffer layer 106 is the same as that of the second well region 102, and the concentration of doped ions in the buffer layer 106 is higher than that in the second well region 102. After the drain region is formed, it means that a buffer layer 106 is provided between the drain region and the second well region 102. When the semiconductor structure is in a high voltage operating state, since the concentration of doped ions in the buffer layer 106 is higher than that in the second well region 102, a depletion region will be formed between the second well region 102 and the buffer layer 106. The buffer layer 106 can slow down the rate at which the boundary of the depletion region gradually approaches the drain, thereby slowing down the rate at which the depletion region expands in depth. Correspondingly, the rate at which the electric field strength increases at the edge of the depletion region near the drain region is also slowed down, reducing the risk of semiconductor structure breakdown due to excessive electric field strength, and thus improving the robustness of the semiconductor structure.

[0100] In this embodiment, the step of forming the buffer layer 106 includes: doping a portion of the thickness of the second well region 102 to form an ion-doped layer in the second well region 102, and using the ion-doped layer as the buffer layer 106.

[0101] As an example, the process of doping the second well region 102 of a certain thickness includes an ion implantation process.

[0102] It should be noted that the ion implantation process has the characteristics of high ion implantation precision and excellent process controllability. By using the ion implantation process to form the buffer layer 106, the implantation depth of the buffer layer 106 in the substrate 100 can meet the process requirements. At the same time, in the process of forming multiple buffer layers 106, by continuously adjusting the doping dose, the doping ion concentration in each buffer layer 106 can be different.

[0103] In this embodiment, during the step of forming the buffer layer 106, when the number of layers of the buffer layer 106 is multiple, the concentration of doped ions in the buffer layer 106 gradually increases in the direction close to the top surface of the second well region 102.

[0104] Specifically, when the buffer layer 106 has multiple layers, the concentration of doped ions in the buffer layer 106 gradually increases in the direction near the top surface of the second well region 102. This allows for the formation of multiple buffer layers 106 with a gradient distribution of doped ion concentration between the subsequently formed drain region and the second well region 102 below the drain region. Since the concentration of doped ions in the buffer layer 106 is higher than that in the second well region 102, meaning that the closer to the drain region, the higher the concentration of doped ions in the buffer layer 106, the slower the rate at which the depletion region formed between the buffer layer 106 and the second well region 102 approaches the drain region. Consequently, the rate at which the electric field strength increases at the edge of the depletion region near the drain region can be further reduced, thereby reducing the risk of semiconductor structure breakdown due to excessive electric field strength and improving the robustness of the semiconductor structure.

[0105] As an example, such as Figure 5 As shown, a buffer layer 106 is illustrated.

[0106] It should be noted that, in the step of forming the buffer layer 106, the concentration of doped ions in the buffer layer 106 should not be too high or too low. If the concentration of doped ions in the buffer layer 106 is too high, the advance rate of the depletion region may approach 0, causing the device to fail to turn on; if the concentration of doped ions in the buffer layer 106 is too low, it will not achieve the effect of slowing down the advance rate of the depletion region. Therefore, in this embodiment, the concentration range of doped ions in the buffer layer 106 is 5.0 E12 atom / cm³. 3 Up to 1.0E15 atom / cm 3 .

[0107] It should also be noted that the thickness of the buffer layer 106 along the normal direction of the surface of the substrate 100 should not be too large or too small. If the thickness of the buffer layer 106 is too large, given a fixed thickness of the second well region 102, the thickness of the second well region 102 below the buffer layer 106 may be too small. Since the thickness of the second well region 102 is positively correlated with the breakdown voltage capability of the LDMOS, a small thickness of the second well region 102 below the buffer layer 106 will result in a smaller voltage value that the LDMOS can withstand, thus affecting the performance of the LDMOS. If the thickness of the buffer layer 106 is too small, the rate at which the depletion region formed between the buffer layer 106 and the second well region 102 approaches the drain region may not be slowed down, thereby increasing the risk of LDMOS breakdown due to excessive electric field strength, and thus affecting the robustness of the semiconductor structure. Therefore, in this embodiment, the thickness of the buffer layer 106 along the normal direction of the surface of the substrate 100 is 300 angstroms to 2000 angstroms.

[0108] In this embodiment, during the step of forming the buffer layer 106, the buffer layer 106 is located in the second well region 102 between adjacent isolation structures 104.

[0109] Specifically, the buffer layer 106 is located in the second well region 102 between adjacent isolation structures 104, enabling the isolation structure 104 to reduce the probability of doped ions in the buffer layer 106 diffusing in the lateral direction, thereby generating leakage current between the subsequently formed source and drain regions.

[0110] refer to Figure 6 After the buffer layer 106 is formed, a source region 112 is formed in the first well region 101. The doping type of the source region 112 is the same as that of the first well region 101, and the concentration of doped ions in the source region 112 is higher than that in the first well region 101. The top surface of the source region 112 is exposed in the first well region 101.

[0111] Specifically, the source region 112 is used for subsequent electrical connection with external circuit structure, so that the source region 112 serves as an electrode input terminal.

[0112] It should be noted that the concentration of doped ions in the source region 112 is higher than that in the first well region 101, which helps to reduce the contact resistance between the source region 112 and the external circuit structure, and at the same time, it can also improve the current driving capability of the semiconductor structure.

[0113] In this embodiment, the step of forming a source region 112 in the first well region 101 includes: performing a doping process on a portion of the thickness of the first well region 101 to form a first doped layer, and using the first doped layer as the source region 112.

[0114] In this embodiment, during the step of forming the source region 112, the source region 112 is located in the first well region 101 between adjacent isolation structures 104.

[0115] Specifically, the source region 112 is located in the first well region 101 between adjacent isolation structures 104, so that the isolation structure 104 provides electrical isolation to the source region 112, reducing the probability of leakage current between the source region 112 and the subsequently formed drain region.

[0116] Continue to refer to Figure 6 After the buffer layer 106 is formed, a drain region 110 is formed in the second well region 102 above the buffer layer 106. The doping type of the drain region 110 is the same as that of the second well region 102, and the concentration of doped ions in the drain region 110 is higher than that in the second well region 102. The top surface of the second well region 102 is exposed.

[0117] Specifically, the drain region 110 is used to electrically connect with an external circuit structure, so that the drain region 110 serves as an electrode output terminal.

[0118] It should be noted that the concentration of doped ions in the drain region 110 is higher than that in the second well region 102, which helps to reduce the contact resistance between the drain region 110 and the external circuit structure, and at the same time, it can also improve the current driving capability of the semiconductor structure.

[0119] It should also be noted that, as an example, the source region 112 is formed first, followed by the drain region 110. In other embodiments, the drain region may be formed first, followed by the source region.

[0120] In this embodiment, the step of forming a drain region 110 in the second well region 102 includes: performing a doping process on the second well region 102 above the buffer layer 106 to form a second doped layer, and using the second doped layer as the drain region 110.

[0121] As an example, in the step of forming the drain region 110, the drain region 110 is located in the second well region 102 between adjacent isolation structures 104.

[0122] Specifically, the drain region 110 is located in the second well region 102 between adjacent isolation structures 104, so that the isolation structure 104 provides electrical isolation to the drain region 110, reducing the probability of leakage current between the drain region 110 and the source region 112.

[0123] refer to Figure 7 A gate oxide layer 116 is formed on top of the substrate 100 at the junction of the first well region 101 and the second well region 102.

[0124] Specifically, the gate oxide layer 116 can filter out most of the weak mixed current and reduce the parameters of the device, thereby enhancing the performance and reliability of the semiconductor structure.

[0125] In this embodiment, the process of forming the gate oxide layer 116 includes a local oxidation of silicon (LOCOS) process. During the local oxidation process, O2 diffuses in all directions and reacts with the substrate 100 to form silicon oxide.

[0126] As an example, the material of the gate oxide layer 116 includes silicon oxide.

[0127] It should be noted that the thickness of the gate oxide layer 116 along the normal direction of the surface of the substrate 100 should not be too large or too small. If the thickness of the gate oxide layer 116 is too large, it can easily lead to an increase in the device turn-on voltage of the semiconductor structure; if the thickness of the gate oxide layer 116 is too small, it can easily affect the electrical isolation between the subsequently formed gate structure and the substrate 100. Therefore, the thickness of the gate oxide layer 116 along the normal direction of the surface of the substrate 100 is 100 angstroms to 280 angstroms.

[0128] refer to Figure 8 After the source region 112 and the drain region 110 are formed, a gate structure 118 is formed on top of the substrate 100 at the junction of the first well region 101 and the second well region 102.

[0129] The gate structure 118 is used to control the opening and closing of the conductive channel of the semiconductor junction.

[0130] It should be noted that after forming the source region 112 and the drain region 110, the gate structure 118 is formed, which can reduce the risk of the gate structure 118 being implanted with doped ions and improve the electrical performance of the gate structure 118.

[0131] In this embodiment, the gate structure 118 is made of polycrystalline silicon.

[0132] Since a gate oxide layer 116 is formed on the top of the substrate 100 at the junction of the first well region 101 and the second well region 102, the gate structure 118 also covers the top surface of the gate oxide layer 116 during the formation of the gate structure 118.

[0133] As an example, the steps of forming the gate structure 118 include: forming a gate material layer (not shown) covering the top of the first well region 101, the second well region 102 and the substrate 100; patterning the gate material layer, retaining the gate material layer on top of the substrate 100 at the junction of the first well region 101 and the second well region 102, and using the gate material layer on top of the substrate 100 at the junction of the first well region 101 and the second well region 102 as the gate structure 118.

[0134] In this embodiment, the gate material layer is patterned using a dry etching process.

[0135] Specifically, patterning the gate material layer using a dry etching process can effectively improve the sidewall morphology quality of the gate structure 118.

[0136] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A first well region is located in the substrate, with the top surface of the first well region exposed above the substrate. The second well region is located in the substrate on the side of the first well region, and the substrate exposes the top surface of the second well region. The doping type of the second well region is different from that of the first well region. One or more buffer layers are located in the second well region and stacked in the longitudinal direction. The doping type of the buffer layer is the same as that of the second well region, and the concentration of doped ions in the buffer layer is higher than that in the second well region. A source region is located in the first well region. The doping type of the source region is the same as that of the first well region, and the concentration of doped ions in the source region is higher than that in the first well region. The top surface of the first well region is exposed. A drain region is located in the second well region. The doping type of the drain region is the same as that of the second well region, and the concentration of doped ions in the drain region is higher than that in the second well region. The top surface of the second well region is exposed. The gate structure is located on top of the substrate at the junction of the first and second well regions.

2. The semiconductor structure as described in claim 1, characterized in that, When the buffer layer has multiple layers, the concentration of doped ions in the buffer layer gradually increases in the direction close to the top surface of the second well region.

3. The semiconductor structure as described in claim 1, characterized in that, The thickness of the buffer layer is 300 angstroms to 2000 angstroms along the normal direction of the substrate surface.

4. The semiconductor structure as described in claim 1, characterized in that, The concentration of doped ions in the buffer layer ranges from 5.0 E12 atom / cm³. 3 Up to 1.0E15 atom / cm 3 .

5. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: an isolation structure located in the first well region and the second well region, wherein the first well region and the second well region expose the top surface of the isolation structure; The buffer layer is located in a second well region between adjacent isolation structures; The source region is located in the first well region between adjacent isolation structures; The leak region is located in the second well region between adjacent isolation structures.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a gate oxide layer located on top of the substrate at the junction of the first well region and the second well region, and the gate structure covers the top surface of the gate oxide layer.

7. The semiconductor structure as described in claim 6, characterized in that, The thickness of the gate oxide layer is 100 angstroms to 280 angstroms along the normal direction of the substrate surface.

8. The semiconductor structure as described in claim 1, characterized in that, The first well region is p-type doped. The second well region is N-type doped.

9. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided in which a first well region is formed, the substrate exposing the top surface of the first well region, and a second well region is also formed in the substrate on the side of the first well region, the substrate exposing the top surface of the second well region, and the doping type of the second well region is different from that of the first well region; One or more buffer layers are formed in the second well region in a longitudinal direction, wherein the doping type of the buffer layer is the same as that of the second well region, and the concentration of doped ions in the buffer layer is higher than that in the second well region. After the buffer layer is formed, a source region is formed in the first well region. The doping type of the source region is the same as that of the first well region, and the concentration of doped ions in the source region is higher than that in the first well region. The top surface of the source region is exposed in the first well region. After the buffer layer is formed, a drain region is formed in the second well region above the buffer layer. The doping type of the drain region is the same as that of the second well region, and the concentration of doped ions in the drain region is higher than that in the second well region. The second well region exposes the top surface of the drain region. After the source region and drain region are formed, a gate structure is formed on top of the substrate at the junction of the first well region and the second well region.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the buffer layer, when the number of layers of the buffer layer is multi-layered, the concentration of doped ions in the buffer layer gradually increases in the direction close to the top surface of the second well region.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming the buffer layer includes: doping a portion of the thickness of the second well region to form an ion-doped layer in the second well region, and using the ion-doped layer as the buffer layer.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process of doping the second well region of a certain thickness includes an ion implantation process.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, The thickness of the buffer layer is 300 angstroms to 2000 angstroms along the normal direction of the substrate surface.

14. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the buffer layer, the concentration of doped ions in the buffer layer is in the range of 5.0 E12 atom / cm³. 3 Up to 1.0E15 atom / cm 3 .

15. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of providing the substrate, an isolation structure is also formed in the first well region and the second well region, with the top surface of the isolation structure exposed in the first well region and the second well region. In the step of forming the buffer layer, the buffer layer is located in a second well region between adjacent isolation structures; In the step of forming the source region, the source region is located in a first well region between adjacent isolation structures; In the step of forming the leak region, the leak region is located in a second well region between adjacent isolation structures.

16. The method for forming a semiconductor structure as described in claim 9, characterized in that, After forming the source region and drain region and before forming the gate structure, the method further includes: forming a gate oxide layer on top of the substrate at the junction of the first well region and the second well region; In the step of forming the gate structure, the gate structure covers the top surface of the gate oxide layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The thickness of the gate oxide layer is 100 angstroms to 280 angstroms along the normal direction of the substrate surface.

18. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first well region is p-type doped. The second well region is N-type doped.

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