IGZO-based multi-electrode nonlinear device, preparation method and chip

Abstract

The invention relates to an IGZO (Indium Gallium Zinc Oxide)-based multi-electrode nonlinear device, a preparation method and a chip, belongs to the technical field of semiconductors, and solves at least one of the problems of over-low temperature, difficulty in industrial application, over-high cost, tedious process, low yield and the like of a traditional single device for realizing Boolean logic. An IGZO-based multi-electrode nonlinear device comprises a substrate, a back gate, a back gate dielectric layer, an IGZO channel layer, a plurality of electrodes and a plurality of connecting lines. According to the invention, the nonlinear characteristic and the Boolean logic function of a single device can be realized at room temperature, the process complexity and the cost of nonlinear device preparation are reduced, and the yield of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a multi-electrode nonlinear device based on IGZO, its fabrication method, and a chip. Background Technology

[0002] Since the invention of the transistor and the introduction of Moore's Law, the number of transistors integrated on a single chip has increased dramatically. However, as the miniaturization of device manufacturing processes has slowed, starting with process nodes below 28nm, transistor feature sizes are no longer used for naming; instead, performance equivalence is more important. Researchers have not stopped exploring miniaturization technologies, including FinFETs, GAA, CAA, and 3D packaging, all methods to increase integration density. Another method under exploration to increase device integration density is to realize single-device Boolean logic through the transport characteristics of a single transistor, thereby increasing chip integration density. Currently, methods to achieve single-device Boolean logic have been implemented at extremely low temperatures, even down to 0.3K. However, such stringent conditions face significant obstacles in practical applications, especially in large-scale chip manufacturing where they are almost impossible to achieve. Summary of the Invention

[0003] Based on the above analysis, the present invention aims to provide a multi-electrode nonlinear device, fabrication method and chip based on IGZO, to solve at least one of the following problems: the temperature for implementing Boolean logic in traditional single devices is too low, making it difficult to industrialize and apply, as well as the cost is too high, the process is cumbersome and the yield is low.

[0004] The objective of this invention is achieved through the following technical solution:

[0005] This invention provides a multi-electrode nonlinear device based on IGZO, comprising: a substrate, a back gate, a back gate dielectric layer, an IGZO channel layer, multiple electrodes, and several interconnects;

[0006] The back gate is disposed on the substrate, and the bottom surface of the back gate is in contact with the top surface of the substrate;

[0007] The back gate dielectric layer covers the top surface and all sides of the back gate;

[0008] The IGZO channel layer is located on the back gate dielectric layer, the bottom surface of the IGZO channel layer is in contact with the top surface of the back gate dielectric layer, the IGZO channel layer is correspondingly arranged with the back gate, and the projection of the IGZO channel layer in the vertical direction is completely within the projection of the back gate in the vertical direction.

[0009] The plurality of electrodes are dispersed on the substrate and spaced apart from the back gate and the IGZO channel layer. The plurality of electrodes include two types: a first electrode and a second electrode. The plurality of interconnects also include two types: a first interconnect and a second interconnect. The first electrode is made of the same material as the back gate and is electrically connected to the back gate through the first interconnect. The second electrode is electrically connected to the IGZO channel layer through the second interconnect. The back gate dielectric layer covers the top and side surfaces of the first interconnect.

[0010] Part or all of the top surface of each electrode is exposed, and the plurality of connecting lines do not contact each other.

[0011] Furthermore, the thickness of the IGZO channel layer is ≤5nm.

[0012] Furthermore, the first connecting line is made of the same material as the back grille; and / or,

[0013] The bottom surfaces of the first electrode and the first connecting line are in contact with the top surface of the substrate, and the top surfaces of the first electrode, the first connecting line, and the back gate are flush.

[0014] Furthermore, the second connection line has a main body and an end portion extending toward the IGZO channel layer, wherein the bottom surface of the main body contacts the top surface of the back gate dielectric layer, and the bottom surface of the end portion contacts the top surface of the IGZO channel layer to form an electrical connection; and / or,

[0015] The bottom surface of the second electrode is in contact with the top surface of the back gate dielectric layer.

[0016] Furthermore, the nonlinear device also includes a protective layer that covers the top and side surfaces of the second connection line, the top and side surfaces of the IGZO channel layer, and the top surface of the back gate dielectric layer.

[0017] Furthermore, the vertical projections of the first connecting line and the adjacent second connecting line have an overlapping area, which extends from the periphery of the back gate to the inside of the IGZO channel layer.

[0018] Furthermore, the width of the second connection line decreases from the second electrode in the direction of extension of the IGZO channel layer.

[0019] This invention provides a method for fabricating a multi-electrode nonlinear device, used to fabricate the aforementioned IGZO-based multi-electrode nonlinear device, comprising:

[0020] Step 1: Fabricate a patterned back gate, a first electrode, and a first interconnect on a substrate; there is a gap between the first electrode and the back gate, and the first electrode is connected to the back gate through the first interconnect;

[0021] Step 2: Fabricate a back gate dielectric layer in the top region of the patterned back gate, first electrode, first interconnect line and substrate; fabricate an IGZO channel layer in the top region of the back gate dielectric layer and at the position corresponding to the back gate;

[0022] Step 3: A patterned second electrode and a second connecting line are fabricated in the top region of the back gate dielectric layer. There is a gap between the second electrode and the IGZO channel layer. The second electrode is connected to the IGZO channel layer through the second connecting line.

[0023] Furthermore, in step 2, after the back gate dielectric layer is prepared, the chamber is not opened, and the IGZO channel layer is prepared.

[0024] The present invention provides a chip, including the IGZO-based multi-electrode nonlinear device or the IGZO-based multi-electrode nonlinear device obtained by the fabrication method described above.

[0025] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0026] (1) This invention proposes a multi-electrode nonlinear device that realizes nonlinear transport at room temperature. Compared with the previous transistors that realize single-device Boolean logic at ultra-low temperature, this invention mainly uses IGZO as the channel layer to realize nonlinear IV transport at room temperature. That is, this invention can realize the nonlinear characteristics and Boolean logic function of a single device at room temperature.

[0027] (2) In some preferred embodiments, by designing and controlling the structure and dimensions of the multi-electrode, back gate, and IGZO channel layers, as well as the wiring regions between them, the nonlinear transfer characteristics of the nonlinear device can be enhanced, further improving its sensitivity to input signals, thereby enabling faster and more accurate Boolean logic operations. Furthermore, the optimized spatial layout allows for higher integration within a limited area, supporting complex logic functions. These improvements not only enhance the performance of the nonlinear device in implementing Boolean logic functions but also strengthen its reliability and reconfigurability in practical applications.

[0028] (3) This invention proposes a method for fabricating IGZO thin-film transistors with nonlinear transport at room temperature. Compared with traditional methods for manufacturing single-device Boolean logic transistors at ultra-low temperatures, this invention has significant advantages in terms of raw material cost, process complexity, equipment cost, performance stability, and industrial applicability. This invention uses relatively inexpensive and readily available IGZO materials, avoiding the use of expensive precious metals (such as gold nanoparticles) and complex organic molecules (such as octylthiol molecules) in traditional processes, thereby significantly reducing raw material costs and minimizing environmental impact. Furthermore, the process flow of this invention is simple, eliminating the need for complex steps such as multiple thermal oxidation, ion implantation, and rapid annealing, significantly reducing process complexity, control difficulty, and cost, improving device yield, production efficiency, and performance stability.

[0029] In this invention, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this invention will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing the invention. The objects and other advantages of this invention can be realized and obtained from what is particularly pointed out in the description and drawings. Attached Figure Description

[0030] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts.

[0031] Figure 1 The diagram shows the structural steps of the fabrication method of the IGZO-based multi-electrode nonlinear device according to an embodiment of the present invention. Figure 1 In this diagram, (a) is a top view and (b) is a cross-sectional view of section A-A' in (a).

[0032] Figure 2 The diagram shows the structural steps of the fabrication method of the IGZO-based multi-electrode nonlinear device according to an embodiment of the present invention. Figure 2 Among them, (a) is a top view and (b) is a cross-sectional view of section B-B' in (a);

[0033] Figure 3 The diagram shows the structural steps of the fabrication method of the IGZO-based multi-electrode nonlinear device according to an embodiment of the present invention. Figure 3 Among them, (a) is a top view and (b) is a cross-sectional view of section C-C' in (a);

[0034] Figure 4 The diagram shows the structural steps of the fabrication method of the IGZO-based multi-electrode nonlinear device according to an embodiment of the present invention. Figure 4In this diagram, (a) is a top view and (b) is a cross-sectional view of section D-D' in (a).

[0035] Figure 5 The diagram shows the structural steps of the fabrication method of the IGZO-based multi-electrode nonlinear device according to an embodiment of the present invention. Figure 5 Among them, (a) is a top view and (b) is a cross-sectional view of section E-E' in (a);

[0036] Figure 6 The diagram shows the structural steps of the fabrication method of the IGZO-based multi-electrode nonlinear device according to an embodiment of the present invention. Figure 6 Among them, (a) is a top view and (b) is a cross-sectional view of section F-F' in (a);

[0037] Figure 7 This is a top view of the multi-electrode nonlinear device based on IGZO according to an embodiment of the present invention, wherein (a) is a top view of the multi-electrode nonlinear device; (b) is an enlarged view of part A in (a); and (c) is an enlarged view of part B in (b).

[0038] Figure 8 for Figure 7 Enlarged structural diagram of section A in the middle;

[0039] Figure 9 for Figure 7 Enlarged structural diagram of section B Figure 1 ;

[0040] Figure 10 for Figure 7 Enlarged structural diagram of section B Figure 2 ;

[0041] Figure 11 for Figure 7 Enlarged structural diagram of section B Figure 3 ;

[0042] Figure 12 The output IV characteristic curve of the IGZO-based multi-electrode nonlinear device in Embodiment 1 of the present invention is shown at room temperature.

[0043] Figure label:

[0044] 1-Substrate; 2-Back gate; 3-Back gate dielectric layer; 4-IGZO channel layer; 51-First electrode; 52-Second electrode; 61-First interconnect line; 61a-First wide interconnect segment; 61b-First narrow interconnect segment; 62-Second interconnect line; 62a-Second wide interconnect segment; 62b-Second intermediate transition segment; 62c-Second narrow interconnect segment; 7-Protective layer. Detailed Implementation

[0045] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings, which form part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not intended to limit the scope of the present invention.

[0046] Single-device Boolean logic is a method that attempts to implement logical operations in a single transistor. In traditional digital circuits, basic logical operations (Boolean logic such as AND, OR, and NOT) are typically implemented using combinations of multiple transistors. For example, a simple AND gate may require two or more transistors to work together to make a logical decision. Single-device Boolean logic, on the other hand, aims to allow a single transistor to output a result that conforms to the rules of Boolean logic operations based on the state of the input electrical signal (such as different combinations of voltage or current). This is akin to integrating a small logic decision system into a single transistor, thereby reducing the number of transistors required to implement logical functions.

[0047] Existing research has explored some theoretical aspects of realizing Boolean logic in single-device applications. For example, key structures constructed using gold nanoparticles with octylthiol molecules for insulation and isolation require ultra-low temperatures (0.3 K) to achieve IV nonlinearity, and the fabrication process and raw materials are extremely demanding, making practical applications difficult and resulting in low yields. Furthermore, doping silicon substrates with boron atoms at a gradient concentration through multiple thermal oxidation processes, ion implantation, and rapid annealing also faces challenges, requiring extremely low temperatures (77 K) to achieve single-device IV nonlinearity, and requiring precise control of the doping concentration. This leads to high process complexity and problems such as low yields and unstable performance.

[0048] In view of the above problems, in a first aspect, the present invention provides a multi-electrode nonlinear device based on IGZO, comprising: a substrate 1, a back gate 2, a back gate dielectric layer 3, an IGZO channel layer 4, multiple electrodes, and several interconnecting lines.

[0049] The back gate is disposed on the substrate, and the bottom surface of the back gate is in contact with the top surface of the substrate;

[0050] The back gate dielectric layer covers the top surface and all sides of the back gate;

[0051] The IGZO channel layer is located on the back gate dielectric layer, the bottom surface of the IGZO channel layer is in contact with the top surface of the back gate dielectric layer, the IGZO channel layer is correspondingly arranged with the back gate, and the projection of the IGZO channel layer in the vertical direction is completely within the projection of the back gate in the vertical direction.

[0052] The plurality of electrodes are dispersed on the substrate and spaced apart from the back gate and the IGZO channel layer. The plurality of electrodes include two types: a first electrode 51 and a second electrode 52. The plurality of connecting lines include two types: a first connecting line 61 and a second connecting line 62. The first electrode is made of the same material as the back gate and is electrically connected to the back gate through the first connecting line. The second electrode is electrically connected to the IGZO channel layer through the second connecting line. The back gate dielectric layer covers the top and side surfaces of the first connecting line.

[0053] Part or all of the top surface of each electrode is exposed, and the plurality of connecting lines do not contact each other.

[0054] Compared with the prior art, the present invention proposes a method for fabricating IGZO thin film transistors that realize nonlinear transport at room temperature. Compared with the previous method of realizing single-device Boolean logic at low temperature, the present invention mainly uses IGZO thin film as channel layer to realize nonlinear IV transport at room temperature.

[0055] This invention utilizes IGZO (indium gallium zinc oxide) to achieve nonlinear transport characteristics and Boolean logic functions at room temperature, primarily based on the percolation transport mechanism of IGZO material. IGZO is a wide-bandgap semiconductor material. The inventors discovered that the non-uniformity of its internal elemental distribution and the undulating band structure in different regions lead to inconsistent electron concentrations, thereby inducing percolation transport phenomena. In the IGZO channel layer, the non-uniform distribution of electron concentration causes electrons to form percolation paths, and the percolation threshold P... C The percolation threshold is inversely proportional to the thickness L of the IGZO channel layer. A thicker IGZO layer creates more 3D transport paths, resulting in a lower percolation threshold and less pronounced percolation. This invention significantly increases the percolation threshold by thinning the IGZO channel layer, making the percolation phenomenon more obvious. This allows for the control of the device's current-voltage characteristics by varying the voltage applied to the control electrode. In simpler terms, by thinning the IGZO channel layer, a modulated nonlinear IV characteristic curve is achieved.

[0056] In some embodiments, the thickness of the IGZO channel layer is ≤5nm. Based on the above principle, the thinner the IGZO semiconductor, the more pronounced the percolation phenomenon, but its mobility also decreases, so thinner is not necessarily better. Exemplarily, the thickness of the IGZO channel layer is 0.5nm, 1.0nm, 1.5nm, 2.0nm, 2.5nm, 3.0nm, 3.5nm, 4.0nm, 4.5nm, or 5.0nm. Preferably, the thickness of the IGZO channel layer is 1.5 to 3.0nm.

[0057] As you can understand, IGZO is an abbreviation for Indium Gallium Zinc Oxide, which is composed of indium (In), gallium (Ga), zinc (Zn), and oxygen (O).

[0058] For example, the substrate is made of silicon oxide.

[0059] For example, the first electrode is made of the same material as the back gate, selected from at least one of Mo, Ir, Pt, and TiN.

[0060] For example, the material of the first connecting wire is selected from at least one of Mo, Ir, Pt, and TiN.

[0061] For example, the material of the second connecting line and the second electrode is selected from at least one of Ni, Au, Ti, Pt, and Al.

[0062] For example, the second connecting line and the second electrode are made of the same material, for example, composed of an Au layer and a Ni layer.

[0063] For example, the thickness of the Au layer is 10-50 nm, such as 10 nm, 20 nm, 30 nm, 40 nm, or 50 nm. The thickness of the Ni layer is 5-10 nm, such as 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, or 10 nm. The thickness ratio of the Ni layer to the Au layer is 0.2 to 1.0. The Ni layer is used as the bottom layer, and the Au layer is used as the top layer; that is, the Ni layer is closer to the substrate than the Au layer.

[0064] For example, the thickness of the back gate is 10-30 nm; for example, 15-25 nm.

[0065] In some embodiments, the first connecting line is made of the same material as the back gate.

[0066] In some embodiments, the bottom surfaces of the first electrode and the first connection line are in contact with the top surface of the substrate, and the top surfaces of the first electrode, the first connection line, and the back gate are flush.

[0067] In some embodiments, the second connection line has a body portion and an end portion extending toward the IGZO channel layer, wherein the bottom surface of the body portion contacts the top surface of the back gate dielectric layer, and the bottom surface of the end portion contacts the top surface of the IGZO channel layer to form an electrical connection.

[0068] In some embodiments, the bottom surface of the second electrode is in contact with the top surface of the back gate dielectric layer.

[0069] In some embodiments, the nonlinear device further includes a protective layer 7 covering the top and side surfaces of the second connection line, the top and side surfaces of the IGZO channel layer, and the top surface of the back gate dielectric layer.

[0070] For example, the side of the back gate dielectric layer is flush with the side of the substrate.

[0071] For example, the side of the protective layer is flush with the side of the substrate.

[0072] For example, the material of the back gate dielectric layer and the material of the protective layer are at least one of aluminum oxide (AlOx), silicon dioxide (SiO2), hafnium oxide (HfO2), and zirconium oxide (ZrO2).

[0073] For example, the thickness of the back gate dielectric layer and the thickness of the protective layer are 20-40 nm; for example, 25-35 nm.

[0074] In some embodiments, the vertical projection of the first connection line 61 on the substrate at least partially overlaps with the vertical projection of the second connection line 62 on the substrate, and the first connection line 61 and the second connection line 62 are isolated by a back gate dielectric layer to ensure that they do not physically contact each other. This structural design achieves both electrical isolation between the connection lines and optimizes space utilization through projection overlap, thereby improving integration.

[0075] For example, the vertical projections of the first connection line 61 and the adjacent second connection line 62 have an overlapping area, which extends from the periphery of the back gate to the inside of the IGZO channel layer.

[0076] In some embodiments, the width of the first connection line 61 decreases from the first electrode in the direction of extension to the back gate.

[0077] For example, the first connection line 61 includes a first wide connection segment 61a and a first narrow connection segment 61b; the first wide connection segment 61a is close to the first electrode, and the first narrow connection segment 61b is close to the back gate 2. The first wide connection segment 61a is wider and is used for stable connection and current transmission; the first narrow connection segment 61b is narrower and is used for electrical connection with the back gate 2.

[0078] For example, the first connecting line 61 makes partial contact with the back gate 2 to achieve electrical connection. For instance, when the first connecting line is flush with the top of the back gate, the end of the first connecting line near the back gate contacts the side of the back gate to achieve electrical connection.

[0079] In some embodiments, the width of the second connection line 62 decreases from the second electrode in the direction of extension to the IGZO channel layer.

[0080] For example, the second connection line 62 includes a second wide connection section 62a, a second intermediate transition section 62b, and a second narrow connection section 62c; wherein, the second wide connection section 62a is close to the second electrode and has a wider width, which is used for stable connection and current transmission; the second intermediate transition section 62b is located between the second wide connection section and the second narrow connection section, and the second narrow connection section is close to the IGZO channel layer and has a narrower width, which is used for local electrical connection with the channel layer.

[0081] For example, the first connecting line and the second connecting line have uniform widths on a cross section perpendicular to their extension direction. In this case, the width of the connecting line is defined as the widest distance measured at the center of the connecting line along a cross section perpendicular to its extension direction.

[0082] For example, the width of the first wide connecting segment 61a is W1, and the width of the first narrow connecting segment 61b is W2, satisfying W1 > W2. Preferably, W2 / W1 is K1 to K2, where K1 ≤ K2.

[0083] Preferably, in the embodiments of the present invention, K1 and K2 each independently take values ​​such as 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, and 0.99.

[0084] For example, the width of the second wide connecting segment 62a is W3, the width of the second intermediate transition segment 62b is W4, and the width of the second narrow connecting segment 62c is W5, satisfying W3 > W4 > W5. Preferably, W4 / W3 is K1 to K2, K1 ≤ K2; and / or, W5 / W4 is K1 to K2, K1 ≤ K2.

[0085] In one embodiment, the first connection line 61 and the adjacent second connection line 62 have a partial overlap region in a direction perpendicular to the substrate. Specifically, the overlap region extends from the periphery of the back gate to the interior of the IGZO channel layer, starting from the transition between the first wide connection segment 61a and the first narrow connection segment 61b of the first connection line 61, where the vertical projections of the wide segments of the first connection line 61 and the second connection line 62 begin to overlap.

[0086] Preferably, the overlapping regions satisfy at least one of the following conditions:

[0087] The vertical projection of the first narrow connecting segment 61b of the first connecting line 61 falls completely within the vertical projection range of the second wide connecting segment 62a; for example, W2 / W3 is K1~K2, K1≤K2.

[0088] The vertical projections of the second intermediate transition segment 62b and the second narrow connecting segment 62c of the second connecting line 62 fall entirely within the vertical projection range of the first narrow connecting segment 61b of the first connecting line 61.

[0089] For example, at least one of the first wide connecting segment 61a, the first narrow connecting segment 61b, the second wide connecting segment 62a, the second intermediate transition segment 62b, and the second narrow connecting segment 62c has a constant cross-sectional width along the extension direction.

[0090] Preferably, the width of the first wide connecting segment 61a in all the first connecting lines is the same. The width of the first narrow connecting segment 61b in all the first connecting lines is the same. The width of the second wide connecting segment 62a in all the second connecting lines is the same. The width of the second intermediate transition segment 62b in all the second connecting lines is the same. The width of the second narrow connecting segment 62c in all the second connecting lines is the same. Through the above width control, not only is the processing difficulty reduced, the current distribution optimized, the local temperature rise reduced, the stress concentration reduced, and the device lifespan improved, but the logic operation performance is also significantly optimized, making it more reliable and efficient in practical applications.

[0091] By optimizing the structure of the multi-electrode, back-gate, and IGZO channel layers, as well as the wiring area between them, the nonlinear transfer characteristics of the nonlinear devices can be enhanced, further improving their sensitivity to input signals and enabling faster and more accurate Boolean logic operations. Simultaneously, the isolation provided by the back-gate dielectric layer effectively prevents electrical interference between interconnects, reduces parasitic effects, and ensures stable operation of the logic gates. Furthermore, the optimized spatial layout allows for higher integration density within a limited area, supporting complex logic functions. These improvements not only enhance the performance of nonlinear devices in implementing Boolean logic functions but also strengthen their reliability and reconfigurability in practical applications.

[0092] In this embodiment of the invention, the IGZO channel layer is correspondingly disposed with respect to the back gate, and the vertical projection of the IGZO channel layer is completely within the vertical projection of the back gate. Specifically, the ratio of the minimum size of the IGZO channel layer in the horizontal direction to the maximum size of the back gate in the horizontal direction is not less than 0.2. This ensures that the IGZO channel layer is completely covered by the back gate in the vertical direction, while having sufficient size in the horizontal direction to achieve good electric field control, further enhancing the nonlinear transmission characteristics of the nonlinear device, improving the switching ratio and sensitivity, and improving the performance, reliability, and reconfigurability of the device when implementing Boolean logic functions.

[0093] For example, the IGZO channel layer is circular, the back gate is circular, and the diameter D1 of the IGZO channel layer and the diameter D2 of the back gate satisfy: D1 / D2 is K1~K2, K1≤K2.

[0094] For example, the ratio of the contact area length L0 between the second connection line and the IGZO channel layer to the radius R1 of the IGZO channel layer satisfies: L0 / R1 ≥ 0.2, where R1 = D1 / 2. Further, L0 / R1 is between 0.2 and 0.8. For example, L0 / R1 is 0.4 or 0.6. By controlling the L0 / R1 value, the conduction characteristics, switching ratio, threshold consistency, and reliability of the nonlinear device can be better synchronized and optimized.

[0095] For example, the included angle θ between all the second connecting lines near the end of the IGZO channel layer, such as the second narrow connecting segments, is not less than 30°, for example, between 30° and 90°. Examples include 30°, 40°, 45°, and 60°; preferably 30° to 60°. Preferably, the included angle between all the second connecting lines near the end of the IGZO channel layer, such as the third narrow connecting segments, is equal.

[0096] It is understandable that near the IGZO channel layer, when the included angle is too large, the distance between the ends of multiple second connection lines is too far, the electric field coupling between the second connection lines and the IGZO channel layer is weakened, resulting in a decrease in the back gate's ability to control the electric field of the IGZO channel layer, thereby reducing the device's switching ratio and nonlinear characteristics. When the included angle is too small, the distance between the ends of multiple second connection lines is too close, which can easily lead to electrical interference and affect the reliability and stability of the logic operation performance of nonlinear devices.

[0097] For example, there are 8 second electrodes and 2 first electrodes. The 10 electrodes are evenly distributed on both sides of the back gate and the IGZO channel layer, forming an axisymmetric structure. Specifically, 5 second electrodes are distributed on one side, and 3 second electrodes and 2 first electrodes are distributed above and below the 3 second electrodes on the other side. This layout ensures a uniform electric field distribution between the IGZO channel layer and the back gate, reducing electrical interference and parasitic effects caused by asymmetrical electrode positions. It is also easier to implement during design and manufacturing. This axisymmetric electrode distribution not only optimizes carrier transport paths, improves Boolean logic performance, and increases device integration, but also enhances the device's thermal stability and reliability.

[0098] In a second aspect, the present invention provides a method for fabricating a multi-electrode nonlinear device, used to fabricate the IGZO-based multi-electrode nonlinear device as described in the first aspect, comprising:

[0099] Step 1: Fabricate a patterned back gate, a first electrode, and a first interconnect on a substrate; there is a gap between the first electrode and the back gate, and the first electrode is connected to the back gate through the first interconnect;

[0100] Step 2: Fabricate a back gate dielectric layer in the top region of the patterned back gate, first electrode, first interconnect line and substrate; fabricate an IGZO channel layer in the top region of the back gate dielectric layer and at the position corresponding to the back gate;

[0101] Step 3: A patterned second electrode and a second connecting line are fabricated in the top region of the back gate dielectric layer. There is a gap between the second electrode and the IGZO channel layer. The second electrode is connected to the IGZO channel layer through the second connecting line.

[0102] In some embodiments, the thickness of the back gate is 10-30 nm; exemplaryly, the thickness of the back gate is 10 nm, 15 nm, 20 nm, 25 nm, or 30 nm. Preferably, it is 15-25 nm.

[0103] In some embodiments, in step 1, a patterned back gate, a first electrode, and a first interconnect are fabricated on a substrate using a magnetron sputtering process. The magnetron sputtering process parameters include: gas: argon; gas flow rate: 20 sccm to 30 sccm, gas pressure: 0.1 Pa to 1 Pa; sputtering power: DC 40 W to 60 W; and substrate temperature: room temperature.

[0104] Preferably, in step 2, after the back gate dielectric layer is fabricated, the chamber is not opened, and the IGZO channel layer is fabricated. This fabrication method can reduce impurity contamination and interface state density, thereby improving the mobility of the IGZO channel layer, reducing leakage current, and increasing the on / off ratio, thus accelerating the switching speed of logic gates and improving signal integrity. High-quality interfaces and clean thin films help reduce threshold voltage drift and reduce the dispersion of electrical parameters, thereby enhancing the reliability and consistency of logic circuits. In addition, low leakage current and high mobility can also reduce the static and dynamic power consumption of logic circuits.

[0105] In some embodiments, in step 2, a back gate dielectric layer and an IGZO channel layer are deposited on the top region of the patterned back gate, the first electrode, the first interconnect, and the substrate by atomic layer deposition (ALD).

[0106] In one embodiment, atomic layer deposition is performed at 200–250°C. Exemplarily, the atomic layer deposition temperature is 200°C, 210°C, 220°C, 230°C, 240°C, or 250°C.

[0107] In one embodiment, the thickness of the back gate dielectric layer is 20-40 nm. Exemplarily, the thickness of the back gate dielectric layer is 20 nm, 25 nm, 30 nm, 35 nm, or 40 nm.

[0108] In one embodiment, the thickness of the IGZO channel layer is 0.5-7nm; exemplaryly, the thickness of the IGZO channel layer is 0.5nm, 1.0nm, 2.0nm, 3.0nm, 4.0nm, 5.0nm, or 6.0nm. Preferably, the thickness of the IGZO channel layer is 0.5-5nm.

[0109] In one embodiment, the parameters for atomic layer deposition during the deposition of the back gate dielectric layer include: precursor pulse time of 150ms-200ms and precursor gas flow rate of 250-300sccm; inert gas (e.g., N2) pulse time of 3s-4s and inert gas flow rate of 50-100sccm; and reactant gas (e.g., O3) pulse time of 1s-2s and reactant gas flow rate of 80-150sccm.

[0110] In one embodiment, the atomic layer deposition parameters during the deposition of the IGZO channel layer include: precursor pulse time of 150ms-600ms and precursor gas flow rate of 250-300sccm; inert gas (e.g., N2) pulse time of 3s-4s and inert gas flow rate of 50-100sccm; and reactant gas (e.g., O3) pulse time of 1s-6s and reactant gas flow rate of 80-150sccm.

[0111] It is understood that IGZO thin films are formed by alternating the introduction of precursors and reactive gases of different elements (such as In, Ga, and Zn) to deposit layer by layer. Preferably, the pulse time for the In and Ga precursors is 150ms-200ms; the pulse time for the Zn precursor is 450ms-600ms. Preferably, the pulse time for the reactive gases of In and Zn is 1s-2s, and the pulse time for the Ga reactive gas is 5s-6s.

[0112] In some embodiments, after depositing the IGZO channel layer, the active region pattern is defined by optical lithography, then the IGZO channel layer is patterned by wet etching, and finally the photoresist is removed to complete the active region fabrication.

[0113] In one embodiment, the resolution of the optical lithography is 500nm-2μm. The thickness of the photoresist used in the optical lithography is 5μm-50μm. Exemplarily, the resolutions are 500nm, 800nm, 1μm, and 2μm. The photoresist thicknesses are 5μm, 10μm, 20μm, 30μm, 40μm, and 50μm.

[0114] In one embodiment, the parameters of the optical lithography include: photoresist type: negative photoresist; coating amount: 1.8-2.2 ml; front spin speed: 400-600 r / min, spin coating time 10-14 s; back spin speed: 3500-4500 r / min, spin coating time 50-70 s; front baking temperature: 130-160℃, time 1.5-3.5 min; exposure mercury lamp power: 280-370 W, exposure time 7-12 s; back baking temperature: 90-130℃, time 1.5-2.5 min; development time: 25-70 s; deionized water rinsing time: 50-70 s; hardening temperature: 110-130℃, time 1.5-2.5 min.

[0115] In one embodiment, the parameters of the wet etching include: etching solution: dilute nitric acid; nitric acid ratio: 1:15 to 1:25 (concentrated nitric acid dilution ratio); etching time: 3s to 2min. By controlling the appropriate nitric acid ratio and etching time, the patterned IGZO channel layer is ensured while avoiding interference with the channel region image. Exemplarily, the nitric acid ratio is 1:15, 1:18, 1:19, 1:20, 1:21, 1:22, or 1:25. Preferably, it is 1:18 to 1:22.

[0116] It is understandable that the nitric acid ratio affects the etching rate and selectivity. A suitable ratio ensures a moderate etching rate, avoiding both excessively fast and slow etching, thereby reducing damage and residue to the channel layer. Etching time determines the etching depth and pattern accuracy. Too short a time may lead to incomplete etching, while too long a time may damage the channel layer or affect pattern accuracy. By controlling these two factors, the patterning of the IGZO channel layer can be optimized, ensuring high device performance and stability. This helps to precisely control the electrical characteristics in multi-electrode structures, maintain stability under nonlinear operating conditions, improve signal transmission accuracy, and reduce electrical parameter fluctuations, thus enabling more reliable Boolean logic functions in complex circuits.

[0117] In one embodiment, the process steps for removing photoresist include: soaking in acetone for 5-30 minutes and sonicating for 1-2 minutes, soaking in isopropanol for 5-30 minutes and sonicating for 1-2 minutes, and finally drying.

[0118] In some embodiments, step 3, the step of preparing the patterned second electrode, includes: defining the second electrode region by optical lithography, and depositing the second electrode material by electron beam evaporation to form the patterned second electrode.

[0119] In some embodiments, step 3, the step of preparing the patterned second connection line, includes: defining the second connection line region by electron beam lithography, and depositing the second connection line material by electron beam evaporation to form the patterned second connection line.

[0120] In some embodiments, step 3 includes:

[0121] Step 3.1: Define the second electrode region and the second wide connection segment 62a region of the second connection line by optical lithography, and deposit the second electrode and the second connection line material by electron beam evaporation to form the patterned second electrode and the second wide connection segment 62a of the second connection line;

[0122] Step 3.2: Define the second intermediate transition section 62b and the second narrow connection section 62c region of the second connection line by electron beam lithography, and deposit the second connection line material by electron beam evaporation to form the patterned second intermediate transition section 62b and the second narrow connection section 62c of the second connection line.

[0123] In one embodiment, the parameters of the electron beam evaporation include: an evaporation rate of... Vacuum degree is 4×10 -7 Torr to 7×10 -7 Torr.

[0124] In one embodiment, the parameters of the electron beam lithography include: an accelerating voltage of 50KV-150KV, a beam current of 0.5nA-2.0nA, a beam spot size of 1nm-5nm, a photoresist type of Pmma-A3, a photoresist thickness of 50nm-200nm, and an exposure dose of 50μC / cm. 2 -200μC / cm 2 The substrate temperature is room temperature.

[0125] In one embodiment, after the fabrication of the second electrode and the second connection line is completed, a protective layer is further fabricated on top of the patterned second electrode and the second connection line, the IGZO channel layer and the back gate dielectric layer.

[0126] In one embodiment, a protective layer is formed by first introducing a precursor gas and then introducing water vapor through an atomic layer deposition (ALD) process.

[0127] For example, during the ALD process for preparing the protective layer, at 200-250°C, the precursor gas and the reactant gas are alternately circulated 6-10 times, with each cycle including one introduction of the precursor gas and one introduction of the reactant gas.

[0128] For example, in the ALD process for preparing the protective layer, the process parameters of the ALD include: precursor pulse time 150ms-200ms, inert gas (such as N2) pulse time 3s-4s, reactant gas (such as O3) pulse time 1s-2s, inert gas flow rate 50-100sccm, precursor gas flow rate 250-300sccm, reaction temperature 200-250℃, and substrate temperature 200-250℃.

[0129] In one embodiment, after the protective layer is prepared, the method further includes: exposing part or all of the top surface areas of the first electrode and the second electrode by optical lithography and wet etching to form an electrode area for connecting to an external circuit.

[0130] For example, in the process of forming the electrode area for connecting external circuits, the wet etching includes the following steps: immersing the photolithographically etched device in concentrated phosphoric acid at 70-90°C and keeping it for 1-5 minutes; then, removing the device and rinsing the surface thoroughly with deionized water, and then removing the surface photoresist.

[0131] Thirdly, the present invention provides a chip comprising an IGZO-based multi-electrode nonlinear device as described in the first aspect or an IGZO-based multi-electrode nonlinear device obtained by the fabrication method described in the second aspect.

[0132] For example, in the chip, the IGZO-based multi-electrode nonlinear device of this invention is integrated with a CMOS circuit and electrically connected through a metal interconnect layer (such as aluminum or copper interconnect). This integration method can utilize the high performance and high integration of the CMOS circuit while taking advantage of the special electrical characteristics of the IGZO-based multi-electrode nonlinear device.

[0133] For example, in the chip, the IGZO-based multi-electrode nonlinear device of this invention is connected to various sensors (such as temperature sensors, pressure sensors, optical sensors, etc.) for signal amplification and processing. Electrical connections to the sensors are achieved via metal leads or pads.

[0134] For example, in the chip, the IGZO-based multi-electrode nonlinear device of this embodiment of the invention is connected to a memory cell (such as RRAM or Flash) to implement a memory function. Electrical connection to the memory cell is achieved through a metal interconnect layer.

[0135] For example, in the chip, the IGZO-based multi-electrode nonlinear device of this invention is connected to other nonlinear devices (such as diodes, transistors, etc.) to construct complex nonlinear circuits. Electrical connections with other devices are achieved through a metal interconnect layer.

[0136] The technical solution of the present invention will be further described in detail below with reference to specific embodiments and comparative examples.

[0137] Example 1:

[0138] This embodiment provides a multi-electrode nonlinear device based on IGZO, including: a substrate 1, a back gate 2, a back gate dielectric layer 3, an IGZO channel layer 4, multiple electrodes, and several interconnects;

[0139] The back gate 2 is disposed on the substrate 1, and the bottom surface of the back gate 2 is in contact with the top surface of the substrate 1;

[0140] The back gate dielectric layer 3 covers the top surface and all sides of the back gate 2;

[0141] The IGZO channel layer 4 is located on the back gate dielectric layer 3. The bottom surface of the IGZO channel layer 4 is in contact with the top surface of the back gate dielectric layer 3. The IGZO channel layer 4 is correspondingly arranged with the back gate 2, and the projection of the IGZO channel layer 4 in the vertical direction is completely within the projection of the back gate 2 in the vertical direction.

[0142] The plurality of electrodes are dispersed on the substrate 1 and spaced apart from the back gate 2 and the IGZO channel layer 4. The plurality of electrodes include two types: a first electrode 51 and a second electrode 52. The plurality of connecting lines include two types: a first connecting line 61 and a second connecting line 62. The first electrode 51 is made of the same material as the back gate 2 and is electrically connected to the back gate 2 through the first connecting line 51. The second electrode 52 is electrically connected to the IGZO channel layer 4 through the second connecting line 62. The back gate dielectric layer 3 covers the top surface and side surface of the first connecting line 51. There are two first electrodes 51 and eight second electrodes 52.

[0143] Part or all of the top surface of each electrode is exposed, and the plurality of connecting lines do not contact each other;

[0144] The bottom surfaces of the first electrode 51 and the first connecting line 61 are in contact with the top surface of the substrate 1, and the top surfaces of the first electrode 51, the first connecting line 61, and the back gate 2 are flush.

[0145] The bottom surface of the second electrode 52 is in contact with the top surface of the back gate dielectric layer 3; the second connecting line has a main body and an end extending toward the IGZO channel layer, wherein the bottom surface of the main body is in contact with the top surface of the back gate dielectric layer, and the bottom surface of the end is in contact with the top surface of the IGZO channel layer to form an electrical connection.

[0146] The vertical projections of the first connecting line 61 and the adjacent second connecting line 62 overlap. The overlapping area extends from the periphery of the back gate to the inside of the IGZO channel layer, starting from the transition between the first wide connecting segment 61a and the first narrow connecting segment 61b of the first connecting line 61, where the wide segments of the first connecting line 61 and the second connecting line 62 begin to overlap. The vertical projections of the second intermediate transition segment 62b and the second narrow connecting segment 62c of the second connecting line 62 completely fall within the vertical projection range of the first narrow connecting segment 61b of the first connecting line 61.

[0147] The width of the first connecting line 61 decreases from the first electrode to the back gate in the direction of extension; the first connecting line 61 includes a first wide connecting segment 61a and a first narrow connecting segment 61b; the first wide connecting segment 61a is close to the first electrode, the first narrow connecting segment 61b is close to the back gate 2, and the first narrow connecting segment 61b of the first connecting line 61 makes partial contact with the back gate 2 to achieve electrical connection.

[0148] The width of the second connection line 62 decreases from the second electrode to the IGZO channel layer in the direction of extension; the second connection line 62 includes a second wide connection section 62a, a second intermediate transition section 62b, and a second narrow connection section 62c. The second narrow connection section 62c of the second connection line 62 makes partial contact with the IGZO channel layer 4 to achieve electrical connection.

[0149] The first wide connecting segment 61a, the first narrow connecting segment 61b, the second wide connecting segment 62a, the second intermediate transition segment 62b, and the second narrow connecting segment 62c each have a constant cross-sectional width along their extension direction; the width of the first wide connecting segment 61a is W1, the width of the first narrow connecting segment 61b is W2, and W2 / W1 = 0.8 is satisfied; the width of the second wide connecting segment 62a is W3, the width of the second intermediate transition segment 62b is W4, and the width of the second narrow connecting segment 62c is W5, and W4 / W3 = 0.2, W5 / W4 = 0.2, and W2 / W3 = 0.5 are satisfied;

[0150] The IGZO channel layer 4 is circular, the back gate 2 is circular, and the diameter D1 of the IGZO channel layer 4 and the diameter D2 of the back gate 2 satisfy: D1 / D2=0.8;

[0151] The ratio of the contact area length L0 between the second connecting line 62 and the IGZO channel layer 4 to the radius R1 of the IGZO channel layer satisfies: L0 / R1=0.8, where R1=D1 / 2;

[0152] All second connectors are located near the end of the IGZO channel layer 4, i.e., the angle between the eight second narrow connector segments 62c is 45°.

[0153] The nonlinear device further includes a protective layer 7, which covers the top and side surfaces of the second connection line, the top and side surfaces of the IGZO channel layer, and the top surface of the back gate dielectric layer; the side surface of the back gate dielectric layer 2 is flush with the side surface of the substrate 1; the side surface of the protective layer 7 is flush with the side surface of the substrate 1.

[0154] The substrate 1 is made of silicon oxide;

[0155] The back gate dielectric layer 2 and the protective layer 7 are made of aluminum oxide (AlOx) and both have a thickness of 30 nm.

[0156] The first electrode 51, the first connecting line 61, and the back gate 2 are all made of molybdenum (Mo) and have a thickness of 20 nm.

[0157] The IGZO channel layer 4 is made of InGaZnO4 and has a thickness of 5nm. The composition of InGaZnO4 is: Indium (In): 30%, Gallium (Ga): 20%, Zinc (Zn): 50%, and Oxygen (O) is present in stoichiometric proportions.

[0158] Example 2:

[0159] This embodiment provides a method for fabricating a multi-electrode nonlinear device, used to fabricate the IGZO-based multi-electrode nonlinear device described in Embodiment 1, comprising:

[0160] Step 1: Using magnetron sputtering, fabricate a patterned back gate 2, a first electrode 51, and a first interconnect line 61 on substrate 1. (See [link]) Figure 1 There is a gap between the first electrode 51 and the back gate 2, and the first electrode 51 is connected to the back gate 2 through the first connecting line 61.

[0161] The process parameters for magnetron sputtering include: gas: argon; gas flow rate: 25 sccm, gas pressure: 0.5 Pa; sputtering power: DC 50W; substrate temperature: room temperature.

[0162] Step 2: Fabricate the back gate dielectric layer on the patterned back gate, first electrode, first interconnect, and top region of the substrate using atomic layer deposition (ALD). See [link to ADP]. Figure 2 After the back gate dielectric layer is fabricated, without opening the chamber, continue to fabricate an IGZO channel layer in the top region of the back gate dielectric layer and at the position corresponding to the back gate. See [link to relevant documentation]. Figure 3 ;

[0163] Among them, the parameters for atomic layer deposition during the deposition of the back gate dielectric layer include: precursor pulse time 170ms, precursor gas flow rate 280sccm; inert gas (such as N2) pulse time 3s, inert gas flow rate 80sccm; reactive gas (such as O3) pulse time 1s, reactive gas flow rate 100sccm, and deposition temperature 200℃.

[0164] When depositing the IGZO channel layer, the atomic layer deposition parameters include: precursor pulse time 300 ms, precursor gas flow rate 300 sccm; inert gas (e.g., N2) pulse time 4 s, inert gas flow rate 100 sccm; reactant gas (e.g., O3) pulse time 3 s, reactant gas flow rate 80 sccm.

[0165] After depositing the IGZO channel layer, the active region pattern is defined by optical lithography, then the IGZO channel layer is patterned by wet etching, and finally the photoresist is removed to complete the active region fabrication.

[0166] The optical lithography process features a resolution of 2 μm and a photoresist thickness of 20 μm. The parameters of the optical lithography include: photoresist type: negative resist; coating amount: 2.0 ml; front spin speed: 500 r / min, spin coating time: 12 s; back spin speed: 4000 r / min, spin coating time: 60 s; front baking temperature: 140℃, time: 3 min; exposure mercury lamp power: 350 W, exposure time: 9 s; back baking temperature: 120℃, time: 2.5 min; development time: 40 s; deionized water rinsing time: 60 s; hardening temperature: 120℃, time: 2.0 min.

[0167] The parameters for the wet etching process include: etching solution: dilute nitric acid; nitric acid ratio: 1:20 (concentrated nitric acid dilution ratio); etching time: 1 min;

[0168] The process steps for removing photoresist include: soaking in acetone for 20 minutes and sonicating for 1 minute, soaking in isopropanol for 10 minutes and sonicating for 2 minutes, and finally drying.

[0169] Step 3: A patterned second electrode and a second connecting line are fabricated in the top region of the back gate dielectric layer. There is a gap between the second electrode and the IGZO channel layer. The second electrode is connected to the IGZO channel layer through the second connecting line.

[0170] Step 3.1: Define the second electrode region and the second wide connection segment 62a region of the second interconnecting line using optical lithography. Deposit the second electrode and second interconnecting line materials using electron beam evaporation to form the patterned second electrode and the second wide connection segment 62a of the second interconnecting line. See [link to relevant documentation]. Figure 4 ;

[0171] Step 3.2: Define the second intermediate transition section 62b and the second narrow connection section 62c region of the second interconnect line using electron beam lithography. Deposit the second interconnect line material using electron beam evaporation to form the patterned second intermediate transition section 62b and the second narrow connection section 62c of the second interconnect line. See [link to relevant documentation]. Figure 5 ;

[0172] The optical lithography process parameters in step 3.1 are the same as in step 2; the electron beam evaporation parameters in step 3.1 include: an evaporation rate of... Vacuum degree is 7×10 -7 Torr;

[0173] The parameters for electron beam lithography in step 3.2 include: an accelerating voltage of 100 kV, a beam current of 1.0 nA, a beam spot size of 2 nm, a photoresist type of Pmma-A3, a photoresist thickness of 100 nm, and an exposure dose of 100 μC / cm. 2 The substrate temperature is room temperature.

[0174] Step 4: Fabricate a protective layer on top of the patterned second electrode and second interconnect, the IGZO channel layer, and the back gate dielectric layer. See [link to documentation]. Figure 6 ;

[0175] Specifically, using atomic layer deposition (ALD) technology, trimethylaluminum (TMA) gas is first introduced, followed by water vapor, to deposit a protective layer. During the ALD process for preparing the protective layer, TMA gas and water vapor are alternately circulated 8 times at 200°C. Specifically, the ALD process parameters include: precursor pulse time 150ms, inert gas (e.g., N2) pulse time 3s, reactant gas (e.g., O3) pulse time 2s, inert gas flow rate 50sccm, precursor gas flow rate 250sccm, reaction temperature 200°C, and substrate temperature 200°C.

[0176] Step 5. Expose part or all of the top surface area of ​​the first electrode and the second electrode by optical lithography and wet etching to form an electrode area for connecting external circuits;

[0177] The process parameters of the optical lithography in step 5 are the same as those in step 2; the wet etching in step 5 includes: immersing the lithographically completed device in concentrated phosphoric acid at 80°C and keeping it for 3 minutes; then, taking the device out and rinsing the surface with deionized water to remove the surface photoresist.

[0178] Example 3

[0179] This embodiment is the same as Embodiment 1, except that the thickness of the IGZO channel layer 4 is 8nm.

[0180] Example 4

[0181] This embodiment is the same as Embodiment 1, except that the thickness of the IGZO channel layer 4 is 3nm.

[0182] Example 5

[0183] This embodiment is the same as Embodiment 1, except that, in all the second connecting lines near the end of the IGZO channel layer 4, that is, among the eight second narrow connecting segments 62c, the included angle between some adjacent second narrow connecting segments 62c is >60°, and the included angle between some adjacent second narrow connecting segments 62c is <30°. Specifically, the first included angle is 70°, the second included angle is 20°, the third included angle is 70°, the fourth included angle is 20°, the fifth included angle is 70°, the sixth included angle is 20°, the seventh included angle is 70°, and the eighth included angle is 20°.

[0184] Example 6

[0185] This embodiment is the same as Embodiment 2, except that an atomic layer deposition (ALD) is used to prepare a back gate dielectric layer on the top region of the patterned back gate, the first electrode, the first interconnect line, and the substrate. After the back gate dielectric layer is prepared, the chamber is opened and exposed to air for a period of time. Then the chamber door is closed, and an IGZO channel layer is prepared on the top region of the back gate dielectric layer at the position corresponding to the back gate.

[0186] Comparative Example 1

[0187] This comparative example provides a nonlinear device that uses gold (Au) nanoparticles with a diameter of 20 nm, the surface of which is modified with 1-octanethiol; the substrate is highly doped silicon (Si, p++) with a 35 nm thick layer of silicon dioxide (SiO2); the electrode consists of a 5 nm thick titanium (Ti) adhesion layer and a 30 nm thick gold (Au) layer, forming a 50 nm wide radial electrode.

[0188] Comparative Example 2

[0189] This comparative example provides a nonlinear device that uses boron-doped silicon (Si:B) as the main nonlinear material. By implanting boron atoms into an n-type silicon substrate, a high-concentration doped region is formed to achieve nonlinear charge transport characteristics.

[0190] The fabrication process is as follows: A 300 nm thermal oxide layer was grown on an n-type silicon substrate. A 26 × 60 μm layer was defined by photolithography and wet etching. 2 The doping window was defined. A 35 nm oxide layer was grown within the doping window as a stop layer. After boron doping (9 keV equivalent, 3.5 × 10⁻⁶), the oxide layer was... 14 cm -2 After activation via rapid thermal annealing (1050°C, 7 seconds), a 35nm stop layer was removed by wet etching. The boron concentration near the silicon surface exceeded 2×10⁻⁶. 19 cm -3To ensure ohmic contact with the electrodes, and to monotonically decrease with increasing depth, eight 1.5 nm Ti / 40 nm Pd nanoelectrodes were fabricated on silicon by electron beam lithography after lift-off of the photolithographically defined pads (1.5 nm Ti / 40 nm Pd). The silicon surface was further etched by reactive ion etching after annealing at 160 °C for 10 minutes. Finally, the surface was treated with mild oxygen plasma followed by etching with 1% HF to remove any potential contaminants.

[0191] Performance testing

[0192] Using a Keithley 4200 as the test instrument, the output characteristics of the devices in each embodiment were tested under a nitrogen atmosphere at room temperature (300K). During testing, to avoid interference from adjacent electrodes, a pair of opposing second electrodes were selected as the source and drain (here, "opposite" means that the second connection lines of the two second electrodes are furthest apart in the contact area with the IGZO channel layer). The source-drain difference was Vds, and either of the two first electrodes was selected as the gate. During testing, the gate-source voltage Vgs was continuously increased from 0V to 14V in step mode, while Vds was scanned from -1V to +1V while Vgs remained constant.

[0193] The results of Example 1 are as follows Figure 12 As shown, this is the output characteristic curve of the device measured at room temperature of 300K. It is clear from the figure that as the gate voltage increases, the device of Example 1 exhibits increasingly pronounced nonlinear transport characteristics. Furthermore, Examples 2 to 6 also achieve nonlinear characteristics and Boolean logic functions at room temperature. At the same gate-source voltage, the nonlinear transport characteristics of Example 4 are more significant than those of Example 1. In contrast, the nonlinear transport characteristics of Examples 3, 5, and 6 are lower than those of Example 1.

[0194] The nonlinear characteristics and Boolean logic of the various embodiments of the present invention are achieved at room temperature, while Comparative Examples 1 and 2 can only exhibit nonlinear transport characteristics at low temperatures (e.g., 0.3K and 77K).

[0195] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A multi-electrode nonlinear device based on IGZO, characterized in that, include: Substrate, back gate, back gate dielectric layer, IGZO channel layer, multiple electrodes, and several interconnects; The back gate is disposed on the substrate, and the bottom surface of the back gate is in contact with the top surface of the substrate; The back gate dielectric layer covers the top surface and all sides of the back gate; The IGZO channel layer is located on the back gate dielectric layer, the bottom surface of the IGZO channel layer is in contact with the top surface of the back gate dielectric layer, the IGZO channel layer is correspondingly arranged with the back gate, and the projection of the IGZO channel layer in the vertical direction is completely within the projection of the back gate in the vertical direction. The plurality of electrodes are dispersed on the substrate and spaced apart from the back gate and the IGZO channel layer. The plurality of electrodes include two types: a first electrode and a second electrode. The plurality of interconnects also include two types: a first interconnect and a second interconnect. The first electrode is made of the same material as the back gate and is electrically connected to the back gate through the first interconnect. The second electrode is electrically connected to the IGZO channel layer through the second interconnect. The back gate dielectric layer covers the top and side surfaces of the first interconnect. Part or all of the top surface of each electrode is exposed, and the plurality of connecting lines do not contact each other.

2. The multi-electrode nonlinear device according to claim 1, characterized in that, The thickness of the IGZO channel layer is ≤5nm.

3. The multi-electrode nonlinear device according to claim 1, characterized in that, The first connecting line is made of the same material as the back grille; and / or, The bottom surfaces of the first electrode and the first connecting line are in contact with the top surface of the substrate, and the top surfaces of the first electrode, the first connecting line, and the back gate are flush.

4. The multi-electrode nonlinear device according to claim 1, characterized in that, The second connection line has a body portion and an end portion extending toward the IGZO channel layer, wherein the bottom surface of the body portion contacts the top surface of the back gate dielectric layer, and the bottom surface of the end portion contacts the top surface of the IGZO channel layer to form an electrical connection; and / or, The bottom surface of the second electrode is in contact with the top surface of the back gate dielectric layer.

5. The multi-electrode nonlinear device according to claim 1, characterized in that, The nonlinear device further includes a protective layer covering the top and side surfaces of the second connection line, the top and side surfaces of the IGZO channel layer, and the top surface of the back gate dielectric layer.

6. The multi-electrode nonlinear device according to claim 1, characterized in that, The vertical projections of the first connecting line and the adjacent second connecting line have an overlapping area, which extends from the periphery of the back gate to the inside of the IGZO channel layer.

7. The multi-electrode nonlinear device according to claim 1, characterized in that, The width of the second connection line decreases from the second electrode in the direction of extension of the IGZO channel layer.

8. A method for fabricating a multi-electrode nonlinear device, characterized in that, For fabricating the IGZO-based multi-electrode nonlinear device according to any one of claims 1-7, comprising: Step 1: Fabricate a patterned back gate, a first electrode, and a first interconnect on a substrate; there is a gap between the first electrode and the back gate, and the first electrode is connected to the back gate through the first interconnect; Step 2: Fabricate a back gate dielectric layer in the top region of the patterned back gate, first electrode, first interconnect line and substrate; fabricate an IGZO channel layer in the top region of the back gate dielectric layer and at the position corresponding to the back gate; Step 3: A patterned second electrode and a second connecting line are fabricated in the top region of the back gate dielectric layer. There is a gap between the second electrode and the IGZO channel layer. The second electrode is connected to the IGZO channel layer through the second connecting line.

9. The method for fabricating a multi-electrode nonlinear device according to claim 8, characterized in that, In step 2, after the back gate dielectric layer is prepared, the chamber is not opened, and the IGZO channel layer is prepared.

10. A chip comprising the IGZO-based multi-electrode nonlinear device according to any one of claims 1-7 or the IGZO-based multi-electrode nonlinear device obtained by the fabrication method according to any one of claims 8-9.

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