Semiconductor device, manufacturing method thereof, power conversion circuit and vehicle

Abstract

The invention provides a semiconductor device, a manufacturing method thereof, a power conversion circuit and a vehicle. The semiconductor device comprises an N-type semiconductor substrate, an epitaxial layer, and a first grid electrode and a second grid electrode which are connected with each other. Wherein the first grid electrode extends along a first direction, and the second grid electrode extends along a second direction. The first grid electrode and the second grid electrode are respectively positioned in different grooves in the epitaxial layer; a first gate medium is filled between the first gate and the groove, and the first gate is isolated from the groove through the first gate medium; a second gate medium is filled between the second gate and the groove, and the second gate is isolated from the groove through the second gate medium; the thickness of the first gate dielectric is larger than that of the second gate dielectric in the direction perpendicular to the plane where the semiconductor substrate is located. According to the embodiment of the invention, the contradictory relationship between the on-resistance and the capacitance can be improved, and the performance of the semiconductor device is improved.

Description

Semiconductor device, manufacturing method thereof, power conversion circuit and vehicle Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a manufacturing method thereof, a power conversion circuit and a vehicle. Background Art

[0002] Silicon carbide (SiC) material has advantages over silicon (Si) material, including a wide bandgap, a high critical breakdown electric field, high thermal conductivity, and a high electron saturation drift velocity. Compared to insulated gate bipolar transistor (IGBT) devices made of Si material, metal-oxide-semiconductor field-effect transistor (MOSFET) devices made of SiC material have characteristics such as high breakdown voltage and low on-state voltage drop. In addition, the unipolar conductivity of SiC material enables SiC MOSFET devices to have faster switching speeds, lower conduction losses, and lower switching losses than Si IGBT devices. Therefore, SiC MOSFET devices have replaced Si IGBT devices in some application scenarios such as on-board microcontroller units (MCUs) and on-board battery chargers (OBCs).

[0003] Compared with devices with a planar gate structure, SiC MOSFET devices with a trench gate structure embed the gate into the SiC body, turning the device's conductive channel from a planar direction to a vertical direction, thereby significantly reducing the device's cell size and greatly improving the device's conductive channel density. This can significantly reduce the chip's on-resistance and improve its current-carrying capacity. Therefore, the trench gate structure has become the mainstream technical direction for future devices.

[0004] However, there is a conflicting relationship between the on-resistance (related to conduction losses) and capacitance (related to switching losses) of SiC MOSFET devices with trench gate structures. Reducing the trench gate spacing can reduce the cell size and increase the channel density, thereby reducing the on-resistance of the device and reducing the conduction losses. However, at the same time, the device capacitance, especially the Miller capacitance (capacitance between the gate and the drain), will increase significantly, causing the device switching speed to slow down and increasing switching losses. Therefore, due to the conflicting relationship between the device's on-resistance and capacitance, it is difficult to further improve the performance of SiC MOSFET devices.

[0005] Summary of the Invention

[0006] The present application provides a semiconductor device, a manufacturing method thereof, a power conversion circuit and a vehicle, which are used to improve the contradictory relationship between the on-resistance and capacitance of the semiconductor device and enhance the performance of the semiconductor device.

[0007] In a first aspect, an embodiment of the present application provides a semiconductor device. The semiconductor device provided by the embodiment of the present application may include: an N-type semiconductor substrate, an epitaxial layer arranged on the semiconductor substrate, and a first gate and a second gate connected to each other. The first gate extends along a first direction, and the second gate extends along a second direction. The first direction and the second direction are two directions parallel to the plane where the semiconductor substrate is located and intersecting with each other. The first gate and the second gate are respectively located in different trenches in the epitaxial layer. A first gate dielectric is filled between the first gate and the trench, and the first gate is isolated from the trench by the first gate dielectric. A second gate dielectric is filled between the second gate and the trench, and the second gate is isolated from the trench by the second gate dielectric. In a direction perpendicular to the plane where the semiconductor substrate is located, the thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

[0008] The semiconductor device in the embodiments of the present application may be a SiC MOSFET device, and the semiconductor substrate and epitaxial layer may both comprise silicon carbide (SiC) material. The semiconductor substrate may be a single crystal silicon carbide substrate doped with a pentavalent element. The epitaxial layer may comprise SiC material doped with corresponding impurities, and the epitaxial layer may be produced using an epitaxial growth process.

[0009] The semiconductor device in the embodiment of the present application is a SiC MOSFET device with a trench gate structure. By setting a plurality of trenches in the epitaxial layer and setting a gate in the trench, the gate can be embedded in the interior of the epitaxial layer so that the conductive channel direction of the semiconductor device is vertical, thereby increasing the conductive channel density of the semiconductor device and reducing the on-resistance. In addition, the semiconductor device in the embodiment of the present application includes: a first gate and a second gate connected to each other, the first gate extending along the first direction, and the second gate extending along the second direction, which can further increase the density of the conductive channel, thereby further reducing the on-resistance. In addition, in the embodiment of the present application, in the direction perpendicular to the plane where the semiconductor substrate is located, the thickness of the first gate dielectric is greater than the thickness of the second gate dielectric. By setting a thicker first gate dielectric, the capacitance of the semiconductor device can be reduced, thereby improving the contradictory relationship between the on-resistance and capacitance, and improving the performance of the semiconductor device.

[0010] In one possible implementation, a plurality of first trenches and a plurality of second trenches are provided in the epitaxial layer. Each first trench extends along a first direction and is aligned along a second direction. Each second trench extends along the second direction and is aligned along the first direction, with each first trench intersecting the second trenches. Each first trench and each second trench extends from a surface of the epitaxial layer facing away from the semiconductor substrate along a third direction into the interior of the epitaxial layer. The third direction is perpendicular to the plane of the semiconductor substrate. Optionally, the first, second, and third directions may be mutually perpendicular. A first gate is located in the first trench, and a second gate is located in the second trench. For example, a first gate may be provided in each first trench, and a second gate may be provided in each second trench. A first gate dielectric is filled between the first gate and the first trench, and the first gate is isolated from the first trench by the first gate dielectric. A second gate dielectric is filled between the second gate and the second trench, and the second gate is isolated from the second trench by the second gate dielectric. The thickness of the first gate dielectric in the third direction is greater than the thickness of the second gate dielectric in the third direction.

[0011] That is, the first gate is filled in the first trench via the first gate dielectric, and the second gate is filled in the second trench via the second gate dielectric, thereby embedding the first gate and the second gate inside the epitaxial layer, so that the semiconductor device in the embodiment of the present application constitutes a SiC MOSFET device with a trench structure.

[0012] In one possible implementation, the first gate and the second gate may be made of polysilicon, or may be made of a metal material such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), molybdenum (Mo), or platinum (Pt). Of course, the first gate and the second gate may also be made of other materials with good electrical conductivity, which is not limited here.

[0013] In an embodiment of the present application, the semiconductor device may further include: an interlayer dielectric layer, a source electrode, and a drain electrode. The interlayer dielectric layer covers the surface of the first gate electrode and the second gate electrode on the side facing away from the semiconductor substrate. A plurality of contact holes are provided in the interlayer dielectric layer, and the orthographic projections of the contact holes on the semiconductor substrate do not overlap with the orthographic projections of the first gate electrode and the second gate electrode on the semiconductor substrate. The source electrode is provided on the side of the interlayer dielectric layer facing away from the semiconductor substrate, and the source electrode contacts the epitaxial layer through the contact holes. The drain electrode is located on the side of the semiconductor substrate facing away from the epitaxial layer. The plurality of contact holes in the interlayer dielectric layer can expose a portion of the epitaxial layer, so that the source electrode can contact the epitaxial layer through the contact holes. The orthographic projections of the contact holes on the semiconductor substrate do not overlap with the orthographic projections of the first gate electrode and the second gate electrode on the semiconductor substrate, thereby preventing the source electrode from contacting the first gate electrode and the second gate electrode.

[0014] In one possible implementation, the interlayer dielectric layer may include a dielectric material, which may include but is not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), etc. The source and drain may be made of a metal material, which may include but is not limited to W, Al, Ti, Cu, Mo, or Pt, for example.

[0015] In one possible implementation, the depth of each first trench can be greater than the depth of each second trench. The thickness of each first gate in the third direction can be consistent with the thickness of each second gate in the third direction. Thus, the thickness of the first gate dielectric in the third direction can be greater than the thickness of the second gate dielectric in the third direction. The portion of the first gate dielectric thicker than the second gate dielectric can be located at the bottom of the first trench to facilitate manufacturing.

[0016] The aforementioned consistency of thickness of the first gate and the second gate in the third direction means that the first gate and the second gate are equal within the process error range. During the manufacturing process, the first gate and the second gate can be manufactured using the same process, thereby saving process steps and reducing process costs. Of course, in some cases, when the first gate and the second gate are manufactured using different processes, the thickness of the first gate and the second gate in the third direction can also be unequal, as long as the thickness of the first gate dielectric in the third direction can be greater than the thickness of the second gate dielectric in the third direction.

[0017] In a specific implementation, the depths of the first trenches can be equal within a process tolerance range. Thus, during the manufacturing process, the first trenches can be manufactured using the same process. Similarly, the depths of the second trenches can be equal within a process tolerance range. Thus, the second trenches can be manufactured using the same process. This can save process steps and reduce process costs.

[0018] The spacing between two adjacent second grooves in the first direction is the first spacing, and the spacing between two adjacent first grooves in the second direction is the second spacing. In specific settings, the specific sizes of the first spacing and the second spacing can be set according to actual needs. The first spacing can be greater than the second spacing; or the first spacing can be equal to the second spacing; or the first spacing can be less than the second spacing. In some embodiments of the present application, the first grooves can be arranged at equal intervals or at unequal intervals; the second grooves can be arranged at equal intervals or at unequal intervals.

[0019] In the embodiment of the present application, the epitaxial layer may include: an N-type semiconductor region and a first P-type semiconductor region. The N-type semiconductor region may be doped with N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As), and the first P-type semiconductor region may be doped with P-type impurities such as boron (B), aluminum (Al), or gallium (Ga).

[0020] The first P-type semiconductor region is located on a side of the N-type semiconductor region facing away from the semiconductor substrate. Each first trench and each second trench penetrates the first P-type semiconductor region in the third direction and extends into the N-type semiconductor region. In this way, the first gate and the second gate can form a SiC MOSFET device with a trench gate structure with the first P-type semiconductor region through a gate dielectric (the first gate dielectric or the second gate dielectric).

[0021] In some embodiments of the present application, the epitaxial layer may further include: a source region and a plurality of P-type connection regions arranged in the same layer. Each P-type connection region corresponds to the position of a contact hole, and the orthographic projection of the P-type connection region on the semiconductor substrate is located within the range of the orthographic projection of the corresponding contact hole on the semiconductor substrate. The P-type connection region connects the first P-type semiconductor region and the source. The doping concentration of the P-type connection region may be greater than the doping concentration of the first P-type semiconductor region so that the conduction performance of the P-type connection region is better. The source region is the region in the layer where the source region is located, excluding the plurality of first trenches, the plurality of second trenches, and the plurality of P-type connection regions. Exemplarily, a portion of the source region may be covered by an interlayer dielectric layer, and the other portion may be electrically connected to the source.

[0022] In specific implementation, an ion implantation process can be used to implant N-type impurities such as nitrogen (N), phosphorus (P) or arsenic (As) into the area where the source region is to be formed to form a source region, and to implant P-type impurities such as boron (B), aluminum (Al) or gallium (Ga) into the area where the P-type connection region is to be formed to form a P-type connection region.

[0023] The first trench (or the second trench) has a first P-type semiconductor region on both sides of the second direction (or the first direction). During the operation of the semiconductor device, under the control of the first gate (or the second gate), the first P-type semiconductor region can form an N-type inversion channel, so that the source electrode passes through the conductive path of the source region, the first P-type semiconductor region, the N-type semiconductor region, and the semiconductor substrate to achieve conduction with the drain electrode.

[0024] In a specific implementation, the semiconductor substrate has a relatively high doping concentration. For example, the doping concentration of the semiconductor substrate can be greater than the doping concentration of the N-type semiconductor region, so as to improve the conductivity of the semiconductor substrate and enable the semiconductor substrate to serve as the drain region of the semiconductor device. The source region also has a relatively high doping concentration. For example, the doping concentration of the source region can be greater than the doping concentration of the N-type semiconductor region, so as to improve the conductivity of the source region. This facilitates conduction between the source and drain electrodes during operation of the semiconductor device, thereby reducing the on-resistance of the semiconductor device.

[0025] The semiconductor device in the embodiment of the present application is a SiC MOSFET device with a trench gate structure. At the bottom and corners of the first trench and the second trench, the gate dielectric (the first gate dielectric or the second gate dielectric) will be subjected to a high electric field strength when the semiconductor device is working. It is a weak point for electric field breakdown and is likely to cause failure of the long-term working reliability of the semiconductor device. In order to effectively shield the gate dielectric from high electric field stress, the epitaxial layer in the embodiment of the present application may also include a second P-type semiconductor region, which is located on the side of the first trench close to the semiconductor substrate, and the second P-type semiconductor region is electrically connected to the source. When the semiconductor device is working, the source will be loaded with voltage. Since the second P-type semiconductor region is electrically connected to the source, the voltage loaded on the source will be input into the second P-type semiconductor region, so that the second P-type semiconductor region also has a corresponding voltage, thereby effectively shielding the electric field of the gate dielectric at the bottom of the first trench and the second trench, thereby improving the robustness of the semiconductor device.

[0026] Exemplarily, the thickness of the second P-type semiconductor region in the third direction may be less than 1 μm. For example, the thickness of the second P-type semiconductor region in the third direction may be 0.3 μm to 0.8 μm. Of course, the thickness of the second P-type semiconductor region in the third direction may also be greater than 1 μm, which is not limited here. Optionally, the second P-type semiconductor region may be doped with P-type impurities such as boron (B), aluminum (Al) or gallium (Ga). In order to make the conductivity of the second P-type semiconductor region better, the doping concentration of the second P-type semiconductor region may be set to be larger. For example, the doping concentration of the second P-type semiconductor region may be greater than the doping concentration of the first P-type semiconductor region.

[0027] In some application scenarios, the source of the semiconductor device can be grounded, and the drain can be electrically connected to other components. Since the second P-type semiconductor region is electrically connected to the source, the voltage of the second P-type semiconductor region is also the ground voltage (0V), thereby effectively shielding the electric field of the gate dielectric at the bottom of the first trench and the second trench, thereby improving the robustness of the semiconductor device. In other application scenarios, the source of the semiconductor device can be electrically connected to other components, and the drain can also be electrically connected to other components. In this case, the voltage of the source is the voltage of the input signal of the other component (which may not be 0). Since the second P-type semiconductor region is electrically connected to the source, the voltage of the second P-type semiconductor region is also the voltage of the input signal, thereby effectively shielding the electric field of the gate dielectric at the bottom of the first trench and the second trench, thereby improving the robustness of the semiconductor device.

[0028] In one possible implementation, the N-type semiconductor region may include: a first N-type semiconductor region and a second N-type semiconductor region. The second N-type semiconductor region is located between the first N-type semiconductor region and the first P-type semiconductor region, and the doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region. Each first trench and each second trench penetrates the second N-type semiconductor region in the third direction and extends into the first N-type semiconductor region. The second P-type semiconductor region may be located in the first N-type semiconductor region. The first N-type semiconductor region and the second N-type semiconductor region may both include N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As). The doping concentration of the first N-type semiconductor region is relatively low, which can improve the withstand voltage performance of the semiconductor device. The doping concentration of the second N-type semiconductor region is relatively high, which can reduce the on-resistance of the semiconductor device.

[0029] In another possible implementation, the N-type semiconductor region may include: a first N-type semiconductor region, a second N-type semiconductor region, and a third N-type semiconductor region. The second N-type semiconductor region is located on a side of the first N-type semiconductor region facing away from the semiconductor substrate, and the third N-type semiconductor region is located between the first and second N-type semiconductor regions. The doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region, and the doping concentration of the third N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region. Each of the first trenches and each of the second trenches penetrates the second N-type semiconductor region in the third direction and extends into the third N-type semiconductor region. The second P-type semiconductor region is located in the third N-type semiconductor region. The first N-type semiconductor region, the second N-type semiconductor region, and the third N-type semiconductor region may all include N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As). The first N-type semiconductor region has a relatively low doping concentration, which can improve the withstand voltage performance of the semiconductor device. The second N-type semiconductor region has a relatively high doping concentration, which can reduce the on-resistance of the semiconductor device. Furthermore, the third N-type semiconductor region has a relatively high doping concentration, which can further reduce the on-resistance of the semiconductor device.

[0030] In other embodiments of the present application, the epitaxial layer may further include: a third P-type semiconductor region, the third P-type semiconductor region being located on a side of the second trench close to the semiconductor substrate, the third P-type semiconductor region being electrically connected to the source. That is, the second P-type semiconductor region at the bottom of the first trench and the third P-type semiconductor region at the bottom of the second trench are both electrically connected to the source. In this way, when the semiconductor device is operating, a voltage is applied to the source. Since the second P-type semiconductor region and the third P-type semiconductor region are both electrically connected to the source, the voltage applied to the source is input into the second P-type semiconductor region and the third P-type semiconductor region, causing the second P-type semiconductor region and the third P-type semiconductor region to also have a corresponding voltage, thereby effectively shielding the electric field of the gate dielectric at the bottom of the first trench and the second trench, further improving the robustness of the semiconductor device.

[0031] Optionally, the third P-type semiconductor region may be doped with P-type impurities such as boron (B), aluminum (Al), or gallium (Ga). To improve the conductivity of the third P-type semiconductor region, the doping concentration of the third P-type semiconductor region may be set to be higher. For example, the doping concentration of the third P-type semiconductor region may be greater than the doping concentration of the first P-type semiconductor region.

[0032] In some application scenarios, the source of the semiconductor device can be grounded, and the drain can be electrically connected to other components. Since the second P-type semiconductor region and the third P-type semiconductor region are electrically connected to the source, the voltage of the second P-type semiconductor region and the third P-type semiconductor region is also the ground voltage (0V), thereby effectively shielding the electric field of the gate dielectric at the bottom of the first trench and the second trench, thereby improving the robustness of the semiconductor device. In other application scenarios, the source of the semiconductor device can be electrically connected to other components, and the drain can also be electrically connected to other components. In this case, the voltage of the source is the voltage of the input signal of the other component (which may not be 0). Since the second P-type semiconductor region and the third P-type semiconductor region are electrically connected to the source, the voltage of the second P-type semiconductor region and the third P-type semiconductor region is also the voltage of the input signal, which can also effectively shield the electric field of the gate dielectric at the bottom of the first trench and the second trench, thereby improving the robustness of the semiconductor device.

[0033] In one possible implementation, the thickness of the third P-type semiconductor region in the third direction can be less than 1 μm, and the thickness of the second P-type semiconductor region and the third P-type semiconductor region in the third direction can be approximately equal within the range of process error. In this way, the second P-type semiconductor region and the third P-type semiconductor region can be manufactured together using the same manufacturing process, thereby saving process steps and reducing manufacturing costs. In another possible implementation, the thickness of the third P-type semiconductor region in the third direction can also be greater than 1 μm, and the thickness of the third P-type semiconductor region in the third direction can be greater than the thickness of the second P-type semiconductor region in the third direction. During the manufacturing process, different process steps can be used to manufacture the second P-type semiconductor region and the third P-type semiconductor region respectively.

[0034] In one possible implementation, the N-type semiconductor region may include: a first N-type semiconductor region and a second N-type semiconductor region. The second N-type semiconductor region is located between the first N-type semiconductor region and the first P-type semiconductor region, and the doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region. Each first trench and each second trench penetrates the second N-type semiconductor region in the third direction and extends into the first N-type semiconductor region. The second P-type semiconductor region and the third P-type semiconductor region are located in the first N-type semiconductor region. The first N-type semiconductor region and the second N-type semiconductor region may both include N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As). The doping concentration of the first N-type semiconductor region is relatively low, which can improve the withstand voltage performance of the semiconductor device. The doping concentration of the second N-type semiconductor region is relatively high, which can reduce the on-resistance of the semiconductor device.

[0035] In some cases, the thickness of the third P-type semiconductor region in the third direction may be smaller. For example, the thickness of the second P-type semiconductor region and the third P-type semiconductor region in the third direction may be approximately equal within the range of process error. In other cases, the thickness of the third P-type semiconductor region in the third direction may be larger. For example, the thickness of the third P-type semiconductor region in the third direction may be greater than the thickness of the second P-type semiconductor region in the third direction.

[0036] In another possible implementation, the N-type semiconductor region includes: a first N-type semiconductor region, a second N-type semiconductor region, and a third N-type semiconductor region. The second N-type semiconductor region is located on a side of the first N-type semiconductor region facing away from the semiconductor substrate, and the third N-type semiconductor region is located between the first N-type semiconductor region and the third N-type semiconductor region. The doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region, and the doping concentration of the third N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region. Each first trench and each second trench penetrates the second N-type semiconductor region in a third direction and extends into the third N-type semiconductor region. The second P-type semiconductor region and the third P-type semiconductor region are located in the third N-type semiconductor region.

[0037] The first N-type semiconductor region, the second N-type semiconductor region, and the third N-type semiconductor region may all include N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As). The first N-type semiconductor region has a relatively low doping concentration, which can improve the withstand voltage performance of the semiconductor device. The second N-type semiconductor region and the third N-type semiconductor region have relatively high doping concentrations, which can reduce the on-resistance of the semiconductor device.

[0038] In a second aspect, an embodiment of the present application further provides a method for manufacturing any of the above-mentioned semiconductor devices. The method for manufacturing a semiconductor device provided in an embodiment of the present application may include:

[0039] Growing an epitaxial layer on an N-type semiconductor substrate;

[0040] Etching the epitaxial layer to form a first trench and a second trench;

[0041] A first gate and a first gate dielectric are formed in the first trench, and a second gate and a second gate dielectric are formed in the second trench; wherein, in a direction perpendicular to the plane of the semiconductor substrate, the thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

[0042] forming an interlayer dielectric layer over the first gate and the second gate, and patterning the interlayer dielectric layer to form a plurality of contact holes in the interlayer dielectric layer. Orthographic projections of the contact holes on the semiconductor substrate do not overlap with orthographic projections of the first gate and the second gate on the semiconductor substrate;

[0043] A source electrode is formed on the interlayer dielectric layer and is in contact with the epitaxial layer through the contact holes. A drain electrode is formed on a side of the semiconductor substrate away from the epitaxial layer.

[0044] In a possible implementation, the step of growing an epitaxial layer on an N-type semiconductor substrate may specifically include:

[0045] An N-type semiconductor region is formed on a semiconductor substrate using an epitaxial process, and ions are implanted into the N-type semiconductor region using an ion implantation process to form a first P-type semiconductor region. For example, the N-type semiconductor region may include N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As). P-type impurities such as boron (B), aluminum (Al), or gallium (Ga) may be implanted into the epitaxial layer to obtain a P-type semiconductor region. In a specific implementation, an epitaxial process may be used to form a first N-type semiconductor region, and then N-type impurities are implanted into the surface of the first N-type semiconductor region to form a second N-type semiconductor region with a higher doping concentration on the surface of the first N-type semiconductor region.

[0046] An ion implantation process is used to implant ions into the surface of the epitaxial layer to form a source region and multiple P-type connection regions disposed in the same layer. Each P-type connection region corresponds to the location of a contact hole to be formed, and the orthographic projection of the P-type connection region on the semiconductor substrate is within the orthographic projection of the corresponding contact hole on the semiconductor substrate. The source region is used to contact the subsequently formed source electrode. Generally, the source region has a higher doping concentration. For example, the doping concentration of the source region can be greater than the doping concentration of the N-type semiconductor region to improve the conductivity of the source region. The P-type connection region is used to connect the first P-type semiconductor region to the subsequently formed source electrode. The doping concentration of the P-type connection region can be greater than the doping concentration of the first P-type semiconductor region to improve the conductivity of the P-type connection region. In a specific implementation, an ion implantation process can be used to implant N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As) into the region where the source region is to be formed to form the source region, and to implant P-type impurities such as boron (B), aluminum (Al), or gallium (Ga) into the region where the P-type connection region is to be formed to form the P-type connection region.

[0047] In some embodiments of the present application, the above-mentioned epitaxial etching to form the first trench and the second trench may specifically include:

[0048] The epitaxial layer is etched to form a plurality of first trenches extending in a first direction and arranged in a second direction. For example, a mask having a pattern consistent with the first trenches can be formed on the epitaxial layer. This mask can be used to cover areas where the first trenches are not required, while exposing areas where the first trenches are required. An etching process is then used to etch the areas of the epitaxial layer not covered by the mask until the etching reaches the N-type semiconductor region of the epitaxial layer, thereby forming the plurality of first trenches.

[0049] An ion implantation process is used to implant ions into the bottom of the first trench to form a second P-type semiconductor region on the side of the first trench near the semiconductor substrate. The second P-type semiconductor region can be electrically connected to the source. During operation of the semiconductor device, a voltage is applied to the source, which is then input into the second P-type semiconductor region, causing the second P-type semiconductor region to also have a corresponding voltage. This effectively shields the electric field of the gate dielectric at the bottom of the trench, thereby improving the robustness of the semiconductor device. In a specific implementation, P-type impurities such as boron (B), aluminum (Al), or gallium (Ga) can be implanted into the bottom of the first trench to form the second P-type semiconductor region. To improve the conductivity of the second P-type semiconductor region, the doping concentration of the second P-type semiconductor region can be higher. For example, the doping concentration of the second P-type semiconductor region can be greater than the doping concentration of the first P-type semiconductor region. For example, the thickness of the second P-type semiconductor region in the third direction can be less than 1 μm. For example, the thickness of the second P-type semiconductor region in the third direction can be 0.3 μm to 0.8 μm. Of course, the thickness of the second P-type semiconductor region in the third direction may also be greater than 1 μm, which is not limited here.

[0050] A first dielectric layer is deposited to fill each first trench and cover the surface of the epitaxial layer, and the first dielectric layer is patterned so that the pattern of the first dielectric layer is consistent with the pattern of the plurality of second trenches to be formed. For example, a photoresist layer can be formed on the surface of the first dielectric layer, and the photoresist layer is photolithographically processed using a mask having a pattern of the plurality of second trenches to be formed as a shield, thereby transferring the pattern on the mask to the photoresist layer. Then, the first dielectric layer is etched using the photoresist layer as a shield, thereby transferring the pattern of the plurality of second trenches to the first dielectric layer. The first dielectric layer can cover areas where second trenches are not required, while exposing areas where second trenches are required.

[0051] Using the first dielectric layer as a mask, the epitaxial layer is etched to form a plurality of second trenches extending along the second direction and arranged along the first direction. Since the first dielectric layer can cover the areas where the second trenches are not required, the areas where the second trenches are required are exposed. Therefore, by etching the areas of the epitaxial layer not covered by the first dielectric layer until the etching reaches the N-type semiconductor region of the epitaxial layer, a plurality of second trenches can be obtained. In an embodiment of the present application, the depth of each first trench can be greater than the depth of each second trench, thereby making the thickness of the subsequently formed first gate dielectric in the third direction greater than the thickness of the second gate dielectric in the third direction.

[0052] The first dielectric layer is removed.

[0053] In a possible implementation, the forming of the first gate and the first gate dielectric in the first trench and the forming of the second gate and the second gate dielectric in the second trench may specifically include:

[0054] A second dielectric layer is deposited to fill each first trench and each second trench and cover the surface of the epitaxial layer. The second dielectric layer is etched until the bottom surface of each second trench is exposed, and a portion of the second dielectric layer remains at the bottom of each first trench. The portion of the second dielectric layer remaining at the bottom of the first trench can serve as part of the first gate dielectric. In the embodiment of the present application, a back etching method is used to first form a portion of the first gate dielectric at the bottom of the first trench. In this way, the same process steps can be used to subsequently form the remaining first and second gate dielectrics, and the same process steps can also be used to form the first and second gates.

[0055] A first gate dielectric is formed on the sidewalls of each first trench, and a second gate dielectric is formed on the sidewalls of each second trench. For example, a deposition process or an oxidation process can be used to form the first gate dielectric (or second gate dielectric) on the sidewalls of the first trench (or second trench).

[0056] A gate layer is deposited to fill each first trench and each second trench and cover the surface of the epitaxial layer. The gate layer can be made of polysilicon or metal. The gate layer is then etched to the surface where it protrudes through the epitaxial layer, forming a first gate in each first trench and a second gate in each second trench. Using a back-etching process to form the first and second gates allows for more accurate gate filling within the trenches, avoiding underfilling or overfilling.

[0057] In some embodiments of the present application, after etching the epitaxial layer using the first dielectric layer as a mask to form a plurality of second trenches extending along the second direction and arranged along the first direction, and before removing the first dielectric layer, the following steps may be further included:

[0058] An ion implantation process is used to implant ions into the bottom of the second trench to form a third P-type semiconductor region on a side of the second trench close to the semiconductor substrate. For example, P-type impurities such as boron (B), aluminum (Al), or gallium (Ga) may be implanted into the bottom of the second trench to form the third P-type semiconductor region. In a specific implementation, to improve the conductivity of the third P-type semiconductor region, the doping concentration of the third P-type semiconductor region may be set to be higher. For example, the doping concentration of the third P-type semiconductor region may be greater than the doping concentration of the first P-type semiconductor region.

[0059] In one possible implementation, the thickness of the third P-type semiconductor region in the third direction can be less than 1 μm, and the thickness of the second P-type semiconductor region and the third P-type semiconductor region in the third direction can be approximately equal within the range of process error. In this way, the second P-type semiconductor region and the third P-type semiconductor region can be manufactured together using the same manufacturing process, thereby saving process steps and reducing manufacturing costs. In another possible implementation, the thickness of the third P-type semiconductor region in the third direction can also be greater than 1 μm, and the thickness of the third P-type semiconductor region in the third direction can be greater than the thickness of the second P-type semiconductor region in the third direction. During the manufacturing process, different process steps can be used to manufacture the second P-type semiconductor region and the third P-type semiconductor region respectively.

[0060] In a third aspect, embodiments of the present application further provide a power conversion circuit, which may be an AC-DC conversion circuit and / or a DC-DC conversion circuit. The power conversion circuit may include: a circuit board and one or more of the aforementioned semiconductor devices, wherein the semiconductor devices are connected to the circuit board. Due to the good performance of the aforementioned semiconductor devices, the power conversion circuit including the aforementioned semiconductor devices also has good performance.

[0061] The principle by which the power conversion circuit solves the problem is similar to the principle by which the aforementioned semiconductor device can solve the problem. Therefore, the technical effects of the power conversion circuit can refer to the technical effects of the aforementioned semiconductor device, and the repeated parts will not be repeated.

[0062] Fourthly, embodiments of the present application further provide a vehicle, comprising the power conversion circuit described above, wherein the power conversion circuit is configured to convert alternating current (AC) and / or direct current (DC) into DC power. Due to the superior performance of the power conversion circuit, the vehicle comprising the power conversion circuit also exhibits superior circuit performance.

[0063] The principle by which this vehicle solves the problem is similar to the principle by which the aforementioned power conversion circuit can solve the problem. Therefore, the technical effects of this vehicle can refer to the technical effects of the aforementioned power conversion circuit, and the repeated parts will not be repeated. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] FIG1 is a schematic structural diagram of an electric vehicle according to an embodiment of the present application;

[0065] FIG2 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

[0066] FIG3 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0067] FIG4 is a schematic cross-sectional view of the dashed line AA′ in FIG3 ;

[0068] FIG5 is a schematic diagram of a top view of the epitaxial layer in an embodiment of the present application;

[0069] FIG6 is a schematic top view of the structure of the interlayer dielectric layer in an embodiment of the present application;

[0070] FIG7 is a schematic diagram comparing characteristics of a semiconductor device in an embodiment of the present application with a semiconductor device in the prior art;

[0071] FIG8 is another schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0072] FIG9 is another schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0073] FIG10 is another schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0074] FIG11 is another schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0075] FIG12 is another schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0076] FIG13 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0077] Figures 14 to 24 are schematic structural diagrams corresponding to the steps of the manufacturing method provided in the embodiment of the present application;

[0078] FIG. 25 is a schematic structural diagram corresponding to the steps of manufacturing the third P-type semiconductor region.

[0079] Reference numerals:

[0080] 110-electric vehicle; 101-power conversion circuit; 1011-DC-DC converter; 102-battery; 103-load; 120-electronic device; 130-power supply; 10-semiconductor substrate; 20-epitaxial layer; 21-N-type semiconductor region; 211-first N-type semiconductor region; 212-second N-type semiconductor region; 213-third N-type semiconductor region; 22-first P-type semiconductor region; 23-source region; 24-P-type connection region; 25-second P-type semiconductor region; 26-third P-type semiconductor region; 31-first trench; 32-second trench; 301-first dielectric layer; 302-second dielectric layer; 41-first gate; 42-second gate; 51-first gate dielectric; 52-second gate dielectric; 60-interlayer dielectric layer; 61-contact hole; 70-source; 80-drain; x-first direction; y-second direction; z-third direction. DETAILED DESCRIPTION

[0081] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. It should be noted that the same figure marks in the drawings of the present application represent the same or similar structures, and thus their repeated descriptions will be omitted. The words expressing position and direction described in the present application are all explained with reference to the accompanying drawings as examples, but changes can be made as needed, and all changes are included in the scope of protection of the present application. The drawings of the present application are only used to illustrate the relative position relationship and do not represent the true proportion.

[0082] In the embodiments of the present application, the specific operating methods in the method embodiments may also be applied to the device embodiments or system embodiments. It should be noted that in the description of the present application, "multiple" refers to two or more, that is, "multiple" may be understood as "at least two". Words such as "first" and "second" are only used to distinguish the purpose of description and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. In addition, it should be pointed out that in the embodiments of the present application, "connection" refers to electrical connection, and the connection between two electrical elements may be a direct or indirect connection between the two electrical elements. For example, A is connected to B, which may be either A and B directly connected, or A and B indirectly connected through one or more other electrical elements, such as A is connected to B, or A is directly connected to C, C is directly connected to B, and A and B are connected through C.

[0083] It should be noted that the following description sets forth specific details to facilitate a full understanding of the present application. However, the present application can be implemented in a variety of ways other than those described herein, and those skilled in the art can make similar generalizations without violating the connotations of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below. The subsequent description of the specification is for the purpose of illustrating the preferred embodiments of the present application. However, the description is for the purpose of illustrating the general principles of the present application and is not intended to limit the scope of the present application.

[0084] In order to facilitate understanding of the semiconductor device, its manufacturing method, power conversion circuit and vehicle provided in the embodiments of the present application, the application scenarios of the present application are first introduced below.

[0085] The semiconductor device provided in the embodiment of the present application can be applied to vehicles, for example, electric vehicles. For example, the semiconductor device can be applied to components such as an on-board microcontroller unit (MCU) and an on-board battery charger (OBC) in a vehicle. It should be noted that the semiconductor device proposed in the embodiment of the present application is intended to include but is not limited to applications in these and any other suitable types of components. The following description will be made using an electric vehicle as an example.

[0086] FIG1 is a schematic diagram of the structure of an electric vehicle according to an embodiment of the present application. As shown in FIG1 , an electric vehicle 110 may include a power conversion circuit 101 and a battery 102 .

[0087] In one possible implementation, the power conversion circuit 101 may include an alternating current (AC) to direct current (DC) conversion circuit and a direct current (DC-DC) conversion circuit. The power conversion circuit 101 may also be referred to as an inverter. For example, when the electric vehicle 110 is charging, the electric vehicle 110 may be connected to a three-phase power grid and receive three-phase alternating current (AC) provided by the three-phase power grid. By controlling the operation of the power switch tubes of the AC-DC conversion circuit in the power conversion circuit 101, the AC-DC conversion circuit may convert the three-phase AC power into DC power. Furthermore, by controlling the operation of the power switch tubes of the DC-DC conversion circuit in the power conversion circuit 101, the DC-DC conversion circuit may regulate the voltage of the DC power output by the AC-DC conversion circuit, thereby providing voltage-adapted DC power to the battery 102. This allows the battery 102 to store the DC power, thereby achieving the charging function.

[0088] In another possible implementation, the power conversion circuit 101 may also be a DC-DC conversion circuit, and the electric vehicle 110 may further include a load 103, which may be an onboard device, a power system, or the like of the electric vehicle 110. By way of example, by controlling the operation of the power switch tubes of the DC-DC conversion circuit of the power conversion circuit 101, the power conversion circuit 101 can regulate the DC power output by the battery and output it to the load 103, thereby providing the load 103 with voltage-adapted DC power.

[0089] The semiconductor device provided in the embodiment of the present application can be a MOSFET device with a trench gate structure, which can improve the contradictory relationship between on-resistance and capacitance, thereby improving the performance of the semiconductor device. For example, the semiconductor device provided in the embodiment of the present application can be applied to the power conversion circuit 101 of the vehicle as a power switch tube in the AC-DC converter and / or DC-DC converter. Since the performance of the semiconductor device provided in the embodiment of the present application is good, when the semiconductor device is applied to the AC-DC converter and / or DC-DC converter, the performance of the AC-DC converter and / or DC-DC converter can be improved, thereby improving the performance of the entire circuit.

[0090] The semiconductor device provided in the embodiments of the present application can also be applied to various electronic devices, for example, electronic devices having logic devices or memory devices. For example, the electronic device can be a smart phone, a smart TV, a laptop computer, a personal digital assistant (PDA), a wearable device with wireless communication function (such as a smart watch, smart glasses, smart bracelet), etc. It should be noted that the semiconductor device proposed in the embodiments of the present application is intended to include but is not limited to application in these and any other suitable types of electronic devices.

[0091] FIG2 is a schematic diagram of the structure of an electronic device in an embodiment of the present application. As shown in FIG2 , the electronic device 120 provided in an embodiment of the present application may include a power conversion circuit 101 and a load 103, and the power conversion circuit 101 is electrically connected to the load 103. For example, the electronic device 120 can be any electrical device, for example, a smart phone, a smart TV, a laptop computer, a personal digital assistant (PDA), a wearable device with wireless communication function (such as a smart watch, smart glasses, a smart bracelet), an on-board microcontroller unit (MCU), an on-board battery charger (OBC), etc. It should be noted that the present application does not impose any restrictions on the specific type of electronic device.

[0092] In some embodiments, the power conversion circuit 101 may be a direct current (DC)-to-DC power conversion circuit, configured to step up or step down DC power and then output DC power to power the load 103. For example, the power conversion circuit 101 may convert the DC power (e.g., 48V) output by the power supply 130 into DC power suitable for all types of loads 103, and output the DC power to the load 103 for operation. This application does not impose any restrictions on the power supply 130 and the load 103. The power supply 130 may be any device or component capable of outputting DC power. For example, the power supply 130 may be a battery (e.g., a storage battery). The power conversion circuit 101 may receive the battery voltage provided by the battery, convert the battery voltage into an operating voltage for the load 103, and then output the voltage to the load 103. The load 103 may be any functional module that uses DC power, such as a processor, a chip, etc.

[0093] 2 , the power conversion circuit 101 may include a DC-DC converter 1011. During operation, the MOSFET in the DC-DC converter 1011 operates at a certain switching frequency, so that the DC-DC converter 1011 steps up or steps down the DC power from the power source 130 and outputs the step-up or step-down process to the load 103 to provide a DC power supply at an operating voltage. For example, the DC-DC converter 1011 may be a Buck converter, a Boost converter, a half-bridge converter, a full-bridge converter, or an inductor-inductor-capacitor (LLC) resonant converter.

[0094] The semiconductor device provided in the embodiment of the present application can be a MOSFET device having a trench gate structure, which can improve the contradictory relationship between on-resistance and capacitance, thereby improving the performance of the semiconductor device. For example, the semiconductor device provided in the embodiment of the present application can be applied to the DC-DC converter 1011 as a MOSFET in the DC-DC converter 1011. Since the device performance of the semiconductor device provided in the embodiment of the present application is good, when the semiconductor device is applied to the MOSFET in the DC-DC converter 1011, the performance of the DC-DC converter 1011 can be improved, thereby improving the performance of the entire electronic device.

[0095] It should be noted that the above scenario descriptions are merely examples of some possible applications of the semiconductor device of the present application. The present application does not limit the specific application scenarios of the semiconductor device provided in the embodiments of the present application, and the scenarios can be determined according to the actual application requirements.

[0096] The above introduces the application scenarios of the present application. The following, in conjunction with the accompanying drawings, describes in detail the specific implementation methods of the semiconductor device, its manufacturing method, power conversion circuit and vehicle provided in the embodiments of the present application.

[0097] FIG3 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application. As shown in FIG3 , the semiconductor device provided in an embodiment of the present application may include: an N-type semiconductor substrate 10, an epitaxial layer 20 disposed on the semiconductor substrate 10, and a first gate 41 and a second gate 42 connected to each other. The first gate 41 extends along a first direction x, and the second gate 42 extends along a second direction y. The first direction x and the second direction y are two directions parallel to the plane of the semiconductor substrate 10 and intersecting with each other. The first gate 41 and the second gate 42 are respectively located in different trenches within the epitaxial layer 20. For example, the first gate 41 may be located in the first trench 31, and the second gate 42 may be located in the second trench 32. A first gate dielectric 51 is filled between the first gate 41 and the first trench 31, isolating the first gate 41 from the second trench 32. A second gate dielectric 52 is filled between the second gate 42 and the second trench 32, isolating the second gate 42 from the second trench 32. In a direction perpendicular to the plane of the semiconductor substrate 10 (eg, the third direction z in the figure), the thickness of the first gate dielectric 51 is greater than the thickness of the second gate dielectric 52 .

[0098] The semiconductor device in the embodiment of the present application may be a SiC MOSFET device, and the semiconductor substrate 10 and epitaxial layer 20 may both comprise silicon carbide (SiC) material. The semiconductor substrate 10 may be a single-crystal silicon carbide substrate doped with a pentavalent element. The epitaxial layer 20 may comprise SiC material doped with corresponding impurities and may be fabricated using an epitaxial growth process.

[0099] It should be noted that in the various figures of the present application, in the layers or regions prefixed with N or P, it is indicated that electrons or holes are the majority carriers, respectively. In addition, the “+” marked on N or P indicates that the doping concentration is higher than the doping concentration of the layer or region not marked with +, and the more “+” there are, the higher the doping concentration. The fact that N or P with the same number of “+”s represent similar doping concentrations is not limited to the same doping concentration. In addition, the fact that “-” marked on N or P represents lower doping concentration than the doping concentration of the layer or region not marked with -, and the more “-” there are, the lower the doping concentration. The fact that N or P with the same number of “-”s represent similar doping concentrations is not limited to the same doping concentration. It should also be noted that the comparison of the doping concentrations of two regions in the present application only refers to the comparison of the concentrations of the impurities doped in the two regions, and does not limit the composition of the impurities or the substrate used to dope the impurities, that is, the composition of the impurities can be the same or different; the material of the substrate used to dope the impurities can be the same or different.

[0100] The semiconductor device in the embodiment of the present application is a SiC MOSFET device with a trench gate structure. By providing a plurality of trenches in the epitaxial layer 20 and providing a gate in the trench, the gate can be embedded in the interior of the epitaxial layer 20 so that the conductive channel direction of the semiconductor device is vertical, thereby increasing the conductive channel density of the semiconductor device and reducing the on-resistance. In addition, the semiconductor device in the embodiment of the present application includes: a first gate 41 and a second gate 42 connected to each other, the first gate 41 extending along a first direction x, and the second gate 42 extending along a second direction y, which can further increase the density of the conductive channel, thereby further reducing the on-resistance. In addition, in the embodiment of the present application, in the direction perpendicular to the plane of the semiconductor substrate 10, the thickness of the first gate dielectric 51 is greater than the thickness of the second gate dielectric 52. By providing a thicker first gate dielectric 51, the capacitance of the semiconductor device can be reduced, thereby improving the contradictory relationship between the on-resistance and capacitance, and improving the performance of the semiconductor device.

[0101] Figure 4 is a schematic cross-sectional view taken along dashed line AA′ in Figure 3 . Combining Figures 3 and 4 , the epitaxial layer 20 is provided with a plurality of first trenches 31 and a plurality of second trenches 32. Each first trench 31 extends along a first direction x and is aligned along a second direction y. Each second trench 32 extends along the second direction y and is aligned along the first direction x. Each first trench 31 and each second trench 32 intersects with each other. Each first trench 31 and each second trench 32 extends from the surface of the epitaxial layer 20 facing away from the semiconductor substrate 10 along a third direction z into the interior of the epitaxial layer 20. The third direction z is perpendicular to the plane of the semiconductor substrate 10. Optionally, the first direction x, the second direction y, and the third direction z may be mutually perpendicular. A first gate 41 is positioned within the first trench 31, and a second gate 42 is positioned within the second trench 32. For example, one first gate 41 may be positioned within each first trench 31, and one second gate 42 may be positioned within each second trench 32. A first gate dielectric 51 is filled between the first gate electrode 41 and the first trench 31, and the first gate electrode 41 is isolated from the first trench 31 by the first gate dielectric 51. A second gate dielectric 52 is filled between the second gate electrode 42 and the second trench 32, and the second gate electrode 42 is isolated from the second trench 32 by the second gate dielectric 52. The thickness of the first gate dielectric 51 in the third direction z is greater than the thickness of the second gate dielectric 52 in the third direction z.

[0102] That is to say, the first gate 41 is filled in the first trench 31 through the first gate dielectric 51, and the second gate 42 is filled in the second trench 32 through the second gate dielectric 52, so that the first gate 41 and the second gate 42 are embedded in the interior of the epitaxial layer 20, so that the semiconductor device in the embodiment of the present application constitutes a SiC MOSFET device with a trench structure.

[0103] In one possible implementation, the first gate 41 and the second gate 42 can be made of polysilicon, or can be made of a metal material such as tungsten (W), aluminum (Al), titanium (Ti), copper (Cu), molybdenum (Mo), or platinum (Pt). Of course, the first gate 41 and the second gate 42 can also be made of other materials with good conductive properties, which is not limited here.

[0104] In an embodiment of the present application, the semiconductor device may further include an interlayer dielectric layer 60, a source electrode 70, and a drain electrode 80. FIG5 is a schematic diagram of a top view of the epitaxial layer structure in an embodiment of the present application. The schematic diagram shown in FIG5 shows the surface of the epitaxial layer facing away from the semiconductor substrate. FIG6 is a schematic diagram of a top view of the interlayer dielectric layer structure in an embodiment of the present application. The schematic diagram shown in FIG6 is obtained by covering the epitaxial layer shown in FIG5 with the interlayer dielectric layer. Referring to FIG3, FIG5, and FIG6, the interlayer dielectric layer 60 covers the surface of the first gate 41 and the second gate 42 facing away from the semiconductor substrate 10. The interlayer dielectric layer 60 is provided with a plurality of contact holes 61. The orthographic projections of each contact hole 61 on the semiconductor substrate 10 do not overlap with the orthographic projections of the first gate 41 and the second gate 42 on the semiconductor substrate 10. The source electrode 70 is provided on the side of the interlayer dielectric layer 60 facing away from the semiconductor substrate 10. The source electrode 70 contacts the epitaxial layer 20 through each contact hole 61. The drain electrode 80 is located on the side of the semiconductor substrate 10 facing away from the epitaxial layer 20.

[0105] Comparing Figures 5 and 6 , it is apparent that the multiple contact holes 61 in the interlayer dielectric layer 60 can expose portions of the epitaxial layer 20, thereby allowing the source electrode 70 to contact the epitaxial layer 20 through the contact holes 61. Continuing with reference to Figures 3 , 5 , and 6 , the orthographic projections of the contact holes 61 on the semiconductor substrate 10 do not overlap with the orthographic projections of the first gate 41 and the second gate 42 on the semiconductor substrate 10, thereby preventing the source electrode 70 from contacting the first gate 41 and the second gate 42.

[0106] In one possible implementation, the interlayer dielectric layer 60 may include a dielectric material, which may include but is not limited to silicon dioxide (SiO2), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), silicon nitride (SiNx), etc. The source 70 and the drain 80 may be made of a metal material, which may include but is not limited to W, Al, Ti, Cu, Mo, or Pt, for example.

[0107] FIG7 is a schematic diagram showing a characteristic comparison of a semiconductor device in an embodiment of the present application and a semiconductor device in the prior art. As shown in FIG7 , the abscissa R represents on-resistance, the ordinate C represents capacitance, curve L1 is a characteristic curve of a semiconductor device in the prior art, and curve L2 is a characteristic curve of a semiconductor device in an embodiment of the present application. By comparing curves L1 and L2, it is apparent that curve L2 has a trend closer to the lower left corner than curve L1 (i.e., a trend with smaller on-resistance and capacitance). In other words, compared to curve L1, at the position of the same on-resistance, the capacitance of curve L2 is smaller, and at the position of the same capacitance, the on-resistance of curve L2 is also smaller. In this way, in the process of reducing on-resistance, the capacitance of curve L2 increases by a smaller amplitude, and the capacitance of the semiconductor device does not increase significantly due to an increase in trench density. Therefore, compared to the semiconductor device in the prior art, the semiconductor device in the embodiment of the present application can improve the contradictory relationship between on-resistance and capacitance, making both on-resistance and capacitance smaller, so as to make the performance of the semiconductor device better.

[0108] In one possible implementation, as shown in FIG3 , the depth of each first trench 31 can be greater than the depth of each second trench 32 . For example, in FIG3 , the depth difference between the first trench 31 and the second trench 32 can be h. The thickness of each first gate electrode 41 in the third direction z can be consistent with the thickness of each second gate electrode 42 in the third direction z. Thus, the thickness of the first gate dielectric 51 in the third direction z can be greater than the thickness of the second gate dielectric 52 in the third direction z. For example, in FIG3 , the thickness difference between the first gate dielectric 51 and the second gate dielectric 52 can also be h. The portion of the first gate dielectric 51 that is thicker than the second gate dielectric 52 can be disposed at the bottom of the first trench 31 to facilitate manufacturing.

[0109] The thickness of the first gate 41 and the second gate 42 in the third direction z is consistent, which means that the first gate 41 and the second gate 42 are equal within the process error range. During the manufacturing process, the first gate 41 and the second gate 42 can be manufactured using the same process, thereby saving process steps and reducing process costs. Of course, in some cases, when the first gate 41 and the second gate 42 are manufactured using different processes, the thickness of the first gate 41 and the second gate 42 in the third direction z can also be unequal, as long as the thickness of the first gate dielectric 51 in the third direction z is greater than the thickness of the second gate dielectric 52 in the third direction z.

[0110] In a specific implementation, the depths of the first trenches 31 can be equal within a process tolerance range. Thus, during the manufacturing process, the same process can be used to manufacture the first trenches 31. Similarly, the depths of the second trenches 32 can be equal within a process tolerance range. Thus, the same process can be used to manufacture the second trenches 32. This can save process steps and reduce process costs.

[0111] Continuing with Figure 3 , the spacing between two adjacent first grooves 31 in the second direction y is C2, and the spacing between two adjacent second grooves 32 in the first direction x is C1. In specific configurations, spacing C1 and spacing C2 can be set as needed. Spacing C1 can be greater than spacing C2; alternatively, spacing C1 can be equal to spacing C2; or alternatively, spacing C1 can be less than spacing C2. In some embodiments of the present application, the first grooves 31 can be arranged at equal or unequal intervals; and the second grooves 32 can be arranged at equal or unequal intervals.

[0112] In the embodiment of the present application, as shown in FIG3 , the epitaxial layer 20 may include an N-type semiconductor region 21 and a first P-type semiconductor region 22. The N-type semiconductor region 21 may be doped with N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As), and the first P-type semiconductor region 22 may be doped with P-type impurities such as boron (B), aluminum (Al), or gallium (Ga).

[0113] The first P-type semiconductor region 22 is located on a side of the N-type semiconductor region 21 facing away from the semiconductor substrate 10. Each of the first trenches 31 and the second trenches 32 penetrates the first P-type semiconductor region 22 in the third direction z and extends into the N-type semiconductor region 21. In this way, the first gate 41 and the second gate 42 can form a SiC MOSFET device having a trench gate structure with the first P-type semiconductor region 22 through the gate dielectric (the first gate dielectric 51 or the second gate dielectric 52).

[0114] In some embodiments of the present application, in conjunction with Figures 3, 5, and 6, the epitaxial layer 20 may further include a source region 23 and multiple P-type connection regions 24 disposed in the same layer. Each P-type connection region 24 corresponds to the location of a contact hole 61. The orthographic projection of the P-type connection region 24 on the semiconductor substrate 10 is located within the orthographic projection of the corresponding contact hole 61 on the semiconductor substrate 10. The P-type connection region 24 connects the first P-type semiconductor region 22 and the source electrode 70. The doping concentration of the P-type connection region 24 may be greater than the doping concentration of the first P-type semiconductor region 22 to improve the conductive performance of the P-type connection region 24. The source region 23 is the region of the layer in which the source region 23 is located, excluding the multiple first trenches 31, the multiple second trenches 32, and the multiple P-type connection regions 24. For example, a portion of the source region 23 may be covered by the interlayer dielectric layer 60, while another portion may be electrically connected to the source electrode 70.

[0115] During specific implementation, an ion implantation process may be used to implant N-type impurities such as nitrogen (N), phosphorus (P) or arsenic (As) into the region where the source region 23 is to be formed to form the source region 23, and to implant P-type impurities such as boron (B), aluminum (Al) or gallium (Ga) into the region where the P-type connection region 24 is to be formed to form the P-type connection region 24.

[0116] The first trench 31 (or the second trench 32) has a first P-type semiconductor region 22 on both sides of the second direction y (or the first direction x). During the operation of the semiconductor device, under the control of the first gate 41 (or the second gate 42), the first P-type semiconductor region 22 can form an N-type inversion channel, so that the source 70 passes through the conduction path of the source region 23, the first P-type semiconductor region 22, the N-type semiconductor region 21, and the semiconductor substrate 10 to achieve conduction with the drain 80.

[0117] In a specific implementation, the doping concentration of semiconductor substrate 10 is relatively high. For example, the doping concentration of semiconductor substrate 10 can be greater than the doping concentration of N-type semiconductor region 21. This improves the conductivity of semiconductor substrate 10, allowing semiconductor substrate 10 to serve as the drain region of the semiconductor device. The doping concentration of source region 23 is also relatively high. For example, the doping concentration of source region 23 can be greater than the doping concentration of N-type semiconductor region 21. This improves the conductivity of source region 23. This facilitates conduction between source electrode 70 and drain electrode 80 during operation of the semiconductor device, thereby reducing the on-resistance of the semiconductor device.

[0118] The semiconductor device in the embodiment of the present application is a SiC MOSFET device with a trench gate structure. At the bottom and corners of the first trench 31 and the second trench 32, the gate dielectric (first gate dielectric 51 or second gate dielectric 52) is subjected to high electric field strength during operation of the semiconductor device, becoming a weak point for electric field breakdown, which can easily cause the long-term reliability failure of the semiconductor device. As shown in Figure 3, in order to effectively shield the gate dielectric from high electric field stress, the epitaxial layer 20 in the embodiment of the present application can also include a second P-type semiconductor region 25. The second P-type semiconductor region 25 is located on the side of the first trench 31 close to the semiconductor substrate 10, and the second P-type semiconductor region 25 is electrically connected to the source 70. When the semiconductor device is working, the source 70 will be loaded with voltage. Since the second P-type semiconductor region 25 is electrically connected to the source 70, the voltage loaded on the source 70 will be input into the second P-type semiconductor region 25, so that the second P-type semiconductor region 25 also has a corresponding voltage, thereby effectively shielding the electric field of the gate dielectric at the bottom of the first trench 31 and the second trench 32, thereby improving the robustness of the semiconductor device.

[0119] Exemplarily, the thickness of the second P-type semiconductor region 25 in the third direction z can be less than 1 μm. For example, the thickness of the second P-type semiconductor region 25 in the third direction z can be 0.3 μm to 0.8 μm. Of course, the thickness of the second P-type semiconductor region 25 in the third direction z can also be greater than 1 μm, which is not limited here. Optionally, the second P-type semiconductor region 25 can be doped with P-type impurities such as boron (B), aluminum (Al) or gallium (Ga). In order to make the conductivity of the second P-type semiconductor region 25 better, the doping concentration of the second P-type semiconductor region 25 can be set to be larger. For example, the doping concentration of the second P-type semiconductor region 25 can be greater than the doping concentration of the first P-type semiconductor region 22.

[0120] In some application scenarios, the source 70 of the semiconductor device can be grounded, and the drain 80 can be electrically connected to other components. Since the second P-type semiconductor region 25 is electrically connected to the source 70, the voltage of the second P-type semiconductor region 25 is also the ground voltage (0V), thereby effectively shielding the electric field of the gate dielectric at the bottom of the first trench 31 and the second trench 32, thereby improving the robustness of the semiconductor device. In other application scenarios, the source 70 of the semiconductor device can be electrically connected to other components, and the drain 80 can also be electrically connected to other components. In this case, the voltage of the source 70 is the voltage of the input signal of the other component (which may not be 0). Since the second P-type semiconductor region 25 is electrically connected to the source 70, the voltage of the second P-type semiconductor region 25 is also the voltage of the input signal, which can also effectively shield the electric field of the gate dielectric at the bottom of the first trench 31 and the second trench 32, thereby improving the robustness of the semiconductor device.

[0121] Continuing with FIG. 3 , in one possible implementation, the N-type semiconductor region 21 may include a first N-type semiconductor region 211 and a second N-type semiconductor region 212. The second N-type semiconductor region 212 is located between the first N-type semiconductor region 211 and the first P-type semiconductor region 22. The doping concentration of the second N-type semiconductor region 212 is greater than the doping concentration of the first N-type semiconductor region 211. Each first trench 31 and each second trench 32 penetrates the second N-type semiconductor region 212 in the third direction z and extends into the first N-type semiconductor region 211. The second P-type semiconductor region 25 may be located in the first N-type semiconductor region 211.

[0122] The first N-type semiconductor region 211 and the second N-type semiconductor region 212 may both include N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As). The first N-type semiconductor region 211 has a relatively low doping concentration, which can improve the withstand voltage performance of the semiconductor device. The second N-type semiconductor region 212 has a relatively high doping concentration, which can reduce the on-resistance of the semiconductor device.

[0123] FIG8 is another schematic structural diagram of a semiconductor device provided in an embodiment of the present application. As shown in FIG8 , in another possible implementation, the N-type semiconductor region 21 may include a first N-type semiconductor region 211, a second N-type semiconductor region 212, and a third N-type semiconductor region 213. The second N-type semiconductor region 212 is located on a side of the first N-type semiconductor region 211 facing away from the semiconductor substrate 10, and the third N-type semiconductor region 213 is located between the first N-type semiconductor region 211 and the second N-type semiconductor region 212. The doping concentration of the second N-type semiconductor region 212 is greater than that of the first N-type semiconductor region 211, and the doping concentration of the third N-type semiconductor region 213 is greater than that of the first N-type semiconductor region 211. Each first trench and each second trench penetrates the second N-type semiconductor region 212 in the third direction and extends into the third N-type semiconductor region 213. The second P-type semiconductor region 25 is located in the third N-type semiconductor region 213.

[0124] The first N-type semiconductor region 211, the second N-type semiconductor region 212, and the third N-type semiconductor region 213 may all include N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As). The first N-type semiconductor region 211 has a relatively low doping concentration, which can improve the withstand voltage performance of the semiconductor device. The second N-type semiconductor region 212 has a relatively high doping concentration, which can reduce the on-resistance of the semiconductor device. Furthermore, the third N-type semiconductor region 213 has a relatively high doping concentration, which can further reduce the on-resistance of the semiconductor device.

[0125] FIG9 is another schematic structural diagram of a semiconductor device provided in an embodiment of the present application. As shown in FIG9 , in some other embodiments of the present application, the epitaxial layer 20 may further include: a third P-type semiconductor region 26, the third P-type semiconductor region 26 being located on a side of the second trench 32 close to the semiconductor substrate 10, and the third P-type semiconductor region 26 being electrically connected to the source 70. That is, compared to the semiconductor device shown in FIG3 , in the semiconductor device shown in FIG9 , a third P-type semiconductor region 26 is provided at the bottom of the second trench 32. That is, the second P-type semiconductor region 25 at the bottom of the first trench 31 and the third P-type semiconductor region 26 at the bottom of the second trench 32 are both electrically connected to the source 70. In this way, when the semiconductor device is working, the source 70 will be loaded with voltage. Since the second P-type semiconductor region 25 and the third P-type semiconductor region 26 are both electrically connected to the source 70, the voltage loaded on the source 70 will be input into the second P-type semiconductor region 25 and the third P-type semiconductor region 26, so that the second P-type semiconductor region 25 and the third P-type semiconductor region 26 also have corresponding voltages, thereby effectively shielding the electric field of the gate dielectric at the bottom of the first trench 31 and the second trench 32, further improving the robustness of the semiconductor device.

[0126] Optionally, the third P-type semiconductor region 26 may be doped with P-type impurities such as boron (B), aluminum (Al), or gallium (Ga). To improve the conductivity of the third P-type semiconductor region 26, the doping concentration of the third P-type semiconductor region 26 may be set to be higher. For example, the doping concentration of the third P-type semiconductor region 26 may be greater than the doping concentration of the first P-type semiconductor region 22.

[0127] In some application scenarios, the source 70 of the semiconductor device can be grounded, and the drain 80 can be electrically connected to other components. Since the second P-type semiconductor region 25 and the third P-type semiconductor region 26 are electrically connected to the source 70, the voltage of the second P-type semiconductor region 25 and the third P-type semiconductor region 26 is also at the ground voltage (0V), thereby effectively shielding the electric field of the gate dielectric at the bottom of the first trench 31 and the second trench 32, thereby improving the robustness of the semiconductor device. In other application scenarios, the source 70 of the semiconductor device can be electrically connected to other components, and the drain 80 can also be electrically connected to other components. In this case, the voltage of the source 70 is the voltage of the input signal of the other component (which may not be 0). Since the second P-type semiconductor region 25 and the third P-type semiconductor region 26 are electrically connected to the source 70, the voltage of the second P-type semiconductor region 25 and the third P-type semiconductor region 26 is also the voltage of the input signal, which can also effectively shield the electric field of the gate dielectric at the bottom of the first trench 31 and the second trench 32, thereby improving the robustness of the semiconductor device.

[0128] Continuing with reference to FIG9 , the thickness of the third P-type semiconductor region 26 in the third direction z can be less than 1 μm, and the thickness of the second P-type semiconductor region 25 and the third P-type semiconductor region 26 in the third direction z can be approximately equal within the range of process error. In this way, the second P-type semiconductor region 25 and the third P-type semiconductor region 26 can be manufactured together using the same manufacturing process, thereby saving process steps and reducing manufacturing costs.

[0129] FIG10 is another schematic structural diagram of a semiconductor device provided in an embodiment of the present application. As shown in FIG10 , the thickness of the third P-type semiconductor region 26 in the third direction z may also be greater than 1 μm, and the thickness of the third P-type semiconductor region 26 in the third direction z may be greater than the thickness of the second P-type semiconductor region 25 in the third direction z. During the manufacturing process, different process steps may be used to separately manufacture the second P-type semiconductor region 25 and the third P-type semiconductor region 26.

[0130] As shown in Figures 9 and 10, in one possible implementation, the N-type semiconductor region 21 may include a first N-type semiconductor region 211 and a second N-type semiconductor region 212. The second N-type semiconductor region 212 is located between the first N-type semiconductor region 211 and the first P-type semiconductor region 22. The doping concentration of the second N-type semiconductor region 212 is greater than the doping concentration of the first N-type semiconductor region 211. Each first trench 31 and each second trench 32 penetrates the second N-type semiconductor region 212 in the third direction z and extends into the first N-type semiconductor region 211. The second P-type semiconductor region 25 and the third P-type semiconductor region 26 are located in the first N-type semiconductor region 211.

[0131] The first N-type semiconductor region 211 and the second N-type semiconductor region 212 may both include N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As). The first N-type semiconductor region 211 has a relatively low doping concentration, which can improve the withstand voltage performance of the semiconductor device. The second N-type semiconductor region 212 has a relatively high doping concentration, which can reduce the on-resistance of the semiconductor device.

[0132] FIG11 is another schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application. In FIG11 , the thickness of the third P-type semiconductor region 26 in the third direction z is relatively small. For example, the thicknesses of the second P-type semiconductor region 25 and the third P-type semiconductor region 26 in the third direction z can be approximately equal within the range of process error. FIG12 is another schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application. In FIG12 , the thickness of the third P-type semiconductor region 26 in the third direction z is relatively large. For example, the thickness of the third P-type semiconductor region 26 in the third direction z can be greater than the thickness of the second P-type semiconductor region 25 in the third direction z.

[0133] As shown in Figures 11 and 12, in another possible implementation, the N-type semiconductor region 21 includes a first N-type semiconductor region 211, a second N-type semiconductor region 212, and a third N-type semiconductor region 213. The second N-type semiconductor region 212 is located on a side of the first N-type semiconductor region 211 facing away from the semiconductor substrate 10, and the third N-type semiconductor region 213 is located between the first N-type semiconductor region 211 and the third N-type semiconductor region 213. The doping concentration of the second N-type semiconductor region 212 is greater than that of the first N-type semiconductor region 211, and the doping concentration of the third N-type semiconductor region 213 is greater than that of the first N-type semiconductor region 211. Each first trench 31 and each second trench 32 penetrates the second N-type semiconductor region 212 in the third direction z and extends into the third N-type semiconductor region 213. The second P-type semiconductor region 25 and the third P-type semiconductor region 26 are located in the third N-type semiconductor region.

[0134] The first N-type semiconductor region 211, the second N-type semiconductor region 212, and the third N-type semiconductor region 213 may all include N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As). The first N-type semiconductor region 211 has a relatively low doping concentration, which can improve the withstand voltage performance of the semiconductor device. The second N-type semiconductor region 212 and the third N-type semiconductor region 213 have relatively high doping concentrations, which can reduce the on-resistance of the semiconductor device.

[0135] The above describes the basic structure of the semiconductor device in the embodiments of the present application. Based on the same technical concept, the embodiments of the present application also provide a method for manufacturing any of the above-mentioned semiconductor devices. Figure 13 is a flow chart of the method for manufacturing a semiconductor device provided in the embodiments of the present application, and Figures 14 to 24 are schematic diagrams of the structures corresponding to the steps in the manufacturing method provided in the embodiments of the present application.

[0136] 13 , taking the manufacturing of the semiconductor device shown in FIG. 3 as an example, the manufacturing method of the semiconductor device provided in the embodiment of the present application may include:

[0137] S91 , referring to FIG. 14 , growing an epitaxial layer 20 on an N-type semiconductor substrate 10 .

[0138] For example, the N-type semiconductor substrate 10 may be a silicon carbide single crystal substrate doped with pentavalent elements. An epitaxial process may be used to grow SiC material doped with N-type impurities on the semiconductor substrate 10 to obtain the epitaxial layer 20 .

[0139] In a possible implementation, step S91 may specifically include:

[0140] 15 , an N-type semiconductor region 21 is formed on a semiconductor substrate 10 using an epitaxial process, and ions are implanted into the N-type semiconductor region 21 using an ion implantation process to form a first P-type semiconductor region 22. For example, the N-type semiconductor region 21 may include N-type impurities such as nitrogen (N), phosphorus (P), or arsenic (As). P-type impurities such as boron (B), aluminum (Al), or gallium (Ga) may be implanted into the epitaxial layer 20 to form the P-type semiconductor region 22. In a specific implementation, an epitaxial process may be used to form a first N-type semiconductor region 211, and then N-type impurities are implanted into the surface of the first N-type semiconductor region 211 to form a second N-type semiconductor region 212 having a higher doping concentration on the surface of the first N-type semiconductor region 211.

[0141] Continuing with reference to Figure 15 , ions are implanted into the surface of the epitaxial layer 20 using an ion implantation process to form a source region 23 and multiple P-type connection regions 24 disposed in the same layer. Each P-type connection region 24 corresponds to the location of a contact hole to be formed, and the orthographic projection of the P-type connection region 24 on the semiconductor substrate 10 is located within the orthographic projection of the corresponding contact hole on the semiconductor substrate 10. The source region 23 is used to contact the subsequently formed source electrode. Generally, the doping concentration of the source region 23 is relatively high. For example, the doping concentration of the source region 23 can be greater than the doping concentration of the N-type semiconductor region 21 to improve the conductivity of the source region 23. The P-type connection region 24 is used to connect the first P-type semiconductor region 22 to the subsequently formed source electrode. The doping concentration of the P-type connection region 24 can be greater than the doping concentration of the first P-type semiconductor region 22 to improve the conductivity of the P-type connection region 24. During specific implementation, an ion implantation process may be used to implant N-type impurities such as nitrogen (N), phosphorus (P) or arsenic (As) into the region where the source region 23 is to be formed to form the source region 23, and to implant P-type impurities such as boron (B), aluminum (Al) or gallium (Ga) into the region where the P-type connection region 24 is to be formed to form the P-type connection region 24.

[0142] S92. Referring to Figures 16 to 20, the epitaxial layer 20 is etched to form first trenches 31 and second trenches 32. In some embodiments of the present application, the epitaxial layer 20 may include multiple first trenches 31 and multiple second trenches 32. Each first trench 31 extends along a first direction x and is arranged along a second direction y. Multiple second trenches 32 extend along the second direction y and are arranged along the first direction x. Each first trench 31 and each second trench 32 intersect each other. The first direction x and the second direction y are two directions parallel to the plane of the semiconductor substrate 10 and intersecting with each other. Each first trench 31 and each second trench 32 extends from the surface of the epitaxial layer 20 facing away from the semiconductor substrate 10 along a third direction z to the interior of the epitaxial layer 20. The third direction z is a direction perpendicular to the plane of the semiconductor substrate 10. By fabricating a channel structure including multiple first trenches 31 and multiple second trenches 32, the density of the conductive channel can be increased, thereby reducing the on-resistance of the semiconductor device.

[0143] In some embodiments of the present application, the above step S92 may specifically include:

[0144] 16 , the epitaxial layer 20 is etched to form a plurality of first trenches 31 extending along a first direction x and arranged along a second direction y. For example, a mask having a pattern consistent with the first trenches 31 can be formed on the epitaxial layer. This mask can be used to cover areas where the first trenches 31 are not required, while exposing areas where the first trenches 31 are required. An etching process is then used to etch the areas of the epitaxial layer 20 not covered by the mask until the etching reaches the N-type semiconductor region 21 of the epitaxial layer 20, thereby forming a plurality of first trenches 31.

[0145] 17 , an ion implantation process is used to implant ions into the bottom of the first trench 31 to form a second P-type semiconductor region 25 on a side of the first trench 31 near the semiconductor substrate 10. The second P-type semiconductor region 25 can be electrically connected to the source 70. When the semiconductor device is operating, a voltage is applied to the source 70. The voltage applied to the source 70 is input into the second P-type semiconductor region 25, causing the second P-type semiconductor region 25 to also have a corresponding voltage. This effectively shields the electric field of the gate dielectric at the bottom of the trench, thereby improving the robustness of the semiconductor device.

[0146] During specific implementation, P-type impurities such as boron (B), aluminum (Al) or gallium (Ga) may be implanted into the bottom of the first trench 31 to obtain the second P-type semiconductor region 25. In order to make the second P-type semiconductor region 25 have better conductivity, the doping concentration of the second P-type semiconductor region 25 may be larger. For example, the doping concentration of the second P-type semiconductor region 25 may be greater than the doping concentration of the first P-type semiconductor region 22. Exemplarily, the thickness of the second P-type semiconductor region 25 in the third direction z may be less than 1 μm. For example, the thickness of the second P-type semiconductor region 25 in the third direction z may be 0.3 μm to 0.8 μm. Of course, the thickness of the second P-type semiconductor region 25 in the third direction z may also be greater than 1 μm, which is not limited here.

[0147] Referring to FIG18 , a first dielectric layer 301 is deposited to fill each first trench 31 and cover the surface of the epitaxial layer 20. Referring to FIG19 , the first dielectric layer 301 is patterned so that the pattern of the first dielectric layer 301 is consistent with the pattern of the plurality of second trenches to be formed. For example, a photoresist layer can be formed on the surface of the first dielectric layer 301. Using a mask having a pattern of the plurality of second trenches to be formed as a shield, the photoresist layer is photolithographically processed, thereby transferring the pattern on the mask to the photoresist layer. Then, using the photoresist layer as a shield, the first dielectric layer 301 is etched, thereby transferring the pattern of the plurality of second trenches to the first dielectric layer 301. The first dielectric layer 301 can cover areas where the second trenches 32 are not required, while exposing areas where the second trenches 32 are required.

[0148] Continuing with FIG. 19 , the epitaxial layer 20 is etched using the first dielectric layer 301 as a mask to form a plurality of second trenches 32 extending along the second direction y and arranged along the first direction x. Since the first dielectric layer 301 can cover areas where the second trenches 32 are not required, while exposing areas where the second trenches 32 are required, a plurality of second trenches 32 can be formed by etching the areas of the epitaxial layer 20 not covered by the first dielectric layer 301 until the etching reaches the N-type semiconductor region 21 of the epitaxial layer 20.

[0149] In the embodiment of the present application, the depth of each first trench 31 may be greater than the depth of each second trench 32. For example, in FIG19 , the depth difference between the first trench 31 and the second trench 32 may be h. Thus, the thickness of the subsequently formed first gate dielectric in the third direction z may be greater than the thickness of the second gate dielectric in the third direction z.

[0150] The first dielectric layer is removed to obtain the structure shown in FIG. 20 .

[0151] S93. Referring to FIG. 21 to FIG. 23 , a first gate electrode 41 and a first gate dielectric 51 are formed in each first trench 31, and a second gate electrode 42 and a second gate dielectric 52 are formed in each second trench 32. Thus, the first gate electrode 41 is filled in the first trench 31 via the first gate dielectric 51, and the second gate electrode 42 is filled in the second trench 32 via the second gate dielectric 52, so that the first gate electrode 41 and the second gate electrode 42 are embedded in the epitaxial layer 20.

[0152] In a possible implementation, step S93 may specifically include:

[0153] Referring to Figure 21, a second dielectric layer 302 is deposited to fill each first trench 31 and each second trench 32 and cover the surface of the epitaxial layer 20. Referring to Figure 22, the second dielectric layer 302 is etched until the bottom surface of each second trench 32 is exposed, and a portion of the second dielectric layer 302 remains at the bottom of each first trench 31. The portion of the second dielectric layer 302 remaining at the bottom of the first trench 31 can serve as part of the first gate dielectric. In the embodiment of the present application, a back etching method is used to first form a portion of the first gate dielectric at the bottom of the first trench 31. In this way, the same process steps can be used to subsequently form the remaining first gate dielectric and second gate dielectric, and the same process steps can also be used to form the first gate and second gate.

[0154] 23 , a first gate dielectric 51 is formed on the sidewalls of each first trench 31, and a second gate dielectric 52 is formed on the sidewalls of each second trench 32. For example, the first gate dielectric 51 (or the second gate dielectric 52) can be formed on the sidewalls of the first trench 31 (or the second trench 32) by a deposition process or an oxidation process.

[0155] A gate layer (not shown) is deposited to fill each first trench 31 and each second trench 32 and cover the surface of the epitaxial layer 20. The gate layer can be made of polysilicon or metal. The gate layer is then etched to the surface where it protrudes from the epitaxial layer 20, forming a first gate 41 in each first trench 31 and a second gate 42 in each second trench 32. Using a back-etching process to form the first and second gates 41, 42 allows for more accurate filling of the trenches with gates, avoiding underfilling or overfilling.

[0156] S94. Continuing with reference to FIG. 23 , an interlayer dielectric layer 60 is formed on the first gate 41 and the second gate 42. Referring to FIG. 24 , the interlayer dielectric layer 60 is patterned to form a plurality of contact holes 61 in the interlayer dielectric layer 60. The orthographic projection of each contact hole 61 on the semiconductor substrate 10 does not overlap with the orthographic projection of the first gate 41 and the second gate 42 on the semiconductor substrate 10. The plurality of contact holes 61 in the interlayer dielectric layer 60 can expose a portion of the epitaxial layer 20, so that the source electrode formed subsequently can contact the epitaxial layer 20 through each contact hole 61. Furthermore, the orthographic projection of each contact hole 61 on the semiconductor substrate 10 does not overlap with the orthographic projection of the first gate 41 and the second gate 42 on the semiconductor substrate 10, thereby preventing the source electrode 70 from contacting the first gate 41 and the second gate 42.

[0157] For example, the interlayer dielectric layer 60 may be made of dielectric materials such as silicon dioxide (SiO 2 ), silicon oxynitride (SiNO), silicon oxycarbide (SiCO), and silicon nitride (SiNx).

[0158] S95. Form a source electrode 70 on the interlayer dielectric layer 60, and make the source electrode 70 contact the epitaxial layer 20 through the contact holes 61. Also, form a drain electrode 80 on the side of the semiconductor substrate 10 facing away from the epitaxial layer 20, thereby obtaining the semiconductor device shown in FIG3. For example, the source electrode 70 and the drain electrode 80 can be made of metal materials such as W, Al, Ti, Cu, Mo, or Pt.

[0159] The semiconductor device shown in FIG3 is used as an example to describe in detail the method for fabricating the semiconductor device in the embodiment of the present application. Compared to the semiconductor device shown in FIG3 , in the semiconductor devices shown in FIG9 and FIG10 , the epitaxial layer 20 may further include a third P-type semiconductor region 26 . The third P-type semiconductor region 26 is located on a side of the second trench 32 close to the semiconductor substrate 10 , and the third P-type semiconductor region 26 is electrically connected to the source 70 .

[0160] Different from the manufacturing method of the semiconductor device shown in FIG3 , the manufacturing method of the semiconductor device shown in FIG9 and FIG10 can be adjusted as follows:

[0161] FIG25 is a schematic structural diagram corresponding to the step of forming the third P-type semiconductor region. Referring to FIG25 , in the above step S92, after etching the epitaxial layer using the first dielectric layer as a mask to form a plurality of second trenches extending along the second direction and arranged along the first direction, before removing the first dielectric layer, the following steps may also be included:

[0162] An ion implantation process is used to implant ions into the bottom of the second trench 32 to form a third P-type semiconductor region 26 on a side of the second trench 32 close to the semiconductor substrate 10 .

[0163] For example, P-type impurities such as boron (B), aluminum (Al), or gallium (Ga) may be implanted into the bottom of the second trench 32 to form the third P-type semiconductor region 26. In a specific implementation, to improve the conductivity of the third P-type semiconductor region 26, the doping concentration of the third P-type semiconductor region 26 may be set to be higher. For example, the doping concentration of the third P-type semiconductor region 26 may be greater than the doping concentration of the first P-type semiconductor region 22.

[0164] In one possible implementation, the thickness of the third P-type semiconductor region 26 in the third direction z can be less than 1 μm, and the thickness of the second P-type semiconductor region 25 and the third P-type semiconductor region 26 in the third direction z can be approximately equal within the range of process error. In this way, the second P-type semiconductor region 25 and the third P-type semiconductor region 26 can be manufactured together using the same manufacturing process, thereby saving process steps and reducing manufacturing costs.

[0165] In another possible implementation, the thickness of the third P-type semiconductor region 26 in the third direction z may also be greater than 1 μm, and the thickness of the third P-type semiconductor region 26 in the third direction z may be greater than the thickness of the second P-type semiconductor region 25 in the third direction z. During the manufacturing process, different process steps may be used to manufacture the second P-type semiconductor region 25 and the third P-type semiconductor region 26 respectively.

[0166] The remaining steps in the method for manufacturing the semiconductor device shown in FIG. 9 and FIG. 10 may be performed with reference to the method for manufacturing the semiconductor device shown in FIG. 3 , and the repeated parts are not repeated here.

[0167] In addition, the manufacturing methods of the semiconductor devices shown in FIG. 8 , FIG. 11 and FIG. 12 may also be performed with reference to the above-mentioned manufacturing methods, or may be adjusted accordingly according to the above-mentioned manufacturing methods, which will not be described one by one here.

[0168] Based on the same technical concept, embodiments of the present application also provide a power conversion circuit, which may be an AC-DC conversion circuit and / or a DC-DC conversion circuit. The power conversion circuit may include: a circuit board and one or more of the above-mentioned semiconductor devices, wherein the semiconductor devices are connected to the circuit board. Due to the good performance of the above-mentioned semiconductor devices, the power conversion circuit including the above-mentioned semiconductor devices also has good performance.

[0169] The principle by which the power conversion circuit solves the problem is similar to the principle by which the aforementioned semiconductor device can solve the problem. Therefore, the technical effects of the power conversion circuit can refer to the technical effects of the aforementioned semiconductor device, and the repeated parts will not be repeated.

[0170] Based on the same technical concept, embodiments of the present application further provide a vehicle, comprising the power conversion circuit described above. The power conversion circuit is configured to convert alternating current (AC) and / or direct current (DC) into DC power and output DC power. Due to the superior performance of the power conversion circuit, the vehicle comprising the power conversion circuit also exhibits superior circuit performance.

[0171] The principle by which this vehicle solves the problem is similar to the principle by which the aforementioned power conversion circuit can solve the problem. Therefore, the technical effects of this vehicle can refer to the technical effects of the aforementioned power conversion circuit, and the repeated parts will not be repeated.

[0172] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0173] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application also intends to include such modifications and variations.

Claims

1. A semiconductor device, characterized in that: include: N-type semiconductor substrate; An epitaxial layer, disposed on the semiconductor substrate; A first gate and a second gate connected to each other, the first gate extending along a first direction, the second gate extending along a second direction, the first direction and the second direction being two directions parallel to the plane where the semiconductor substrate is located and intersecting with each other; The first gate and the second gate are respectively located in different trenches in the epitaxial layer; A first gate dielectric is filled between the first gate and the trench, and the first gate is isolated from the trench by the first gate dielectric; a second gate dielectric is filled between the second gate and the trench, and the second gate is isolated from the trench by the second gate dielectric; In a direction perpendicular to a plane where the semiconductor substrate is located, a thickness of the first gate dielectric is greater than a thickness of the second gate dielectric.

2. The semiconductor device according to claim 1, wherein A plurality of first trenches and a plurality of second trenches are provided in the epitaxial layer; the plurality of first trenches extend along the first direction and are arranged along the second direction, the plurality of second trenches extend along the second direction and are arranged along the first direction, and the plurality of first trenches and the plurality of second trenches intersect each other; the plurality of first trenches and the plurality of second trenches extend from a surface of the epitaxial layer away from the semiconductor substrate along a third direction to the interior of the epitaxial layer; The third direction is a direction perpendicular to the plane where the semiconductor substrate is located; The first gate is located in the first trench, and the second gate is located in the second trench.

3. The semiconductor device according to claim 2, wherein: The depth of each of the first grooves is greater than the depth of each of the second grooves; The thickness of each of the first grid electrodes in the third direction is consistent with the thickness of each of the second grid electrodes in the third direction.

4. The semiconductor device according to claim 2, wherein: The epitaxial layer includes: an N-type semiconductor region, a first P-type semiconductor region and a second P-type semiconductor region; The first P-type semiconductor region is located on a side of the N-type semiconductor region away from the semiconductor substrate; The plurality of first trenches and the plurality of second trenches penetrate the first P-type semiconductor region in the third direction and extend into the N-type semiconductor region; The second P-type semiconductor region is located at a side of the first trench close to the semiconductor substrate, and the second P-type semiconductor region is electrically connected to the source.

5. The semiconductor device according to claim 4, wherein: The N-type semiconductor region includes: a first N-type semiconductor region and a second N-type semiconductor region; The second N-type semiconductor region is located between the first N-type semiconductor region and the first P-type semiconductor region; The doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region; The plurality of first trenches and the plurality of second trenches penetrate the second N-type semiconductor region in the third direction and extend into the first N-type semiconductor region; The second P-type semiconductor region is located in the first N-type semiconductor region.

6. The semiconductor device according to claim 4, wherein: The N-type semiconductor region includes: a first N-type semiconductor region, a second N-type semiconductor region and a third N-type semiconductor region; The second N-type semiconductor region is located at a side of the first N-type semiconductor region away from the semiconductor substrate, and the third N-type semiconductor region is located between the first N-type semiconductor region and the second N-type semiconductor region; The doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region, and the doping concentration of the third N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region; The plurality of first trenches and the plurality of second trenches penetrate the second N-type semiconductor region in the third direction and extend into the third N-type semiconductor region; The second P-type semiconductor region is located in the third N-type semiconductor region.

7. The semiconductor device according to claim 4, wherein: The epitaxial layer further includes: a third P-type semiconductor region; The third P-type semiconductor region is located on a side of the second trench close to the semiconductor substrate, and the third P-type semiconductor region is electrically connected to the source.

8. The semiconductor device according to claim 7, wherein: The N-type semiconductor region includes: a first N-type semiconductor region and a second N-type semiconductor region; The second N-type semiconductor region is located between the first N-type semiconductor region and the first P-type semiconductor region; The doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region; The plurality of first trenches and the plurality of second trenches penetrate the second N-type semiconductor region in the third direction and extend into the first N-type semiconductor region; The second P-type semiconductor region and the third P-type semiconductor region are located in the first N-type semiconductor region.

9. The semiconductor device according to claim 7, wherein: The N-type semiconductor region includes: a first N-type semiconductor region, a second N-type semiconductor region and a third N-type semiconductor region; The second N-type semiconductor region is located at a side of the first N-type semiconductor region away from the semiconductor substrate, and the third N-type semiconductor region is located between the first N-type semiconductor region and the third N-type semiconductor region; The doping concentration of the second N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region, and the doping concentration of the third N-type semiconductor region is greater than the doping concentration of the first N-type semiconductor region; The plurality of first trenches and the plurality of second trenches penetrate the second N-type semiconductor region in the third direction and extend into the third N-type semiconductor region; The second P-type semiconductor region and the third P-type semiconductor region are located in the third N-type semiconductor region.

10. The semiconductor device according to any one of claims 4 to 9, characterized in that: The semiconductor device further comprises: an interlayer dielectric layer, the interlayer dielectric layer covering the surface of the first gate and the second gate facing away from the semiconductor substrate, the interlayer dielectric layer being provided with a plurality of contact holes; the orthographic projections of the plurality of contact holes on the semiconductor substrate not overlapping with the orthographic projections of the first gate and the second gate on the semiconductor substrate; A source electrode, the source electrode being arranged on a side of the interlayer dielectric layer away from the semiconductor substrate; the source electrode being in contact with the epitaxial layer through the plurality of contact holes; A drain electrode is located on a side of the semiconductor substrate away from the epitaxial layer.

11. The semiconductor device according to claim 10, wherein: The epitaxial layer further comprises: a source region and a plurality of P-type connection regions arranged in the same layer; Each of the P-type connection regions corresponds to a position of the contact hole, an orthographic projection of the P-type connection region on the semiconductor substrate is located within the range of an orthographic projection of the corresponding contact hole on the semiconductor substrate, and the P-type connection region connects the first P-type semiconductor region and the source electrode; The source region is a layer where the source region is located except for the plurality of first trenches, the plurality of second trenches and the plurality of P Area outside the type connection area.

12. The semiconductor device according to claim 11, wherein A portion of the source region is covered by the interlayer dielectric layer, and another portion is electrically connected to the source electrode.

13. A method for manufacturing a semiconductor device according to any one of claims 1 to 12, characterized in that: include: Growing an epitaxial layer on an N-type semiconductor substrate; Etching the epitaxial layer to form a first trench and a second trench; A first gate and a first gate dielectric are formed in the first trench, and a second gate and a second gate dielectric are formed in the second trench; wherein, in a direction perpendicular to the plane where the semiconductor substrate is located, the thickness of the first gate dielectric is greater than the thickness of the second gate dielectric.

14. The method according to claim 13, characterized in that: The step of growing an epitaxial layer on an N-type semiconductor substrate comprises: Forming an N-type semiconductor region on the semiconductor substrate by an epitaxial process, and implanting ions into the N-type semiconductor region by an ion implantation process to form a first P-type semiconductor region; An ion implantation process is used to implant ions into the surface of the epitaxial layer to form a source region and multiple P-type connection regions arranged in the same layer; wherein each of the P-type connection regions corresponds to the position of a contact hole to be formed, and the orthographic projection of the P-type connection region on the semiconductor substrate is located within the range of the orthographic projection of the corresponding contact hole on the semiconductor substrate.

15. The production method according to claim 13 or 14, characterized in that: The step of etching the epitaxial layer to form a first trench and a second trench comprises: Etching the epitaxial layer to form the plurality of first trenches extending along a first direction and arranged along a second direction; the first direction and the second direction are two directions parallel to the plane where the semiconductor substrate is located and intersecting with each other; Depositing a first dielectric layer filling each of the first trenches and covering the surface of the epitaxial layer, and patterning the first dielectric layer so that a pattern of the first dielectric layer is consistent with a pattern of the plurality of second trenches to be formed; Using the first dielectric layer as a mask, etching the epitaxial layer to form the plurality of second trenches extending along the second direction and arranged along the first direction; The first dielectric layer is removed.

16. The method of claim 15, wherein: After etching the epitaxial layer to form the plurality of first trenches extending along the first direction and arranged along the second direction, and before depositing a first dielectric layer filling the first trenches and covering the surface of the epitaxial layer, the method further includes: An ion implantation process is used to implant ions into the bottom of the first trench to form a second P-type semiconductor region on a side of the first trench close to the semiconductor substrate.

17. The method of claim 15, wherein: After the epitaxial layer is etched using the first dielectric layer as a mask to form the plurality of second trenches extending along the second direction and arranged along the first direction, and before the first dielectric layer is removed, the method further includes: An ion implantation process is used to implant ions into the bottom of the second trench to form a third P-type semiconductor region on a side of the second trench close to the semiconductor substrate.

18. The method according to any one of claims 13 to 17, characterized in that: The forming of a first gate and a first gate dielectric in the first trench, and forming a second gate and a second gate dielectric in the second trench, comprises: Depositing a second dielectric layer filling each of the first trenches and each of the second trenches and covering the surface of the epitaxial layer; The second dielectric layer is etched until the bottom surface of each second groove is exposed, and a second dielectric layer is formed in each first groove. a bottom remaining portion of the second dielectric layer; forming a first gate dielectric on a sidewall of each of the first trenches, and forming a second gate dielectric on a sidewall of each of the second trenches; Depositing a gate layer that fills each of the first trenches and each of the second trenches and covers the surface of the epitaxial layer; The gate layer is etched to a surface where the epitaxial layer is exposed, so as to form the first gate in each of the first trenches and to form the second gate in each of the second trenches.

19. The method according to any one of claims 13 to 18, characterized in that: The production method further comprises: An interlayer dielectric layer is formed on the first gate and the second gate, and the interlayer dielectric layer is patterned to form a plurality of contact holes in the interlayer dielectric layer; the orthographic projections of the plurality of contact holes on the semiconductor substrate do not overlap with the orthographic projections of the first gate and the second gate on the semiconductor substrate; A source electrode is formed on the interlayer dielectric layer, and the source electrode is in contact with the epitaxial layer through the plurality of contact holes; and a drain electrode is formed on a side of the semiconductor substrate away from the epitaxial layer.

20. A power conversion circuit, characterized in that: The invention comprises a circuit board and one or more semiconductor devices according to any one of claims 1 to 12, wherein the semiconductor device is connected to the circuit board.

21. A vehicle, characterized in that: It includes the power conversion circuit as described in claim 20, wherein the power conversion circuit is used to convert alternating current and / or direct current and then output direct current.

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