Test method and system, terminal equipment and storage medium
By inputting a dedicated signal for each test channel and comparing its frequency characteristics, the problem of test inaccuracy caused by QTMU line connection errors was solved, achieving efficient and accurate multi-channel chip testing.
Patent Information
- Application Number
- CN202511233040.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-28
- Publication Date
- 2025-11-28
AI Technical Summary
In existing technologies, QTMU line connection errors during multi-station synchronous test simulation lead to inaccurate test results. There is a lack of effective detection methods, which affects the reliability and efficiency of chip testing.
By inputting a dedicated signal to each test channel, receiving the corresponding signal and performing targeted comparisons, and utilizing frequency characteristics for fault testing, the accuracy and independence of signal transmission are ensured, enabling multi-channel parallel testing.
It improves the efficiency and accuracy of chip testing, can accurately locate channel faults, and avoids misjudgments caused by inter-channel interference.
Smart Images
Figure CN121027791A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of chip testing technology, and in particular relates to testing methods, systems, terminal equipment and readable storage media. Background Technology
[0002] In the field of chip testing technology, multi-station synchronous test simulation is often used to improve chip testing efficiency. In this mode, multiple QTMU lines need to be connected between the tester and the test board to measure time-related parameters (such as signal frequency, duty cycle, etc.). However, due to the large number of QTMU lines, connection errors are very easy to occur when wiring manually. Such errors may cause test component mixing problems, which will seriously affect the accuracy of chip test results.
[0003] The relevant technologies lack effective methods to detect whether the QTMU wiring is correct, making it impossible to prevent test errors caused by incorrect wiring connections in advance, and making it difficult to guarantee the reliability and efficiency of chip testing. Summary of the Invention
[0004] This application provides a testing method, system, terminal device, and storage medium that performs parallel testing on multiple test channels, thereby improving testing efficiency and enabling precise location of channel faults.
[0005] In a first aspect, embodiments of this application provide a testing method applied to a testing device in a testing system. The testing system further includes a device under test, which includes at least one first channel. The method includes:
[0006] Input the corresponding first signal to the input terminal of at least one first channel;
[0007] Each of the corresponding second signals is received at the output of at least one first channel;
[0008] The first channel is tested for faults based on the first and second signals corresponding to each first channel.
[0009] In this embodiment, by inputting a dedicated first signal for each first channel, receiving a corresponding second signal, and performing targeted comparison, it is possible to achieve parallel testing of multiple channels to improve testing efficiency. Furthermore, by conducting independent correlation analysis of the "input-output" signals, it is possible to accurately locate the faults of each channel and avoid misjudgments caused by interference between channels. While ensuring the accuracy of testing, it significantly improves the detection efficiency and effectiveness of the testing system for multi-channel devices.
[0010] In one possible implementation of the first aspect, the step of inputting a corresponding first signal to the input terminal of each first channel includes:
[0011] Set a first frequency corresponding to the first channel; wherein the first frequency conforms to the transmission frequency of the signal of the first channel;
[0012] A first signal corresponding to the first channel is generated according to the first frequency;
[0013] Input the first signal to the input terminal of the first channel.
[0014] In this embodiment of the application, by setting a first frequency that conforms to the transmission frequency of the first channel and generating and inputting a corresponding first signal, the matching between the input signal and the channel characteristics is ensured, providing an accurate reference signal for subsequent fault testing.
[0015] In one possible implementation of the first aspect, the device under test further includes a second channel and a first device corresponding to each first channel; the output terminal of the second channel corresponding to the first channel is connected to the input terminal of the first device corresponding to the first channel, and the output terminal of the first device corresponding to the first channel is connected to the input terminal of the first channel; inputting a first signal to the input terminal of the first channel includes:
[0016] The first device corresponding to the first channel is controlled to change from a first state to a second state, so as to connect the second channel and the first channel;
[0017] A first signal is input to the input terminal of the second channel corresponding to the first channel, so that the first signal is input to the input terminal of the first channel through the second channel.
[0018] In this embodiment of the application, by controlling the first device to connect the second channel to the first channel and input the first signal through the second channel, the controllable switching of the signal transmission path is realized, which not only ensures the accuracy of the first signal input, but also provides a reliable signal transmission foundation for subsequent fault testing of the first channel.
[0019] In one possible implementation of the first aspect, the step of performing a fault test on the first channel based on the first signal and the second signal corresponding to each first channel includes:
[0020] By performing feature analysis on the second signal, the second frequency corresponding to the second signal is obtained;
[0021] The first channel is tested for faults based on the first frequency and the second frequency.
[0022] In this embodiment of the application, by extracting the second frequency of the second signal and comparing it with the first frequency, accurate fault determination based on frequency characteristics is achieved, providing a clear and reliable basis for fault testing of the first channel.
[0023] In one possible implementation of the first aspect, fault testing of the first channel is performed based on a first frequency and a second frequency, including:
[0024] Calculate the error between the first frequency and the second frequency;
[0025] If the error is within the preset range, it is determined that the first channel has not malfunctioned;
[0026] If the error is not within the preset range, then the first channel is determined to be faulty.
[0027] In this embodiment of the application, by calculating and comparing whether the error between the first frequency and the second frequency is within a preset range, a quantitative judgment of the fault of the first channel is realized, which not only ensures the objectivity of the judgment standard, but also improves the accuracy of fault identification.
[0028] Secondly, embodiments of this application provide a testing system, including a testing device and a device under test, wherein the device under test includes at least one first channel;
[0029] The testing apparatus is used to implement the testing method as described in any of the first aspects above, to perform fault testing on each first channel.
[0030] In one possible implementation of the second aspect, the testing apparatus includes a signal generation device and a signal acquisition device corresponding to each first channel;
[0031] The signal generating device is used to set a first frequency corresponding to the first channel; generate a first signal corresponding to the first channel according to the first frequency; and input the first signal to the input terminal of the first channel; wherein the first frequency conforms to the transmission frequency of the signal of the first channel;
[0032] The signal acquisition device is used to acquire the second signal output from the output terminal of the first channel corresponding to the signal acquisition device.
[0033] In one possible implementation of the second aspect, the test apparatus includes a signal control device corresponding to each first channel, and the device under test also includes a second channel and a first device corresponding to each first channel.
[0034] For each first channel, the output of the second channel corresponding to the first channel is connected to the input of the first device corresponding to the first channel; the output of the first device corresponding to the first channel is connected to the input of the first channel.
[0035] The signal control device corresponding to the first channel is used to control the first device corresponding to the first channel to change from the first state to the second state, so as to conduct the first channel and its corresponding second channel.
[0036] Thirdly, embodiments of this application provide a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the test method as described in any of the first aspects above.
[0037] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the test method as described in any of the first aspects above.
[0038] Fifthly, embodiments of this application provide a computer program product that, when run on a terminal device, causes the terminal device to execute any of the testing methods described in the first aspect above.
[0039] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description
[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 This is a schematic diagram of the structure of the testing system provided in the embodiments of this application;
[0042] Figure 2 This is a flowchart illustrating the testing method provided in an embodiment of this application;
[0043] Figure 3 This is a schematic diagram of the process of inputting the first signal provided in the embodiments of this application. Figure 1 ;
[0044] Figure 4 This is a schematic diagram of the process of inputting the first signal provided in the embodiments of this application. Figure 2 ;
[0045] Figure 5 This is a schematic diagram of the structure of the device under test provided in an embodiment of this application;
[0046] Figure 6 This is a schematic diagram of the fault testing process provided in an embodiment of this application;
[0047] Figure 7 This is a schematic diagram of the test device structure provided in the embodiments of this application. Figure 1 ;
[0048] Figure 8 This is a schematic diagram of the test device structure provided in the embodiments of this application. Figure 2 ;
[0049] Figure 9This is a schematic diagram of the overall structure of the testing method provided in the embodiments of this application;
[0050] Figure 10 This is a schematic diagram of the structure of the terminal device provided in the embodiments of this application. Detailed Implementation
[0051] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.
[0052] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.
[0053] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0054] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."
[0055] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0056] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized.
[0057] In the field of chip testing technology, multi-station synchronous test simulation is often used to improve chip testing efficiency. In this mode, multiple QTMU lines need to be connected between the tester and the test board to measure time-related parameters (such as signal frequency, duty cycle, etc.). However, due to the large number of QTMU lines, connection errors are very easy to occur when wiring manually. Such errors may cause test component mixing problems, which will seriously affect the accuracy of chip test results.
[0058] The relevant technologies lack effective methods to detect whether the QTMU wiring is correct, making it impossible to prevent test errors caused by incorrect wiring connections in advance, and making it difficult to guarantee the reliability and efficiency of chip testing.
[0059] To address the problems in the aforementioned related technologies, this application addresses the issue of test material mixing caused by errors in manual wiring of QTMU lines during multi-station synchronous testing. It utilizes the FOVI100 resource board to generate preset frequency waveforms (e.g., 1kHz, 2kHz, 3kHz, and 4kHz for four stations), which are then connected to the QTMU board (channel A) via relay control. The QTMU continuously detects each channel for 20ms, sampling 10 times to obtain the actual frequency. This is compared to the preset frequency range for each station (e.g., 1kHz corresponds to 0.9kHz-1.1kHz). If the frequency is within the range, testing continues; otherwise, testing is terminated. This method allows for parallel testing of multiple test channels, improving testing efficiency and enabling precise fault location within each channel.
[0060] See Figure 1 This is a schematic diagram of the structure of the testing system provided in the embodiments of this application, as shown below. Figure 1 As shown, it includes a testing device and a device under test, wherein the device under test includes a first channel.
[0061] Among them, the core of the device under test refers to the "QTMU line between the tester and the test board" that needs to be verified to ensure the correctness of the wiring, as well as the interface circuit on the test board that is connected to the QTMU line; the device under test includes the first channel, which is the measurement channel corresponding to the QTMU resource board. The QTMU board has 4 groups of channels (each group contains A and B channels). Frequency measurement only uses the A channel and 1 group of channels corresponds to 1 station. Therefore, the "first channel" is the QTMU A channel of each station (e.g., 4 stations correspond to 4 first channels).
[0062] See Figure 2 This is a flowchart illustrating the testing method provided in an embodiment of this application. It is applied to a testing device within a testing system. The testing system also includes a device under test, which includes at least one first channel. This is an example, not a limitation. The method may include the following steps:
[0063] S101, input the corresponding first signal to the input terminal of at least one first channel.
[0064] In this embodiment, the first signal refers to a signal uniquely matched to each "first channel" and possessing distinctive characteristics (such as different frequencies). Each channel corresponds to only one dedicated signal, and the signal characteristics must meet the judgment criteria for subsequent testing (such as the frequency being within a specific measurable range). The testing device (tester) in the testing system accurately transmits the signal exclusively configured for each "first channel" to the signal receiving end of that channel according to a one-to-one correspondence, providing a basic reference for subsequent judgment of whether the QTMU line wiring is correct through signal detection.
[0065] S102, receiving the corresponding second signal at the output of at least one first channel.
[0066] In this embodiment, the second signal refers to the actual signal output from the output terminal of the first channel after the first signal has been transmitted through the first channel (the QTMU line and supporting circuit to be tested). Since the transmission status of the first channel (such as whether the QTMU wiring is correct and whether the line is unobstructed) directly affects the signal transmission result, the second signal is the "actual result signal" after the first signal has been transmitted through the channel.
[0067] Each "first channel" output corresponds to only one "second signal." Specifically, the output of the "first channel" at station 1 corresponds to the "second signal" transmitted through that channel, and the output of the "first channel" at station 2 corresponds to the "second signal" transmitted through that channel. This ensures that the signal transmission result of each channel can be traced independently, avoiding signal confusion between multiple channels. The testing device is directly connected to the output of the first channel (QTMU A channel) through relevant acquisition interfaces to acquire the "second signal" output by each "first channel."
[0068] S103, perform fault testing on the first channel based on the first signal and the second signal corresponding to each first channel.
[0069] In this embodiment, for each first channel consisting of the QTMU line to be tested and its matching interface circuit, a first signal with specific frequency characteristics that was previously input to that channel is used as a reference. The second signal obtained from the output after the first signal is transmitted through the channel is compared with the first signal to determine whether there is a fault in the first channel. This achieves foolproof verification (fault detection) of key links such as QTMU wiring.
[0070] In the above method, by inputting a dedicated first signal for each first channel, receiving the corresponding second signal, and performing targeted comparison, it is possible to achieve parallel testing of multiple channels to improve testing efficiency. At the same time, it is possible to accurately locate the faults of each channel through independent correlation analysis of the "input-output" signals, avoiding misjudgments caused by interference between channels. While ensuring the accuracy of testing, it significantly improves the detection efficiency and effectiveness of the testing system for multi-channel devices.
[0071] In one embodiment, see Figure 3 This is a flowchart illustrating the input of the first signal provided in an embodiment of this application. Figure 1 ,like Figure 3 As shown, step S101, which involves inputting the corresponding first signal to the input terminal of each first channel, includes:
[0072] S201, Set the first frequency corresponding to the first channel; wherein, the first frequency conforms to the transmission frequency of the signal of the first channel.
[0073] In the embodiments of this application, the "first frequency" is a reference frequency value individually assigned to each "first channel" for verifying the correctness of the line connection. Each "first channel" is matched with only one unique "first frequency," and the "first frequencies" of different "first channels" are not repeated and have no overlapping ranges. For example, the "first channels" of the four workstations in the patent correspond to "first frequencies" of 1KHz, 2KHz, 3KHz, and 4KHz, respectively, ensuring that the frequency identification of each channel is independent and avoiding subsequent detection misjudgments.
[0074] The first frequency must be within the range of signal measurement frequencies of the test device's detection components, such as 0.1Hz-10MHz. Therefore, the "first frequency" must fall within this range to ensure that the signal can be transmitted stably in the "first channel" and can be accurately acquired and calculated by the test device's detection components.
[0075] S202, Generate the first signal corresponding to the first channel according to the first frequency.
[0076] In this embodiment, a unique first frequency with no frequency range overlap is set for each first channel (for example, the first channels of the four workstations correspond to 1KHz, 2KHz, 3KHz, and 4KHz respectively). Then, the signal generation module in the test device generates a waveform signal with the frequency attribute (the waveform can be a sine wave, a triangle wave, etc.) according to the first frequency corresponding to each first channel, and finally obtains a unique first signal for each first channel, which is prepared for the subsequent input of the signal into the channel and the QTMU wiring error-proof verification.
[0077] S203, input the first signal to the input terminal of the first channel.
[0078] In this embodiment, the test device conducts the signal transmission path and then accurately transmits the first signal with specific frequency characteristics, which is exclusively generated for the first channel (the QTMU line to be tested and the corresponding measurement channel), to the starting port of the channel receiving signals, so that the signal can be transmitted along the line to be tested, laying the foundation for subsequent judgment of whether the line is normal by detecting the output signal.
[0079] In the above method, by setting a first frequency that conforms to the transmission frequency of the first channel and generating and inputting a corresponding first signal, the matching between the input signal and the channel characteristics is ensured, providing an accurate reference signal for subsequent fault testing.
[0080] In one embodiment, the device under test further includes a second channel and a first device corresponding to each first channel; the output terminal of the second channel corresponding to the first channel is connected to the input terminal of the first device corresponding to the first channel, and the output terminal of the first device corresponding to the first channel is connected to the input terminal of the first channel; see also Figure 4 This is a flowchart illustrating the input of the first signal provided in an embodiment of this application. Figure 2 ,like Figure 4 As shown, step S203 includes:
[0081] S301, control the first device corresponding to the first channel to change from the first state to the second state, so as to connect the second channel and the first channel.
[0082] In the embodiments of this application, see Figure 5 This is a schematic diagram of the structure of the device under test provided in an embodiment of this application, as shown below. Figure 5 As shown, the device under test consists of not only the first channel (the core of which is the QTMU line and measurement channel to be verified), but also a "second channel" and a "first device" that are matched with each first channel. The three have a clear connection relationship: the signal output terminal of the second channel corresponding to the first channel is connected to the signal input terminal of the first device matched with the first channel; and the signal output terminal of the first device is further connected to the signal input terminal of the corresponding first channel, forming a signal transmission link of "second channel → first device → first channel", which provides a hardware connection basis for subsequent error-proof verification through multi-stage signal transmission.
[0083] When the first device (such as a relay) is in the first state (usually the open state), the signal transmission path between the second channel and the first channel is not connected. Through control commands or signal triggering, the first device is switched from the first state to the second state (usually the closed state). At this time, the output of the second channel forms a conductive signal path through the first device and the input of the first channel, ensuring that the signal can be transmitted from the second channel through the first device to the first channel, providing a physical connection basis for subsequent signal transmission and detection. If the first device is a relay, this process involves controlling the relay to identify energization (or de-energization), causing its contacts to switch from open (first state) to closed (second state), thereby connecting the circuit.
[0084] S302, input a first signal to the input terminal of the second channel corresponding to the first channel, so that the first signal is input to the input terminal of the first channel through the second channel.
[0085] In this embodiment, the first signal generated specifically for the first channel is first sent to the signal input of the second channel that is associated with the first channel. At this time, since the first device (such as a relay) has switched from the first state to the second state (closed state), a conduction path of "second channel → first device → first channel" is formed. Therefore, the first signal input to the second channel will be transmitted sequentially along this path and finally reach the input end of the first channel, realizing the effective transmission of the signal from the second channel to the first channel, laying the foundation for the subsequent transmission and detection of the signal through the first channel.
[0086] In the above method, by controlling the first device to connect the second channel to the first channel and input the first signal through the second channel, the controllable switching of the signal transmission path is realized, which not only ensures the accuracy of the first signal input, but also provides a reliable signal transmission foundation for subsequent fault testing of the first channel.
[0087] In one embodiment, see Figure 6 This is a schematic diagram of the fault testing process provided in the embodiments of this application, such as... Figure 6 As shown, step S103, which involves performing a fault test on the first channel based on the first signal and the second signal corresponding to each first channel, includes:
[0088] S401, Perform feature analysis on the second signal to obtain the second frequency corresponding to the second signal.
[0089] In this embodiment of the application, the second signal obtained from the output end of the first channel after the first signal is transmitted through the "second channel → first device → first channel" focuses on its key features (i.e. frequency) for detection and calculation.
[0090] The second signal is sampled and processed by the testing device (e.g., continuous detection for 20ms and sampling 10 times to reduce errors). The actual frequency attribute of the signal during transmission is extracted, and the actual frequency value is finally determined and recorded as the second frequency corresponding to the second signal. This provides key actual data basis for subsequent comparison with the first frequency of the first signal and for judging whether the channel is faulty.
[0091] S402, perform fault testing on the first channel based on the first frequency and the second frequency.
[0092] In this embodiment, the first frequency of the first signal (a reference frequency specifically set for the first channel) is used as a reference, and the second frequency (the actual detected frequency) corresponding to the second signal obtained after the first signal is transmitted is used. The correlation and comparison of the two are used to determine whether there is a fault in the first channel, thereby completing the foolproof verification of the first channel.
[0093] In the above method, by extracting the second frequency of the second signal and comparing it with the first frequency, accurate fault determination based on frequency characteristics is achieved, providing a clear and reliable basis for fault testing of the first channel.
[0094] In one embodiment, step S402 includes:
[0095] Calculate the error between the first frequency and the second frequency; if the error is within a preset range, it is determined that the first channel is not faulty; if the error is not within the preset range, it is determined that the first channel is faulty.
[0096] In this embodiment of the application, the numerical deviation (i.e., error) between the first frequency (the reference frequency set for the first channel) and the second frequency (the actual detection frequency of the second signal) is obtained by the specific execution module of the test system. Then, the error is compared with the acceptable error range (e.g., ±0.1KHz) preset in the scheme. If the calculated error falls within this preset range, it indicates that the frequency of the first signal has not shifted abnormally after transmission through the channel, thus determining that the first channel has not failed. If the error exceeds the preset range, it indicates that there is a problem in the signal transmission process, thus determining that the first channel has failed.
[0097] In the above method, by calculating and comparing whether the error between the first frequency and the second frequency is within a preset range, the quantitative judgment of the fault of the first channel is realized, which not only ensures the objectivity of the judgment standard, but also improves the accuracy of fault identification.
[0098] This application provides a testing system, including a testing device and a device under test, wherein the device under test includes at least one first channel; the testing device is used to implement the testing method as described in any of the above testing steps, so as to perform fault testing on each first channel.
[0099] In one embodiment, see Figure 7 This is a schematic diagram of the test device structure provided in the embodiments of this application. Figure 1 ,like Figure 7 As shown, the testing device includes a signal generation device and a signal acquisition device for each first channel; the signal generation device is used to set the first frequency corresponding to the first channel; generate the first signal corresponding to the first channel according to the first frequency; and input the first signal to the input terminal of the first channel; wherein the first frequency conforms to the transmission frequency of the signal of the first channel; the signal acquisition device is used to acquire the second signal output by the output terminal of the first channel corresponding to the signal acquisition device.
[0100] In this embodiment, the testing apparatus further includes a signal generation device, which can be an FOVI100 resource board. This device has an AWG (arbitrary waveform generator) function and can generate a specified waveform. The FOVI100 has 8 channels, and one channel is typically used. Generally, one workstation will occupy the 8 channels of one FOVI100 board. With multiple workstations, there will be multiple FOVI100 resource boards. It can be understood that one FOVI100 resource board corresponds to one workstation. The FOVI100 can generate waveform signals with corresponding frequency characteristics (such as sine waves, triangle waves, and square waves, which do not affect frequency testing).
[0101] The testing setup also includes a signal acquisition device, which is a QTMU board. QTMU stands for Time Measurement Unit, capable of measuring frequency. One QTMU resource board has four measurement channels, each with two channels: A and B. Only channel A is used when measuring frequency. Channels A and B are typically used for measuring time differences and are not needed here. Generally, one channel is used for one workstation, so four channels are used for four workstations. The first channel, formed by connecting the QTMU line to the workstation under test, outputs a second signal after the first signal is transmitted via "FOVI100 → Relay → First Channel." Channel A of the QTMU board receives this second signal.
[0102] The FOVI100 and QTMU collaborate through a "signal generation-transmission-acquisition" link: the FOVI100 generates and inputs a first signal that meets the requirements of the first channel. After the signal is transmitted through the first channel, it becomes a second signal. The QTMU board then accurately acquires this second signal. Together, they form an "input-output" signal closed loop, providing complete signal data support for subsequent frequency comparison to determine the fault of the first channel.
[0103] In one embodiment, see Figure 8 This is a schematic diagram of the test device structure provided in the embodiments of this application. Figure 2 ,like Figure 8 As shown, the testing device includes a signal control device corresponding to each first channel, and the device under test also includes a second channel and a first device corresponding to each first channel. For each first channel, the output terminal of the second channel corresponding to the first channel is connected to the input terminal of the first device corresponding to the first channel. The output terminal of the first device corresponding to the first channel is connected to the input terminal of the first channel. The signal control device corresponding to the first channel is used to control the first device corresponding to the first channel to change from a first state to a second state, so as to turn on the first channel and its corresponding second channel.
[0104] In this embodiment of the application, the testing device also includes a signal control device, which can be a CBIT128 resource board. The CBIT128 outputs a control signal and provides a +5V power supply to drive the relay contacts to close, so that the output terminal of the second channel forms a conduction path with the input terminal of the first channel through the relay (first device).
[0105] Only after the CBIT128 controls the first device to switch to the second state (path on) can the first signal generated by the FOVI100 resource board be transmitted to the input terminal of the first channel via the second channel and the first device (closed relay). This provides a physical path for the subsequent signal transmission of the first channel and the signal acquisition (acquiring the second signal) of the QTMU board. This is a key step in the "signal transmission link construction" in the QTMU line foolproof verification.
[0106] See Figure 9 This is a schematic diagram of the overall structure of the testing method provided in the embodiments of this application, as shown below. Figure 9 As shown, a foolproof verification scheme is constructed with the STS8200 test machine as the core, and equipped with QTMU resource board (frequency detection), FOVI100 resource board (signal generation), and CBIT128 resource board (relay control).
[0107] By assigning a unique first frequency to each workstation's corresponding first channel (e.g., for 4 workstations, four first channels correspond to 1KHz, 2KHz, 3KHz, and 4KHz; the attached diagram only shows a schematic of one channel), a 5V amplitude waveform signal (first signal) is generated by the FOVI100. This signal is then controlled by the CBIT128 to activate the relay (channel 0) and input to the QTMU circuit (first channel). The QTMU board continuously monitors for 20ms and samples 10 times to obtain the second signal corresponding to the second frequency. The first frequency is compared with the second frequency (e.g., 1KHz corresponds to the 0.9KHz-1.1KHz control range). If the frequency exceeds the range, the test is terminated. This method helps to troubleshoot wiring faults and improves test reliability.
[0108] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0109] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0110] Figure 10 This is a schematic diagram of the structure of the terminal device provided in the embodiments of this application. For example... Figure 10 As shown, the terminal device 10 of this embodiment includes: at least one processor 100 ( Figure 10 (Only one is shown) a processor, a memory 101, and a computer program 102 stored in the memory 101 and executable on at least one processor 100, wherein the processor 100 executes the computer program 102 to implement the steps in any of the above test method embodiments.
[0111] The terminal device can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. This terminal device may include, but is not limited to, a processor and memory. Those skilled in the art will understand that... Figure 10 This is merely an example of terminal device 10 and does not constitute a limitation on terminal device 10. It may include more or fewer components than shown, or combine certain components, or different components, such as input / output devices, network access devices, etc.
[0112] The processor 100 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.
[0113] In some embodiments, memory 101 may be an internal storage unit of terminal device 10, such as a hard disk or memory of terminal device 10. In other embodiments, memory 101 may be an external storage device of terminal device 10, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on terminal device 10. Furthermore, memory 101 may include both internal and external storage units of terminal device 10. Memory 101 is used to store operating system, applications, boot loader, data, and other programs, such as program code of computer programs. Memory 101 can also be used to temporarily store data that has been output or will be output.
[0114] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the steps in the above-described method embodiments.
[0115] This application provides a computer program product that, when run on a terminal device, enables the terminal device to implement the steps described in the various method embodiments above.
[0116] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. A computer-readable medium can include at least: any entity or device capable of carrying computer program code to a device / terminal equipment, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.
[0117] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0118] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0119] In the embodiments provided in this application, it should be understood that the disclosed apparatus / terminal devices and methods can be implemented in other ways. For example, the apparatus / terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.
[0120] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0121] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A testing method, characterized in that, A test apparatus applied to a test system, the test system further comprising a device under test, the device under test including at least one first channel, the method comprising: Input a corresponding first signal to at least one input terminal of the first channel; At least one of the output terminals of the first channel receives its corresponding second signal. The first channel is tested for faults based on the first signal and the second signal corresponding to each first channel.
2. The test method as described in claim 1, characterized in that, The step of inputting the corresponding first signal to the input terminal of each of the first channels includes: Set a first frequency corresponding to the first channel; wherein the first frequency conforms to the transmission frequency of the signal of the first channel; Generate a first signal corresponding to the first channel according to the first frequency; The first signal is input to the input terminal of the first channel.
3. The test method as described in claim 1, characterized in that, The device under test also includes a second channel and a first device corresponding to each of the first channels; the output terminal of the second channel corresponding to the first channel is connected to the input terminal of the first device corresponding to the first channel, and the output terminal of the first device corresponding to the first channel is connected to the input terminal of the first channel; The step of inputting the first signal to the input terminal of the first channel includes: Control the first device corresponding to the first channel to change from a first state to a second state, so as to connect the second channel and the first channel; The first signal is input to the input terminal of the second channel corresponding to the first channel, so that the first signal is input to the input terminal of the first channel through the second channel.
4. The test method as described in claim 2, characterized in that, The steps for performing fault testing on the first channel based on the first signal and the second signal corresponding to each first channel include: Perform feature analysis on the second signal to obtain the second frequency corresponding to the second signal; The first channel is tested for faults based on the first frequency and the second frequency.
5. The test method as described in claim 4, characterized in that, The fault test of the first channel based on the first frequency and the second frequency includes: Calculate the error between the first frequency and the second frequency; If the error is within the preset range, then it is determined that the first channel has not malfunctioned; If the error is not within the preset range, then the first channel is determined to be faulty.
6. A testing system, characterized in that, It includes a testing apparatus and a device under test, wherein the device under test includes at least one first channel; The testing apparatus is used to implement the testing method as described in any one of claims 1-5 above, to perform fault testing on each of the first channels.
7. The testing system as described in claim 6, characterized in that, The testing device includes a signal generation device and a signal acquisition device for each of the first channels; The signal generating device is used to set a first frequency corresponding to the first channel; generate a first signal corresponding to the first channel according to the first frequency; and input the first signal to the input terminal of the first channel; wherein the first frequency conforms to the transmission frequency of the signal of the first channel; The signal acquisition device is used to acquire the second signal output from the output terminal of the first channel corresponding to the signal acquisition device.
8. The testing system as described in claim 7, characterized in that, The testing device includes a signal control device corresponding to each of the first channels, and the device under test also includes a second channel and a first device corresponding to each of the first channels. For each of the first channels, the output of the second channel corresponding to the first channel is connected to the input of the first device corresponding to the first channel; the output of the first device corresponding to the first channel is connected to the input of the first channel. The signal control device corresponding to the first channel is used to control the first device corresponding to the first channel to change from a first state to a second state, so as to turn on the first channel and its corresponding second channel.
9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 5.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 7.