Programmable capacitive load and test system

Abstract

The invention discloses a programmable capacitive load and a test system, and relates to the technical field of power electronics, the programmable capacitive load comprises a first connecting end, a second connecting end and at least two parallel capacitor branches, one end of all the parallel capacitor branches is used as the first connecting end, and the other end of all the parallel capacitor branches is used as the second connecting end. The other ends of all the capacitor branches are used as the second connecting end after the capacitor branches are connected in parallel, the at least two capacitor branches connected in parallel have gears which are arranged from high to low and are in one-to-one correspondence, and the gear capacitance values corresponding to the adjacent gears are in a preset multiple number relation; each capacitance branch comprises a plurality of sub-branches which are arranged in parallel and have capacitance values, the sub-branches can be switched on or switched off, the programmable capacitance load can solve the problems that a capacitance load in the prior art is complex in structure and poor in capacitance adjusting precision, wide-range and high-precision capacitance value combination is achieved, and the programmable capacitance load is high in practicability. The bandwidth testing requirements of different chips and different testing environments can be met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronics, and particularly relates to a programmable capacitance load and a test system. BACKGROUND

[0002] Chip bandwidth refers to the amount of data or rate that can be processed by the chip within a certain time. The test of bandwidth is a key test item of the chip, and the test of chip bandwidth usually needs to be carried out under different load capacitance conditions. By observing the signal transmission characteristics of the chip under different capacitance values, the bandwidth range of stable work is determined. Therefore, the capacitance load with flexible adjustment capacity becomes an indispensable key device in the chip test link. The capacitance load scheme in the related art generally has problems such as large size, complicated operation, limited capacitance value range and the like. SUMMARY

[0003] The present application provides a programmable capacitance load and a test system to at least solve one or more of the problems of large size, complicated circuit design, inconvenient use and high cost of the programmable capacitance load in the related art.

[0004] In a first aspect, the present application provides a programmable capacitance load, which comprises a first connection end and a second connection end, and further comprises at least two parallel capacitance branches, one end of all the parallel capacitance branches is the first connection end, and the other end of all the parallel capacitance branches is the second connection end, the at least two parallel capacitance branches have one-to-one corresponding gears arranged from high to low, and the gear capacitance values corresponding to adjacent gears are a preset multiple; Each of the capacitance branches comprises a plurality of parallelly arranged sub-branches with capacitance values, and the sub-branches can be turned on or turned off.

[0005] In a second aspect, the present application further provides a test system, which comprises: a test device, and the programmable capacitance load of the first aspect of the present application, one of the first interface and the second interface of the programmable capacitance load is connected to a ground wire, the other of the first interface and the second interface of the programmable capacitance load is connected to the test device and a product to be tested.

[0006] The programmable capacitance load of the present application adopts a multi-gear parallel capacitance branch structure, each capacitance branch has different gears, and each capacitance branch works independently and does not interfere with each other. The on-off state of the plurality of sub-branches of each capacitance branch is controlled, so that the capacitance value of the capacitance branch changes, and the different capacitance value design of the programmable capacitance load is further realized. Therefore, the programmable capacitance load of the present application can solve the problems of complex capacitance load structure and poor capacitance adjustment precision in related art, realize wide range and high precision capacitance value combination, and the capacitance value adjustment is simple and can adapt to the bandwidth test requirements of different chips. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0008] Figure 1 Circuit schematic diagram of a related art adjustable capacitance box; Figure 2 Circuit schematic diagram of a substrate capacitance circuit unit of a related art programmable capacitance load; Figure 3 Circuit schematic diagram of a programmable capacitance load composed of a plurality of basic capacitance circuit units of related art; Figure 4 Circuit structure schematic diagram of a programmable capacitance load provided by an embodiment of the present application is shown; Figure 5 Circuit structure schematic diagram of a programmable capacitance load of an optional embodiment of the present application is shown; Figure 6 Conduction schematic diagram of a programmable capacitance load of an example of the present application is shown; Figure 7 Product structure schematic diagram of a programmable capacitance load of another optional embodiment of the present application is shown; Figure 8 Architecture schematic diagram of a test system provided by the present application is shown. DETAILED DESCRIPTION

[0009] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0010] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0011] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0012] Chip bandwidth refers to the amount or rate at which a chip can process data within a certain time. Bandwidth testing is a critical test item for chips. Chip bandwidth testing usually needs to be carried out under different load capacitance conditions. By observing the signal transmission characteristics of the chip under different capacitance values, its stable operating bandwidth range can be determined. Therefore, a capacitive load with flexible adjustment capability has become an indispensable key component in the chip testing process.

[0013] In related technologies, commonly used capacitive load solutions are mainly divided into two categories: one is an adjustable capacitive load, such as an adjustable capacitor bank. Figure 1 As shown, the capacitor box uses capacitors 131' with different capacitance values ​​connected in parallel, and switches (K1'~K7') control the on / off state of the capacitors to adjust the capacitance value. However, this type of capacitor box has significant drawbacks: it is bulky, occupies a lot of space, and is inconvenient to move and carry; the manufacturing cost is high, especially for the selection and assembly of high-precision capacitors, which further increases the equipment cost; at the same time, the adjustable capacitance value range of this capacitor box is limited, making it difficult to meet the fine-grained requirements for special capacitance values ​​in chip testing.

[0014] Another type of adjustable capacitive load is a programmable capacitive load, where the on / off state of the capacitor connection line is controlled by an external voltage level. A basic capacitor circuit unit 100 can then have different capacitance values. For example,... Figure 2 As shown, two switches (K1' and K2', K3' and K4') are added to each of the two stages of capacitor 131'. The switching on and off of each switch is controlled by a voltage level, giving the basic capacitor circuit unit 100 four capacitance values. Furthermore, this basic capacitor circuit unit 100 can be connected in series or parallel to create a programmable capacitor load 10', as shown... Figure 3 As shown, controlling different switching states of different basic capacitor circuit units 100 can achieve more capacitance value adjustments.

[0015] However, this type of programmable capacitive load requires external circuitry to control the switching of each node, for example... Figure 3The programmable capacitive load 10' shown requires a control circuit with at least 16 switches, making its application complex. Multiple circuit node switches need to be adjusted to obtain the desired capacitance value. Therefore, programmable capacitive loads of this technology require specialized control chips and drive circuits to function, increasing both the difficulty and cost of equipment development and cumbersome operation. Users need to adjust the switching states of multiple circuit nodes to obtain the target capacitance value, significantly impacting testing efficiency. Furthermore, the capacitance adjustment accuracy of this type of programmable capacitive load is easily affected by parasitic parameters of the electronic switches, making it difficult to guarantee the accuracy of test data.

[0016] Furthermore, adjustable capacitors are used for multiple tests in some scenarios. However, the capacitance adjustment range of adjustable capacitors is narrow, typically only allowing for fine-tuning within a small range, which cannot meet the wide range of capacitance values ​​required for chip testing, ranging from a few picofarads to several thousand picofarads. At the same time, adjustable capacitors have low adjustment precision and poor capacitance stability, making them susceptible to environmental factors such as temperature and humidity, leading to significant deviations in test results. Therefore, they are unsuitable for chip performance testing scenarios with high precision requirements.

[0017] Existing capacitive load solutions generally suffer from problems such as large size, high cost, cumbersome operation, insufficient adjustment accuracy, and limited capacitance value range, failing to fully meet the current testing industry's demand for efficient, accurate, and flexible capacitive load devices. Therefore, developing a programmable capacitive load that is simple in structure, low in cost, easy to adjust, and reliable in accuracy has become an urgent technical challenge to be solved in this field.

[0018] In view of this, this application proposes a programmable capacitive load, a test system, a method, an electronic device, a storage medium, and a computer program product to solve one or more of the above problems.

[0019] The first embodiment of this application proposes a programmable capacitor load, such as Figure 4 As shown, the programmable capacitor load 10 includes a first connection terminal 11 and a second connection terminal 12. The programmable capacitor load 10 also includes at least two parallel capacitor branches 13. One end of all the capacitor branches 13 connected in parallel is used as the first connection terminal 11, and the other end of all the capacitor branches 13 connected in parallel is used as the second connection terminal 12. At least two parallel capacitor branches 13 have corresponding levels arranged from high to low, and the capacitance values ​​of adjacent levels are a preset multiple. In other words, the levels of adjacent capacitor branches 13 are different and are a preset multiple. Each capacitor branch 13 includes multiple sub-branches 13A connected in parallel, each with a capacitance value. The sub-branches 13A are either turned on or off.

[0020] The programmable capacitive load 10 of this application adopts a structure of multi-level parallel capacitor branches 13. Each capacitor branch 13 has different levels, and each capacitor branch 13 works independently without interfering with each other. By independently controlling the conduction state of each sub-branch 13A in the capacitor branch 13 at different levels, the capacitance value of the capacitor branch 13 corresponding to the sub-branch 13A changes, thereby further realizing the design of different capacitance values ​​for the programmable capacitive load 10. Users can flexibly select the level of the capacitor branch 13 to be turned on and the number of sub-branch 13A according to actual needs, without the need for complicated circuit debugging, effectively simplifying the operation process.

[0021] The programmable capacitor load of this application can achieve a wide range of high-precision capacitance value combinations, and the capacitance value adjustment is simple, which can adapt to the bandwidth testing requirements of different chips. At the same time, this structural design does not rely on expensive control chips and complex drive circuits, which significantly reduces the manufacturing cost of the device, and the overall structure is compact, which facilitates miniaturization design and improves the portability of the device.

[0022] For example, the programmable capacitor load of this application can be applied to various scenarios that require flexible adjustment of load capacitance, such as chip bandwidth testing, RF circuit debugging, and power electronic equipment performance verification. It can be widely used in industries such as consumer electronics, industrial control, and artificial intelligence hardware research and development, and has broad adaptability.

[0023] In this embodiment, the preset multiplier can be flexibly set according to the needs of the actual application scenario. 10 times is selected as the increment multiplier to conform to the decimal counting logic, which makes it convenient for users to quickly calculate and locate the target capacitance value.

[0024] For example, the range of this application can be 1pF, 10pF, 100pF, 1nF. In other examples, the range of this application can be more precise to 0.1pF, 0.01pF, 0.001pF. In yet another example, the range of this application can be expanded to 10nF, 100nF, etc. By combining multiple ranges, capacitance value adjustment from 0.1pF to 99999pF or even a wider range can be achieved.

[0025] In another example, the preset multiplier can also be a power of 10, such as 10 to the power of 1, which is 10 times, or 10 to the power of 2, which is 100 times. Based on this setting, capacitive loads under different design requirements can be achieved. For example, if one setting is 0.01pF and the adjacent setting is 1pF, then the programmable capacitive load can achieve capacitance value adjustment at the single-digit picofarad and hundredth-digit picofarad levels.

[0026] In other words, the range described in this application is determined based on the unit of capacitance value that can be achieved by related technologies, thereby realizing multi-range capacitance expansion.

[0027] For example, when the capacitor branch 13 of this application has 1pF and 10pF settings, the programmable load capacitor of this application can achieve capacitance value adjustment from 0 to 99pF. In another example, when the capacitor branch 13 of this application has 1pF, 10pF, 100pF, and 1nF settings, the programmable load capacitor of this application can achieve capacitance value adjustment from 0 to 9999pF. When four settings of 0.1pF, 1pF, 10pF, and 100pF are set, fine capacitance value adjustment from 0.1pF to 999.9pF can be achieved. Therefore, depending on the setting of different settings, the programmable capacitor load of this application can expand the capacitance value, which is suitable for test requirements of different precision and range.

[0028] In an optional embodiment, in the capacitor branch 13 of the same level, each capacitor branch 13 is decimal, and the capacitance value of each sub-branch 13A is the same. With this design, the capacitor branch 13 of the same level can achieve an adjustment of 0 to 9 times the basic capacitance value.

[0029] For example, the capacitor branch 13 in the 10pF range contains nine 10pF sub-branches 13A. By activating different numbers of sub-branches 13A, capacitance values ​​of 10pF, 20pF...90pF can be obtained. This decimal range design not only facilitates users in quickly calculating the target capacitance value but also ensures the uniformity and accuracy of capacitance value adjustment, avoiding capacitance value gaps. At the same time, the design of nine sub-branches 13A ensures the adjustment range within the range without complicating the circuit structure due to an excessive number of sub-branches 13A, achieving a balance between practicality and simplicity.

[0030] For example, the various embodiments of the programmable capacitor load of this application will be described using four levels: 1pF, 10pF, 100pF, and 1nF, as examples of the 13th level of the capacitor branch.

[0031] The number of sub-branch 13A described in this application is designed according to the design requirements of the programmable capacitor load. For example, if the maximum design requirement of the programmable capacitor load is 560pF, then the maximum number of sub-branch 13A can be 5 at the 100pF level, 6 at the 10pF level, and 9 at the 1pF level. In other words, the number of sub-branch of the capacitor branch in this embodiment is different and is designed according to actual needs to adapt to various capacitor load scenarios.

[0032] In an optional embodiment, such as Figure 5 As shown, each sub-branch 13A includes: Capacitor 131; Switch 132, for example, is a single-pole single-throw switch; The first connecting line 133 connects capacitor 131 and switch 132 in series; Second connecting wires 134, each second connecting wire 134 connecting switch 132 and first connecting terminal 11; and The third connecting line 135 connects to capacitor 131 and the second connecting terminal 12. Among them, the second connecting line 134 of all sub-branch 13A is connected to the first connecting terminal 11, and the third connecting line 135 of all sub-branch 13A is connected to the second connecting terminal 12.

[0033] In this embodiment, each sub-branch 13A specifically consists of one capacitor 131, one switch 132, a first connecting line 133, a second connecting line 134, and a third connecting line 135. For example... Figure 5 As shown, taking any sub-branch 13A of the 10pF branch as an example, the first connecting line 133 connects one end of the 10pF capacitor 131 to one end of the switch 132, the second connecting line 134 connects the other end of the switch 132 to the first connecting terminal 11, and the third connecting line 135 connects the other end of the capacitor 131 to the second connecting terminal 12. The second connecting lines 134 of all sub-branch 13A converge to the first connecting terminal 11, and the third connecting lines 135 converge to the second connecting terminal 12, ensuring the uniformity of the circuit connection.

[0034] like Figure 5 The programmable capacitive load 10 shown includes four parallel capacitor branches 13, with capacitive values ​​of 1pF, 10pF, 100pF, and 1nF respectively. The 1pF capacitor branch 13 contains nine parallel sub-branches 13A with a capacitance value of 1pF, and nine switches 132 (K1-K9). Each switch 132 corresponds to one capacitor 131. The 10pF capacitor branch 13 contains nine parallel sub-branches 13A with a capacitance value of 10pF. The 100pF capacitor branch 13 contains nine parallel sub-branches 13A with a capacitance value of 100pF. The 1nF capacitor branch 13 contains nine parallel sub-branches 13A with a capacitance value of 1nF. By turning different sub-branches 13A on or off, arbitrary capacitance values ​​from 0 to 9999pF can be combined, achieving a wide range and high precision capacitance value combinations.

[0035] In an optional embodiment, the programmable capacitive load is configured to turn on the capacitor branch 13 of the corresponding range and the switch 132 of the sub-branch 13A of the corresponding range, based on the target capacitance value of the product under test.

[0036] To meet the bandwidth testing requirements of the product under test, for example, if the chip needs to be tested under a target capacitance value of 50pF, the five sub-branches 13A of the 10pF level capacitor branch 13 can be turned on, and the five DIP switches 132 under the 10pF level capacitor branch 13 can be turned on to provide a stable 50pF load for the chip, and the bandwidth test of the product under test can be completed in conjunction with the testing device.

[0037] For example, if the target capacitance value is 123pF, such as Figure 6 As shown, this allows the conduction of one sub-branch 13A of the 100pF capacitor branch 13, two sub-branch 13A of the 10pF capacitor branch 13, and three sub-branch 13A of the 1pF branch.

[0038] Therefore, users can quickly configure the capacitance value according to specific testing needs without complicated circuit adjustments. The programmable capacitor load in this embodiment adapts to the diverse capacitance value requirements of different products under test, improving the practicality and flexibility of the product.

[0039] In an optional embodiment, the first connecting line 132 of the same grade adopts an equal length design to avoid signal delay caused by differences in line length and ensure the consistency of each sub-branch 13A.

[0040] This embodiment clarifies the specific composition and connection method of sub-branch 13A, standardizes the circuit structure, facilitates manufacturing and subsequent maintenance, and controls the on / off state of each sub-branch 13A through an independent switch 132, allowing for precise selection of the required capacitor 131 and avoiding interference from irrelevant capacitors 131 on the test accuracy.

[0041] In an optional embodiment, such as Figure 7 As shown, the programmable capacitor load 10 also includes a substrate 14. The thickness of the substrate 14 can be selected according to the overall size and strength requirements of the capacitor load, ensuring structural strength while facilitating wiring and component installation.

[0042] In this embodiment, capacitor branches 13 of different levels are arranged on the substrate 14 along the first direction D1. Each level occupies an independent area, and a gap is reserved between the areas of different levels to facilitate wiring and later maintenance.

[0043] At the same level, multiple capacitors 131 corresponding to each capacitor branch 13 are arranged on the substrate 14 along the second direction D2. At the same gear level, the switches 132 corresponding to each capacitor 131 are arranged on the substrate 14 along the second direction D2. The first direction D1 is perpendicular to the second direction D2.

[0044] Figure 7 This illustrates the actual product structure of the programmable capacitor load 10 of this application, where the first direction D1 is...Figure 7 The horizontal direction shown is shown, and the second direction D2 is... Figure 7 As shown in the vertical direction, capacitor branches 13 with four settings of 1pF, 10pF, 100pF, and 1nF are arranged sequentially along the horizontal direction of the substrate 14. Each capacitor branch 13 includes nine capacitors 131 corresponding to nine sub-branches 13A. The nine capacitors 131 are arranged in a row along the vertical direction, and the nine DIP switches 132 corresponding to the nine capacitors 131 are also arranged adjacent to the capacitors 131 along the vertical direction, forming a layout structure in which different settings are arranged in rows and capacitors 131 in columns under the same setting.

[0045] The above arrangement effectively utilizes the space of the substrate 14 and reduces circuit cross-interference. This layout not only makes the circuit structure clear and intuitive, making it easy for users to operate and debug, but also effectively utilizes the space of the substrate 14 to achieve miniaturized design of the equipment, making it easy to carry or integrate into the test system.

[0046] In an optional embodiment, such as Figure 7 As shown, substrate 14 also includes: The first interface 141 corresponding to the first connection end 11; and Corresponding to the second interface 142 of the second connection terminal 12, The first interface 141 and the second interface 142 include multiple pin headers. The number of pin headers is set according to connection requirements, with the design based on ensuring connection stability and versatility. The pin headers are located at the edge of the substrate 14, facilitating the insertion and removal of test leads while avoiding occupying component mounting area.

[0047] In this embodiment, one of the first interface 141 and the second interface 142 is connected to the ground wire. Another interface in the first interface 141 and the second interface 142 connects to the product under test and to the testing device.

[0048] The first interface 141 and the second interface 142 are located at the edge of the substrate 14, and both employ a multi-pin header structure. For example, the multiple pin headers of the second interface 142 are all connected to the ground wire to enhance the grounding effect, reduce electromagnetic interference, and improve the accuracy of test data.

[0049] The pin headers of the first interface 141 are connected to the chip under test (DUT) and the test device, respectively. The number of pin headers connecting the DUT and the test device is allocated according to the signal transmission requirements. The standardized pin header interface can be adapted to different types of test devices and DUTs.

[0050] In one alternative embodiment, such as Figure 7 As shown, switch 132 and capacitor 131 are located on the same side or opposite side of substrate 14, and there is a gap between the switch and capacitor 131 in the orthographic projection of substrate 14.

[0051] In this embodiment, all switches 132 and capacitors 131 can be mounted on the front side of the substrate 14. Alternatively, the switches and capacitors can be mounted on opposite sides of the substrate, for example, the switches on the front side and the capacitors on the back side. This facilitates direct observation and manual operation of the switches 132, reducing debugging difficulty. Each capacitor 131 and its corresponding switch 132 have a gap in their projection onto the substrate 14 to avoid direct overlap and reduce the influence of parasitic parameters. In an optional embodiment, such as... Figure 7 As shown, a gear position indicator silkscreen 143 is provided on the surface of the substrate 14 at the corresponding position of the capacitor branch 13 in all gear positions. A switch sequence indicator silkscreen 144 is provided on the surface of the substrate 14 at all switch 132 positions in the same gear position; A switch on / off indicator silkscreen 145 is provided on the surface of the substrate 14 at the on / off position of switch 132.

[0052] For example, on the front side of the substrate 14, the capacitor branch 13 for each setting is silkscreened with markings such as "1pF", "10pF", "100pF", and "1nF". Next to the nine switches 132 in the same setting, the sequence markings "1", "2", ..., "9" are silkscreened. An "ON" terminal is silkscreened at the on position of each switch 132 as a confirmation. Users can quickly locate the switch 132 that needs to be turned on based on the target capacitance value, avoiding adjustment errors caused by confusion about the setting or switch position. The switch 132 on / off indicator helps users quickly confirm the switch status, improving operational efficiency, and is especially suitable for scenarios requiring fast capacitance value adjustment.

[0053] In another alternative embodiment, the switch and capacitor are located on opposite side surfaces of the substrate. The switches in adjacent sub-branches have a gap in their orthographic projection onto the substrate; The capacitors and corresponding switches in the same sub-branch have at least partial overlap in their orthographic projections onto the substrate; The substrate has connection holes, and the first connection line connects to the switch and capacitor in the same sub-branch through the connection holes.

[0054] This embodiment adopts a double-sided layout design, with all capacitors mounted on the back of the substrate and all switches mounted on the front. The capacitor arrangement follows the layout structure of the previous embodiment, where capacitors are arranged in rows for different speed ranges and in columns for the same speed range. The switch arrangement also follows the layout of the previous embodiment, corresponding to the capacitors.

[0055] Each capacitor and its corresponding switch have overlapping projections on the substrate. A diameter connection hole is opened at the position of the overlapping projection on the substrate. The first connection line passes through the connection hole to realize the electrical connection between the capacitor and the switch, ensuring the reliability of the circuit connection. This double-sided layout can reduce the overall size of the capacitor load while ensuring the convenience of setting the capacitance value, realizing the miniaturization of the device and making it easy to carry to different testing environments.

[0056] In one optional embodiment, capacitor 131 can be fixed to substrate 14 by soldering. In other embodiments, when capacitor 131 and switch 132 are located on opposite surfaces of substrate 14, capacitor 131 can be a surface-mount capacitor or a magnetic capacitor that can be fixed without soldering. When a capacitor is damaged or its capacitance value needs to be adjusted, the old capacitor can be directly replaced and a new capacitor of the same specification can be installed without disassembling substrate 14 or other components, which facilitates later debugging and component replacement and ensures the stability of the test.

[0057] In an alternative embodiment, switch 132 includes one or more of a slide switch, push-button switch, or DIP switch.

[0058] This embodiment allows for the selection of different types of switches based on the actual application scenario. For example, in laboratory scenarios requiring frequent capacitance value adjustment, DIP switches are used for the 1pF and 10pF ranges for convenient and quick switching; in industrial batch testing scenarios, push-button switches are used, enabling automated control via external control signals. The variety of switch types available in this embodiment allows the product to adapt to various application scenarios, enhancing its versatility.

[0059] In an optional embodiment, the size, specification accuracy, and temperature coefficient of each capacitor 131 in the same range are kept consistent to ensure the accuracy of the capacitance value during testing.

[0060] In an optional embodiment, the programmable capacitor load further includes an overcurrent protection circuit disposed between the first connection terminal 11 and the second connection terminal 12 and the capacitor branch 13. The overcurrent protection circuit may employ a fusible resistor or a resettable fuse. When an abnormally large current occurs in the circuit, the fusible resistor melts or the resettable fuse opens, cutting off the circuit and preventing damage to capacitor 131 and switch 132 due to overcurrent, thereby improving the safety and reliability of the equipment.

[0061] In this embodiment, the rated current of the fusible resistor is selected based on the maximum operating current of the capacitor branch. The resettable fuse is suitable for scenarios with frequent switching; its operating current is set higher than the normal operating current to ensure it does not trip during normal operation and quickly disconnects the circuit in case of an abnormality.

[0062] The programmable capacitor load based on the above embodiments of this application has the characteristics of wide range, high precision and wide applicability. When the test load of the product under test is low, the low-level capacitor 131 can be turned on for testing according to the test requirements.

[0063] For example, if a product under test needs to be tested under a 50pF load condition, and it is determined that the five sub-branch 13A of the 10pF level capacitor branch 13 needs to be turned on, the tester can switch the first five DIP switches 132 of the 10pF level to the on position, which can provide a stable 50pF load for the chip and complete the bandwidth test with the help of the test equipment.

[0064] If a product under test needs to be tested under a load of 9000pF, and it is determined that the nine sub-branches 13A of the 1nF capacitor branch 13 need to be turned on, the tester can switch the nine DIP switches 132 of the 1nF range to the on position to provide a stable 9000pF load for the chip and complete the bandwidth test with the help of the test equipment.

[0065] Therefore, the programmable capacitor load of this application can quickly configure the capacitance value according to specific test requirements without complex circuit adjustments, adapt to the diverse capacitance value requirements of different products under test, improve the practicality and flexibility of the product, ensure the efficient conduct of testing, and has wide applicability.

[0066] Embodiments of this application also provide a testing system, such as Figure 8 As shown, the test system includes: Test device 20; and The programmable capacitor load 10 of the first aspect of this application, One of the first interface 141 and the second interface 142 of the programmable capacitive load 10 is connected to the ground wire. The programmable capacitive load 10 connects to the test device 20 and the product under test 30 via another interface of the first interface 141 and the second interface 142.

[0067] In this embodiment, the testing device 20 can be selected from commonly used testing equipment such as network analyzers, oscilloscopes, and signal generators, depending on the testing requirements. Taking chip bandwidth testing as an example, the testing device 20 preferentially uses a network analyzer, which can output test signals of different frequencies and accurately acquire the amplitude and phase changes of the output signal of the chip under test, thereby determining the bandwidth parameters of the chip under test.

[0068] Figure 8 A connection diagram of the test apparatus 20, the capacitive load, and the product under test 30 is shown. Before testing, the first interface 141 of the programmable capacitive load 10 is connected to the ground wire, and the test device 20 and the product under test 30 are connected to the second interface 142. The input terminal of the product under test 30 is connected to the signal output terminal of the test device 20, and the output terminal of the product under test 30 is connected to the second interface 142 and the signal input terminal of the test device 20 respectively.

[0069] During the test, the network analyzer outputs test signals of different frequencies to the product under test 30. The capacitor load is adjusted, and the network analyzer collects the output signal of the product under test 30 after the capacitor load adjustment in real time. The frequency at -3dB of the gain is analyzed as the chip bandwidth.

[0070] The entire process can quickly and accurately test different capacitive loads and meet the testing requirements of chips of different specifications, thus broadening the application scope of the testing system and improving its overall performance.

[0071] In this embodiment, the description of the features of the programmable capacitor load corresponding to the test system in the embodiment can be found in the relevant descriptions of the above embodiments, and will not be repeated here.

[0072] An embodiment of this application also provides a testing method, the testing method including: S10. Connect one of the first interface 141 and the second interface 142 of the programmable capacitive load 10 to the ground wire; S20. Connect the test device 20 and the product under test 30 to the other interface of the first interface 141 and the second interface 142 of the programmable capacitive load 10. S30. Connect the input terminal of the product under test 30 to the signal output terminal of the test device 20; S40. Connect the output terminal of the product under test 30 to the second interface 142 and the signal input terminal of the test device 20 respectively. S50. Determine the range of the capacitor branch 13 that needs to be turned on or off and the number of sub-branch 13A under the corresponding range based on the target capacitance value of the product under test 30. For example, depending on the testing requirements of the product under test 30, such as if the product under test 30 needs to be tested under different load conditions such as 15pF, 30pF, 50pF, and 100pF, then the range of the capacitor branch 13 and the number of sub-branch 13A corresponding to each test point need to be determined separately.

[0073] S60, switch 132 of sub-branch 13A of programmable capacitive load 10 is turned on or off for testing.

[0074] For example, when the target capacitance value is 30pF, it is determined that the capacitor branch 13 at the 10pF level and its three sub-branches 13A at that level need to be activated. Then, the three switches 132 at the 10pF level are turned on, and the test device 20 is started. The test device 20 outputs a test signal to the product under test 30. The test device 20 acquires the output signal of the product under test 30 after adjustment by the capacitor load, records the frequency at the gain of -3dB, and completes the load test under the 30pF load. During this process, the switching state of the capacitor load can also be changed to perform tests under different loads such as 15pF, 50pF, and 100pF.

[0075] The entire testing process is simple to operate and the steps are easy to understand. No complex professional knowledge is required to complete the operation. The rapid adjustment capability of the programmable capacitor load can significantly shorten the testing cycle and improve testing efficiency. At the same time, the precise capacitance adjustment ensures the reliability of the test data and provides an accurate basis for the performance evaluation of the product under test.

[0076] For a description of the features of the programmable capacitor load in this embodiment, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0077] Embodiments of this application also provide an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the above-described test method.

[0078] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the above-described test method.

[0079] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0080] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in the above-described test method embodiments.

[0081] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in the above-described test method embodiments.

[0082] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0083] The above provides a detailed description of a programmable capacitor load provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A programmable capacitive load, the programmable capacitive load comprising a first connection terminal and a second connection terminal, characterized in that, The programmable capacitive load also includes at least two parallel capacitor branches. One end of the parallel connection of all the capacitor branches is used as the first connection terminal, and the other end of the parallel connection of all the capacitor branches is used as the second connection terminal. The at least two parallel capacitor branches have corresponding levels arranged from high to low, and the capacitance values ​​of adjacent levels are a preset multiple. Each of the capacitor branches includes multiple sub-branches with capacitance values ​​connected in parallel, and the sub-branches can be turned on or off.

2. The programmable capacitive load according to claim 1, characterized in that, Each of the sub-branches includes: capacitance; switch; A first connecting line that connects the capacitor and the switch in series; Second connecting wires, each of the second connecting wires connecting the switch and the first connecting terminal; and The third connecting line, each of the third connecting lines, connects the capacitor and the second connecting terminal. The second connecting line of all sub-branches is connected to the first connecting end, and the third connecting line of all sub-branches is connected to the second connecting end.

3. The programmable capacitor load according to claim 2, characterized in that, In capacitor branches of the same grade, the capacitance value of each sub-branch is the same.

4. The programmable capacitor load according to claim 2, characterized in that, The programmable capacitor load also includes a substrate. All capacitor branches for each gear are arranged along the first direction on the substrate. At the same gear level, the capacitors corresponding to all sub-branches are arranged along the second direction on the substrate. At the same gear position, the switches corresponding to all sub-branches are arranged on the base plate along the second direction. The first direction is perpendicular to the second direction.

5. The programmable capacitor load according to claim 4, characterized in that, The substrate further includes: The first interface corresponding to the first connection end; and Corresponding to the second interface of the second connection end, The first interface and the second interface each include multiple pin headers. One of the first interface and the second interface is connected to the ground wire. The first interface and the other interface of the second interface are connected to the product under test and the testing device.

6. The programmable capacitor load according to claim 5, characterized in that, The switch and the capacitor are located on the same side or opposite side of the substrate, and there is a gap between the switch and the capacitor's orthographic projection on the substrate.

7. The programmable capacitor load according to claim 5, characterized in that, The switch and the capacitor are located on opposite side surfaces of the substrate. The switches in adjacent sub-branches are spaced apart in the orthographic projection of the substrate; The capacitor and the corresponding switch in the same sub-branch have at least partial overlap in their orthographic projections on the substrate; The substrate has connection holes, and the first connection line connects the switch and the capacitor in the same sub-branch through the connection holes.

8. The programmable capacitor load according to claim 4, characterized in that, A level indicator silkscreen is set on the substrate surface at the corresponding position of the capacitor branch for all levels; A switch sequence indicator silkscreen is printed on the surface of the substrate at all switch positions within the same gear. A switch on / off indicator silkscreen is provided on the substrate surface at the on / off position of the switch; The switch includes one or more of a slide switch, a push-button switch, or a DIP switch.

9. The programmable capacitor load according to any one of claims 2 to 8, characterized in that, The programmable capacitor load is configured to: turn on or off capacitor branches at different speeds and turn on the switches of the sub-branches at the corresponding speeds, based on the target capacitance value of the product under test.

10. A testing system, characterized in that, The testing system includes: Test equipment, and The programmable capacitor load according to any one of claims 1 to 9, One of the first and second interfaces of the programmable capacitive load is connected to the ground wire. The other interface of the first and second interfaces of the programmable capacitive load is connected to the test device and the product under test. The input terminal of the product under test is connected to the signal output terminal of the testing device, and the output terminal of the product under test is connected to the second interface and the signal input terminal of the testing device, respectively.

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