Delay power-down circuit, power module and electronic device

Abstract

The application discloses a delay power-off circuit, a power module and electronic equipment, and relates to the technical field of power management of electronic equipment, and comprises a switching module, a power-off energy holding unit and a load point power module, wherein the switching module is electrically connected with the first power supply end and the power-off energy holding unit respectively, the switching module is configured to be in an open state when system power supply is abnormal, so as to isolate the power-off energy holding unit; the power-off energy holding unit is also electrically connected with the load point power module, the load point power module is also electrically connected with a target controller, and the power-off energy holding unit is configured to supply power to the target controller through the load point power module when the system power supply is abnormal, so as to complete fault log writing. Thus, by decoupling the power supply of the target controller from the system power supply and providing independent energy support by using the power-off energy holding unit, the problem that the target controller cannot complete fault log recording due to instantaneous power failure of the target controller caused by abnormal system power supply in the prior art is solved.

Description

Technical Field

[0001] This application relates to the field of power management technology for electronic devices, and in particular to a delayed power-down circuit, a power module, and an electronic device. Background Technology

[0002] With the accelerating pace of digitalization, data centers, communication networks, and various intelligent computing systems have become critical infrastructure supporting the operation of modern society. Electronic devices such as servers, switches, and storage devices play a central role, and their stable operation is directly related to business continuity, data security, and system reliability. However, with the continuous increase in device power density, the stability of power systems faces unprecedented challenges, and any accidental power outage can lead to system crashes. In order to effectively recover and diagnose after a power outage, critical management controllers must have the ability to maintain short-term operation after a mains power interruption to complete necessary cleanup operations.

[0003] In related technologies, the target controller (such as the BMC (Baseboard Management Controller)) is typically powered directly by the system power supply. When a power anomaly is detected, an interrupt signal is sent to the target controller, which is expected to complete the fault log recording operation during this period. However, because the power supply of the target controller is strongly coupled to the system power supply, its power supply will be interrupted synchronously when the system loses power, causing the target controller to be unable to complete subsequent operations, which urgently needs to be addressed. Summary of the Invention

[0004] This invention provides a delayed power-down circuit, a power module, and an electronic device to at least solve the problem in the prior art where the target controller cannot complete fault log recording due to a sudden power outage caused by abnormal system power supply, thereby significantly improving the fault diagnosis capability and system recovery efficiency of electronic devices in the event of a sudden power outage.

[0005] This invention provides a delayed power-down circuit, comprising: a switching module, a power-down energy retention unit, and a point-of-load power supply module, wherein,

[0006] The first end of the switch module is electrically connected to the first power supply end, and the second end of the switch module is electrically connected to the input end of the power failure energy retention unit. The switch module is configured to be in an open state when the system power supply is abnormal, so as to isolate the power failure energy retention unit.

[0007] The output terminal of the power failure energy retention unit is electrically connected to the first input terminal of the load point power module, wherein the output terminal of the load point power module is electrically connected to the target controller, and the power failure energy retention unit is configured to supply power to the target controller through the load point power module when the system power supply is abnormal, so as to complete the fault log writing.

[0008] The present invention provides a power module, including the aforementioned delayed power-down circuit.

[0009] The present invention also provides an electronic device, including: the power module described above.

[0010] This invention decouples the power supply of the target controller from the system power supply through a switching module and adds a power-loss energy retention unit to the isolated power supply path. When a system power supply abnormality is detected, the main power supply connection can be quickly cut off, and the power-loss energy retention unit provides independent energy support, ensuring that the BMC has sufficient time to complete the recording of the fault log. This solves the problem in the prior art that the target controller cannot complete the fault log recording due to the instantaneous power failure caused by the system power supply abnormality, thereby significantly improving the fault diagnosis capability and system recovery efficiency of electronic equipment in the event of a sudden power failure. Attached Figure Description

[0011] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a delayed power-down circuit provided in an embodiment of the present invention;

[0013] Figure 2 This is a schematic diagram of the BMC power supply circuit in related technologies. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0015] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] The present invention provides a delayed power-down circuit, and the circuit structure of the delayed power-down circuit is described in detail below.

[0018] Figure 1 This is a schematic diagram of the delayed power-down circuit according to an embodiment of the present invention.

[0019] Before introducing the delayed power-down circuit proposed in the embodiments of the present invention, let’s briefly introduce the relevant technical background.

[0020] Understandably, the process of the BMC recording power failure logs is a complex mechanism involving multiple collaborative steps, primarily including hardware-level power status detection, interrupt triggering for abnormal situations, log data storage and processing, and system recovery. This mechanism first monitors the system's power supply status in real time using dedicated hardware sensors. When abnormal voltage fluctuations or an impending power outage are detected, a high-priority interrupt signal is immediately triggered. Subsequently, the system initiates an emergency handling process, quickly writing critical information such as the current operating status and error codes into non-volatile memory in a specific data format. Even in extreme situations such as sudden power outages, this ensures that critical fault information is recorded completely and accurately, providing a reliable basis for subsequent problem diagnosis and system recovery. This design fully considers the stringent reliability requirements of industrial applications, minimizing the risk of data loss through multiple safeguards.

[0021] In related technologies, such as Figure 2As shown, the BMC's power supply design adopts a scheme that shares the same power rail with the CPLD (Complex Programmable Logic Device) and other onboard components. This effectively optimizes the board layout, significantly saving valuable onboard space. Furthermore, by reducing the number of independent power rails, overall material costs can be effectively reduced. In other words, this shared power supply design avoids the need for a separate power supply line for the BMC, simplifies the complexity of the power distribution network, and reduces the number of power management ICs (Integrated Circuits) and related passive components used due to multiple functional modules sharing the power rail. From a system-level design perspective, this achieves higher integration and cost-effectiveness.

[0022] In such Figure 2 In the circuit structure shown, the BMC establishes a hardware-level connection with the CPLD or other logic control circuits to construct a real-time power status monitoring network. In this monitoring system, the CPLD, as the front-end detection unit, can continuously collect key status signals from multiple power modules, including but not limited to the PowerGood (PG) signal, the Reset signal, and the voltage reference signal. When abnormal power conditions occur during circuit system operation (such as a sudden drop in input voltage, unexpected signal level inversion, timing disorder, etc.), the CPLD can identify the abnormal state within microseconds through hardware circuitry and send a high-priority interrupt alarm signal to the BMC via a specially designed interrupt signal line. Upon receiving the hardware interrupt alarm signal from the CPLD, the BMC's built-in interrupt controller immediately triggers a dedicated interrupt service routine. This routine is specially optimized to complete the diagnostic analysis of abnormal power states in a very short time (typically within milliseconds) and automatically generate a power failure event log.

[0023] However, this design has serious systemic defects: (1) Since the power supply design of the BMC module adopts a scheme of direct conversion from the system power supply P12V_STBY, when the main power supply of the system fails, the P12V_STBY voltage will drop rapidly, causing the BMC power supply to be interrupted synchronously. Through actual waveform analysis, it was found that the P12V_STBY voltage drops extremely quickly, from the normal 12V working voltage value to below 3.3V, and the whole process only takes a very short time window of 3-5ms. In such a short time interval, the BMC control chip cannot complete the critical fault log storage operation. More seriously, the onboard eMMC (Embedded Multi Media Card) flash memory chip needs a continuous and stable power supply for at least 110ms to ensure that the fault data is reliably written and stored. Obviously, this cannot meet the basic reliability requirements and has major defects. (2) Since no dedicated energy storage capacitor bank is configured, the overall energy storage capacity of the system-side filter capacitor is significantly insufficient. More notably, these filter capacitors are distributed throughout the circuit to optimize high-frequency filtering performance. When the system encounters a sudden power supply failure, the energy stored in these distributed capacitors cannot be centrally integrated and utilized, but will instead be rapidly dissipated as heat through the fault point. At the same time, the enable control signal (EN) of the point load (POL) power supply will prematurely shut down the power output when the input voltage drops to the undervoltage protection (UVP) threshold (usually set to 10.8V). This premature action of the protection mechanism further reduces the system's utilization efficiency of residual energy, resulting in a waste of available energy. (3) The EN signal control of the POL power supply lacks in-depth hardware-level optimization design, and its main problem lies in the special characteristics of the BMC power supply line. Under normal circumstances, the BMC power supply adopts the STBY (Standby) power supply mode, which has obvious timing management defects. Due to the lack of effective hardware-level isolation measures, the EN signal will be directly coupled to the input voltage terminal, forming an uncontrolled signal path. When system voltage fluctuates, especially when the P12V_STBY voltage drops to the critical threshold of 11V, the shutdown mechanism is immediately triggered. This overly sensitive shutdown response causes the BMC power supply to be interrupted too early, with the actual power outage time significantly preceding the complete depletion of the energy storage capacitor, resulting in the abnormal premature termination of critical system functions. This timing misalignment not only affects system stability but can also lead to the loss or corruption of important data.

[0024] Based on the aforementioned problems, this invention proposes a delayed power-down circuit. By using a switching module to decouple the power supply of the target controller from the system power supply, and adding a power-down energy retention unit on the isolated power supply path, the main power connection can be quickly cut off when a system power supply anomaly is detected. The power-down energy retention unit provides independent energy support, ensuring that the BMC has sufficient time to complete fault log recording. This solves the problem in the prior art where the target controller cannot complete fault log recording due to a momentary power outage caused by a system power supply anomaly, thus significantly improving the fault diagnosis capability and system recovery efficiency of electronic devices under sudden power outages.

[0025] For example, such as Figure 1 As shown, the delayed power-down circuit 10 includes: a switching module Q1, a power-down energy retention unit 100, and a load point power supply module 200. The first terminal of the switching module Q1 is electrically connected to a first power supply terminal, and the second terminal of the switching module Q1 is electrically connected to the input terminal of the power-down energy retention unit 100. The switching module Q1 is configured to be in an open state when the system power supply is abnormal, thus isolating the power-down energy retention unit 100. The output terminal of the power-down energy retention unit 100 is electrically connected to the first input terminal of the load point power supply module 200. The output terminal of the load point power supply module 200 is electrically connected to the target controller. The power-down energy retention unit 100 is configured to supply power to the target controller via the load point power supply module 200 when the system power supply is abnormal, thereby completing the fault log writing.

[0026] Specifically, such as Figure 1 As shown, the delayed power-down circuit 10 mainly consists of a switching module Q1, a power-down energy retention unit 100, and a load point power module 200. The switching module Q1 is located between the first power supply terminal and the power-down energy retention unit 100, and can decouple the power supply to the target controller (BMC) from the system's main power supply through its own switching. The first power supply terminal is the output terminal of the main power supply, which is the energy source for the entire circuit system (from P12V_STBY, i.e., 12V standby power, which can be obtained from the +12V DC output of the main power supply unit (P12V_PSU) of the electronic equipment, passing through an eFuse (Electronic Fuse). The eFuse can continuously monitor the current and voltage flowing through it. In the event of a short circuit, overvoltage, or overcurrent, the eFuse will immediately (usually on the μs level) automatically disconnect the circuit to prevent the fault from spreading), providing power when the system is operating normally.

[0027] The power-down energy retention unit 100, as an energy storage component, has its input terminal electrically connected to the second output terminal of the switching module Q1. During normal system power supply, it receives power from the first power supply terminal, is charged, and stores energy. Its output terminal is electrically connected to the first input terminal (POL_VIN) of the point-of-load power module 200. When the system experiences a power supply abnormality, the power-down energy retention unit 100 uses the energy stored inside to continue providing power to the target controller through the downstream point-of-load power module 200.

[0028] When the system detects a power supply anomaly (such as the main power supply dropping below a critical value), the control logic can quickly turn off the switching module Q1. That is, the switching module Q1 immediately switches to the off state, physically disconnecting the electrical connection between the first power supply terminal and the power failure energy retention unit 100, thereby achieving isolation function. This prevents the energy storage capacitor in the power failure energy retention unit 100 from being instantly depleted or generating surge current due to the rapid collapse of the main power supply, thus protecting the power failure energy retention unit 100 and ensuring that the energy stored therein can be effectively utilized.

[0029] The first input terminal (POL_VIN) of the point-of-load (POLO) power module 200 is connected to the output terminal of the power-down energy retention unit 100, and the output terminal of the PLO power module 200 is directly connected to the target controller (BMC). The PLO power module 200 is typically a DC-DC (Direct Current to Direct Current) step-down converter. Under normal system power conditions, it can convert the 12V input voltage to a lower voltage (such as 3.3V (P3V3_STBY) or 1.8V (P1V8_STBY)) required by the target controller (BMC). In the event of a system power failure, after the switching module Q1 is disconnected, it can obtain energy from the power-down energy retention unit 100 to continue providing a stable low-voltage power supply to the target controller (BMC), thereby achieving delayed power-down.

[0030] In other words, when the system power supply is normal, the switch module Q1 is in the on state, and the first power supply terminal charges the power-down energy storage unit 100 through the switch module Q1, and at the same time charges the target controller (BMC) through the load point power module 200. When an abnormal system power supply is detected (such as a voltage drop), the disconnect logic is executed, that is, the switch module Q1 is controlled to be in the off state, isolating the power-down energy storage unit 100 from the first power supply terminal. At this time, the power-down energy storage unit 100 can be used as a "backup battery", and the energy stored in the power-down energy storage unit 100 can continue to supply power to the target controller (BMC) through the load point power module 200. Thus, even when the main power supply is abnormal, the target controller (BMC) can still be powered to ensure reliable recording of the fault log.

[0031] Optionally, in some embodiments, the aforementioned delayed power-down circuit 10 further includes: an on / off control module, which is electrically connected to the second power supply terminal, the control terminal of the switch module Q1, the interrupt signal output terminal, the enable signal output terminal, and the second input terminal of the load point power module 200, respectively; wherein, the on / off control module is configured to output a disconnect signal to the switch module Q1 when the system power supply is abnormal, and output a load point enable signal to the second input terminal of the load point power module 200, so that the load point power module 200 supplies power to the target controller based on the load point enable signal.

[0032] It is understood that the interrupt signal output terminal and the enable signal output terminal can be implemented by a CPLD (this embodiment of the application uses this as an example for illustration). The CPLD is configured to monitor the power status of the system in real time. For example, when the system power supply is normal, the interrupt signal output terminal of the CPLD can output a high-level signal (invalid state), while the enable signal output terminal of the CPLD can output a normal power control signal (high level). When the system power supply is abnormal, an interrupt signal (low level) can be immediately output from the interrupt signal output terminal of the CPLD, and then the on / off control module outputs a disconnect signal based on the interrupt signal. The output state of the enable signal output terminal of the CPLD is uncertain, but its intention is to try to maintain a high level before the CPLD loses power.

[0033] Furthermore, the interrupt signal output and enable signal output can also be implemented using a general-purpose MCU (Microcontroller Unit) with GPIO (General Purpose Input / Output) pins and ADC (Analog-to-Digital Converter) functionality. The MCU can output an interrupt signal through one GPIO pin and an enable signal through another. Alternatively, the interrupt signal output and enable signal output can be implemented using an FPGA (Field-Programmable Gate Array), operating on a similar principle to a CPLD, where the required logic functions are implemented within programmable logic. It should be noted that the implementation of the interrupt signal output and enable signal output is not limited to the above methods; other equivalent circuits or functional devices known to those skilled in the art can also be used.

[0034] Specifically, the delayed power-down circuit 10 also includes an on / off control module. This module, electrically connected to the second power supply terminal (the output terminal of the main power supply plays another functional role in the circuit, specifically referring to the power node used by the on / off control module to monitor the system power supply status), can determine whether a power supply abnormality has occurred in the system, thus accurately triggering the delayed power-down mechanism. The on / off control module, electrically connected to the interrupt signal output terminal, can receive an interrupt signal (CPLD_INT#) from the CPLD, which can serve as a rapid indicator of system-level faults. Furthermore, the on / off control module, electrically connected to the control terminal of the switching module Q1, can control the on / off state of the switching module Q1, i.e., during system power supply... In case of an anomaly, a disconnect signal is output to the switch module Q1, thereby controlling the switch module Q1 to turn off quickly. The on / off control module is electrically connected to the enable signal output terminal. When the system power supply is normal, it can receive the normal power control signal (CPLD_EN) issued by the CPLD, thereby ensuring the continuous power supply to the target controller (BMC). The on / off control module is electrically connected to the second input terminal of the load point power module 200, which can control the enable of the load point power module 200. That is, when the system power supply is abnormal, it outputs a load point enable signal to the second input terminal of the load point power module 200, so that the load point power module 200 supplies power to the target controller (BMC) based on the load point enable signal.

[0035] Therefore, the on / off control module can be used to achieve coordinated control of the switching module and the load point power module. When the system power supply is abnormal, it can immediately send a disconnect signal to isolate the faulty power supply and force the output of the load point enable signal to maintain the BMC power supply, thereby ensuring that the delayed power-down function is executed reliably and robustly.

[0036] To facilitate understanding, the on / off control module will be further explained below.

[0037] Optionally, in some embodiments, the on / off control module includes: a comparison unit U1, a NOR unit, and a first OR gate U3, wherein the comparison unit U1 is electrically connected to the second power supply input port, the reference voltage output node, the power input node, and the first input terminal of the NOR unit, respectively; the comparison unit U1 is configured to generate a comparison signal based on the second voltage and the output voltage of the reference voltage output node, and output the comparison signal to the first input terminal of the NOR unit; the first input terminal of the NOR unit is electrically connected to the output terminal of the comparison unit U1; the second input terminal of the NOR unit is electrically connected to the interrupt signal output terminal; the output terminal of the NOR unit is electrically connected to the control terminal of the switch module Q1 and the first input terminal of the first OR gate U3, respectively; the second input terminal of the first OR gate U3 is electrically connected to the enable signal output terminal; and the output terminal of the first OR gate U3 is electrically connected to the second input terminal of the load point power module 200.

[0038] Specifically, such as Figure 1As shown, the on / off control module mainly consists of a comparison unit U1, a NOR unit, and a first OR gate U3. The comparison unit U1 is a voltage comparison unit, electrically connected to the second power supply input port and the reference voltage output node. It compares the second voltage from the second power supply input port (i.e., the system power supply voltage P12V_STBY_REF, obtained by dividing P12V_STBY through a voltage divider resistor) with the reference voltage (Vref) from the reference voltage output node, thereby outputting a comparison signal reflecting the power supply status (normal or abnormal). This comparison signal can be sent to the first input terminal of the NOR unit. Simultaneously, the second input terminal of the NOR unit can receive a signal from the CPLD interrupt signal output terminal, which indicates the presence of a sudden fault event. The NOR unit performs logical operations on the comparison signal from the comparison unit U1 and the signal from the CPLD interrupt signal output terminal to generate corresponding control commands at its output terminal. This instruction can be sent directly to the control terminal of the switch module Q1 to control the on and off of the switch module Q1. Alternatively, it can be input to the first OR gate U3. The first OR gate U3 performs a logical OR operation on the signal from the NOR unit and the signal output from the CPLD enable signal output terminal to generate the load point enable signal, which is then output to the second input terminal of the load point power module 200 to provide power to the target controller (BMC).

[0039] Therefore, by introducing a comparison unit, the on / off control module can monitor the system power supply status in real time and respond quickly when the voltage is abnormal, ensuring that the system can switch to the backup power supply path in time when the power supply is abnormal, further improving the system's reliability and fault tolerance. By introducing a NOR unit, the on / off control module can control according to the combination logic of multiple signals, improving the system's response speed and control accuracy. By introducing a first OR gate, the enable signal of the load point power supply module can be dynamically controlled according to the combination logic of multiple signals, ensuring that the power supply of the target controller is not affected when the system power supply is abnormal.

[0040] Next, the control logic of the on / off control module will be further explained in conjunction with the structure of the NOR unit.

[0041] Optionally, in some embodiments, the NOR unit includes: a second OR gate U2 and a NOT gate, wherein the first input terminal of the second OR gate U2 is electrically connected to the output terminal of the comparison unit U1, and the output terminal of the second OR gate U2 is electrically connected to the control terminal of the switch module Q1 and the first input terminal of the first OR gate U3, respectively; the input terminal of the NOT gate is electrically connected to the interrupt signal output terminal, and the output terminal of the NOT gate is electrically connected to the second input terminal of the second OR gate U2.

[0042] Specifically, in the embodiments of the present invention, the NOR unit does not refer to a NOR gate, but rather to a logic circuit composed of an OR gate (i.e., the second OR gate U2) and a NOT gate. When the system power supply is normal, the second voltage is greater than the reference voltage. The comparison signal output by the comparison unit U1 is a low-level signal, and this low-level signal is output to the first input terminal of the NOR unit (i.e., the second OR gate U2 in the NOR unit). At this time, the CPLD interrupt signal output terminal is high-level (indicating no interruption), and this high-level signal is output to the second input terminal of the NOR unit (i.e., the NOT gate in the NOR unit). After receiving the high-level signal output by the CPLD interrupt signal output terminal, the NOT gate in the NOR unit can output a low-level signal, and this low-level signal is also output to the second OR gate U2 in the NOR unit. Thus, the second OR gate U2 receives both the low-level signal from the comparison unit U1 and the low-level signal from the NOT gate (the high-level signal output by the CPLD interrupt signal output terminal is flipped by the NOT gate). According to the logic of the OR gate (as long as one input is high-level, the output is high-level; only when all inputs are low-level, the output is low-level), the NOR unit can finally output a low-level signal (P12V_OK_N). The low-level signal can be further output by the output terminal of the NOR unit to the control terminal of the switching module Q1 and the first input terminal of the first OR gate U3. Since the system power supply is normal, the CPLD enable signal output terminal can output a high-level signal (CPLD_EN). The low-level signal output by the NOR unit puts the switching module Q1 in the conducting state, so that the main power supply can charge the power-down energy retention unit 100 and supply power to the subsequent circuits. Since the high-level signal output by the CPLD enable signal output terminal is sent to the first OR gate U3, and the low-level signal output by the NOR unit is also sent to the first OR gate U3, according to the OR gate logic (as long as one input is high, the output is high; only when all inputs are low, the output is low), the output terminal of the first OR gate U3 can output a high-level signal. This high-level signal can be output to the second input terminal (enable terminal POL_EN) of the load point power module 200. Because the enable terminal is high, the load point power module 200 works normally, converting the input 12V voltage into the P3V3_STBY and P1V8_STBY voltages required by the target controller (BMC), thereby providing a stable operating power supply for the target controller (BMC).

[0043] In the event of a system power supply anomaly, the second voltage is lower than the reference voltage. The comparison signal output by the comparison unit U1 is a high-level signal, which is then output to the first input terminal of the NOR unit (i.e., the second OR gate U2 in the NOR unit). When the CPLD is functioning normally, the signal output from the CPLD interrupt signal output terminal is low (indicating an interrupt). This low-level signal can be output to the second input terminal of the NOR unit (i.e., the NOT gate in the NOR unit). Upon receiving the low-level signal from the CPLD interrupt signal output terminal, the NOT gate in the NOR unit outputs a high-level signal, which is also output to the second OR gate U2 in the NOR unit. Thus, the second OR gate U2 receives both the high-level signal from the comparison unit U1 and the high-level signal from the NOT gate (the low-level signal output from the CPLD interrupt signal output terminal is toggled by the NOT gate). Based on the OR gate logic, the NOR unit ultimately outputs a high-level signal (P12V_OK_N). The high-level signal, as a disconnect signal, can be further output by the output terminal of the NOR unit to the control terminal of the switching module Q1 and the first input terminal of the first OR gate U3, so that the switching module Q1 is in the off state. Thus, the main power supply is isolated from the power-down energy storage unit 100. The energy stored in the power-down energy storage unit 100 can be used as backup power for subsequent target controller (BMC) delayed power-down. Due to a system power supply anomaly, the CPLD enable signal output terminal will output a low-level signal (CPLD_EN), or the high-level signal ultimately output by the non-cell will be sent to the first OR gate U3. The low-level signal output by the CPLD enable signal output terminal will also be sent to the first OR gate U3. According to the OR gate logic, the output terminal of the first OR gate U3 can output a high-level signal. This high-level signal can be output to the second input terminal (enable terminal POL_EN) of the load point power module 200 as a load point enable signal. The high level of the enable terminal enables the load point power module 200 to continue to work normally, converting the energy stored in the power failure energy retention unit 100 into the P3V3_STBY and P1V8_STBY voltages required by the target controller (BMC), thereby providing continuous operating power to the target controller (BMC) and achieving delayed power failure.

[0044] Furthermore, in the event of CPLD failure (malfunction), the comparator unit U1 can also serve as a hardware backup (dual protection mechanism). That is, without relying on the CPLD, the comparator unit U1 can directly monitor the second voltage and compare it with the reference voltage in real time. In the event of a system power supply abnormality, when the second voltage is lower than the reference voltage, the comparator unit U1 can immediately respond and output a high-level signal. This high-level signal is then sent to the second OR gate U2 in the NOR unit. Since there is no CPLD interrupt signal output in this case, the signal output from the NOR unit is input to the NOT gate in the NOR unit. Therefore, the NOR unit can still output a high-level signal, thereby controlling the switch module Q1 to turn off and providing continuous operating power to the target controller (BMC) through the load point power module 200 via the power-down energy retention unit 100, thus achieving delayed power-down.

[0045] It should be noted that the CPLD can also achieve a controllable, soft power restart of the target controller (BMC). Specifically, when the system needs to restart the target controller (BMC) normally, the CPLD can actively output the control signal CPLD_EN (CPLD enable signal output terminal) to a low level. This low-level signal can be input to the first OR gate U3 together with the final output signal (P12V_OK_N) of the NOR unit. Under the premise of normal power supply (P12V_OK_N is low), CPLD_EN is also low, which will cause the output of the first OR gate U3 to be low (POL_EN), thereby shutting down the output of the load point power module 200 and cutting off the power supply to the target controller (BMC). Subsequently, the CPLD can pull CPLD_EN high again, so that POL_EN also returns to a high level, re-enabling the load point power module 200, realizing a controlled restart of the power supply to the target controller (BMC), and completing a soft reset operation led by the CPLD.

[0046] Therefore, by configuring the NOR unit to consist of a second OR gate and a NOT gate, the NOR unit can generate a control signal based on the output signal of the comparator unit (voltage anomaly detection) and the CPLD interrupt signal. This design ensures that the switching module can disconnect in time when the system power supply is abnormal, while the point-of-load power supply module can continue to supply power to the target controller.

[0047] Optionally, in some embodiments, the switching module Q1 is a MOSFET, the gate of the MOSFET is electrically connected to the output terminal of the second OR gate U2, the source of the MOSFET is electrically connected to the first input terminal of the load point power supply module 200, and the drain of the MOSFET is electrically connected to the first power supply terminal.

[0048] Optionally, in some embodiments, the MOS transistor is a PMOS transistor.

[0049] Specifically, in this embodiment of the invention, the switching module Q1 uses a P-channel MOSFET (i.e., a PMOS transistor). Its core function is to conduct when the system power supply is normal to transfer power, and to turn off when the power supply is abnormal to achieve power isolation. Figure 1 As shown, the specific connection and operation of the MOSFET (switching module Q1) are as follows: The gate of the MOSFET is connected to the output of the second OR gate U2 to receive the control signal (P12V_OK_N) finally output by the NOR unit. When this signal is low, the MOSFET is turned on (for P-MOSFETs, a low gate voltage can keep it in the on state); when this signal is high, the MOSFET is turned off. This characteristic allows the switching module Q1 to precisely control the current flow according to the instructions of the on / off control module. The source of the MOSFET is connected to the first input terminal (POL_VIN) of the point-of-load power module 200. This means that when the switching module Q1 is turned on, the main power supply (P12V_STBY) current flows from the drain to the source, charging the power-down energy retention unit 100 and powering the target controller (BMC). The drain of the MOSFET is connected to the first power supply terminal, indicating that the upstream energy source of the switching module Q1 is the system's main power supply. Under normal system operation, the main power supply flows to the subsequent circuits through the switching module Q1.

[0050] Therefore, the above connection method can ensure that when the system is powered normally, the main power supply can supply power to the power failure energy retention unit, the load point power module and the target controller through the MOSFET; and when the system power supply is abnormal, the MOSFET can be quickly disconnected to achieve intelligent power isolation and ensure that the target controller can still maintain stable operation at the moment of power failure.

[0051] It should be noted that, in addition to using a PMOS transistor and the connection method described above to achieve specific functions, the switching module Q1 can also achieve the same function by using an N-channel MOSFET (NMOS transistor) in conjunction with a charge pump or high-side driver. For example, when the switching module Q1 is an NMOS transistor, a dedicated high-side driver or charge pump circuit can be configured for its gate. The driver can output a voltage higher than the main power supply (such as 15V) to fully turn on the NMOS transistor when the system power supply is normal. When the system power supply is abnormal, the driver pulls the gate low, turns off the NMOS, and achieves electrical isolation.

[0052] Optionally, in some embodiments, the comparison unit U1 is a voltage comparator, with its first input terminal electrically connected to the second power supply terminal, its second input terminal electrically connected to the reference voltage output node, and its power input terminal electrically connected to the power supply access node.

[0053] Specifically, in the circuit of this embodiment of the invention, the comparison unit U1 adopts a voltage comparator, and its connection relationship can be as follows: Figure 1As shown, the first input of the voltage comparator is not directly connected to the main power supply, but rather through a resistor divider network. That is, the main power supply, after being divided by the resistor divider network, yields a proportionally reduced voltage signal. This signal is then fed into the voltage comparator through the second power supply terminal as the actual voltage sample value to be detected. The second input of the voltage comparator is connected to the reference voltage output node. The reference voltage is a stable and accurate DC voltage (such as 2.5V or 3.0V) generated by a voltage regulator circuit (such as a dedicated reference source), unaffected by fluctuations in the main power supply, and thus serves as a reference threshold for determining whether the system power supply is normal. The power input of the voltage comparator is connected to the power input node (VCC) to receive external power.

[0054] Thus, the comparison unit forms an independent and reliable hardware monitoring loop by sampling the actual voltage, comparing it with the reference voltage, and powering itself. This loop triggers protection when the power supply is abnormal, ensuring that the target controller can complete the critical fault log writing.

[0055] Next, the power failure energy retention unit 100 will be described in detail.

[0056] Optionally, in some embodiments, the power-down energy retention unit 100 includes: a first power network and a filter-energy storage capacitor module, wherein the first power network is used to provide a third voltage; the filter-energy storage capacitor module is connected between the first power network and the ground node, wherein when the system power supply is normal, the filter-energy storage capacitor module is configured to decouple and filter the first power network; when the system power supply is abnormal, the filter-energy storage capacitor module is configured to supply power to the target controller through the load point power module 200 to complete the fault log writing.

[0057] Specifically, the power-down energy retention unit 100 acts as the "energy warehouse" of the entire circuit, specifically designed to provide brief but critical continuous power to the target controller (BMC) in the event of a sudden interruption or drop in main power, ensuring its ability to complete the fault log writing operation. For example... Figure 1As shown, the power-down energy retention unit 100 can be composed of two core parts: a first power network and a filter-energy storage capacitor module. The first power network is an independent power node. Its input terminal is electrically connected to the first power supply terminal through the switch module Q1, and its output terminal is connected to the load point power module 200 to provide a third voltage (P12V_STBY_CAP). When the system power supply is normal, the third voltage is basically equal to the main power supply P12V_STBY (about 12V). However, due to the switching module Q1 and the filter-energy storage capacitor module, its voltage is more stable and the noise is lower. When the system power supply is abnormal and the switch module Q1 is turned off, the first power network is isolated from the main power supply, and the third voltage is maintained by the filter-energy storage capacitor module. It will slowly decrease as the target controller (BMC) consumes power (gradually decreasing from 12V).

[0058] The filter-energy storage capacitor module can be composed of multiple large-capacity capacitors (such as electrolytic capacitors, tantalum capacitors, or high-capacitance ceramic capacitors) connected in parallel between the first power network and the ground node. When the system power supply is normal, the filter-energy storage capacitor module can decouple and filter the first power network to stabilize the power supply. It is understandable that when the operating current of the target controller (BMC) or other downstream circuits changes rapidly (such as during sudden CPU (Central Processing Unit) operations), a momentary current demand will occur. The filter-energy storage capacitor module can provide this transient current locally, avoiding drawing it from the distant main power supply (first power supply terminal), thus preventing main power supply voltage fluctuations from affecting system stability. Furthermore, as a low-pass filter, this filter-energy storage capacitor module can absorb and bypass high-frequency noise and ripple transmitted from the main power supply, ensuring a clean and stable voltage on the first power network, which is crucial for powering sensitive control chips such as the BMC. When the system power supply is abnormal, after the switching module Q1 is disconnected due to the abnormal power supply, the power-down energy retention unit 100 is isolated from the main power supply (first power supply terminal). At this time, the electrical energy stored in the filter-energy storage capacitor module becomes the only energy source. The filter-energy storage capacitor module begins to discharge to the load point power module 200 to provide the necessary power to maintain the operation of the target controller (BMC), thereby ensuring that the capacitor can continuously supply power for at least 110ms to meet the time requirement for the target controller (BMC) to complete the fault log writing.

[0059] Therefore, in traditional designs, filter capacitors and energy storage capacitors are usually designed separately. Filter capacitors are used to stabilize the power supply, while energy storage capacitors are used to provide energy during power failures. This design often leads to complex circuits and low efficiency. Integrating filtering and energy storage functions into a single module, namely the filter-energy storage capacitor module, simplifies circuit design and improves energy utilization efficiency when the system is powered normally and provides power to the target controller when the system is powered abnormally. Furthermore, the filter-energy storage capacitor module works in conjunction with the first power network to achieve the goal of seamlessly maintaining power supply to the target controller during a power outage.

[0060] To ensure that the filter-energy storage capacitor module can provide sufficient energy to allow critical components (such as the target controller (BMC) or eMMC) to continue operating for a period of time after the main power supply fails in order to complete the writing of the fault log, the number of capacitors in the filter-energy storage capacitor module needs to be determined according to actual requirements (such as the required voltage range to be maintained, load power consumption, and the required power supply duration).

[0061] Specifically, the operating voltage range of the first power network is 12V-5V (5V is the minimum input voltage required to maintain the normal operation of the downstream load point power module 200), meaning the effective operating voltage range of the filter-energy storage capacitor module is 12V-5V. Ideally, the target controller (BMC) and its connected eMMC storage chip will both operate normally, resulting in a total load power consumption of 5W. In an extreme safety net scenario, only the eMMC chip is required to continue operating (the target controller (BMC) may be off or operating at low power) to ensure logs can be written to storage, resulting in a load power consumption of 0.5W. Based on this, the physical formula for calculating capacitor energy storage can be expressed as follows:

[0062]

[0063] in, This represents the initial energy stored in the capacitor at 12V. This represents the remaining energy stored in the capacitor at 5V. For capacitors, The initial voltage is 12V. The remaining voltage is 5V. Power consumption of the load (BMC / eMMC) The required power supply duration (110ms).

[0064] Therefore, the energy released by the capacitor during the discharge process from 12V to 5V must be greater than or equal to the energy consumed by the load within time t.

[0065] Optionally, in some embodiments, the number of capacitors in the filter-energy storage capacitor module is determined by the first power consumption of the target controller and the time required to save the first power failure log.

[0066] Specifically, based on the physical formula for calculating capacitor energy storage, assuming that the target controller (BMC) and its connected eMMC storage chip are working normally, the required capacitor can be calculated based on the first power consumption of the target controller (BMC) and the time required to save the first power failure log (110ms), thereby determining the number of capacitors in the filter-energy storage capacitor module.

[0067] Therefore, by properly configuring the number of capacitors in the filter-energy storage capacitor module, it can be ensured that when the target controller (BMC) and its connected eMMC storage chip are working normally, the capacitor energy storage can meet the energy consumption requirements of the load during a specific power failure log retention period.

[0068] Optionally, in some embodiments, the number of capacitors in the filter-energy storage capacitor module is determined by the second power consumption and the time required to save the second power-down log of the non-volatile storage carrier of the target controller.

[0069] Specifically, under extreme minimum requirements, when only the eMMC chip is required to continue operating, based on the physical formula for calculating capacitor energy storage mentioned above, the required capacitor can be calculated according to the second power consumption and the second power failure log saving time (110ms) of the target controller's non-volatile storage medium (i.e., eMMC), thereby determining the number of capacitors in the filter-energy storage capacitor module.

[0070] Therefore, when only the eMMC chip is required to continue working to ensure that logs can be written to storage, the energy storage capacity and number of capacitors can be calibrated and optimized according to the load power consumption and the time required to save the logs after a power failure, so as to ensure the stable operation of the system and the secure storage of data under various operating conditions.

[0071] Optionally, in some embodiments, when the number of capacitors in the filter-energy storage capacitor module is less than a preset number, the filter-energy storage capacitor module and the first power network are integrated into one structure.

[0072] Understandably, with only the eMMC memory chip operating normally, the total load power consumption is 0.5W and the power supply duration is 110ms. Based on the physical formula for calculating capacitor energy storage, the required capacitor is 2.5mF (i.e., 2500μF). A conventional capacitor is 470μF. The number of capacitors required for hardware implementation is small, and the size is small, so it can be directly designed on the motherboard (onboard capacitor). That is, the filter-energy storage capacitor module and the first power network are set as an integrated structure, without the need for additional space.

[0073] Therefore, the integrated structural design not only simplifies the circuit layout and reduces the number of hardware components, but also lowers the overall cost. At the same time, because the capacitors are directly designed on the motherboard, the current path is shortened, power supply efficiency is improved, and system stability is further enhanced.

[0074] Optionally, in some embodiments, when the number of capacitors in the filter-energy storage capacitor module is greater than or equal to a preset number, at least a portion of the capacitors in the filter-energy storage capacitor module are arranged on a capacitor plate.

[0075] Understandably, assuming the target controller (BMC) and its connected eMMC storage chips are functioning normally, the total load power consumption is 5W, and the power supply duration is 110ms. Based on the physical formula for capacitor energy storage calculation mentioned above, the required capacitor is 25mF (i.e., 25000μF). A typical capacitor is 470μF. In hardware implementation, the required number of capacitors is relatively large (exceeding the preset number, such as 20). If all of them are placed on the motherboard, they will occupy too much valuable space, affecting layout and cost. Therefore, an external capacitor board can be used to concentrate the large number of capacitors of the filter-energy storage capacitor module on a separate small circuit board (capacitor board). This capacitor board is connected to the first power network on the motherboard through a power connector (such as Molex, Hirose, etc.).

[0076] Therefore, by using an external capacitor board design, not only can space be effectively utilized, avoiding the layout congestion caused by too many capacitors on the motherboard, but the capacitor board can also be easily replaced or upgraded when needed, improving the system's flexibility and maintainability. At the same time, because the capacitor board is independent of the motherboard, its heat dissipation performance is also improved, helping to maintain the system's stability and reliability.

[0077] Optionally, in some embodiments, when the filter-energy storage capacitor module includes multiple capacitors, the multiple capacitors are connected in parallel.

[0078] In other words, when a filter-energy storage capacitor module requires a large total capacitance to meet energy storage needs, multiple capacitors are usually connected in parallel. Each capacitor has a certain internal resistance. By connecting multiple capacitors in parallel, the equivalent series resistance can be reduced, which is beneficial for filtering out high-frequency noise and improving filtering performance.

[0079] Therefore, by using a parallel capacitor design, not only can the energy storage capacity of the circuit be enhanced, but the power quality can also be optimized, reducing energy loss and voltage fluctuations caused by resistance.

[0080] Optionally, in some embodiments, the aforementioned delayed power-down circuit 10 further includes a power supply module, comprising a second power network, a first resistor, and a second resistor, wherein the second power network is used to provide a first voltage; one end of the first resistor is electrically connected to the second power network and a first end of the switching module to form a first power supply terminal; one end of the second resistor is electrically connected to the other end of the first resistor and the on / off control module, and the other end of the second resistor is electrically connected to a ground node; the first resistor and the second resistor are configured to provide a second voltage to the on / off control module to form a second power supply terminal.

[0081] Specifically, the delayed power-down circuit 10 also includes a power supply module, which is a key component responsible for power distribution and voltage sampling. It not only provides the main power supply to the system but also generates a voltage divider signal for monitoring by the on / off control module (especially the comparator unit U1). The power supply module mainly consists of a second power network, a first resistor, and a second resistor. The second power network is the main power supply for the entire delayed power-down circuit 10, providing the system with a first voltage (typically a +12V DC voltage, sourced from the electronic device or its main power module). This first voltage serves as the energy source for the entire system, flowing through the first power supply terminal to the switching module Q1 to power the circuit. The first and second resistors form a voltage divider network, used to extract a proportionally reduced voltage signal (i.e., a second voltage) from the main power supply. This second voltage can flow through the second power supply terminal to the on / off control module, serving as a direct basis for determining whether a power supply abnormality has occurred.

[0082] Therefore, the power supply module provides main power through the second power network, and generates a sampling voltage for real-time monitoring of the main power status through a voltage divider network composed of the first resistor and the second resistor, thereby ensuring that the delayed power-down circuit can detect power supply abnormalities in a timely manner.

[0083] Optionally, in some embodiments, the first power supply terminal is configured to output a first voltage, and the second power supply terminal is configured to output a second voltage, wherein the first voltage is greater than the second voltage.

[0084] Understandably, the first power supply terminal is the output interface of the main power supply, used to output the first voltage (+12V). The first power supply terminal is responsible for providing high-power main power to the entire delayed power-down circuit and the subsequent system (through the switching module Q1 and the load point power module 200). The second power supply terminal is the output node of the voltage divider network composed of the first resistor and the second resistor, used to output the second voltage (the second voltage is the proportionally reduced value obtained after the first voltage is divided by the resistors, that is, the first voltage is greater than the second voltage). In other words, the second power supply terminal does not provide power, but provides a sampling signal representing the main power supply status to the comparison unit U1 in the on / off control module, accurately reflecting the changes in the main power supply voltage, for real-time monitoring and fault detection.

[0085] Therefore, by configuring the first and second power supply terminals differently, the delayed power-down circuit can more precisely control the power supply's on / off state. When the main power supply is operating normally, the first power supply terminal provides a stable high-power output, ensuring the normal operation of electronic equipment. Simultaneously, the second power supply terminal provides a sampling signal through a voltage divider network, enabling the on / off control module to monitor the main power supply voltage in real time. Once a voltage anomaly or fault is detected, a protection mechanism can be immediately triggered to prevent equipment damage. This design not only improves power management efficiency but also enhances system stability and reliability.

[0086] Optionally, in some embodiments, the aforementioned delayed power-down circuit 10 further includes: a display module, which is communicatively connected to the target controller and configured to display fault logs written in the non-volatile storage medium of the target controller.

[0087] Understandably, the delayed power-down circuit 10 is not merely a passive power protection device; it also integrates a fault information visualization function. Specifically, a display module visually presents the fault information recorded by the system before the power outage to maintenance personnel. This display module establishes a connection with the target controller (BMC) via a communication interface. The communication method can be a common digital interface, such as UART (Universal Asynchronous Receiver / Transmitter), SPI (Serial Peripheral Interface), or GPIO (General Purpose Input / Output), used to read and display fault logs stored in the target controller's internal or external non-volatile memory. The fault log content can include key information such as power outage time, power supply voltage, system status, and error codes.

[0088] Therefore, by setting up a display module, the fault logs successfully saved by the target controller at the moment of power failure can be displayed locally, realizing the visualization and easy access to fault information.

[0089] Optionally, in some embodiments, the aforementioned delayed power-down circuit 10 further includes: a communication module, which is communicatively connected to the target controller and configured to send fault logs written in the non-volatile storage medium of the target controller to a preset mobile terminal.

[0090] Specifically, the delayed power-down circuit 10 also includes a communication module, which is an extended functional unit of the delayed power-down circuit 10. It can be connected to the target controller (BMC) through a standard communication interface (such as UART, SPI or Ethernet), receive fault log data processed and stored by the target controller (BMC), and send this log data to one or more remote mobile devices (i.e., preset mobile terminals, such as smartphones, tablets, monitoring servers, cloud platforms, etc.) through wireless or wired communication.

[0091] Therefore, this communication module can proactively push key information from fault logs to remote mobile devices, enabling remote real-time alarms and notifications of fault information, and achieving the high-reliability operation and maintenance goal of "no data loss during power outages and immediate awareness of faults".

[0092] Optionally, in some embodiments, the aforementioned delayed power-down circuit 10 further includes: an alert module, which is communicatively connected to the target controller and configured to issue a write completion alert after the fault log is written to the non-volatile storage medium of the target controller.

[0093] Specifically, the delayed power-down circuit 10 also integrates a status feedback mechanism, namely an alert module. Its core function is to send a clear task completion signal to the outside world after the successful completion of a critical operation (fault log writing), providing intuitive operation confirmation for maintenance personnel or the system. This alert module can be connected to the target controller (BMC) through a communication interface (such as GPIO, UART, etc.). After completing the log writing operation, it sends a "complete" signal to the alert module. Upon receiving the "complete" signal, the alert module immediately triggers an alert action, informing the user or system that "power-down protection has been completed and the log has been safely saved" in a visual or perceptible way (such as acoustic alerts (such as buzzers), optical alerts (such as LED indicators), vibration alerts, simple text alerts, etc.).

[0094] Therefore, by setting up a reminder module, a reminder can be sent after the fault log is written, realizing a closed loop from "execution protection" to "confirmation of success", which greatly improves the user-friendliness and operational reliability of the system.

[0095] According to the delayed power-down circuit proposed in this embodiment of the invention, the power supply of the target controller is decoupled from the system power supply through a switching module, and a power-down energy retention unit is added to the isolated power supply path. When an abnormality in the system power supply is detected, the main power supply connection can be quickly cut off, and the power-down energy retention unit can provide independent energy support to ensure that the BMC has sufficient time to complete the recording of the fault log. Thus, the problem that the target controller cannot complete the recording of the fault log due to the instantaneous power failure caused by the abnormality in the system power supply is solved in the prior art. This significantly improves the fault diagnosis capability and system recovery efficiency of electronic equipment in the event of a sudden power failure.

[0096] Through the above description of the embodiments, those skilled in the art can clearly understand that the system according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0097] Embodiments of the present invention also provide a power module, which includes Figure 1 The delayed power-down circuit in the embodiment.

[0098] According to the power module proposed in the embodiments of the present invention, the delayed power-down circuit solves the problem in the prior art that the target controller cannot complete fault log recording due to the instantaneous power failure caused by abnormal system power supply, thereby significantly improving the fault diagnosis capability and system recovery efficiency of electronic devices in the event of sudden power failure.

[0099] Embodiments of the present invention also provide an electronic device that includes the power module described above.

[0100] The electronic device proposed in the embodiments of the present invention solves the problem in the prior art that the target controller cannot complete fault log recording due to the instantaneous power failure caused by abnormal system power supply, thereby significantly improving the fault diagnosis capability and system recovery efficiency of the electronic device in the event of a sudden power failure.

[0101] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0102] The above provides a detailed description of a delayed power-down circuit provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of the above embodiments are only intended to help understand the circuit and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A delay power down circuit, characterized by, The application relates to a power supply system, comprising: a switch module, a power-off energy holding unit and a load point power supply module, wherein, a first end of the switch module is electrically connected with a first power supply end, a second end of the switch module is electrically connected with an input end of the power-off energy holding unit, and the switch module is configured to be in an off state when system power supply is abnormal, so as to isolate the power-off energy holding unit; an output end of the power-off energy holding unit is electrically connected with a first input end of the load point power supply module, wherein an output end of the load point power supply module is electrically connected with a target controller, and the power-off energy holding unit is configured to supply power to the target controller through the load point power supply module when the system power supply is abnormal, so as to complete fault log writing; wherein the power-off energy holding unit comprises a first power supply network and a filter-energy storage capacitor module, the first power supply network is used for providing a third voltage, and the filter-energy storage capacitor module is connected between the first power supply network and a ground node, wherein when the system power supply is normal, the filter-energy storage capacitor module is configured to decouple and filter the first power supply network; when the system power supply is abnormal, the filter-energy storage capacitor module is configured to supply power to the target controller through the load point power supply module to complete fault log writing.

2. The delay power-down circuit according to claim 1, wherein Further comprising: a on-off control module, the on-off control module is respectively electrically connected with a second power supply end, a control end of the switch module, an interrupt signal output end, an enable signal output end and a second input end of the load point power supply module; wherein, the on-off control module is configured to output an off signal to the switch module when the system power supply is abnormal, and output a load point enable signal to the second input end of the load point power supply module, so that the load point power supply module supplies power to the target controller based on the load point enable signal.

3. The delay power-down circuit according to claim 2, wherein the on-off control module comprises a comparison unit, a NOR unit and a first OR gate, wherein, the comparison unit is respectively electrically connected with the second power supply input port, a reference voltage output node, a power supply input node and a first input end of the NOR unit, and the comparison unit is configured to generate a comparison signal according to a second voltage and an output voltage of the reference voltage output node, and output the comparison signal to the first input end of the NOR unit; the first input end of the NOR unit is electrically connected with the output end of the comparison unit, the second input end of the NOR unit is electrically connected with the interrupt signal output end, and the output end of the NOR unit is respectively electrically connected with the control end of the switch module and the first input end of the first OR gate; the second input end of the first OR gate is electrically connected with the enable signal output end, and the output end of the first OR gate is electrically connected with the second input end of the load point power supply module.

4. The delay power-down circuit according to claim 3, wherein the NOR unit comprises: a second OR gate, the first input end of the second OR gate is electrically connected with the output end of the comparison unit, and the output end of the second OR gate is respectively electrically connected with the control end of the switch module and the first input end of the first OR gate. A NOT gate, an input end of the NOT gate being electrically connected with the interrupt signal output end, and an output end of the NOT gate being electrically connected with a second input end of the second OR gate.

5. The delay power-down circuit according to claim 4, wherein The switch module is a MOS tube, a gate of the MOS tube being electrically connected with the output end of the second OR gate, a source of the MOS tube being electrically connected with the first input end of the load point power supply module, and a drain of the MOS tube being electrically connected with the first power supply end.

6. The delay power-down circuit of claim 3, wherein, The comparison unit is a voltage comparator, a first input end of the voltage comparator being electrically connected with the second power supply end, a second input end of the voltage comparator being electrically connected with a reference voltage output node, and a power supply input end of the voltage comparator being electrically connected with a power supply access node.

7. The delay power-down circuit of claim 1, wherein, The number of capacitors of the filter-energy storage capacitor module is determined by the first power consumption of the target controller and the time required for saving the first power-off log.

8. The delay power-down circuit according to claim 1 or 7, wherein The number of capacitors of the filter-energy storage capacitor module is determined by the second power consumption of the nonvolatile storage carrier of the target controller and the time required for saving the second power-off log.

9. The delay power-down circuit of claim 8, wherein, When the number of capacitors of the filter-energy storage capacitor module is less than a preset number, the filter-energy storage capacitor module and the first power supply network are integrated.

10. The delay power-down circuit of claim 8, wherein, When the number of capacitors of the filter-energy storage capacitor module is greater than or equal to the preset number, at least part of the capacitors of the filter-energy storage capacitor module are arranged on a capacitor board.

11. The delay power-down circuit of claim 1, wherein, Further comprising: The power supply module includes a second power supply network, a first resistor and a second resistor, wherein, The second power supply network is configured to provide a first voltage. One end of the first resistor is electrically connected with the second power supply network and a first end of the switch module respectively, to form the first power supply end. One end of the second resistor is electrically connected with the other end of the first resistor and the on-off control module respectively, and the other end of the second resistor is electrically connected with a ground node, and the first resistor and the second resistor are configured to provide a second voltage to the on-off control module, to form a second power supply end.

12. The delay power-down circuit of claim 11, wherein, The first power supply end is configured to output the first voltage, and the second power supply end is configured to output the second voltage, wherein the first voltage is greater than the second voltage.

13. A power module, characterized by Comprising: The delay power-off circuit of any one of claims 1-12.

14. An electronic device, comprising: Comprising: The power supply module of claim 13.

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